err.no Git - linux-2.6/blob - drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/tech/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ecc support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *
  28  * This program is free software; you can redistribute it and/or modify
  29  * it under the terms of the GNU General Public License version 2 as
  30  * published by the Free Software Foundation.
  31  *
  32  */
  33
  34 #include <linux/module.h>
  35 #include <linux/delay.h>
  36 #include <linux/errno.h>
  37 #include <linux/err.h>
  38 #include <linux/sched.h>
  39 #include <linux/slab.h>
  40 #include <linux/types.h>
  41 #include <linux/mtd/mtd.h>
  42 #include <linux/mtd/nand.h>
  43 #include <linux/mtd/nand_ecc.h>
  44 #include <linux/mtd/compatmac.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/bitops.h>
  47 #include <linux/leds.h>
  48 #include <asm/io.h>
  49
  50 #ifdef CONFIG_MTD_PARTITIONS
  51 #include <linux/mtd/partitions.h>
  52 #endif
  53
  54 /* Define default oob placement schemes for large and small page devices */
  55 static struct nand_oobinfo nand_oob_8 = {
  56         .useecc = MTD_NANDECC_AUTOPLACE,
  57         .eccbytes = 3,
  58         .eccpos = {0, 1, 2},
  59         .oobfree = {{3, 2}, {6, 2}}
  60 };
  61
  62 static struct nand_oobinfo nand_oob_16 = {
  63         .useecc = MTD_NANDECC_AUTOPLACE,
  64         .eccbytes = 6,
  65         .eccpos = {0, 1, 2, 3, 6, 7},
  66         .oobfree = {{8, 8}}
  67 };
  68
  69 static struct nand_oobinfo nand_oob_64 = {
  70         .useecc = MTD_NANDECC_AUTOPLACE,
  71         .eccbytes = 24,
  72         .eccpos = {
  73                    40, 41, 42, 43, 44, 45, 46, 47,
  74                    48, 49, 50, 51, 52, 53, 54, 55,
  75                    56, 57, 58, 59, 60, 61, 62, 63},
  76         .oobfree = {{2, 38}}
  77 };
  78
  79 /* This is used for padding purposes in nand_write_oob */
  80 static uint8_t ffchars[] = {
  81         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  82         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  83         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  84         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  85         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  86         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  87         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  88         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  89 };
  90
  91 static int nand_write_oob(struct mtd_info *mtd, loff_t to, size_t len,
  92                           size_t *retlen, const uint8_t *buf);
  93 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
  94                            int new_state);
  95
  96 /*
  97  * For devices which display every fart in the system on a seperate LED. Is
  98  * compiled away when LED support is disabled.
  99  */
 100 DEFINE_LED_TRIGGER(nand_led_trigger);
 101
 102 /**
 103  * nand_release_device - [GENERIC] release chip
 104  * @mtd:        MTD device structure
 105  *
 106  * Deselect, release chip lock and wake up anyone waiting on the device
 107  */
 108 static void nand_release_device(struct mtd_info *mtd)
 109 {
 110         struct nand_chip *chip = mtd->priv;
 111
 112         /* De-select the NAND device */
 113         chip->select_chip(mtd, -1);
 114
 115         /* Release the controller and the chip */
 116         spin_lock(&chip->controller->lock);
 117         chip->controller->active = NULL;
 118         chip->state = FL_READY;
 119         wake_up(&chip->controller->wq);
 120         spin_unlock(&chip->controller->lock);
 121 }
 122
 123 /**
 124  * nand_read_byte - [DEFAULT] read one byte from the chip
 125  * @mtd:        MTD device structure
 126  *
 127  * Default read function for 8bit buswith
 128  */
 129 static uint8_t nand_read_byte(struct mtd_info *mtd)
 130 {
 131         struct nand_chip *chip = mtd->priv;
 132         return readb(chip->IO_ADDR_R);
 133 }
 134
 135 /**
 136  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 137  * @mtd:        MTD device structure
 138  *
 139  * Default read function for 16bit buswith with
 140  * endianess conversion
 141  */
 142 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 143 {
 144         struct nand_chip *chip = mtd->priv;
 145         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 146 }
 147
 148 /**
 149  * nand_read_word - [DEFAULT] read one word from the chip
 150  * @mtd:        MTD device structure
 151  *
 152  * Default read function for 16bit buswith without
 153  * endianess conversion
 154  */
 155 static u16 nand_read_word(struct mtd_info *mtd)
 156 {
 157         struct nand_chip *chip = mtd->priv;
 158         return readw(chip->IO_ADDR_R);
 159 }
 160
 161 /**
 162  * nand_select_chip - [DEFAULT] control CE line
 163  * @mtd:        MTD device structure
 164  * @chip:       chipnumber to select, -1 for deselect
 165  *
 166  * Default select function for 1 chip devices.
 167  */
 168 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 169 {
 170         struct nand_chip *chip = mtd->priv;
 171
 172         switch (chipnr) {
 173         case -1:
 174                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 175                 break;
 176         case 0:
 177                 break;
 178
 179         default:
 180                 BUG();
 181         }
 182 }
 183
 184 /**
 185  * nand_write_buf - [DEFAULT] write buffer to chip
 186  * @mtd:        MTD device structure
 187  * @buf:        data buffer
 188  * @len:        number of bytes to write
 189  *
 190  * Default write function for 8bit buswith
 191  */
 192 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 193 {
 194         int i;
 195         struct nand_chip *chip = mtd->priv;
 196
 197         for (i = 0; i < len; i++)
 198                 writeb(buf[i], chip->IO_ADDR_W);
 199 }
 200
 201 /**
 202  * nand_read_buf - [DEFAULT] read chip data into buffer
 203  * @mtd:        MTD device structure
 204  * @buf:        buffer to store date
 205  * @len:        number of bytes to read
 206  *
 207  * Default read function for 8bit buswith
 208  */
 209 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 210 {
 211         int i;
 212         struct nand_chip *chip = mtd->priv;
 213
 214         for (i = 0; i < len; i++)
 215                 buf[i] = readb(chip->IO_ADDR_R);
 216 }
 217
 218 /**
 219  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 220  * @mtd:        MTD device structure
 221  * @buf:        buffer containing the data to compare
 222  * @len:        number of bytes to compare
 223  *
 224  * Default verify function for 8bit buswith
 225  */
 226 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 227 {
 228         int i;
 229         struct nand_chip *chip = mtd->priv;
 230
 231         for (i = 0; i < len; i++)
 232                 if (buf[i] != readb(chip->IO_ADDR_R))
 233                         return -EFAULT;
 234         return 0;
 235 }
 236
 237 /**
 238  * nand_write_buf16 - [DEFAULT] write buffer to chip
 239  * @mtd:        MTD device structure
 240  * @buf:        data buffer
 241  * @len:        number of bytes to write
 242  *
 243  * Default write function for 16bit buswith
 244  */
 245 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 246 {
 247         int i;
 248         struct nand_chip *chip = mtd->priv;
 249         u16 *p = (u16 *) buf;
 250         len >>= 1;
 251
 252         for (i = 0; i < len; i++)
 253                 writew(p[i], chip->IO_ADDR_W);
 254
 255 }
 256
 257 /**
 258  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 259  * @mtd:        MTD device structure
 260  * @buf:        buffer to store date
 261  * @len:        number of bytes to read
 262  *
 263  * Default read function for 16bit buswith
 264  */
 265 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 266 {
 267         int i;
 268         struct nand_chip *chip = mtd->priv;
 269         u16 *p = (u16 *) buf;
 270         len >>= 1;
 271
 272         for (i = 0; i < len; i++)
 273                 p[i] = readw(chip->IO_ADDR_R);
 274 }
 275
 276 /**
 277  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 278  * @mtd:        MTD device structure
 279  * @buf:        buffer containing the data to compare
 280  * @len:        number of bytes to compare
 281  *
 282  * Default verify function for 16bit buswith
 283  */
 284 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 285 {
 286         int i;
 287         struct nand_chip *chip = mtd->priv;
 288         u16 *p = (u16 *) buf;
 289         len >>= 1;
 290
 291         for (i = 0; i < len; i++)
 292                 if (p[i] != readw(chip->IO_ADDR_R))
 293                         return -EFAULT;
 294
 295         return 0;
 296 }
 297
 298 /**
 299  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 300  * @mtd:        MTD device structure
 301  * @ofs:        offset from device start
 302  * @getchip:    0, if the chip is already selected
 303  *
 304  * Check, if the block is bad.
 305  */
 306 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 307 {
 308         int page, chipnr, res = 0;
 309         struct nand_chip *chip = mtd->priv;
 310         u16 bad;
 311
 312         if (getchip) {
 313                 page = (int)(ofs >> chip->page_shift);
 314                 chipnr = (int)(ofs >> chip->chip_shift);
 315
 316                 nand_get_device(chip, mtd, FL_READING);
 317
 318                 /* Select the NAND device */
 319                 chip->select_chip(mtd, chipnr);
 320         } else
 321                 page = (int)ofs;
 322
 323         if (chip->options & NAND_BUSWIDTH_16) {
 324                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
 325                               page & chip->pagemask);
 326                 bad = cpu_to_le16(chip->read_word(mtd));
 327                 if (chip->badblockpos & 0x1)
 328                         bad >>= 8;
 329                 if ((bad & 0xFF) != 0xff)
 330                         res = 1;
 331         } else {
 332                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
 333                               page & chip->pagemask);
 334                 if (chip->read_byte(mtd) != 0xff)
 335                         res = 1;
 336         }
 337
 338         if (getchip)
 339                 nand_release_device(mtd);
 340
 341         return res;
 342 }
 343
 344 /**
 345  * nand_default_block_markbad - [DEFAULT] mark a block bad
 346  * @mtd:        MTD device structure
 347  * @ofs:        offset from device start
 348  *
 349  * This is the default implementation, which can be overridden by
 350  * a hardware specific driver.
 351 */
 352 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 353 {
 354         struct nand_chip *chip = mtd->priv;
 355         uint8_t buf[2] = { 0, 0 };
 356         size_t retlen;
 357         int block;
 358
 359         /* Get block number */
 360         block = ((int)ofs) >> chip->bbt_erase_shift;
 361         if (chip->bbt)
 362                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 363
 364         /* Do we have a flash based bad block table ? */
 365         if (chip->options & NAND_USE_FLASH_BBT)
 366                 return nand_update_bbt(mtd, ofs);
 367
 368         /* We write two bytes, so we dont have to mess with 16 bit access */
 369         ofs += mtd->oobsize + (chip->badblockpos & ~0x01);
 370         return nand_write_oob(mtd, ofs, 2, &retlen, buf);
 371 }
 372
 373 /**
 374  * nand_check_wp - [GENERIC] check if the chip is write protected
 375  * @mtd:        MTD device structure
 376  * Check, if the device is write protected
 377  *
 378  * The function expects, that the device is already selected
 379  */
 380 static int nand_check_wp(struct mtd_info *mtd)
 381 {
 382         struct nand_chip *chip = mtd->priv;
 383         /* Check the WP bit */
 384         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 385         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 386 }
 387
 388 /**
 389  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 390  * @mtd:        MTD device structure
 391  * @ofs:        offset from device start
 392  * @getchip:    0, if the chip is already selected
 393  * @allowbbt:   1, if its allowed to access the bbt area
 394  *
 395  * Check, if the block is bad. Either by reading the bad block table or
 396  * calling of the scan function.
 397  */
 398 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 399                                int allowbbt)
 400 {
 401         struct nand_chip *chip = mtd->priv;
 402
 403         if (!chip->bbt)
 404                 return chip->block_bad(mtd, ofs, getchip);
 405
 406         /* Return info from the table */
 407         return nand_isbad_bbt(mtd, ofs, allowbbt);
 408 }
 409
 410 /*
 411  * Wait for the ready pin, after a command
 412  * The timeout is catched later.
 413  */
 414 static void nand_wait_ready(struct mtd_info *mtd)
 415 {
 416         struct nand_chip *chip = mtd->priv;
 417         unsigned long timeo = jiffies + 2;
 418
 419         led_trigger_event(nand_led_trigger, LED_FULL);
 420         /* wait until command is processed or timeout occures */
 421         do {
 422                 if (chip->dev_ready(mtd))
 423                         break;
 424                 touch_softlockup_watchdog();
 425         } while (time_before(jiffies, timeo));
 426         led_trigger_event(nand_led_trigger, LED_OFF);
 427 }
 428
 429 /**
 430  * nand_command - [DEFAULT] Send command to NAND device
 431  * @mtd:        MTD device structure
 432  * @command:    the command to be sent
 433  * @column:     the column address for this command, -1 if none
 434  * @page_addr:  the page address for this command, -1 if none
 435  *
 436  * Send command to NAND device. This function is used for small page
 437  * devices (256/512 Bytes per page)
 438  */
 439 static void nand_command(struct mtd_info *mtd, unsigned int command,
 440                          int column, int page_addr)
 441 {
 442         register struct nand_chip *chip = mtd->priv;
 443         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 444
 445         /*
 446          * Write out the command to the device.
 447          */
 448         if (command == NAND_CMD_SEQIN) {
 449                 int readcmd;
 450
 451                 if (column >= mtd->writesize) {
 452                         /* OOB area */
 453                         column -= mtd->writesize;
 454                         readcmd = NAND_CMD_READOOB;
 455                 } else if (column < 256) {
 456                         /* First 256 bytes --> READ0 */
 457                         readcmd = NAND_CMD_READ0;
 458                 } else {
 459                         column -= 256;
 460                         readcmd = NAND_CMD_READ1;
 461                 }
 462                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 463                 ctrl &= ~NAND_CTRL_CHANGE;
 464         }
 465         chip->cmd_ctrl(mtd, command, ctrl);
 466
 467         /*
 468          * Address cycle, when necessary
 469          */
 470         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 471         /* Serially input address */
 472         if (column != -1) {
 473                 /* Adjust columns for 16 bit buswidth */
 474                 if (chip->options & NAND_BUSWIDTH_16)
 475                         column >>= 1;
 476                 chip->cmd_ctrl(mtd, column, ctrl);
 477                 ctrl &= ~NAND_CTRL_CHANGE;
 478         }
 479         if (page_addr != -1) {
 480                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 481                 ctrl &= ~NAND_CTRL_CHANGE;
 482                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 483                 /* One more address cycle for devices > 32MiB */
 484                 if (chip->chipsize > (32 << 20))
 485                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 486         }
 487         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 488
 489         /*
 490          * program and erase have their own busy handlers
 491          * status and sequential in needs no delay
 492          */
 493         switch (command) {
 494
 495         case NAND_CMD_PAGEPROG:
 496         case NAND_CMD_ERASE1:
 497         case NAND_CMD_ERASE2:
 498         case NAND_CMD_SEQIN:
 499         case NAND_CMD_STATUS:
 500                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
 501                 return;
 502
 503         case NAND_CMD_RESET:
 504                 if (chip->dev_ready)
 505                         break;
 506                 udelay(chip->chip_delay);
 507                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 508                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 509                 chip->cmd_ctrl(mtd,
 510                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 511                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 512                 return;
 513
 514                 /* This applies to read commands */
 515         default:
 516                 /*
 517                  * If we don't have access to the busy pin, we apply the given
 518                  * command delay
 519                  */
 520                 if (!chip->dev_ready) {
 521                         udelay(chip->chip_delay);
 522                         return;
 523                 }
 524         }
 525         /* Apply this short delay always to ensure that we do wait tWB in
 526          * any case on any machine. */
 527         ndelay(100);
 528
 529         nand_wait_ready(mtd);
 530 }
 531
 532 /**
 533  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 534  * @mtd:        MTD device structure
 535  * @command:    the command to be sent
 536  * @column:     the column address for this command, -1 if none
 537  * @page_addr:  the page address for this command, -1 if none
 538  *
 539  * Send command to NAND device. This is the version for the new large page
 540  * devices We dont have the separate regions as we have in the small page
 541  * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
 542  *
 543  */
 544 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 545                             int column, int page_addr)
 546 {
 547         register struct nand_chip *chip = mtd->priv;
 548
 549         /* Emulate NAND_CMD_READOOB */
 550         if (command == NAND_CMD_READOOB) {
 551                 column += mtd->writesize;
 552                 command = NAND_CMD_READ0;
 553         }
 554
 555         /* Command latch cycle */
 556         chip->cmd_ctrl(mtd, command & 0xff,
 557                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 558
 559         if (column != -1 || page_addr != -1) {
 560                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 561
 562                 /* Serially input address */
 563                 if (column != -1) {
 564                         /* Adjust columns for 16 bit buswidth */
 565                         if (chip->options & NAND_BUSWIDTH_16)
 566                                 column >>= 1;
 567                         chip->cmd_ctrl(mtd, column, ctrl);
 568                         ctrl &= ~NAND_CTRL_CHANGE;
 569                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 570                 }
 571                 if (page_addr != -1) {
 572                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 573                         chip->cmd_ctrl(mtd, page_addr >> 8,
 574                                        NAND_NCE | NAND_ALE);
 575                         /* One more address cycle for devices > 128MiB */
 576                         if (chip->chipsize > (128 << 20))
 577                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 578                                                NAND_NCE | NAND_ALE);
 579                 }
 580         }
 581         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 582
 583         /*
 584          * program and erase have their own busy handlers
 585          * status, sequential in, and deplete1 need no delay
 586          */
 587         switch (command) {
 588
 589         case NAND_CMD_CACHEDPROG:
 590         case NAND_CMD_PAGEPROG:
 591         case NAND_CMD_ERASE1:
 592         case NAND_CMD_ERASE2:
 593         case NAND_CMD_SEQIN:
 594         case NAND_CMD_STATUS:
 595         case NAND_CMD_DEPLETE1:
 596                 return;
 597
 598                 /*
 599                  * read error status commands require only a short delay
 600                  */
 601         case NAND_CMD_STATUS_ERROR:
 602         case NAND_CMD_STATUS_ERROR0:
 603         case NAND_CMD_STATUS_ERROR1:
 604         case NAND_CMD_STATUS_ERROR2:
 605         case NAND_CMD_STATUS_ERROR3:
 606                 udelay(chip->chip_delay);
 607                 return;
 608
 609         case NAND_CMD_RESET:
 610                 if (chip->dev_ready)
 611                         break;
 612                 udelay(chip->chip_delay);
 613                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 614                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 615                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 616                                NAND_NCE | NAND_CTRL_CHANGE);
 617                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 618                 return;
 619
 620         case NAND_CMD_READ0:
 621                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 622                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 623                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 624                                NAND_NCE | NAND_CTRL_CHANGE);
 625
 626                 /* This applies to read commands */
 627         default:
 628                 /*
 629                  * If we don't have access to the busy pin, we apply the given
 630                  * command delay
 631                  */
 632                 if (!chip->dev_ready) {
 633                         udelay(chip->chip_delay);
 634                         return;
 635                 }
 636         }
 637
 638         /* Apply this short delay always to ensure that we do wait tWB in
 639          * any case on any machine. */
 640         ndelay(100);
 641
 642         nand_wait_ready(mtd);
 643 }
 644
 645 /**
 646  * nand_get_device - [GENERIC] Get chip for selected access
 647  * @this:       the nand chip descriptor
 648  * @mtd:        MTD device structure
 649  * @new_state:  the state which is requested
 650  *
 651  * Get the device and lock it for exclusive access
 652  */
 653 static int
 654 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 655 {
 656         spinlock_t *lock = &chip->controller->lock;
 657         wait_queue_head_t *wq = &chip->controller->wq;
 658         DECLARE_WAITQUEUE(wait, current);
 659  retry:
 660         spin_lock(lock);
 661
 662         /* Hardware controller shared among independend devices */
 663         /* Hardware controller shared among independend devices */
 664         if (!chip->controller->active)
 665                 chip->controller->active = chip;
 666
 667         if (chip->controller->active == chip && chip->state == FL_READY) {
 668                 chip->state = new_state;
 669                 spin_unlock(lock);
 670                 return 0;
 671         }
 672         if (new_state == FL_PM_SUSPENDED) {
 673                 spin_unlock(lock);
 674                 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
 675         }
 676         set_current_state(TASK_UNINTERRUPTIBLE);
 677         add_wait_queue(wq, &wait);
 678         spin_unlock(lock);
 679         schedule();
 680         remove_wait_queue(wq, &wait);
 681         goto retry;
 682 }
 683
 684 /**
 685  * nand_wait - [DEFAULT]  wait until the command is done
 686  * @mtd:        MTD device structure
 687  * @this:       NAND chip structure
 688  * @state:      state to select the max. timeout value
 689  *
 690  * Wait for command done. This applies to erase and program only
 691  * Erase can take up to 400ms and program up to 20ms according to
 692  * general NAND and SmartMedia specs
 693  *
 694 */
 695 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip, int state)
 696 {
 697
 698         unsigned long timeo = jiffies;
 699         int status;
 700
 701         if (state == FL_ERASING)
 702                 timeo += (HZ * 400) / 1000;
 703         else
 704                 timeo += (HZ * 20) / 1000;
 705
 706         led_trigger_event(nand_led_trigger, LED_FULL);
 707
 708         /* Apply this short delay always to ensure that we do wait tWB in
 709          * any case on any machine. */
 710         ndelay(100);
 711
 712         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
 713                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 714         else
 715                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 716
 717         while (time_before(jiffies, timeo)) {
 718                 /* Check, if we were interrupted */
 719                 if (chip->state != state)
 720                         return 0;
 721
 722                 if (chip->dev_ready) {
 723                         if (chip->dev_ready(mtd))
 724                                 break;
 725                 } else {
 726                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 727                                 break;
 728                 }
 729                 cond_resched();
 730         }
 731         led_trigger_event(nand_led_trigger, LED_OFF);
 732
 733         status = (int)chip->read_byte(mtd);
 734         return status;
 735 }
 736
 737 /**
 738  * nand_read_page_swecc - {REPLACABLE] software ecc based page read function
 739  * @mtd:        mtd info structure
 740  * @chip:       nand chip info structure
 741  * @buf:        buffer to store read data
 742  */
 743 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
 744                                 uint8_t *buf)
 745 {
 746         int i, eccsize = chip->ecc.size;
 747         int eccbytes = chip->ecc.bytes;
 748         int eccsteps = chip->ecc.steps;
 749         uint8_t *p = buf;
 750         uint8_t *ecc_calc = chip->buffers.ecccalc;
 751         uint8_t *ecc_code = chip->buffers.ecccode;
 752         int *eccpos = chip->autooob->eccpos;
 753
 754         chip->read_buf(mtd, buf, mtd->writesize);
 755         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 756
 757         if (chip->ecc.mode == NAND_ECC_NONE)
 758                 return 0;
 759
 760         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 761                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 762
 763         for (i = 0; i < chip->ecc.total; i++)
 764                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 765
 766         eccsteps = chip->ecc.steps;
 767         p = buf;
 768
 769         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 770                 int stat;
 771
 772                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 773                 if (stat == -1)
 774                         mtd->ecc_stats.failed++;
 775                 else
 776                         mtd->ecc_stats.corrected += stat;
 777         }
 778         return 0;
 779 }
 780
 781 /**
 782  * nand_read_page_hwecc - {REPLACABLE] hardware ecc based page read function
 783  * @mtd:        mtd info structure
 784  * @chip:       nand chip info structure
 785  * @buf:        buffer to store read data
 786  *
 787  * Not for syndrome calculating ecc controllers which need a special oob layout
 788  */
 789 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 790                                 uint8_t *buf)
 791 {
 792         int i, eccsize = chip->ecc.size;
 793         int eccbytes = chip->ecc.bytes;
 794         int eccsteps = chip->ecc.steps;
 795         uint8_t *p = buf;
 796         uint8_t *ecc_calc = chip->buffers.ecccalc;
 797         uint8_t *ecc_code = chip->buffers.ecccode;
 798         int *eccpos = chip->autooob->eccpos;
 799
 800         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 801                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 802                 chip->read_buf(mtd, p, eccsize);
 803                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 804         }
 805         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 806
 807         for (i = 0; i < chip->ecc.total; i++)
 808                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 809
 810         eccsteps = chip->ecc.steps;
 811         p = buf;
 812
 813         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 814                 int stat;
 815
 816                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 817                 if (stat == -1)
 818                         mtd->ecc_stats.failed++;
 819                 else
 820                         mtd->ecc_stats.corrected += stat;
 821         }
 822         return 0;
 823 }
 824
 825 /**
 826  * nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read
 827  * @mtd:        mtd info structure
 828  * @chip:       nand chip info structure
 829  * @buf:        buffer to store read data
 830  *
 831  * The hw generator calculates the error syndrome automatically. Therefor
 832  * we need a special oob layout and handling.
 833  */
 834 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
 835                                    uint8_t *buf)
 836 {
 837         int i, eccsize = chip->ecc.size;
 838         int eccbytes = chip->ecc.bytes;
 839         int eccsteps = chip->ecc.steps;
 840         uint8_t *p = buf;
 841         uint8_t *oob = chip->oob_poi;
 842
 843         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 844                 int stat;
 845
 846                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 847                 chip->read_buf(mtd, p, eccsize);
 848
 849                 if (chip->ecc.prepad) {
 850                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 851                         oob += chip->ecc.prepad;
 852                 }
 853
 854                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
 855                 chip->read_buf(mtd, oob, eccbytes);
 856                 stat = chip->ecc.correct(mtd, p, oob, NULL);
 857
 858                 if (stat == -1)
 859                         mtd->ecc_stats.failed++;
 860                 else
 861                         mtd->ecc_stats.corrected += stat;
 862
 863                 oob += eccbytes;
 864
 865                 if (chip->ecc.postpad) {
 866                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 867                         oob += chip->ecc.postpad;
 868                 }
 869         }
 870
 871         /* Calculate remaining oob bytes */
 872         i = oob - chip->oob_poi;
 873         if (i)
 874                 chip->read_buf(mtd, oob, i);
 875
 876         return 0;
 877 }
 878
 879 /**
 880  * nand_do_read - [Internal] Read data with ECC
 881  *
 882  * @mtd:        MTD device structure
 883  * @from:       offset to read from
 884  * @len:        number of bytes to read
 885  * @retlen:     pointer to variable to store the number of read bytes
 886  * @buf:        the databuffer to put data
 887  *
 888  * Internal function. Called with chip held.
 889  */
 890 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
 891                  size_t *retlen, uint8_t *buf)
 892 {
 893         int chipnr, page, realpage, col, bytes, aligned;
 894         struct nand_chip *chip = mtd->priv;
 895         struct mtd_ecc_stats stats;
 896         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
 897         int sndcmd = 1;
 898         int ret = 0;
 899         uint32_t readlen = len;
 900         uint8_t *bufpoi;
 901
 902         stats = mtd->ecc_stats;
 903
 904         chipnr = (int)(from >> chip->chip_shift);
 905         chip->select_chip(mtd, chipnr);
 906
 907         realpage = (int)(from >> chip->page_shift);
 908         page = realpage & chip->pagemask;
 909
 910         col = (int)(from & (mtd->writesize - 1));
 911         chip->oob_poi = chip->buffers.oobrbuf;
 912
 913         while(1) {
 914                 bytes = min(mtd->writesize - col, readlen);
 915                 aligned = (bytes == mtd->writesize);
 916
 917                 /* Is the current page in the buffer ? */
 918                 if (realpage != chip->pagebuf) {
 919                         bufpoi = aligned ? buf : chip->buffers.databuf;
 920
 921                         if (likely(sndcmd)) {
 922                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
 923                                 sndcmd = 0;
 924                         }
 925
 926                         /* Now read the page into the buffer */
 927                         ret = chip->ecc.read_page(mtd, chip, bufpoi);
 928                         if (ret < 0)
 929                                 break;
 930
 931                         /* Transfer not aligned data */
 932                         if (!aligned) {
 933                                 chip->pagebuf = realpage;
 934                                 memcpy(buf, chip->buffers.databuf + col, bytes);
 935                         }
 936
 937                         if (!(chip->options & NAND_NO_READRDY)) {
 938                                 /*
 939                                  * Apply delay or wait for ready/busy pin. Do
 940                                  * this before the AUTOINCR check, so no
 941                                  * problems arise if a chip which does auto
 942                                  * increment is marked as NOAUTOINCR by the
 943                                  * board driver.
 944                                  */
 945                                 if (!chip->dev_ready)
 946                                         udelay(chip->chip_delay);
 947                                 else
 948                                         nand_wait_ready(mtd);
 949                         }
 950                 } else
 951                         memcpy(buf, chip->buffers.databuf + col, bytes);
 952
 953                 buf += bytes;
 954                 readlen -= bytes;
 955
 956                 if (!readlen)
 957                         break;
 958
 959                 /* For subsequent reads align to page boundary. */
 960                 col = 0;
 961                 /* Increment page address */
 962                 realpage++;
 963
 964                 page = realpage & chip->pagemask;
 965                 /* Check, if we cross a chip boundary */
 966                 if (!page) {
 967                         chipnr++;
 968                         chip->select_chip(mtd, -1);
 969                         chip->select_chip(mtd, chipnr);
 970                 }
 971
 972                 /* Check, if the chip supports auto page increment
 973                  * or if we have hit a block boundary.
 974                  */
 975                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
 976                         sndcmd = 1;
 977         }
 978
 979         *retlen = len - (size_t) readlen;
 980
 981         if (ret)
 982                 return ret;
 983
 984         return mtd->ecc_stats.failed - stats.failed ? -EBADMSG : 0;
 985 }
 986
 987 /**
 988  * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
 989  * @mtd:        MTD device structure
 990  * @from:       offset to read from
 991  * @len:        number of bytes to read
 992  * @retlen:     pointer to variable to store the number of read bytes
 993  * @buf:        the databuffer to put data
 994  *
 995  * Get hold of the chip and call nand_do_read
 996  */
 997 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
 998                      size_t *retlen, uint8_t *buf)
 999 {
1000         int ret;
1001
1002         *retlen = 0;
1003         /* Do not allow reads past end of device */
1004         if ((from + len) > mtd->size)
1005                 return -EINVAL;
1006         if (!len)
1007                 return 0;
1008
1009         nand_get_device(mtd->priv, mtd, FL_READING);
1010
1011         ret = nand_do_read(mtd, from, len, retlen, buf);
1012
1013         nand_release_device(mtd);
1014
1015         return ret;
1016 }
1017
1018 /**
1019  * nand_read_oob - [MTD Interface] NAND read out-of-band
1020  * @mtd:        MTD device structure
1021  * @from:       offset to read from
1022  * @len:        number of bytes to read
1023  * @retlen:     pointer to variable to store the number of read bytes
1024  * @buf:        the databuffer to put data
1025  *
1026  * NAND read out-of-band data from the spare area
1027  */
1028 static int nand_read_oob(struct mtd_info *mtd, loff_t from, size_t len,
1029                          size_t *retlen, uint8_t *buf)
1030 {
1031         int col, page, realpage, chipnr, sndcmd = 1;
1032         struct nand_chip *chip = mtd->priv;
1033         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1034         int readlen = len;
1035
1036         DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08x, len = %i\n",
1037               (unsigned int)from, (int)len);
1038
1039         /* Initialize return length value */
1040         *retlen = 0;
1041
1042         /* Do not allow reads past end of device */
1043         if ((from + len) > mtd->size) {
1044                 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1045                       "Attempt read beyond end of device\n");
1046                 return -EINVAL;
1047         }
1048
1049         nand_get_device(chip, mtd, FL_READING);
1050
1051         chipnr = (int)(from >> chip->chip_shift);
1052         chip->select_chip(mtd, chipnr);
1053
1054         /* Shift to get page */
1055         realpage = (int)(from >> chip->page_shift);
1056         page = realpage & chip->pagemask;
1057
1058         /* Mask to get column */
1059         col = from & (mtd->oobsize - 1);
1060
1061         while(1) {
1062                 int bytes = min((int)(mtd->oobsize - col), readlen);
1063
1064                 if (likely(sndcmd)) {
1065                         chip->cmdfunc(mtd, NAND_CMD_READOOB, col, page);
1066                         sndcmd = 0;
1067                 }
1068
1069                 chip->read_buf(mtd, buf, bytes);
1070
1071                 readlen -= bytes;
1072                 if (!readlen)
1073                         break;
1074
1075                 if (!(chip->options & NAND_NO_READRDY)) {
1076                         /*
1077                          * Apply delay or wait for ready/busy pin. Do this
1078                          * before the AUTOINCR check, so no problems arise if a
1079                          * chip which does auto increment is marked as
1080                          * NOAUTOINCR by the board driver.
1081                          */
1082                         if (!chip->dev_ready)
1083                                 udelay(chip->chip_delay);
1084                         else
1085                                 nand_wait_ready(mtd);
1086                 }
1087
1088                 buf += bytes;
1089                 bytes = mtd->oobsize;
1090                 col = 0;
1091
1092                 /* Increment page address */
1093                 realpage++;
1094
1095                 page = realpage & chip->pagemask;
1096                 /* Check, if we cross a chip boundary */
1097                 if (!page) {
1098                         chipnr++;
1099                         chip->select_chip(mtd, -1);
1100                         chip->select_chip(mtd, chipnr);
1101                 }
1102
1103                 /* Check, if the chip supports auto page increment
1104                  * or if we have hit a block boundary.
1105                  */
1106                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1107                         sndcmd = 1;
1108         }
1109
1110         /* Deselect and wake up anyone waiting on the device */
1111         nand_release_device(mtd);
1112
1113         *retlen = len;
1114         return 0;
1115 }
1116
1117 /**
1118  * nand_read_raw - [GENERIC] Read raw data including oob into buffer
1119  * @mtd:        MTD device structure
1120  * @buf:        temporary buffer
1121  * @from:       offset to read from
1122  * @len:        number of bytes to read
1123  * @ooblen:     number of oob data bytes to read
1124  *
1125  * Read raw data including oob into buffer
1126  */
1127 int nand_read_raw(struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len,
1128                   size_t ooblen)
1129 {
1130         struct nand_chip *chip = mtd->priv;
1131         int page = (int)(from >> chip->page_shift);
1132         int chipnr = (int)(from >> chip->chip_shift);
1133         int sndcmd = 1;
1134         int cnt = 0;
1135         int pagesize = mtd->writesize + mtd->oobsize;
1136         int blockcheck;
1137
1138         /* Do not allow reads past end of device */
1139         if ((from + len) > mtd->size) {
1140                 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_raw: "
1141                       "Attempt read beyond end of device\n");
1142                 return -EINVAL;
1143         }
1144
1145         /* Grab the lock and see if the device is available */
1146         nand_get_device(chip, mtd, FL_READING);
1147
1148         chip->select_chip(mtd, chipnr);
1149
1150         /* Add requested oob length */
1151         len += ooblen;
1152         blockcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1153
1154         while (len) {
1155                 if (likely(sndcmd)) {
1156                         chip->cmdfunc(mtd, NAND_CMD_READ0, 0,
1157                                       page & chip->pagemask);
1158                         sndcmd = 0;
1159                 }
1160
1161                 chip->read_buf(mtd, &buf[cnt], pagesize);
1162
1163                 len -= pagesize;
1164                 cnt += pagesize;
1165                 page++;
1166
1167                 if (!(chip->options & NAND_NO_READRDY)) {
1168                         if (!chip->dev_ready)
1169                                 udelay(chip->chip_delay);
1170                         else
1171                                 nand_wait_ready(mtd);
1172                 }
1173
1174                 /*
1175                  * Check, if the chip supports auto page increment or if we
1176                  * cross a block boundary.
1177                  */
1178                 if (!NAND_CANAUTOINCR(chip) || !(page & blockcheck))
1179                         sndcmd = 1;
1180         }
1181
1182         /* Deselect and wake up anyone waiting on the device */
1183         nand_release_device(mtd);
1184         return 0;
1185 }
1186
1187 /**
1188  * nand_write_page_swecc - {REPLACABLE] software ecc based page write function
1189  * @mtd:        mtd info structure
1190  * @chip:       nand chip info structure
1191  * @buf:        data buffer
1192  */
1193 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1194                                   const uint8_t *buf)
1195 {
1196         int i, eccsize = chip->ecc.size;
1197         int eccbytes = chip->ecc.bytes;
1198         int eccsteps = chip->ecc.steps;
1199         uint8_t *ecc_calc = chip->buffers.ecccalc;
1200         const uint8_t *p = buf;
1201         int *eccpos = chip->autooob->eccpos;
1202
1203         if (chip->ecc.mode != NAND_ECC_NONE) {
1204                 /* Software ecc calculation */
1205                 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1206                         chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1207
1208                 for (i = 0; i < chip->ecc.total; i++)
1209                         chip->oob_poi[eccpos[i]] = ecc_calc[i];
1210         }
1211
1212         chip->write_buf(mtd, buf, mtd->writesize);
1213         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1214 }
1215
1216 /**
1217  * nand_write_page_hwecc - {REPLACABLE] hardware ecc based page write function
1218  * @mtd:        mtd info structure
1219  * @chip:       nand chip info structure
1220  * @buf:        data buffer
1221  */
1222 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1223                                   const uint8_t *buf)
1224 {
1225         int i, eccsize = chip->ecc.size;
1226         int eccbytes = chip->ecc.bytes;
1227         int eccsteps = chip->ecc.steps;
1228         uint8_t *ecc_calc = chip->buffers.ecccalc;
1229         const uint8_t *p = buf;
1230         int *eccpos = chip->autooob->eccpos;
1231
1232         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1233                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1234                 chip->write_buf(mtd, p, eccsize);
1235                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1236         }
1237
1238         for (i = 0; i < chip->ecc.total; i++)
1239                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1240
1241         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1242 }
1243
1244 /**
1245  * nand_write_page_syndrome - {REPLACABLE] hardware ecc syndrom based page write
1246  * @mtd:        mtd info structure
1247  * @chip:       nand chip info structure
1248  * @buf:        data buffer
1249  *
1250  * The hw generator calculates the error syndrome automatically. Therefor
1251  * we need a special oob layout and handling.
1252  */
1253 static void nand_write_page_syndrome(struct mtd_info *mtd,
1254                                     struct nand_chip *chip, const uint8_t *buf)
1255 {
1256         int i, eccsize = chip->ecc.size;
1257         int eccbytes = chip->ecc.bytes;
1258         int eccsteps = chip->ecc.steps;
1259         const uint8_t *p = buf;
1260         uint8_t *oob = chip->oob_poi;
1261
1262         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1263
1264                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1265                 chip->write_buf(mtd, p, eccsize);
1266
1267                 if (chip->ecc.prepad) {
1268                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1269                         oob += chip->ecc.prepad;
1270                 }
1271
1272                 chip->ecc.calculate(mtd, p, oob);
1273                 chip->write_buf(mtd, oob, eccbytes);
1274                 oob += eccbytes;
1275
1276                 if (chip->ecc.postpad) {
1277                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1278                         oob += chip->ecc.postpad;
1279                 }
1280         }
1281
1282         /* Calculate remaining oob bytes */
1283         i = oob - chip->oob_poi;
1284         if (i)
1285                 chip->write_buf(mtd, oob, i);
1286 }
1287
1288 /**
1289  * nand_write_page - [INTERNAL] write one page
1290  * @mtd:        MTD device structure
1291  * @chip:       NAND chip descriptor
1292  * @buf:        the data to write
1293  * @page:       page number to write
1294  * @cached:     cached programming
1295  */
1296 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1297                            const uint8_t *buf, int page, int cached)
1298 {
1299         int status;
1300
1301         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1302
1303         chip->ecc.write_page(mtd, chip, buf);
1304
1305         /*
1306          * Cached progamming disabled for now, Not sure if its worth the
1307          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1308          */
1309         cached = 0;
1310
1311         if (!cached || !(chip->options & NAND_CACHEPRG)) {
1312
1313                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1314                 status = chip->waitfunc(mtd, chip, FL_WRITING);
1315                 /*
1316                  * See if operation failed and additional status checks are
1317                  * available
1318                  */
1319                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1320                         status = chip->errstat(mtd, chip, FL_WRITING, status,
1321                                                page);
1322
1323                 if (status & NAND_STATUS_FAIL)
1324                         return -EIO;
1325         } else {
1326                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1327                 status = chip->waitfunc(mtd, chip, FL_WRITING);
1328         }
1329
1330 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1331         /* Send command to read back the data */
1332         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1333
1334         if (chip->verify_buf(mtd, buf, mtd->writesize))
1335                 return -EIO;
1336 #endif
1337         return 0;
1338 }
1339
1340 #define NOTALIGNED(x) (x & (mtd->writesize-1)) != 0
1341
1342 /**
1343  * nand_write - [MTD Interface] NAND write with ECC
1344  * @mtd:        MTD device structure
1345  * @to:         offset to write to
1346  * @len:        number of bytes to write
1347  * @retlen:     pointer to variable to store the number of written bytes
1348  * @buf:        the data to write
1349  *
1350  * NAND write with ECC
1351  */
1352 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1353                           size_t *retlen, const uint8_t *buf)
1354 {
1355         int chipnr, realpage, page, blockmask;
1356         struct nand_chip *chip = mtd->priv;
1357         uint32_t writelen = len;
1358         int bytes = mtd->writesize;
1359         int ret = -EIO;
1360
1361         *retlen = 0;
1362
1363         /* Do not allow write past end of device */
1364         if ((to + len) > mtd->size) {
1365                 DEBUG(MTD_DEBUG_LEVEL0, "nand_write: "
1366                       "Attempt to write past end of page\n");
1367                 return -EINVAL;
1368         }
1369
1370         /* reject writes, which are not page aligned */
1371         if (NOTALIGNED(to) || NOTALIGNED(len)) {
1372                 printk(KERN_NOTICE "nand_write: "
1373                        "Attempt to write not page aligned data\n");
1374                 return -EINVAL;
1375         }
1376
1377         if (!len)
1378                 return 0;
1379
1380         nand_get_device(chip, mtd, FL_WRITING);
1381
1382         /* Check, if it is write protected */
1383         if (nand_check_wp(mtd))
1384                 goto out;
1385
1386         chipnr = (int)(to >> chip->chip_shift);
1387         chip->select_chip(mtd, chipnr);
1388
1389         realpage = (int)(to >> chip->page_shift);
1390         page = realpage & chip->pagemask;
1391         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1392
1393         /* Invalidate the page cache, when we write to the cached page */
1394         if (to <= (chip->pagebuf << chip->page_shift) &&
1395             (chip->pagebuf << chip->page_shift) < (to + len))
1396                 chip->pagebuf = -1;
1397
1398         chip->oob_poi = chip->buffers.oobwbuf;
1399
1400         while(1) {
1401                 int cached = writelen > bytes && page != blockmask;
1402
1403                 ret = nand_write_page(mtd, chip, buf, page, cached);
1404                 if (ret)
1405                         break;
1406
1407                 writelen -= bytes;
1408                 if (!writelen)
1409                         break;
1410
1411                 buf += bytes;
1412                 realpage++;
1413
1414                 page = realpage & chip->pagemask;
1415                 /* Check, if we cross a chip boundary */
1416                 if (!page) {
1417                         chipnr++;
1418                         chip->select_chip(mtd, -1);
1419                         chip->select_chip(mtd, chipnr);
1420                 }
1421         }
1422  out:
1423         *retlen = len - writelen;
1424         nand_release_device(mtd);
1425         return ret;
1426 }
1427
1428 /**
1429  * nand_write_raw - [GENERIC] Write raw data including oob
1430  * @mtd:        MTD device structure
1431  * @buf:        source buffer
1432  * @to:         offset to write to
1433  * @len:        number of bytes to write
1434  * @buf:        source buffer
1435  * @oob:        oob buffer
1436  *
1437  * Write raw data including oob
1438  */
1439 int nand_write_raw(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
1440                    const uint8_t *buf, uint8_t *oob)
1441 {
1442         struct nand_chip *chip = mtd->priv;
1443         int page = (int)(to >> chip->page_shift);
1444         int chipnr = (int)(to >> chip->chip_shift);
1445         int ret;
1446
1447         *retlen = 0;
1448
1449         /* Do not allow writes past end of device */
1450         if ((to + len) > mtd->size) {
1451                 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_raw: Attempt write "
1452                       "beyond end of device\n");
1453                 return -EINVAL;
1454         }
1455
1456         /* Grab the lock and see if the device is available */
1457         nand_get_device(chip, mtd, FL_WRITING);
1458
1459         chip->select_chip(mtd, chipnr);
1460         chip->oob_poi = oob;
1461
1462         while (len != *retlen) {
1463                 ret = nand_write_page(mtd, chip, buf, page, 0);
1464                 if (ret)
1465                         return ret;
1466                 page++;
1467                 *retlen += mtd->writesize;
1468                 buf += mtd->writesize;
1469                 chip->oob_poi += mtd->oobsize;
1470         }
1471
1472         /* Deselect and wake up anyone waiting on the device */
1473         nand_release_device(mtd);
1474         return 0;
1475 }
1476 EXPORT_SYMBOL_GPL(nand_write_raw);
1477
1478 /**
1479  * nand_write_oob - [MTD Interface] NAND write out-of-band
1480  * @mtd:        MTD device structure
1481  * @to:         offset to write to
1482  * @len:        number of bytes to write
1483  * @retlen:     pointer to variable to store the number of written bytes
1484  * @buf:        the data to write
1485  *
1486  * NAND write out-of-band
1487  */
1488 static int nand_write_oob(struct mtd_info *mtd, loff_t to, size_t len,
1489                           size_t *retlen, const uint8_t *buf)
1490 {
1491         int column, page, status, ret = -EIO, chipnr;
1492         struct nand_chip *chip = mtd->priv;
1493
1494         DEBUG(MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1495               (unsigned int)to, (int)len);
1496
1497         /* Initialize return length value */
1498         *retlen = 0;
1499
1500         /* Do not allow write past end of page */
1501         column = to & (mtd->oobsize - 1);
1502         if ((column + len) > mtd->oobsize) {
1503                 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
1504                       "Attempt to write past end of page\n");
1505                 return -EINVAL;
1506         }
1507
1508         nand_get_device(chip, mtd, FL_WRITING);
1509
1510         chipnr = (int)(to >> chip->chip_shift);
1511         chip->select_chip(mtd, chipnr);
1512
1513         /* Shift to get page */
1514         page = (int)(to >> chip->page_shift);
1515
1516         /*
1517          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
1518          * of my DiskOnChip 2000 test units) will clear the whole data page too
1519          * if we don't do this. I have no clue why, but I seem to have 'fixed'
1520          * it in the doc2000 driver in August 1999.  dwmw2.
1521          */
1522         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1523
1524         /* Check, if it is write protected */
1525         if (nand_check_wp(mtd))
1526                 goto out;
1527
1528         /* Invalidate the page cache, if we write to the cached page */
1529         if (page == chip->pagebuf)
1530                 chip->pagebuf = -1;
1531
1532         if (NAND_MUST_PAD(chip)) {
1533                 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize,
1534                               page & chip->pagemask);
1535                 /* prepad 0xff for partial programming */
1536                 chip->write_buf(mtd, ffchars, column);
1537                 /* write data */
1538                 chip->write_buf(mtd, buf, len);
1539                 /* postpad 0xff for partial programming */
1540                 chip->write_buf(mtd, ffchars, mtd->oobsize - (len + column));
1541         } else {
1542                 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize + column,
1543                               page & chip->pagemask);
1544                 chip->write_buf(mtd, buf, len);
1545         }
1546         /* Send command to program the OOB data */
1547         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1548
1549         status = chip->waitfunc(mtd, chip, FL_WRITING);
1550
1551         /* See if device thinks it succeeded */
1552         if (status & NAND_STATUS_FAIL) {
1553                 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
1554                       "Failed write, page 0x%08x\n", page);
1555                 ret = -EIO;
1556                 goto out;
1557         }
1558         *retlen = len;
1559
1560 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1561         /* Send command to read back the data */
1562         chip->cmdfunc(mtd, NAND_CMD_READOOB, column, page & chip->pagemask);
1563
1564         if (chip->verify_buf(mtd, buf, len)) {
1565                 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
1566                       "Failed write verify, page 0x%08x\n", page);
1567                 ret = -EIO;
1568                 goto out;
1569         }
1570 #endif
1571         ret = 0;
1572  out:
1573         /* Deselect and wake up anyone waiting on the device */
1574         nand_release_device(mtd);
1575
1576         return ret;
1577 }
1578
1579 /**
1580  * single_erease_cmd - [GENERIC] NAND standard block erase command function
1581  * @mtd:        MTD device structure
1582  * @page:       the page address of the block which will be erased
1583  *
1584  * Standard erase command for NAND chips
1585  */
1586 static void single_erase_cmd(struct mtd_info *mtd, int page)
1587 {
1588         struct nand_chip *chip = mtd->priv;
1589         /* Send commands to erase a block */
1590         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
1591         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1592 }
1593
1594 /**
1595  * multi_erease_cmd - [GENERIC] AND specific block erase command function
1596  * @mtd:        MTD device structure
1597  * @page:       the page address of the block which will be erased
1598  *
1599  * AND multi block erase command function
1600  * Erase 4 consecutive blocks
1601  */
1602 static void multi_erase_cmd(struct mtd_info *mtd, int page)
1603 {
1604         struct nand_chip *chip = mtd->priv;
1605         /* Send commands to erase a block */
1606         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1607         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1608         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1609         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
1610         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1611 }
1612
1613 /**
1614  * nand_erase - [MTD Interface] erase block(s)
1615  * @mtd:        MTD device structure
1616  * @instr:      erase instruction
1617  *
1618  * Erase one ore more blocks
1619  */
1620 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1621 {
1622         return nand_erase_nand(mtd, instr, 0);
1623 }
1624
1625 #define BBT_PAGE_MASK   0xffffff3f
1626 /**
1627  * nand_erase_nand - [Internal] erase block(s)
1628  * @mtd:        MTD device structure
1629  * @instr:      erase instruction
1630  * @allowbbt:   allow erasing the bbt area
1631  *
1632  * Erase one ore more blocks
1633  */
1634 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1635                     int allowbbt)
1636 {
1637         int page, len, status, pages_per_block, ret, chipnr;
1638         struct nand_chip *chip = mtd->priv;
1639         int rewrite_bbt[NAND_MAX_CHIPS]={0};
1640         unsigned int bbt_masked_page = 0xffffffff;
1641
1642         DEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
1643               (unsigned int)instr->addr, (unsigned int)instr->len);
1644
1645         /* Start address must align on block boundary */
1646         if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
1647                 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
1648                 return -EINVAL;
1649         }
1650
1651         /* Length must align on block boundary */
1652         if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
1653                 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1654                       "Length not block aligned\n");
1655                 return -EINVAL;
1656         }
1657
1658         /* Do not allow erase past end of device */
1659         if ((instr->len + instr->addr) > mtd->size) {
1660                 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1661                       "Erase past end of device\n");
1662                 return -EINVAL;
1663         }
1664
1665         instr->fail_addr = 0xffffffff;
1666
1667         /* Grab the lock and see if the device is available */
1668         nand_get_device(chip, mtd, FL_ERASING);
1669
1670         /* Shift to get first page */
1671         page = (int)(instr->addr >> chip->page_shift);
1672         chipnr = (int)(instr->addr >> chip->chip_shift);
1673
1674         /* Calculate pages in each block */
1675         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1676
1677         /* Select the NAND device */
1678         chip->select_chip(mtd, chipnr);
1679
1680         /* Check, if it is write protected */
1681         if (nand_check_wp(mtd)) {
1682                 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1683                       "Device is write protected!!!\n");
1684                 instr->state = MTD_ERASE_FAILED;
1685                 goto erase_exit;
1686         }
1687
1688         /*
1689          * If BBT requires refresh, set the BBT page mask to see if the BBT
1690          * should be rewritten. Otherwise the mask is set to 0xffffffff which
1691          * can not be matched. This is also done when the bbt is actually
1692          * erased to avoid recusrsive updates
1693          */
1694         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
1695                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
1696
1697         /* Loop through the pages */
1698         len = instr->len;
1699
1700         instr->state = MTD_ERASING;
1701
1702         while (len) {
1703                 /*
1704                  * heck if we have a bad block, we do not erase bad blocks !
1705                  */
1706                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
1707                                         chip->page_shift, 0, allowbbt)) {
1708                         printk(KERN_WARNING "nand_erase: attempt to erase a "
1709                                "bad block at page 0x%08x\n", page);
1710                         instr->state = MTD_ERASE_FAILED;
1711                         goto erase_exit;
1712                 }
1713
1714                 /*
1715                  * Invalidate the page cache, if we erase the block which
1716                  * contains the current cached page
1717                  */
1718                 if (page <= chip->pagebuf && chip->pagebuf <
1719                     (page + pages_per_block))
1720                         chip->pagebuf = -1;
1721
1722                 chip->erase_cmd(mtd, page & chip->pagemask);
1723
1724                 status = chip->waitfunc(mtd, chip, FL_ERASING);
1725
1726                 /*
1727                  * See if operation failed and additional status checks are
1728                  * available
1729                  */
1730                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1731                         status = chip->errstat(mtd, chip, FL_ERASING,
1732                                                status, page);
1733
1734                 /* See if block erase succeeded */
1735                 if (status & NAND_STATUS_FAIL) {
1736                         DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1737                               "Failed erase, page 0x%08x\n", page);
1738                         instr->state = MTD_ERASE_FAILED;
1739                         instr->fail_addr = (page << chip->page_shift);
1740                         goto erase_exit;
1741                 }
1742
1743                 /*
1744                  * If BBT requires refresh, set the BBT rewrite flag to the
1745                  * page being erased
1746                  */
1747                 if (bbt_masked_page != 0xffffffff &&
1748                     (page & BBT_PAGE_MASK) == bbt_masked_page)
1749                             rewrite_bbt[chipnr] = (page << chip->page_shift);
1750
1751                 /* Increment page address and decrement length */
1752                 len -= (1 << chip->phys_erase_shift);
1753                 page += pages_per_block;
1754
1755                 /* Check, if we cross a chip boundary */
1756                 if (len && !(page & chip->pagemask)) {
1757                         chipnr++;
1758                         chip->select_chip(mtd, -1);
1759                         chip->select_chip(mtd, chipnr);
1760
1761                         /*
1762                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
1763                          * page mask to see if this BBT should be rewritten
1764                          */
1765                         if (bbt_masked_page != 0xffffffff &&
1766                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
1767                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
1768                                         BBT_PAGE_MASK;
1769                 }
1770         }
1771         instr->state = MTD_ERASE_DONE;
1772
1773  erase_exit:
1774
1775         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1776         /* Do call back function */
1777         if (!ret)
1778                 mtd_erase_callback(instr);
1779
1780         /* Deselect and wake up anyone waiting on the device */
1781         nand_release_device(mtd);
1782
1783         /*
1784          * If BBT requires refresh and erase was successful, rewrite any
1785          * selected bad block tables
1786          */
1787         if (bbt_masked_page == 0xffffffff || ret)
1788                 return ret;
1789
1790         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
1791                 if (!rewrite_bbt[chipnr])
1792                         continue;
1793                 /* update the BBT for chip */
1794                 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
1795                       "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
1796                       chip->bbt_td->pages[chipnr]);
1797                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
1798         }
1799
1800         /* Return more or less happy */
1801         return ret;
1802 }
1803
1804 /**
1805  * nand_sync - [MTD Interface] sync
1806  * @mtd:        MTD device structure
1807  *
1808  * Sync is actually a wait for chip ready function
1809  */
1810 static void nand_sync(struct mtd_info *mtd)
1811 {
1812         struct nand_chip *chip = mtd->priv;
1813
1814         DEBUG(MTD_DEBUG_LEVEL3, "nand_sync: called\n");
1815
1816         /* Grab the lock and see if the device is available */
1817         nand_get_device(chip, mtd, FL_SYNCING);
1818         /* Release it and go back */
1819         nand_release_device(mtd);
1820 }
1821
1822 /**
1823  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
1824  * @mtd:        MTD device structure
1825  * @ofs:        offset relative to mtd start
1826  */
1827 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1828 {
1829         /* Check for invalid offset */
1830         if (offs > mtd->size)
1831                 return -EINVAL;
1832
1833         return nand_block_checkbad(mtd, offs, 1, 0);
1834 }
1835
1836 /**
1837  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
1838  * @mtd:        MTD device structure
1839  * @ofs:        offset relative to mtd start
1840  */
1841 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1842 {
1843         struct nand_chip *chip = mtd->priv;
1844         int ret;
1845
1846         if ((ret = nand_block_isbad(mtd, ofs))) {
1847                 /* If it was bad already, return success and do nothing. */
1848                 if (ret > 0)
1849                         return 0;
1850                 return ret;
1851         }
1852
1853         return chip->block_markbad(mtd, ofs);
1854 }
1855
1856 /**
1857  * nand_suspend - [MTD Interface] Suspend the NAND flash
1858  * @mtd:        MTD device structure
1859  */
1860 static int nand_suspend(struct mtd_info *mtd)
1861 {
1862         struct nand_chip *chip = mtd->priv;
1863
1864         return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
1865 }
1866
1867 /**
1868  * nand_resume - [MTD Interface] Resume the NAND flash
1869  * @mtd:        MTD device structure
1870  */
1871 static void nand_resume(struct mtd_info *mtd)
1872 {
1873         struct nand_chip *chip = mtd->priv;
1874
1875         if (chip->state == FL_PM_SUSPENDED)
1876                 nand_release_device(mtd);
1877         else
1878                 printk(KERN_ERR "nand_resume() called for a chip which is not "
1879                        "in suspended state\n");
1880 }
1881
1882 /*
1883  * Set default functions
1884  */
1885 static void nand_set_defaults(struct nand_chip *chip, int busw)
1886 {
1887         /* check for proper chip_delay setup, set 20us if not */
1888         if (!chip->chip_delay)
1889                 chip->chip_delay = 20;
1890
1891         /* check, if a user supplied command function given */
1892         if (chip->cmdfunc == NULL)
1893                 chip->cmdfunc = nand_command;
1894
1895         /* check, if a user supplied wait function given */
1896         if (chip->waitfunc == NULL)
1897                 chip->waitfunc = nand_wait;
1898
1899         if (!chip->select_chip)
1900                 chip->select_chip = nand_select_chip;
1901         if (!chip->read_byte)
1902                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
1903         if (!chip->read_word)
1904                 chip->read_word = nand_read_word;
1905         if (!chip->block_bad)
1906                 chip->block_bad = nand_block_bad;
1907         if (!chip->block_markbad)
1908                 chip->block_markbad = nand_default_block_markbad;
1909         if (!chip->write_buf)
1910                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
1911         if (!chip->read_buf)
1912                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
1913         if (!chip->verify_buf)
1914                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
1915         if (!chip->scan_bbt)
1916                 chip->scan_bbt = nand_default_bbt;
1917
1918         if (!chip->controller) {
1919                 chip->controller = &chip->hwcontrol;
1920                 spin_lock_init(&chip->controller->lock);
1921                 init_waitqueue_head(&chip->controller->wq);
1922         }
1923
1924 }
1925
1926 /*
1927  * Get the flash and manufacturer id and lookup if the type is supported
1928  */
1929 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
1930                                                   struct nand_chip *chip,
1931                                                   int busw, int *maf_id)
1932 {
1933         struct nand_flash_dev *type = NULL;
1934         int i, dev_id, maf_idx;
1935
1936         /* Select the device */
1937         chip->select_chip(mtd, 0);
1938
1939         /* Send the command for reading device ID */
1940         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1941
1942         /* Read manufacturer and device IDs */
1943         *maf_id = chip->read_byte(mtd);
1944         dev_id = chip->read_byte(mtd);
1945
1946         /* Lookup the flash id */
1947         for (i = 0; nand_flash_ids[i].name != NULL; i++) {
1948                 if (dev_id == nand_flash_ids[i].id) {
1949                         type =  &nand_flash_ids[i];
1950                         break;
1951                 }
1952         }
1953
1954         if (!type)
1955                 return ERR_PTR(-ENODEV);
1956
1957         chip->chipsize = nand_flash_ids[i].chipsize << 20;
1958
1959         /* Newer devices have all the information in additional id bytes */
1960         if (!nand_flash_ids[i].pagesize) {
1961                 int extid;
1962                 /* The 3rd id byte contains non relevant data ATM */
1963                 extid = chip->read_byte(mtd);
1964                 /* The 4th id byte is the important one */
1965                 extid = chip->read_byte(mtd);
1966                 /* Calc pagesize */
1967                 mtd->writesize = 1024 << (extid & 0x3);
1968                 extid >>= 2;
1969                 /* Calc oobsize */
1970                 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
1971                 extid >>= 2;
1972                 /* Calc blocksize. Blocksize is multiples of 64KiB */
1973                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
1974                 extid >>= 2;
1975                 /* Get buswidth information */
1976                 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
1977
1978         } else {
1979                 /*
1980                  * Old devices have chip data hardcoded in the device id table
1981                  */
1982                 mtd->erasesize = nand_flash_ids[i].erasesize;
1983                 mtd->writesize = nand_flash_ids[i].pagesize;
1984                 mtd->oobsize = mtd->writesize / 32;
1985                 busw = nand_flash_ids[i].options & NAND_BUSWIDTH_16;
1986         }
1987
1988         /* Try to identify manufacturer */
1989         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_id++) {
1990                 if (nand_manuf_ids[maf_idx].id == *maf_id)
1991                         break;
1992         }
1993
1994         /*
1995          * Check, if buswidth is correct. Hardware drivers should set
1996          * chip correct !
1997          */
1998         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
1999                 printk(KERN_INFO "NAND device: Manufacturer ID:"
2000                        " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2001                        dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2002                 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2003                        (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2004                        busw ? 16 : 8);
2005                 return ERR_PTR(-EINVAL);
2006         }
2007
2008         /* Calculate the address shift from the page size */
2009         chip->page_shift = ffs(mtd->writesize) - 1;
2010         /* Convert chipsize to number of pages per chip -1. */
2011         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2012
2013         chip->bbt_erase_shift = chip->phys_erase_shift =
2014                 ffs(mtd->erasesize) - 1;
2015         chip->chip_shift = ffs(chip->chipsize) - 1;
2016
2017         /* Set the bad block position */
2018         chip->badblockpos = mtd->writesize > 512 ?
2019                 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2020
2021         /* Get chip options, preserve non chip based options */
2022         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2023         chip->options |= nand_flash_ids[i].options & NAND_CHIPOPTIONS_MSK;
2024
2025         /*
2026          * Set chip as a default. Board drivers can override it, if necessary
2027          */
2028         chip->options |= NAND_NO_AUTOINCR;
2029
2030         /* Check if chip is a not a samsung device. Do not clear the
2031          * options for chips which are not having an extended id.
2032          */
2033         if (*maf_id != NAND_MFR_SAMSUNG && !nand_flash_ids[i].pagesize)
2034                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2035
2036         /* Check for AND chips with 4 page planes */
2037         if (chip->options & NAND_4PAGE_ARRAY)
2038                 chip->erase_cmd = multi_erase_cmd;
2039         else
2040                 chip->erase_cmd = single_erase_cmd;
2041
2042         /* Do not replace user supplied command function ! */
2043         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2044                 chip->cmdfunc = nand_command_lp;
2045
2046         printk(KERN_INFO "NAND device: Manufacturer ID:"
2047                " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2048                nand_manuf_ids[maf_idx].name, type->name);
2049
2050         return type;
2051 }
2052
2053 /* module_text_address() isn't exported, and it's mostly a pointless
2054    test if this is a module _anyway_ -- they'd have to try _really_ hard
2055    to call us from in-kernel code if the core NAND support is modular. */
2056 #ifdef MODULE
2057 #define caller_is_module() (1)
2058 #else
2059 #define caller_is_module() \
2060         module_text_address((unsigned long)__builtin_return_address(0))
2061 #endif
2062
2063 /**
2064  * nand_scan - [NAND Interface] Scan for the NAND device
2065  * @mtd:        MTD device structure
2066  * @maxchips:   Number of chips to scan for
2067  *
2068  * This fills out all the uninitialized function pointers
2069  * with the defaults.
2070  * The flash ID is read and the mtd/chip structures are
2071  * filled with the appropriate values.
2072  * The mtd->owner field must be set to the module of the caller
2073  *
2074  */
2075 int nand_scan(struct mtd_info *mtd, int maxchips)
2076 {
2077         int i, busw, nand_maf_id;
2078         struct nand_chip *chip = mtd->priv;
2079         struct nand_flash_dev *type;
2080
2081         /* Many callers got this wrong, so check for it for a while... */
2082         if (!mtd->owner && caller_is_module()) {
2083                 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2084                 BUG();
2085         }
2086
2087         /* Get buswidth to select the correct functions */
2088         busw = chip->options & NAND_BUSWIDTH_16;
2089         /* Set the default functions */
2090         nand_set_defaults(chip, busw);
2091
2092         /* Read the flash type */
2093         type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2094
2095         if (IS_ERR(type)) {
2096                 printk(KERN_WARNING "No NAND device found!!!\n");
2097                 chip->select_chip(mtd, -1);
2098                 return PTR_ERR(type);
2099         }
2100
2101         /* Check for a chip array */
2102         for (i = 1; i < maxchips; i++) {
2103                 chip->select_chip(mtd, i);
2104                 /* Send the command for reading device ID */
2105                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2106                 /* Read manufacturer and device IDs */
2107                 if (nand_maf_id != chip->read_byte(mtd) ||
2108                     type->id != chip->read_byte(mtd))
2109                         break;
2110         }
2111         if (i > 1)
2112                 printk(KERN_INFO "%d NAND chips detected\n", i);
2113
2114         /* Store the number of chips and calc total size for mtd */
2115         chip->numchips = i;
2116         mtd->size = i * chip->chipsize;
2117
2118         /* Preset the internal oob write buffer */
2119         memset(chip->buffers.oobwbuf, 0xff, mtd->oobsize);
2120
2121         /*
2122          * If no default placement scheme is given, select an appropriate one
2123          */
2124         if (!chip->autooob) {
2125                 switch (mtd->oobsize) {
2126                 case 8:
2127                         chip->autooob = &nand_oob_8;
2128                         break;
2129                 case 16:
2130                         chip->autooob = &nand_oob_16;
2131                         break;
2132                 case 64:
2133                         chip->autooob = &nand_oob_64;
2134                         break;
2135                 default:
2136                         printk(KERN_WARNING "No oob scheme defined for "
2137                                "oobsize %d\n", mtd->oobsize);
2138                         BUG();
2139                 }
2140         }
2141
2142         /*
2143          * The number of bytes available for the filesystem to place fs
2144          * dependend oob data
2145          */
2146         mtd->oobavail = 0;
2147         for (i = 0; chip->autooob->oobfree[i][1]; i++)
2148                 mtd->oobavail += chip->autooob->oobfree[i][1];
2149
2150         /*
2151          * check ECC mode, default to software if 3byte/512byte hardware ECC is
2152          * selected and we have 256 byte pagesize fallback to software ECC
2153          */
2154         switch (chip->ecc.mode) {
2155         case NAND_ECC_HW:
2156                 /* Use standard hwecc read page function ? */
2157                 if (!chip->ecc.read_page)
2158                         chip->ecc.read_page = nand_read_page_hwecc;
2159                 if (!chip->ecc.write_page)
2160                         chip->ecc.write_page = nand_write_page_hwecc;
2161
2162         case NAND_ECC_HW_SYNDROME:
2163                 if (!chip->ecc.calculate || !chip->ecc.correct ||
2164                     !chip->ecc.hwctl) {
2165                         printk(KERN_WARNING "No ECC functions supplied, "
2166                                "Hardware ECC not possible\n");
2167                         BUG();
2168                 }
2169                 /* Use standard syndrome read/write page function ? */
2170                 if (!chip->ecc.read_page)
2171                         chip->ecc.read_page = nand_read_page_syndrome;
2172                 if (!chip->ecc.write_page)
2173                         chip->ecc.write_page = nand_write_page_syndrome;
2174
2175                 if (mtd->writesize >= chip->ecc.size)
2176                         break;
2177                 printk(KERN_WARNING "%d byte HW ECC not possible on "
2178                        "%d byte page size, fallback to SW ECC\n",
2179                        chip->ecc.size, mtd->writesize);
2180                 chip->ecc.mode = NAND_ECC_SOFT;
2181
2182         case NAND_ECC_SOFT:
2183                 chip->ecc.calculate = nand_calculate_ecc;
2184                 chip->ecc.correct = nand_correct_data;
2185                 chip->ecc.read_page = nand_read_page_swecc;
2186                 chip->ecc.write_page = nand_write_page_swecc;
2187                 chip->ecc.size = 256;
2188                 chip->ecc.bytes = 3;
2189                 break;
2190
2191         case NAND_ECC_NONE:
2192                 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2193                        "This is not recommended !!\n");
2194                 chip->ecc.read_page = nand_read_page_swecc;
2195                 chip->ecc.write_page = nand_write_page_swecc;
2196                 chip->ecc.size = mtd->writesize;
2197                 chip->ecc.bytes = 0;
2198                 break;
2199         default:
2200                 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2201                        chip->ecc.mode);
2202                 BUG();
2203         }
2204
2205         /*
2206          * Set the number of read / write steps for one page depending on ECC
2207          * mode
2208          */
2209         chip->ecc.steps = mtd->writesize / chip->ecc.size;
2210         if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2211                 printk(KERN_WARNING "Invalid ecc parameters\n");
2212                 BUG();
2213         }
2214         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2215
2216         /* Initialize state */
2217         chip->state = FL_READY;
2218
2219         /* De-select the device */
2220         chip->select_chip(mtd, -1);
2221
2222         /* Invalidate the pagebuffer reference */
2223         chip->pagebuf = -1;
2224
2225         /* Fill in remaining MTD driver data */
2226         mtd->type = MTD_NANDFLASH;
2227         mtd->flags = MTD_CAP_NANDFLASH;
2228         mtd->ecctype = MTD_ECC_SW;
2229         mtd->erase = nand_erase;
2230         mtd->point = NULL;
2231         mtd->unpoint = NULL;
2232         mtd->read = nand_read;
2233         mtd->write = nand_write;
2234         mtd->read_oob = nand_read_oob;
2235         mtd->write_oob = nand_write_oob;
2236         mtd->sync = nand_sync;
2237         mtd->lock = NULL;
2238         mtd->unlock = NULL;
2239         mtd->suspend = nand_suspend;
2240         mtd->resume = nand_resume;
2241         mtd->block_isbad = nand_block_isbad;
2242         mtd->block_markbad = nand_block_markbad;
2243
2244         /* and make the autooob the default one */
2245         memcpy(&mtd->oobinfo, chip->autooob, sizeof(mtd->oobinfo));
2246
2247         /* Check, if we should skip the bad block table scan */
2248         if (chip->options & NAND_SKIP_BBTSCAN)
2249                 return 0;
2250
2251         /* Build bad block table */
2252         return chip->scan_bbt(mtd);
2253 }
2254
2255 /**
2256  * nand_release - [NAND Interface] Free resources held by the NAND device
2257  * @mtd:        MTD device structure
2258 */
2259 void nand_release(struct mtd_info *mtd)
2260 {
2261         struct nand_chip *chip = mtd->priv;
2262
2263 #ifdef CONFIG_MTD_PARTITIONS
2264         /* Deregister partitions */
2265         del_mtd_partitions(mtd);
2266 #endif
2267         /* Deregister the device */
2268         del_mtd_device(mtd);
2269
2270         /* Free bad block table memory */
2271         kfree(chip->bbt);
2272 }
2273
2274 EXPORT_SYMBOL_GPL(nand_scan);
2275 EXPORT_SYMBOL_GPL(nand_release);
2276
2277 static int __init nand_base_init(void)
2278 {
2279         led_trigger_register_simple("nand-disk", &nand_led_trigger);
2280         return 0;
2281 }
2282
2283 static void __exit nand_base_exit(void)
2284 {
2285         led_trigger_unregister_simple(nand_led_trigger);
2286 }
2287
2288 module_init(nand_base_init);
2289 module_exit(nand_base_exit);
2290
2291 MODULE_LICENSE("GPL");
2292 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2293 MODULE_DESCRIPTION("Generic NAND flash driver code");