2 * drivers/mtd/nand/au1550nd.c
4 * Copyright (C) 2004 Embedded Edge, LLC
6 * $Id: au1550nd.c,v 1.13 2005/11/07 11:14:30 gleixner Exp $
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <linux/slab.h>
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/nand.h>
20 #include <linux/mtd/partitions.h>
21 #include <linux/version.h>
24 /* fixme: this is ugly */
25 #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 0)
26 #include <asm/mach-au1x00/au1xxx.h>
28 #include <asm/au1000.h>
29 #ifdef CONFIG_MIPS_PB1550
30 #include <asm/pb1550.h>
32 #ifdef CONFIG_MIPS_DB1550
33 #include <asm/db1x00.h>
38 * MTD structure for NAND controller
40 static struct mtd_info *au1550_mtd = NULL;
41 static void __iomem *p_nand;
42 static int nand_width = 1; /* default x8 */
43 static void (*au1550_write_byte)(struct mtd_info *, u_char);
46 * Define partitions for flash device
48 static const struct mtd_partition partition_info[] = {
52 .size = 8 * 1024 * 1024},
55 .offset = MTDPART_OFS_APPEND,
56 .size = MTDPART_SIZ_FULL}
60 * au_read_byte - read one byte from the chip
61 * @mtd: MTD device structure
63 * read function for 8bit buswith
65 static u_char au_read_byte(struct mtd_info *mtd)
67 struct nand_chip *this = mtd->priv;
68 u_char ret = readb(this->IO_ADDR_R);
74 * au_write_byte - write one byte to the chip
75 * @mtd: MTD device structure
76 * @byte: pointer to data byte to write
78 * write function for 8it buswith
80 static void au_write_byte(struct mtd_info *mtd, u_char byte)
82 struct nand_chip *this = mtd->priv;
83 writeb(byte, this->IO_ADDR_W);
88 * au_read_byte16 - read one byte endianess aware from the chip
89 * @mtd: MTD device structure
91 * read function for 16bit buswith with
92 * endianess conversion
94 static u_char au_read_byte16(struct mtd_info *mtd)
96 struct nand_chip *this = mtd->priv;
97 u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
103 * au_write_byte16 - write one byte endianess aware to the chip
104 * @mtd: MTD device structure
105 * @byte: pointer to data byte to write
107 * write function for 16bit buswith with
108 * endianess conversion
110 static void au_write_byte16(struct mtd_info *mtd, u_char byte)
112 struct nand_chip *this = mtd->priv;
113 writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
118 * au_read_word - read one word from the chip
119 * @mtd: MTD device structure
121 * read function for 16bit buswith without
122 * endianess conversion
124 static u16 au_read_word(struct mtd_info *mtd)
126 struct nand_chip *this = mtd->priv;
127 u16 ret = readw(this->IO_ADDR_R);
133 * au_write_buf - write buffer to chip
134 * @mtd: MTD device structure
136 * @len: number of bytes to write
138 * write function for 8bit buswith
140 static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
143 struct nand_chip *this = mtd->priv;
145 for (i = 0; i < len; i++) {
146 writeb(buf[i], this->IO_ADDR_W);
152 * au_read_buf - read chip data into buffer
153 * @mtd: MTD device structure
154 * @buf: buffer to store date
155 * @len: number of bytes to read
157 * read function for 8bit buswith
159 static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
162 struct nand_chip *this = mtd->priv;
164 for (i = 0; i < len; i++) {
165 buf[i] = readb(this->IO_ADDR_R);
171 * au_verify_buf - Verify chip data against buffer
172 * @mtd: MTD device structure
173 * @buf: buffer containing the data to compare
174 * @len: number of bytes to compare
176 * verify function for 8bit buswith
178 static int au_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
181 struct nand_chip *this = mtd->priv;
183 for (i = 0; i < len; i++) {
184 if (buf[i] != readb(this->IO_ADDR_R))
193 * au_write_buf16 - write buffer to chip
194 * @mtd: MTD device structure
196 * @len: number of bytes to write
198 * write function for 16bit buswith
200 static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
203 struct nand_chip *this = mtd->priv;
204 u16 *p = (u16 *) buf;
207 for (i = 0; i < len; i++) {
208 writew(p[i], this->IO_ADDR_W);
215 * au_read_buf16 - read chip data into buffer
216 * @mtd: MTD device structure
217 * @buf: buffer to store date
218 * @len: number of bytes to read
220 * read function for 16bit buswith
222 static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
225 struct nand_chip *this = mtd->priv;
226 u16 *p = (u16 *) buf;
229 for (i = 0; i < len; i++) {
230 p[i] = readw(this->IO_ADDR_R);
236 * au_verify_buf16 - Verify chip data against buffer
237 * @mtd: MTD device structure
238 * @buf: buffer containing the data to compare
239 * @len: number of bytes to compare
241 * verify function for 16bit buswith
243 static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len)
246 struct nand_chip *this = mtd->priv;
247 u16 *p = (u16 *) buf;
250 for (i = 0; i < len; i++) {
251 if (p[i] != readw(this->IO_ADDR_R))
258 /* Select the chip by setting nCE to low */
259 #define NAND_CTL_SETNCE 1
260 /* Deselect the chip by setting nCE to high */
261 #define NAND_CTL_CLRNCE 2
262 /* Select the command latch by setting CLE to high */
263 #define NAND_CTL_SETCLE 3
264 /* Deselect the command latch by setting CLE to low */
265 #define NAND_CTL_CLRCLE 4
266 /* Select the address latch by setting ALE to high */
267 #define NAND_CTL_SETALE 5
268 /* Deselect the address latch by setting ALE to low */
269 #define NAND_CTL_CLRALE 6
271 static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
273 register struct nand_chip *this = mtd->priv;
277 case NAND_CTL_SETCLE:
278 this->IO_ADDR_W = p_nand + MEM_STNAND_CMD;
281 case NAND_CTL_CLRCLE:
282 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
285 case NAND_CTL_SETALE:
286 this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR;
289 case NAND_CTL_CLRALE:
290 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
291 /* FIXME: Nobody knows why this is necessary,
292 * but it works only that way */
296 case NAND_CTL_SETNCE:
297 /* assert (force assert) chip enable */
298 au_writel((1 << (4 + NAND_CS)), MEM_STNDCTL);
301 case NAND_CTL_CLRNCE:
302 /* deassert chip enable */
303 au_writel(0, MEM_STNDCTL);
307 this->IO_ADDR_R = this->IO_ADDR_W;
309 /* Drain the writebuffer */
313 int au1550_device_ready(struct mtd_info *mtd)
315 int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0;
321 * au1550_select_chip - control -CE line
322 * Forbid driving -CE manually permitting the NAND controller to do this.
323 * Keeping -CE asserted during the whole sector reads interferes with the
324 * NOR flash and PCMCIA drivers as it causes contention on the static bus.
325 * We only have to hold -CE low for the NAND read commands since the flash
326 * chip needs it to be asserted during chip not ready time but the NAND
327 * controller keeps it released.
329 * @mtd: MTD device structure
330 * @chip: chipnumber to select, -1 for deselect
332 static void au1550_select_chip(struct mtd_info *mtd, int chip)
337 * au1550_command - Send command to NAND device
338 * @mtd: MTD device structure
339 * @command: the command to be sent
340 * @column: the column address for this command, -1 if none
341 * @page_addr: the page address for this command, -1 if none
343 static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
345 register struct nand_chip *this = mtd->priv;
346 int ce_override = 0, i;
349 /* Begin command latch cycle */
350 au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
352 * Write out the command to the device.
354 if (command == NAND_CMD_SEQIN) {
357 if (column >= mtd->writesize) {
359 column -= mtd->writesize;
360 readcmd = NAND_CMD_READOOB;
361 } else if (column < 256) {
362 /* First 256 bytes --> READ0 */
363 readcmd = NAND_CMD_READ0;
366 readcmd = NAND_CMD_READ1;
368 au1550_write_byte(mtd, readcmd);
370 au1550_write_byte(mtd, command);
372 /* Set ALE and clear CLE to start address cycle */
373 au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
375 if (column != -1 || page_addr != -1) {
376 au1550_hwcontrol(mtd, NAND_CTL_SETALE);
378 /* Serially input address */
380 /* Adjust columns for 16 bit buswidth */
381 if (this->options & NAND_BUSWIDTH_16)
383 au1550_write_byte(mtd, column);
385 if (page_addr != -1) {
386 au1550_write_byte(mtd, (u8)(page_addr & 0xff));
388 if (command == NAND_CMD_READ0 ||
389 command == NAND_CMD_READ1 ||
390 command == NAND_CMD_READOOB) {
392 * NAND controller will release -CE after
393 * the last address byte is written, so we'll
394 * have to forcibly assert it. No interrupts
395 * are allowed while we do this as we don't
396 * want the NOR flash or PCMCIA drivers to
397 * steal our precious bytes of data...
400 local_irq_save(flags);
401 au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
404 au1550_write_byte(mtd, (u8)(page_addr >> 8));
406 /* One more address cycle for devices > 32MiB */
407 if (this->chipsize > (32 << 20))
408 au1550_write_byte(mtd, (u8)((page_addr >> 16) & 0x0f));
410 /* Latch in address */
411 au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
415 * Program and erase have their own busy handlers.
416 * Status and sequential in need no delay.
420 case NAND_CMD_PAGEPROG:
421 case NAND_CMD_ERASE1:
422 case NAND_CMD_ERASE2:
424 case NAND_CMD_STATUS:
432 case NAND_CMD_READOOB:
433 /* Check if we're really driving -CE low (just in case) */
434 if (unlikely(!ce_override))
437 /* Apply a short delay always to ensure that we do wait tWB. */
439 /* Wait for a chip to become ready... */
440 for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i)
443 /* Release -CE and re-enable interrupts. */
444 au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
445 local_irq_restore(flags);
448 /* Apply this short delay always to ensure that we do wait tWB. */
451 while(!this->dev_ready(mtd));
456 * Main initialization routine
458 static int __init au1xxx_nand_init(void)
460 struct nand_chip *this;
461 u16 boot_swapboot = 0; /* default value */
466 /* Allocate memory for MTD device structure and private data */
467 au1550_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
469 printk("Unable to allocate NAND MTD dev structure.\n");
473 /* Get pointer to private data */
474 this = (struct nand_chip *)(&au1550_mtd[1]);
476 /* Initialize structures */
477 memset(au1550_mtd, 0, sizeof(struct mtd_info));
478 memset(this, 0, sizeof(struct nand_chip));
480 /* Link the private data with the MTD structure */
481 au1550_mtd->priv = this;
482 au1550_mtd->owner = THIS_MODULE;
485 /* MEM_STNDCTL: disable ints, disable nand boot */
486 au_writel(0, MEM_STNDCTL);
488 #ifdef CONFIG_MIPS_PB1550
489 /* set gpio206 high */
490 au_writel(au_readl(GPIO2_DIR) & ~(1 << 6), GPIO2_DIR);
492 boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr->status >> 6) & 0x1);
493 switch (boot_swapboot) {
511 printk("Pb1550 NAND: bad boot:swap\n");
517 /* Configure chip-select; normally done by boot code, e.g. YAMON */
520 au_writel(NAND_STCFG, MEM_STCFG0);
521 au_writel(NAND_STTIME, MEM_STTIME0);
522 au_writel(NAND_STADDR, MEM_STADDR0);
525 au_writel(NAND_STCFG, MEM_STCFG1);
526 au_writel(NAND_STTIME, MEM_STTIME1);
527 au_writel(NAND_STADDR, MEM_STADDR1);
530 au_writel(NAND_STCFG, MEM_STCFG2);
531 au_writel(NAND_STTIME, MEM_STTIME2);
532 au_writel(NAND_STADDR, MEM_STADDR2);
535 au_writel(NAND_STCFG, MEM_STCFG3);
536 au_writel(NAND_STTIME, MEM_STTIME3);
537 au_writel(NAND_STADDR, MEM_STADDR3);
541 /* Locate NAND chip-select in order to determine NAND phys address */
542 mem_staddr = 0x00000000;
543 if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0))
544 mem_staddr = au_readl(MEM_STADDR0);
545 else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1))
546 mem_staddr = au_readl(MEM_STADDR1);
547 else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2))
548 mem_staddr = au_readl(MEM_STADDR2);
549 else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3))
550 mem_staddr = au_readl(MEM_STADDR3);
552 if (mem_staddr == 0x00000000) {
553 printk("Au1xxx NAND: ERROR WITH NAND CHIP-SELECT\n");
557 nand_phys = (mem_staddr << 4) & 0xFFFC0000;
559 p_nand = (void __iomem *)ioremap(nand_phys, 0x1000);
561 /* make controller and MTD agree */
563 nand_width = au_readl(MEM_STCFG0) & (1 << 22);
565 nand_width = au_readl(MEM_STCFG1) & (1 << 22);
567 nand_width = au_readl(MEM_STCFG2) & (1 << 22);
569 nand_width = au_readl(MEM_STCFG3) & (1 << 22);
571 /* Set address of hardware control function */
572 this->dev_ready = au1550_device_ready;
573 this->select_chip = au1550_select_chip;
574 this->cmdfunc = au1550_command;
576 /* 30 us command delay time */
577 this->chip_delay = 30;
578 this->ecc.mode = NAND_ECC_SOFT;
580 this->options = NAND_NO_AUTOINCR;
583 this->options |= NAND_BUSWIDTH_16;
585 this->read_byte = (!nand_width) ? au_read_byte16 : au_read_byte;
586 au1550_write_byte = (!nand_width) ? au_write_byte16 : au_write_byte;
587 this->read_word = au_read_word;
588 this->write_buf = (!nand_width) ? au_write_buf16 : au_write_buf;
589 this->read_buf = (!nand_width) ? au_read_buf16 : au_read_buf;
590 this->verify_buf = (!nand_width) ? au_verify_buf16 : au_verify_buf;
592 /* Scan to find existence of the device */
593 if (nand_scan(au1550_mtd, 1)) {
598 /* Register the partitions */
599 add_mtd_partitions(au1550_mtd, partition_info, ARRAY_SIZE(partition_info));
604 iounmap((void *)p_nand);
611 module_init(au1xxx_nand_init);
616 static void __exit au1550_cleanup(void)
618 struct nand_chip *this = (struct nand_chip *)&au1550_mtd[1];
620 /* Release resources, unregister device */
621 nand_release(au1550_mtd);
623 /* Free the MTD device structure */
627 iounmap((void *)p_nand);
630 module_exit(au1550_cleanup);
632 MODULE_LICENSE("GPL");
633 MODULE_AUTHOR("Embedded Edge, LLC");
634 MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");