2 * tifm_sd.c - TI FlashMedia driver
4 * Copyright (C) 2006 Alex Dubov <oakad@yahoo.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
13 #include <linux/tifm.h>
14 #include <linux/mmc/protocol.h>
15 #include <linux/mmc/host.h>
16 #include <linux/highmem.h>
19 #define DRIVER_NAME "tifm_sd"
20 #define DRIVER_VERSION "0.8"
22 static int no_dma = 0;
23 static int fixed_timeout = 0;
24 module_param(no_dma, bool, 0644);
25 module_param(fixed_timeout, bool, 0644);
27 /* Constants here are mostly from OMAP5912 datasheet */
28 #define TIFM_MMCSD_RESET 0x0002
29 #define TIFM_MMCSD_CLKMASK 0x03ff
30 #define TIFM_MMCSD_POWER 0x0800
31 #define TIFM_MMCSD_4BBUS 0x8000
32 #define TIFM_MMCSD_RXDE 0x8000 /* rx dma enable */
33 #define TIFM_MMCSD_TXDE 0x0080 /* tx dma enable */
34 #define TIFM_MMCSD_BUFINT 0x0c00 /* set bits: AE, AF */
35 #define TIFM_MMCSD_DPE 0x0020 /* data timeout counted in kilocycles */
36 #define TIFM_MMCSD_INAB 0x0080 /* abort / initialize command */
37 #define TIFM_MMCSD_READ 0x8000
39 #define TIFM_MMCSD_ERRMASK 0x01e0 /* set bits: CCRC, CTO, DCRC, DTO */
40 #define TIFM_MMCSD_EOC 0x0001 /* end of command phase */
41 #define TIFM_MMCSD_CB 0x0004 /* card enter busy state */
42 #define TIFM_MMCSD_BRS 0x0008 /* block received/sent */
43 #define TIFM_MMCSD_EOFB 0x0010 /* card exit busy state */
44 #define TIFM_MMCSD_DTO 0x0020 /* data time-out */
45 #define TIFM_MMCSD_DCRC 0x0040 /* data crc error */
46 #define TIFM_MMCSD_CTO 0x0080 /* command time-out */
47 #define TIFM_MMCSD_CCRC 0x0100 /* command crc error */
48 #define TIFM_MMCSD_AF 0x0400 /* fifo almost full */
49 #define TIFM_MMCSD_AE 0x0800 /* fifo almost empty */
50 #define TIFM_MMCSD_CERR 0x4000 /* card status error */
52 #define TIFM_MMCSD_ODTO 0x0040 /* open drain / extended timeout */
53 #define TIFM_MMCSD_CARD_RO 0x0200 /* card is read-only */
55 #define TIFM_MMCSD_FIFO_SIZE 0x0020
57 #define TIFM_MMCSD_RSP_R0 0x0000
58 #define TIFM_MMCSD_RSP_R1 0x0100
59 #define TIFM_MMCSD_RSP_R2 0x0200
60 #define TIFM_MMCSD_RSP_R3 0x0300
61 #define TIFM_MMCSD_RSP_R4 0x0400
62 #define TIFM_MMCSD_RSP_R5 0x0500
63 #define TIFM_MMCSD_RSP_R6 0x0600
65 #define TIFM_MMCSD_RSP_BUSY 0x0800
67 #define TIFM_MMCSD_CMD_BC 0x0000
68 #define TIFM_MMCSD_CMD_BCR 0x1000
69 #define TIFM_MMCSD_CMD_AC 0x2000
70 #define TIFM_MMCSD_CMD_ADTC 0x3000
85 unsigned short eject:1,
88 unsigned short cmd_flags;
90 unsigned int clk_freq;
92 unsigned long timeout_jiffies;
94 struct tasklet_struct finish_tasklet;
95 struct timer_list timer;
96 struct mmc_request *req;
98 size_t written_blocks;
104 static char* tifm_sd_data_buffer(struct mmc_data *data)
106 return page_address(data->sg->page) + data->sg->offset;
109 static int tifm_sd_transfer_data(struct tifm_dev *sock, struct tifm_sd *host,
110 unsigned int host_status)
112 struct mmc_command *cmd = host->req->cmd;
113 unsigned int t_val = 0, cnt = 0;
116 if (host_status & TIFM_MMCSD_BRS) {
117 /* in non-dma rx mode BRS fires when fifo is still not empty */
118 if (host->no_dma && (cmd->data->flags & MMC_DATA_READ)) {
119 buffer = tifm_sd_data_buffer(host->req->data);
120 while (host->buffer_size > host->buffer_pos) {
121 t_val = readl(sock->addr + SOCK_MMCSD_DATA);
122 buffer[host->buffer_pos++] = t_val & 0xff;
123 buffer[host->buffer_pos++] =
128 } else if (host->no_dma) {
129 buffer = tifm_sd_data_buffer(host->req->data);
130 if ((cmd->data->flags & MMC_DATA_READ) &&
131 (host_status & TIFM_MMCSD_AF)) {
132 for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
133 t_val = readl(sock->addr + SOCK_MMCSD_DATA);
134 if (host->buffer_size > host->buffer_pos) {
135 buffer[host->buffer_pos++] =
137 buffer[host->buffer_pos++] =
141 } else if ((cmd->data->flags & MMC_DATA_WRITE)
142 && (host_status & TIFM_MMCSD_AE)) {
143 for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
144 if (host->buffer_size > host->buffer_pos) {
145 t_val = buffer[host->buffer_pos++]
147 t_val |= ((buffer[host->buffer_pos++])
150 sock->addr + SOCK_MMCSD_DATA);
158 static unsigned int tifm_sd_op_flags(struct mmc_command *cmd)
162 switch (mmc_resp_type(cmd)) {
164 rc |= TIFM_MMCSD_RSP_R0;
167 rc |= TIFM_MMCSD_RSP_BUSY; // deliberate fall-through
169 rc |= TIFM_MMCSD_RSP_R1;
172 rc |= TIFM_MMCSD_RSP_R2;
175 rc |= TIFM_MMCSD_RSP_R3;
181 switch (mmc_cmd_type(cmd)) {
183 rc |= TIFM_MMCSD_CMD_BC;
186 rc |= TIFM_MMCSD_CMD_BCR;
189 rc |= TIFM_MMCSD_CMD_AC;
192 rc |= TIFM_MMCSD_CMD_ADTC;
200 static void tifm_sd_exec(struct tifm_sd *host, struct mmc_command *cmd)
202 struct tifm_dev *sock = host->dev;
203 unsigned int cmd_mask = tifm_sd_op_flags(cmd);
205 if (host->open_drain)
206 cmd_mask |= TIFM_MMCSD_ODTO;
208 if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
209 cmd_mask |= TIFM_MMCSD_READ;
211 dev_dbg(&sock->dev, "executing opcode 0x%x, arg: 0x%x, mask: 0x%x\n",
212 cmd->opcode, cmd->arg, cmd_mask);
214 writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);
215 writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);
216 writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND);
219 static void tifm_sd_fetch_resp(struct mmc_command *cmd, struct tifm_dev *sock)
221 cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)
222 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);
223 cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)
224 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);
225 cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)
226 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);
227 cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)
228 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);
231 static void tifm_sd_check_status(struct tifm_sd *host)
233 struct tifm_dev *sock = host->dev;
234 struct mmc_command *cmd = host->req->cmd;
236 if (cmd->error != MMC_ERR_NONE)
239 if (!(host->cmd_flags & CMD_READY))
243 if (cmd->data->error != MMC_ERR_NONE) {
244 if ((host->cmd_flags & SCMD_ACTIVE)
245 && !(host->cmd_flags & SCMD_READY))
251 if (!(host->cmd_flags & BRS_READY))
254 if (!(host->no_dma || (host->cmd_flags & FIFO_READY)))
257 if (cmd->data->flags & MMC_DATA_WRITE) {
258 if (host->req->stop) {
259 if (!(host->cmd_flags & SCMD_ACTIVE)) {
260 host->cmd_flags |= SCMD_ACTIVE;
261 writel(TIFM_MMCSD_EOFB
263 + SOCK_MMCSD_INT_ENABLE),
265 + SOCK_MMCSD_INT_ENABLE);
266 tifm_sd_exec(host, host->req->stop);
269 if (!(host->cmd_flags & SCMD_READY)
270 || (host->cmd_flags & CARD_BUSY))
272 writel((~TIFM_MMCSD_EOFB)
274 + SOCK_MMCSD_INT_ENABLE),
276 + SOCK_MMCSD_INT_ENABLE);
279 if (host->cmd_flags & CARD_BUSY)
281 writel((~TIFM_MMCSD_EOFB)
283 + SOCK_MMCSD_INT_ENABLE),
284 sock->addr + SOCK_MMCSD_INT_ENABLE);
287 if (host->req->stop) {
288 if (!(host->cmd_flags & SCMD_ACTIVE)) {
289 host->cmd_flags |= SCMD_ACTIVE;
290 tifm_sd_exec(host, host->req->stop);
293 if (!(host->cmd_flags & SCMD_READY))
300 tasklet_schedule(&host->finish_tasklet);
303 /* Called from interrupt handler */
304 static void tifm_sd_data_event(struct tifm_dev *sock)
306 struct tifm_sd *host;
307 unsigned int fifo_status = 0;
308 struct mmc_data *r_data = NULL;
310 spin_lock(&sock->lock);
311 host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
312 fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
313 dev_dbg(&sock->dev, "data event: fifo_status %x, flags %x\n",
314 fifo_status, host->cmd_flags);
317 r_data = host->req->cmd->data;
319 if (r_data && (fifo_status & TIFM_FIFO_READY)) {
320 host->cmd_flags |= FIFO_READY;
321 tifm_sd_check_status(host);
325 writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
326 spin_unlock(&sock->lock);
329 /* Called from interrupt handler */
330 static void tifm_sd_card_event(struct tifm_dev *sock)
332 struct tifm_sd *host;
333 unsigned int host_status = 0;
334 int cmd_error = MMC_ERR_NONE;
335 struct mmc_command *cmd = NULL;
338 spin_lock(&sock->lock);
339 host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
340 host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
341 dev_dbg(&sock->dev, "host event: host_status %x, flags %x\n",
342 host_status, host->cmd_flags);
345 cmd = host->req->cmd;
347 if (host_status & TIFM_MMCSD_ERRMASK) {
348 writel(host_status & TIFM_MMCSD_ERRMASK,
349 sock->addr + SOCK_MMCSD_STATUS);
350 if (host_status & TIFM_MMCSD_CTO)
351 cmd_error = MMC_ERR_TIMEOUT;
352 else if (host_status & TIFM_MMCSD_CCRC)
353 cmd_error = MMC_ERR_BADCRC;
356 if (host_status & TIFM_MMCSD_DTO)
357 cmd->data->error = MMC_ERR_TIMEOUT;
358 else if (host_status & TIFM_MMCSD_DCRC)
359 cmd->data->error = MMC_ERR_BADCRC;
362 writel(TIFM_FIFO_INT_SETALL,
363 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
364 writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
366 if (host->req->stop) {
367 if (host->cmd_flags & SCMD_ACTIVE) {
368 host->req->stop->error = cmd_error;
369 host->cmd_flags |= SCMD_READY;
371 cmd->error = cmd_error;
372 host->cmd_flags |= SCMD_ACTIVE;
373 tifm_sd_exec(host, host->req->stop);
377 cmd->error = cmd_error;
379 if (host_status & (TIFM_MMCSD_EOC | TIFM_MMCSD_CERR)) {
380 if (!(host->cmd_flags & CMD_READY)) {
381 host->cmd_flags |= CMD_READY;
382 tifm_sd_fetch_resp(cmd, sock);
383 } else if (host->cmd_flags & SCMD_ACTIVE) {
384 host->cmd_flags |= SCMD_READY;
385 tifm_sd_fetch_resp(host->req->stop,
389 if (host_status & TIFM_MMCSD_BRS)
390 host->cmd_flags |= BRS_READY;
393 if (host->no_dma && cmd->data) {
394 if (host_status & TIFM_MMCSD_AE)
395 writel(host_status & TIFM_MMCSD_AE,
396 sock->addr + SOCK_MMCSD_STATUS);
398 if (host_status & (TIFM_MMCSD_AE | TIFM_MMCSD_AF
400 local_irq_save(flags);
401 tifm_sd_transfer_data(sock, host, host_status);
402 local_irq_restore(flags);
403 host_status &= ~TIFM_MMCSD_AE;
407 if (host_status & TIFM_MMCSD_EOFB)
408 host->cmd_flags &= ~CARD_BUSY;
409 else if (host_status & TIFM_MMCSD_CB)
410 host->cmd_flags |= CARD_BUSY;
412 tifm_sd_check_status(host);
415 writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
416 spin_unlock(&sock->lock);
419 static void tifm_sd_prepare_data(struct tifm_sd *host, struct mmc_command *cmd)
421 struct tifm_dev *sock = host->dev;
422 unsigned int dest_cnt;
425 dev_dbg(&sock->dev, "setting dma for %d blocks\n",
427 writel(TIFM_FIFO_INT_SETALL,
428 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
429 writel(ilog2(cmd->data->blksz) - 2,
430 sock->addr + SOCK_FIFO_PAGE_SIZE);
431 writel(TIFM_FIFO_ENABLE, sock->addr + SOCK_FIFO_CONTROL);
432 writel(TIFM_FIFO_INTMASK, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
434 dest_cnt = (cmd->data->blocks) << 8;
436 writel(sg_dma_address(cmd->data->sg), sock->addr + SOCK_DMA_ADDRESS);
438 writel(cmd->data->blocks - 1, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
439 writel(cmd->data->blksz - 1, sock->addr + SOCK_MMCSD_BLOCK_LEN);
441 if (cmd->data->flags & MMC_DATA_WRITE) {
442 writel(TIFM_MMCSD_TXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
443 writel(dest_cnt | TIFM_DMA_TX | TIFM_DMA_EN,
444 sock->addr + SOCK_DMA_CONTROL);
446 writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
447 writel(dest_cnt | TIFM_DMA_EN, sock->addr + SOCK_DMA_CONTROL);
451 static void tifm_sd_set_data_timeout(struct tifm_sd *host,
452 struct mmc_data *data)
454 struct tifm_dev *sock = host->dev;
455 unsigned int data_timeout = data->timeout_clks;
460 data_timeout += data->timeout_ns /
461 ((1000000000UL / host->clk_freq) * host->clk_div);
463 if (data_timeout < 0xffff) {
464 writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
465 writel((~TIFM_MMCSD_DPE)
466 & readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
467 sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
469 data_timeout = (data_timeout >> 10) + 1;
470 if (data_timeout > 0xffff)
471 data_timeout = 0; /* set to unlimited */
472 writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
473 writel(TIFM_MMCSD_DPE
474 | readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
475 sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
479 static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq)
481 struct tifm_sd *host = mmc_priv(mmc);
482 struct tifm_dev *sock = host->dev;
485 struct mmc_data *r_data = mrq->cmd->data;
487 spin_lock_irqsave(&sock->lock, flags);
489 spin_unlock_irqrestore(&sock->lock, flags);
494 printk(KERN_ERR DRIVER_NAME ": unfinished request detected\n");
495 spin_unlock_irqrestore(&sock->lock, flags);
500 tifm_sd_set_data_timeout(host, r_data);
503 host->buffer_size = mrq->cmd->data->blocks
504 * mrq->cmd->data->blksz;
506 writel(TIFM_MMCSD_BUFINT
507 | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
508 sock->addr + SOCK_MMCSD_INT_ENABLE);
509 writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8)
510 | (TIFM_MMCSD_FIFO_SIZE - 1),
511 sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
513 host->written_blocks = 0;
514 host->cmd_flags &= ~CARD_BUSY;
515 host->buffer_pos = 0;
516 writel(r_data->blocks - 1,
517 sock->addr + SOCK_MMCSD_NUM_BLOCKS);
518 writel(r_data->blksz - 1,
519 sock->addr + SOCK_MMCSD_BLOCK_LEN);
521 sg_count = tifm_map_sg(sock, r_data->sg, r_data->sg_len,
522 mrq->cmd->flags & MMC_DATA_WRITE
524 : PCI_DMA_FROMDEVICE);
526 printk(KERN_ERR DRIVER_NAME
527 ": scatterlist map failed\n");
528 spin_unlock_irqrestore(&sock->lock, flags);
532 host->written_blocks = 0;
533 host->cmd_flags &= ~CARD_BUSY;
534 tifm_sd_prepare_data(host, mrq->cmd);
539 mod_timer(&host->timer, jiffies + host->timeout_jiffies);
541 writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
542 sock->addr + SOCK_CONTROL);
543 tifm_sd_exec(host, mrq->cmd);
544 spin_unlock_irqrestore(&sock->lock, flags);
549 tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
550 (r_data->flags & MMC_DATA_WRITE)
551 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
553 mrq->cmd->error = MMC_ERR_TIMEOUT;
554 mmc_request_done(mmc, mrq);
557 static void tifm_sd_end_cmd(unsigned long data)
559 struct tifm_sd *host = (struct tifm_sd*)data;
560 struct tifm_dev *sock = host->dev;
561 struct mmc_host *mmc = tifm_get_drvdata(sock);
562 struct mmc_request *mrq;
563 struct mmc_data *r_data = NULL;
566 spin_lock_irqsave(&sock->lock, flags);
568 del_timer(&host->timer);
573 printk(KERN_ERR DRIVER_NAME ": no request to complete?\n");
574 spin_unlock_irqrestore(&sock->lock, flags);
578 r_data = mrq->cmd->data;
581 writel((~TIFM_MMCSD_BUFINT) &
582 readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
583 sock->addr + SOCK_MMCSD_INT_ENABLE);
585 if (r_data->flags & MMC_DATA_WRITE) {
586 r_data->bytes_xfered = host->written_blocks
589 r_data->bytes_xfered = r_data->blocks -
590 readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS)
592 r_data->bytes_xfered *= r_data->blksz;
593 r_data->bytes_xfered += r_data->blksz
594 - readl(sock->addr + SOCK_MMCSD_BLOCK_LEN)
597 host->buffer_pos = 0;
598 host->buffer_size = 0;
600 if (r_data->flags & MMC_DATA_WRITE) {
601 r_data->bytes_xfered = host->written_blocks
604 r_data->bytes_xfered = r_data->blocks -
605 readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
606 r_data->bytes_xfered *= r_data->blksz;
607 r_data->bytes_xfered += r_data->blksz -
608 readl(sock->addr + SOCK_MMCSD_BLOCK_LEN)
611 tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
612 (r_data->flags & MMC_DATA_WRITE)
613 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
617 writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
618 sock->addr + SOCK_CONTROL);
620 spin_unlock_irqrestore(&sock->lock, flags);
621 mmc_request_done(mmc, mrq);
624 static void tifm_sd_abort(unsigned long data)
626 struct tifm_sd *host = (struct tifm_sd*)data;
628 printk(KERN_ERR DRIVER_NAME
629 ": card failed to respond for a long period of time\n");
631 tifm_eject(host->dev);
634 static void tifm_sd_ios(struct mmc_host *mmc, struct mmc_ios *ios)
636 struct tifm_sd *host = mmc_priv(mmc);
637 struct tifm_dev *sock = host->dev;
638 unsigned int clk_div1, clk_div2;
641 spin_lock_irqsave(&sock->lock, flags);
643 dev_dbg(&sock->dev, "Setting bus width %d, power %d\n", ios->bus_width,
645 if (ios->bus_width == MMC_BUS_WIDTH_4) {
646 writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG),
647 sock->addr + SOCK_MMCSD_CONFIG);
649 writel((~TIFM_MMCSD_4BBUS)
650 & readl(sock->addr + SOCK_MMCSD_CONFIG),
651 sock->addr + SOCK_MMCSD_CONFIG);
655 clk_div1 = 20000000 / ios->clock;
659 clk_div2 = 24000000 / ios->clock;
663 if ((20000000 / clk_div1) > ios->clock)
665 if ((24000000 / clk_div2) > ios->clock)
667 if ((20000000 / clk_div1) > (24000000 / clk_div2)) {
668 host->clk_freq = 20000000;
669 host->clk_div = clk_div1;
670 writel((~TIFM_CTRL_FAST_CLK)
671 & readl(sock->addr + SOCK_CONTROL),
672 sock->addr + SOCK_CONTROL);
674 host->clk_freq = 24000000;
675 host->clk_div = clk_div2;
676 writel(TIFM_CTRL_FAST_CLK
677 | readl(sock->addr + SOCK_CONTROL),
678 sock->addr + SOCK_CONTROL);
683 host->clk_div &= TIFM_MMCSD_CLKMASK;
685 | ((~TIFM_MMCSD_CLKMASK)
686 & readl(sock->addr + SOCK_MMCSD_CONFIG)),
687 sock->addr + SOCK_MMCSD_CONFIG);
689 host->open_drain = (ios->bus_mode == MMC_BUSMODE_OPENDRAIN);
691 /* chip_select : maybe later */
693 //power is set before probe / after remove
695 spin_unlock_irqrestore(&sock->lock, flags);
698 static int tifm_sd_ro(struct mmc_host *mmc)
701 struct tifm_sd *host = mmc_priv(mmc);
702 struct tifm_dev *sock = host->dev;
705 spin_lock_irqsave(&sock->lock, flags);
706 if (TIFM_MMCSD_CARD_RO & readl(sock->addr + SOCK_PRESENT_STATE))
708 spin_unlock_irqrestore(&sock->lock, flags);
712 static const struct mmc_host_ops tifm_sd_ops = {
713 .request = tifm_sd_request,
714 .set_ios = tifm_sd_ios,
718 static int tifm_sd_initialize_host(struct tifm_sd *host)
721 unsigned int host_status = 0;
722 struct tifm_dev *sock = host->dev;
724 writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
727 host->clk_freq = 20000000;
728 writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL);
729 writel(host->clk_div | TIFM_MMCSD_POWER,
730 sock->addr + SOCK_MMCSD_CONFIG);
732 /* wait up to 0.51 sec for reset */
733 for (rc = 32; rc <= 256; rc <<= 1) {
734 if (1 & readl(sock->addr + SOCK_MMCSD_SYSTEM_STATUS)) {
742 printk(KERN_ERR "%s : controller failed to reset\n",
747 writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
748 writel(host->clk_div | TIFM_MMCSD_POWER,
749 sock->addr + SOCK_MMCSD_CONFIG);
750 writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
752 // command timeout fixed to 64 clocks for now
753 writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO);
754 writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND);
756 for (rc = 16; rc <= 64; rc <<= 1) {
757 host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
758 writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
759 if (!(host_status & TIFM_MMCSD_ERRMASK)
760 && (host_status & TIFM_MMCSD_EOC)) {
769 "%s : card not ready - probe failed on initialization\n",
774 writel(TIFM_MMCSD_CERR | TIFM_MMCSD_BRS | TIFM_MMCSD_EOC
775 | TIFM_MMCSD_ERRMASK,
776 sock->addr + SOCK_MMCSD_INT_ENABLE);
782 static int tifm_sd_probe(struct tifm_dev *sock)
784 struct mmc_host *mmc;
785 struct tifm_sd *host;
788 if (!(TIFM_SOCK_STATE_OCCUPIED
789 & readl(sock->addr + SOCK_PRESENT_STATE))) {
790 printk(KERN_WARNING DRIVER_NAME ": card gone, unexpectedly\n");
794 mmc = mmc_alloc_host(sizeof(struct tifm_sd), &sock->dev);
798 host = mmc_priv(mmc);
799 host->no_dma = no_dma;
800 tifm_set_drvdata(sock, mmc);
802 host->timeout_jiffies = msecs_to_jiffies(1000);
804 tasklet_init(&host->finish_tasklet, tifm_sd_end_cmd,
805 (unsigned long)host);
806 setup_timer(&host->timer, tifm_sd_abort, (unsigned long)host);
808 mmc->ops = &tifm_sd_ops;
809 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
810 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE;
811 mmc->f_min = 20000000 / 60;
812 mmc->f_max = 24000000;
813 mmc->max_hw_segs = 1;
814 mmc->max_phys_segs = 1;
815 // limited by DMA counter - it's safer to stick with
816 // block counter has 11 bits though
817 mmc->max_blk_count = 256;
818 // 2k maximum hw block length
819 mmc->max_blk_size = 2048;
820 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
821 mmc->max_seg_size = mmc->max_req_size;
822 sock->card_event = tifm_sd_card_event;
823 sock->data_event = tifm_sd_data_event;
824 rc = tifm_sd_initialize_host(host);
827 rc = mmc_add_host(mmc);
837 static void tifm_sd_remove(struct tifm_dev *sock)
839 struct mmc_host *mmc = tifm_get_drvdata(sock);
840 struct tifm_sd *host = mmc_priv(mmc);
843 spin_lock_irqsave(&sock->lock, flags);
845 writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
847 spin_unlock_irqrestore(&sock->lock, flags);
849 tasklet_kill(&host->finish_tasklet);
851 spin_lock_irqsave(&sock->lock, flags);
853 writel(TIFM_FIFO_INT_SETALL,
854 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
855 writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
856 host->req->cmd->error = MMC_ERR_TIMEOUT;
858 host->req->stop->error = MMC_ERR_TIMEOUT;
859 tasklet_schedule(&host->finish_tasklet);
861 spin_unlock_irqrestore(&sock->lock, flags);
862 mmc_remove_host(mmc);
863 dev_dbg(&sock->dev, "after remove\n");
865 /* The meaning of the bit majority in this constant is unknown. */
866 writel(0xfff8 & readl(sock->addr + SOCK_CONTROL),
867 sock->addr + SOCK_CONTROL);
874 static int tifm_sd_suspend(struct tifm_dev *sock, pm_message_t state)
876 struct mmc_host *mmc = tifm_get_drvdata(sock);
879 rc = mmc_suspend_host(mmc, state);
880 /* The meaning of the bit majority in this constant is unknown. */
881 writel(0xfff8 & readl(sock->addr + SOCK_CONTROL),
882 sock->addr + SOCK_CONTROL);
886 static int tifm_sd_resume(struct tifm_dev *sock)
888 struct mmc_host *mmc = tifm_get_drvdata(sock);
889 struct tifm_sd *host = mmc_priv(mmc);
892 rc = tifm_sd_initialize_host(host);
893 dev_dbg(&sock->dev, "resume initialize %d\n", rc);
898 rc = mmc_resume_host(mmc);
905 #define tifm_sd_suspend NULL
906 #define tifm_sd_resume NULL
908 #endif /* CONFIG_PM */
910 static struct tifm_device_id tifm_sd_id_tbl[] = {
911 { TIFM_TYPE_SD }, { }
914 static struct tifm_driver tifm_sd_driver = {
919 .id_table = tifm_sd_id_tbl,
920 .probe = tifm_sd_probe,
921 .remove = tifm_sd_remove,
922 .suspend = tifm_sd_suspend,
923 .resume = tifm_sd_resume
926 static int __init tifm_sd_init(void)
928 return tifm_register_driver(&tifm_sd_driver);
931 static void __exit tifm_sd_exit(void)
933 tifm_unregister_driver(&tifm_sd_driver);
936 MODULE_AUTHOR("Alex Dubov");
937 MODULE_DESCRIPTION("TI FlashMedia SD driver");
938 MODULE_LICENSE("GPL");
939 MODULE_DEVICE_TABLE(tifm, tifm_sd_id_tbl);
940 MODULE_VERSION(DRIVER_VERSION);
942 module_init(tifm_sd_init);
943 module_exit(tifm_sd_exit);