2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/pci.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/scatterlist.h>
22 #include <linux/leds.h>
24 #include <linux/mmc/host.h>
28 #define DRIVER_NAME "sdhci"
30 #define DBG(f, x...) \
31 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
33 static unsigned int debug_quirks = 0;
36 * Different quirks to handle when the hardware deviates from a strict
37 * interpretation of the SDHCI specification.
40 /* Controller doesn't honor resets unless we touch the clock register */
41 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
42 /* Controller has bad caps bits, but really supports DMA */
43 #define SDHCI_QUIRK_FORCE_DMA (1<<1)
44 /* Controller doesn't like to be reset when there is no card inserted. */
45 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
46 /* Controller doesn't like clearing the power reg before a change */
47 #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
48 /* Controller has flaky internal state so reset it on each ios change */
49 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
50 /* Controller has an unusable DMA engine */
51 #define SDHCI_QUIRK_BROKEN_DMA (1<<5)
52 /* Controller can only DMA from 32-bit aligned addresses */
53 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<6)
54 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
55 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<7)
56 /* Controller needs to be reset after each request to stay stable */
57 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<8)
58 /* Controller needs voltage and power writes to happen separately */
59 #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<9)
60 /* Controller has an off-by-one issue with timeout value */
61 #define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<10)
63 static const struct pci_device_id pci_ids[] __devinitdata = {
65 .vendor = PCI_VENDOR_ID_RICOH,
66 .device = PCI_DEVICE_ID_RICOH_R5C822,
67 .subvendor = PCI_VENDOR_ID_IBM,
68 .subdevice = PCI_ANY_ID,
69 .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
70 SDHCI_QUIRK_FORCE_DMA,
74 .vendor = PCI_VENDOR_ID_RICOH,
75 .device = PCI_DEVICE_ID_RICOH_R5C822,
76 .subvendor = PCI_VENDOR_ID_SAMSUNG,
77 .subdevice = PCI_ANY_ID,
78 .driver_data = SDHCI_QUIRK_FORCE_DMA |
79 SDHCI_QUIRK_NO_CARD_NO_RESET,
83 .vendor = PCI_VENDOR_ID_RICOH,
84 .device = PCI_DEVICE_ID_RICOH_R5C822,
85 .subvendor = PCI_ANY_ID,
86 .subdevice = PCI_ANY_ID,
87 .driver_data = SDHCI_QUIRK_FORCE_DMA,
91 .vendor = PCI_VENDOR_ID_TI,
92 .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
93 .subvendor = PCI_ANY_ID,
94 .subdevice = PCI_ANY_ID,
95 .driver_data = SDHCI_QUIRK_FORCE_DMA,
99 .vendor = PCI_VENDOR_ID_ENE,
100 .device = PCI_DEVICE_ID_ENE_CB712_SD,
101 .subvendor = PCI_ANY_ID,
102 .subdevice = PCI_ANY_ID,
103 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
104 SDHCI_QUIRK_BROKEN_DMA,
108 .vendor = PCI_VENDOR_ID_ENE,
109 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
110 .subvendor = PCI_ANY_ID,
111 .subdevice = PCI_ANY_ID,
112 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
113 SDHCI_QUIRK_BROKEN_DMA,
117 .vendor = PCI_VENDOR_ID_ENE,
118 .device = PCI_DEVICE_ID_ENE_CB714_SD,
119 .subvendor = PCI_ANY_ID,
120 .subdevice = PCI_ANY_ID,
121 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
122 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
123 SDHCI_QUIRK_BROKEN_DMA,
127 .vendor = PCI_VENDOR_ID_ENE,
128 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
129 .subvendor = PCI_ANY_ID,
130 .subdevice = PCI_ANY_ID,
131 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
132 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
133 SDHCI_QUIRK_BROKEN_DMA,
137 .vendor = PCI_VENDOR_ID_MARVELL,
138 .device = PCI_DEVICE_ID_MARVELL_CAFE_SD,
139 .subvendor = PCI_ANY_ID,
140 .subdevice = PCI_ANY_ID,
141 .driver_data = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
142 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL,
146 .vendor = PCI_VENDOR_ID_JMICRON,
147 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
148 .subvendor = PCI_ANY_ID,
149 .subdevice = PCI_ANY_ID,
150 .driver_data = SDHCI_QUIRK_32BIT_DMA_ADDR |
151 SDHCI_QUIRK_32BIT_DMA_SIZE |
152 SDHCI_QUIRK_RESET_AFTER_REQUEST,
155 { /* Generic SD host controller */
156 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
159 { /* end: all zeroes */ },
162 MODULE_DEVICE_TABLE(pci, pci_ids);
164 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
165 static void sdhci_finish_data(struct sdhci_host *);
167 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
168 static void sdhci_finish_command(struct sdhci_host *);
170 static void sdhci_dumpregs(struct sdhci_host *host)
172 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
174 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
175 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
176 readw(host->ioaddr + SDHCI_HOST_VERSION));
177 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
178 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
179 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
180 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
181 readl(host->ioaddr + SDHCI_ARGUMENT),
182 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
183 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
184 readl(host->ioaddr + SDHCI_PRESENT_STATE),
185 readb(host->ioaddr + SDHCI_HOST_CONTROL));
186 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
187 readb(host->ioaddr + SDHCI_POWER_CONTROL),
188 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
189 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
190 readb(host->ioaddr + SDHCI_WAKE_UP_CONTROL),
191 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
192 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
193 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
194 readl(host->ioaddr + SDHCI_INT_STATUS));
195 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
196 readl(host->ioaddr + SDHCI_INT_ENABLE),
197 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
198 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
199 readw(host->ioaddr + SDHCI_ACMD12_ERR),
200 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
201 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
202 readl(host->ioaddr + SDHCI_CAPABILITIES),
203 readl(host->ioaddr + SDHCI_MAX_CURRENT));
205 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
208 /*****************************************************************************\
210 * Low level functions *
212 \*****************************************************************************/
214 static void sdhci_reset(struct sdhci_host *host, u8 mask)
216 unsigned long timeout;
218 if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
219 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
224 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
226 if (mask & SDHCI_RESET_ALL)
229 /* Wait max 100 ms */
232 /* hw clears the bit when it's done */
233 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
235 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
236 mmc_hostname(host->mmc), (int)mask);
237 sdhci_dumpregs(host);
245 static void sdhci_init(struct sdhci_host *host)
249 sdhci_reset(host, SDHCI_RESET_ALL);
251 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
252 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
253 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
254 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
255 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
256 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
258 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
259 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
262 static void sdhci_activate_led(struct sdhci_host *host)
266 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
267 ctrl |= SDHCI_CTRL_LED;
268 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
271 static void sdhci_deactivate_led(struct sdhci_host *host)
275 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
276 ctrl &= ~SDHCI_CTRL_LED;
277 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
280 #ifdef CONFIG_LEDS_CLASS
281 static void sdhci_led_control(struct led_classdev *led,
282 enum led_brightness brightness)
284 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
287 spin_lock_irqsave(&host->lock, flags);
289 if (brightness == LED_OFF)
290 sdhci_deactivate_led(host);
292 sdhci_activate_led(host);
294 spin_unlock_irqrestore(&host->lock, flags);
298 /*****************************************************************************\
302 \*****************************************************************************/
304 static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
306 return sg_virt(host->cur_sg);
309 static inline int sdhci_next_sg(struct sdhci_host* host)
312 * Skip to next SG entry.
320 if (host->num_sg > 0) {
322 host->remain = host->cur_sg->length;
328 static void sdhci_read_block_pio(struct sdhci_host *host)
330 int blksize, chunk_remain;
335 DBG("PIO reading\n");
337 blksize = host->data->blksz;
341 buffer = sdhci_sg_to_buffer(host) + host->offset;
344 if (chunk_remain == 0) {
345 data = readl(host->ioaddr + SDHCI_BUFFER);
346 chunk_remain = min(blksize, 4);
349 size = min(host->remain, chunk_remain);
351 chunk_remain -= size;
353 host->offset += size;
354 host->remain -= size;
357 *buffer = data & 0xFF;
363 if (host->remain == 0) {
364 if (sdhci_next_sg(host) == 0) {
365 BUG_ON(blksize != 0);
368 buffer = sdhci_sg_to_buffer(host);
373 static void sdhci_write_block_pio(struct sdhci_host *host)
375 int blksize, chunk_remain;
380 DBG("PIO writing\n");
382 blksize = host->data->blksz;
387 buffer = sdhci_sg_to_buffer(host) + host->offset;
390 size = min(host->remain, chunk_remain);
392 chunk_remain -= size;
394 host->offset += size;
395 host->remain -= size;
399 data |= (u32)*buffer << 24;
404 if (chunk_remain == 0) {
405 writel(data, host->ioaddr + SDHCI_BUFFER);
406 chunk_remain = min(blksize, 4);
409 if (host->remain == 0) {
410 if (sdhci_next_sg(host) == 0) {
411 BUG_ON(blksize != 0);
414 buffer = sdhci_sg_to_buffer(host);
419 static void sdhci_transfer_pio(struct sdhci_host *host)
425 if (host->num_sg == 0)
428 if (host->data->flags & MMC_DATA_READ)
429 mask = SDHCI_DATA_AVAILABLE;
431 mask = SDHCI_SPACE_AVAILABLE;
433 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
434 if (host->data->flags & MMC_DATA_READ)
435 sdhci_read_block_pio(host);
437 sdhci_write_block_pio(host);
439 if (host->num_sg == 0)
443 DBG("PIO transfer complete.\n");
446 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
449 unsigned target_timeout, current_timeout;
457 BUG_ON(data->blksz * data->blocks > 524288);
458 BUG_ON(data->blksz > host->mmc->max_blk_size);
459 BUG_ON(data->blocks > 65535);
462 host->data_early = 0;
465 target_timeout = data->timeout_ns / 1000 +
466 data->timeout_clks / host->clock;
469 * Figure out needed cycles.
470 * We do this in steps in order to fit inside a 32 bit int.
471 * The first step is the minimum timeout, which will have a
472 * minimum resolution of 6 bits:
473 * (1) 2^13*1000 > 2^22,
474 * (2) host->timeout_clk < 2^16
479 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
480 while (current_timeout < target_timeout) {
482 current_timeout <<= 1;
488 * Compensate for an off-by-one error in the CaFe hardware; otherwise,
489 * a too-small count gives us interrupt timeouts.
491 if ((host->chip->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL))
495 printk(KERN_WARNING "%s: Too large timeout requested!\n",
496 mmc_hostname(host->mmc));
500 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
502 if (host->flags & SDHCI_USE_DMA)
503 host->flags |= SDHCI_REQ_USE_DMA;
505 if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
506 (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
507 ((data->blksz * data->blocks) & 0x3))) {
508 DBG("Reverting to PIO because of transfer size (%d)\n",
509 data->blksz * data->blocks);
510 host->flags &= ~SDHCI_REQ_USE_DMA;
514 * The assumption here being that alignment is the same after
515 * translation to device address space.
517 if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
518 (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
519 (data->sg->offset & 0x3))) {
520 DBG("Reverting to PIO because of bad alignment\n");
521 host->flags &= ~SDHCI_REQ_USE_DMA;
524 if (host->flags & SDHCI_REQ_USE_DMA) {
527 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
528 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
531 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
533 host->cur_sg = data->sg;
534 host->num_sg = data->sg_len;
537 host->remain = host->cur_sg->length;
540 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
541 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
542 host->ioaddr + SDHCI_BLOCK_SIZE);
543 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
546 static void sdhci_set_transfer_mode(struct sdhci_host *host,
547 struct mmc_data *data)
554 WARN_ON(!host->data);
556 mode = SDHCI_TRNS_BLK_CNT_EN;
557 if (data->blocks > 1)
558 mode |= SDHCI_TRNS_MULTI;
559 if (data->flags & MMC_DATA_READ)
560 mode |= SDHCI_TRNS_READ;
561 if (host->flags & SDHCI_REQ_USE_DMA)
562 mode |= SDHCI_TRNS_DMA;
564 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
567 static void sdhci_finish_data(struct sdhci_host *host)
569 struct mmc_data *data;
576 if (host->flags & SDHCI_REQ_USE_DMA) {
577 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
578 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
582 * The specification states that the block count register must
583 * be updated, but it does not specify at what point in the
584 * data flow. That makes the register entirely useless to read
585 * back so we have to assume that nothing made it to the card
586 * in the event of an error.
589 data->bytes_xfered = 0;
591 data->bytes_xfered = data->blksz * data->blocks;
595 * The controller needs a reset of internal state machines
596 * upon error conditions.
599 sdhci_reset(host, SDHCI_RESET_CMD);
600 sdhci_reset(host, SDHCI_RESET_DATA);
603 sdhci_send_command(host, data->stop);
605 tasklet_schedule(&host->finish_tasklet);
608 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
612 unsigned long timeout;
619 mask = SDHCI_CMD_INHIBIT;
620 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
621 mask |= SDHCI_DATA_INHIBIT;
623 /* We shouldn't wait for data inihibit for stop commands, even
624 though they might use busy signaling */
625 if (host->mrq->data && (cmd == host->mrq->data->stop))
626 mask &= ~SDHCI_DATA_INHIBIT;
628 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
630 printk(KERN_ERR "%s: Controller never released "
631 "inhibit bit(s).\n", mmc_hostname(host->mmc));
632 sdhci_dumpregs(host);
634 tasklet_schedule(&host->finish_tasklet);
641 mod_timer(&host->timer, jiffies + 10 * HZ);
645 sdhci_prepare_data(host, cmd->data);
647 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
649 sdhci_set_transfer_mode(host, cmd->data);
651 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
652 printk(KERN_ERR "%s: Unsupported response type!\n",
653 mmc_hostname(host->mmc));
654 cmd->error = -EINVAL;
655 tasklet_schedule(&host->finish_tasklet);
659 if (!(cmd->flags & MMC_RSP_PRESENT))
660 flags = SDHCI_CMD_RESP_NONE;
661 else if (cmd->flags & MMC_RSP_136)
662 flags = SDHCI_CMD_RESP_LONG;
663 else if (cmd->flags & MMC_RSP_BUSY)
664 flags = SDHCI_CMD_RESP_SHORT_BUSY;
666 flags = SDHCI_CMD_RESP_SHORT;
668 if (cmd->flags & MMC_RSP_CRC)
669 flags |= SDHCI_CMD_CRC;
670 if (cmd->flags & MMC_RSP_OPCODE)
671 flags |= SDHCI_CMD_INDEX;
673 flags |= SDHCI_CMD_DATA;
675 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
676 host->ioaddr + SDHCI_COMMAND);
679 static void sdhci_finish_command(struct sdhci_host *host)
683 BUG_ON(host->cmd == NULL);
685 if (host->cmd->flags & MMC_RSP_PRESENT) {
686 if (host->cmd->flags & MMC_RSP_136) {
687 /* CRC is stripped so we need to do some shifting. */
688 for (i = 0;i < 4;i++) {
689 host->cmd->resp[i] = readl(host->ioaddr +
690 SDHCI_RESPONSE + (3-i)*4) << 8;
692 host->cmd->resp[i] |=
694 SDHCI_RESPONSE + (3-i)*4-1);
697 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
701 host->cmd->error = 0;
703 if (host->data && host->data_early)
704 sdhci_finish_data(host);
706 if (!host->cmd->data)
707 tasklet_schedule(&host->finish_tasklet);
712 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
716 unsigned long timeout;
718 if (clock == host->clock)
721 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
726 for (div = 1;div < 256;div *= 2) {
727 if ((host->max_clk / div) <= clock)
732 clk = div << SDHCI_DIVIDER_SHIFT;
733 clk |= SDHCI_CLOCK_INT_EN;
734 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
738 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
739 & SDHCI_CLOCK_INT_STABLE)) {
741 printk(KERN_ERR "%s: Internal clock never "
742 "stabilised.\n", mmc_hostname(host->mmc));
743 sdhci_dumpregs(host);
750 clk |= SDHCI_CLOCK_CARD_EN;
751 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
757 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
761 if (host->power == power)
764 if (power == (unsigned short)-1) {
765 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
770 * Spec says that we should clear the power reg before setting
771 * a new value. Some controllers don't seem to like this though.
773 if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
774 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
776 pwr = SDHCI_POWER_ON;
778 switch (1 << power) {
779 case MMC_VDD_165_195:
780 pwr |= SDHCI_POWER_180;
784 pwr |= SDHCI_POWER_300;
788 pwr |= SDHCI_POWER_330;
795 * At least the CaFe chip gets confused if we set the voltage
796 * and set turn on power at the same time, so set the voltage first.
798 if ((host->chip->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER))
799 writeb(pwr & ~SDHCI_POWER_ON,
800 host->ioaddr + SDHCI_POWER_CONTROL);
802 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
808 /*****************************************************************************\
812 \*****************************************************************************/
814 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
816 struct sdhci_host *host;
819 host = mmc_priv(mmc);
821 spin_lock_irqsave(&host->lock, flags);
823 WARN_ON(host->mrq != NULL);
825 #ifndef CONFIG_LEDS_CLASS
826 sdhci_activate_led(host);
831 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
832 host->mrq->cmd->error = -ENOMEDIUM;
833 tasklet_schedule(&host->finish_tasklet);
835 sdhci_send_command(host, mrq->cmd);
838 spin_unlock_irqrestore(&host->lock, flags);
841 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
843 struct sdhci_host *host;
847 host = mmc_priv(mmc);
849 spin_lock_irqsave(&host->lock, flags);
852 * Reset the chip on each power off.
853 * Should clear out any weird states.
855 if (ios->power_mode == MMC_POWER_OFF) {
856 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
860 sdhci_set_clock(host, ios->clock);
862 if (ios->power_mode == MMC_POWER_OFF)
863 sdhci_set_power(host, -1);
865 sdhci_set_power(host, ios->vdd);
867 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
869 if (ios->bus_width == MMC_BUS_WIDTH_4)
870 ctrl |= SDHCI_CTRL_4BITBUS;
872 ctrl &= ~SDHCI_CTRL_4BITBUS;
874 if (ios->timing == MMC_TIMING_SD_HS)
875 ctrl |= SDHCI_CTRL_HISPD;
877 ctrl &= ~SDHCI_CTRL_HISPD;
879 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
882 * Some (ENE) controllers go apeshit on some ios operation,
883 * signalling timeout and CRC errors even on CMD0. Resetting
884 * it on each ios seems to solve the problem.
886 if(host->chip->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
887 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
890 spin_unlock_irqrestore(&host->lock, flags);
893 static int sdhci_get_ro(struct mmc_host *mmc)
895 struct sdhci_host *host;
899 host = mmc_priv(mmc);
901 spin_lock_irqsave(&host->lock, flags);
903 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
905 spin_unlock_irqrestore(&host->lock, flags);
907 return !(present & SDHCI_WRITE_PROTECT);
910 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
912 struct sdhci_host *host;
916 host = mmc_priv(mmc);
918 spin_lock_irqsave(&host->lock, flags);
920 ier = readl(host->ioaddr + SDHCI_INT_ENABLE);
922 ier &= ~SDHCI_INT_CARD_INT;
924 ier |= SDHCI_INT_CARD_INT;
926 writel(ier, host->ioaddr + SDHCI_INT_ENABLE);
927 writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
931 spin_unlock_irqrestore(&host->lock, flags);
934 static const struct mmc_host_ops sdhci_ops = {
935 .request = sdhci_request,
936 .set_ios = sdhci_set_ios,
937 .get_ro = sdhci_get_ro,
938 .enable_sdio_irq = sdhci_enable_sdio_irq,
941 /*****************************************************************************\
945 \*****************************************************************************/
947 static void sdhci_tasklet_card(unsigned long param)
949 struct sdhci_host *host;
952 host = (struct sdhci_host*)param;
954 spin_lock_irqsave(&host->lock, flags);
956 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
958 printk(KERN_ERR "%s: Card removed during transfer!\n",
959 mmc_hostname(host->mmc));
960 printk(KERN_ERR "%s: Resetting controller.\n",
961 mmc_hostname(host->mmc));
963 sdhci_reset(host, SDHCI_RESET_CMD);
964 sdhci_reset(host, SDHCI_RESET_DATA);
966 host->mrq->cmd->error = -ENOMEDIUM;
967 tasklet_schedule(&host->finish_tasklet);
971 spin_unlock_irqrestore(&host->lock, flags);
973 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
976 static void sdhci_tasklet_finish(unsigned long param)
978 struct sdhci_host *host;
980 struct mmc_request *mrq;
982 host = (struct sdhci_host*)param;
984 spin_lock_irqsave(&host->lock, flags);
986 del_timer(&host->timer);
991 * The controller needs a reset of internal state machines
992 * upon error conditions.
994 if (mrq->cmd->error ||
995 (mrq->data && (mrq->data->error ||
996 (mrq->data->stop && mrq->data->stop->error))) ||
997 (host->chip->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
999 /* Some controllers need this kick or reset won't work here */
1000 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1003 /* This is to force an update */
1004 clock = host->clock;
1006 sdhci_set_clock(host, clock);
1009 /* Spec says we should do both at the same time, but Ricoh
1010 controllers do not like that. */
1011 sdhci_reset(host, SDHCI_RESET_CMD);
1012 sdhci_reset(host, SDHCI_RESET_DATA);
1019 #ifndef CONFIG_LEDS_CLASS
1020 sdhci_deactivate_led(host);
1024 spin_unlock_irqrestore(&host->lock, flags);
1026 mmc_request_done(host->mmc, mrq);
1029 static void sdhci_timeout_timer(unsigned long data)
1031 struct sdhci_host *host;
1032 unsigned long flags;
1034 host = (struct sdhci_host*)data;
1036 spin_lock_irqsave(&host->lock, flags);
1039 printk(KERN_ERR "%s: Timeout waiting for hardware "
1040 "interrupt.\n", mmc_hostname(host->mmc));
1041 sdhci_dumpregs(host);
1044 host->data->error = -ETIMEDOUT;
1045 sdhci_finish_data(host);
1048 host->cmd->error = -ETIMEDOUT;
1050 host->mrq->cmd->error = -ETIMEDOUT;
1052 tasklet_schedule(&host->finish_tasklet);
1057 spin_unlock_irqrestore(&host->lock, flags);
1060 /*****************************************************************************\
1062 * Interrupt handling *
1064 \*****************************************************************************/
1066 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1068 BUG_ON(intmask == 0);
1071 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1072 "though no command operation was in progress.\n",
1073 mmc_hostname(host->mmc), (unsigned)intmask);
1074 sdhci_dumpregs(host);
1078 if (intmask & SDHCI_INT_TIMEOUT)
1079 host->cmd->error = -ETIMEDOUT;
1080 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1082 host->cmd->error = -EILSEQ;
1084 if (host->cmd->error)
1085 tasklet_schedule(&host->finish_tasklet);
1086 else if (intmask & SDHCI_INT_RESPONSE)
1087 sdhci_finish_command(host);
1090 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1092 BUG_ON(intmask == 0);
1096 * A data end interrupt is sent together with the response
1097 * for the stop command.
1099 if (intmask & SDHCI_INT_DATA_END)
1102 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1103 "though no data operation was in progress.\n",
1104 mmc_hostname(host->mmc), (unsigned)intmask);
1105 sdhci_dumpregs(host);
1110 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1111 host->data->error = -ETIMEDOUT;
1112 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1113 host->data->error = -EILSEQ;
1115 if (host->data->error)
1116 sdhci_finish_data(host);
1118 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1119 sdhci_transfer_pio(host);
1122 * We currently don't do anything fancy with DMA
1123 * boundaries, but as we can't disable the feature
1124 * we need to at least restart the transfer.
1126 if (intmask & SDHCI_INT_DMA_END)
1127 writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
1128 host->ioaddr + SDHCI_DMA_ADDRESS);
1130 if (intmask & SDHCI_INT_DATA_END) {
1133 * Data managed to finish before the
1134 * command completed. Make sure we do
1135 * things in the proper order.
1137 host->data_early = 1;
1139 sdhci_finish_data(host);
1145 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1148 struct sdhci_host* host = dev_id;
1152 spin_lock(&host->lock);
1154 intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1156 if (!intmask || intmask == 0xffffffff) {
1161 DBG("*** %s got interrupt: 0x%08x\n",
1162 mmc_hostname(host->mmc), intmask);
1164 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1165 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1166 host->ioaddr + SDHCI_INT_STATUS);
1167 tasklet_schedule(&host->card_tasklet);
1170 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1172 if (intmask & SDHCI_INT_CMD_MASK) {
1173 writel(intmask & SDHCI_INT_CMD_MASK,
1174 host->ioaddr + SDHCI_INT_STATUS);
1175 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1178 if (intmask & SDHCI_INT_DATA_MASK) {
1179 writel(intmask & SDHCI_INT_DATA_MASK,
1180 host->ioaddr + SDHCI_INT_STATUS);
1181 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1184 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1186 intmask &= ~SDHCI_INT_ERROR;
1188 if (intmask & SDHCI_INT_BUS_POWER) {
1189 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1190 mmc_hostname(host->mmc));
1191 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
1194 intmask &= ~SDHCI_INT_BUS_POWER;
1196 if (intmask & SDHCI_INT_CARD_INT)
1199 intmask &= ~SDHCI_INT_CARD_INT;
1202 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1203 mmc_hostname(host->mmc), intmask);
1204 sdhci_dumpregs(host);
1206 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
1209 result = IRQ_HANDLED;
1213 spin_unlock(&host->lock);
1216 * We have to delay this as it calls back into the driver.
1219 mmc_signal_sdio_irq(host->mmc);
1224 /*****************************************************************************\
1228 \*****************************************************************************/
1232 static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1234 struct sdhci_chip *chip;
1237 chip = pci_get_drvdata(pdev);
1241 DBG("Suspending...\n");
1243 for (i = 0;i < chip->num_slots;i++) {
1244 if (!chip->hosts[i])
1246 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1248 for (i--;i >= 0;i--)
1249 mmc_resume_host(chip->hosts[i]->mmc);
1254 pci_save_state(pdev);
1255 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1257 for (i = 0;i < chip->num_slots;i++) {
1258 if (!chip->hosts[i])
1260 free_irq(chip->hosts[i]->irq, chip->hosts[i]);
1263 pci_disable_device(pdev);
1264 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1269 static int sdhci_resume (struct pci_dev *pdev)
1271 struct sdhci_chip *chip;
1274 chip = pci_get_drvdata(pdev);
1278 DBG("Resuming...\n");
1280 pci_set_power_state(pdev, PCI_D0);
1281 pci_restore_state(pdev);
1282 ret = pci_enable_device(pdev);
1286 for (i = 0;i < chip->num_slots;i++) {
1287 if (!chip->hosts[i])
1289 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1290 pci_set_master(pdev);
1291 ret = request_irq(chip->hosts[i]->irq, sdhci_irq,
1292 IRQF_SHARED, mmc_hostname(chip->hosts[i]->mmc),
1296 sdhci_init(chip->hosts[i]);
1298 ret = mmc_resume_host(chip->hosts[i]->mmc);
1306 #else /* CONFIG_PM */
1308 #define sdhci_suspend NULL
1309 #define sdhci_resume NULL
1311 #endif /* CONFIG_PM */
1313 /*****************************************************************************\
1315 * Device probing/removal *
1317 \*****************************************************************************/
1319 static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1322 unsigned int version;
1323 struct sdhci_chip *chip;
1324 struct mmc_host *mmc;
1325 struct sdhci_host *host;
1330 chip = pci_get_drvdata(pdev);
1333 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1337 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1339 if (first_bar > 5) {
1340 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1344 if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1345 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1349 if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
1350 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1351 "You may experience problems.\n");
1354 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1355 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1359 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1360 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1364 mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1368 host = mmc_priv(mmc);
1372 chip->hosts[slot] = host;
1374 host->bar = first_bar + slot;
1376 host->addr = pci_resource_start(pdev, host->bar);
1377 host->irq = pdev->irq;
1379 DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1381 ret = pci_request_region(pdev, host->bar, mmc_hostname(mmc));
1385 host->ioaddr = ioremap_nocache(host->addr,
1386 pci_resource_len(pdev, host->bar));
1387 if (!host->ioaddr) {
1392 sdhci_reset(host, SDHCI_RESET_ALL);
1394 version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1395 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1397 printk(KERN_ERR "%s: Unknown controller version (%d). "
1398 "You may experience problems.\n", mmc_hostname(mmc),
1402 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1404 if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1405 host->flags |= SDHCI_USE_DMA;
1406 else if (!(caps & SDHCI_CAN_DO_DMA))
1407 DBG("Controller doesn't have DMA capability\n");
1409 host->flags |= SDHCI_USE_DMA;
1411 if ((chip->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1412 (host->flags & SDHCI_USE_DMA)) {
1413 DBG("Disabling DMA as it is marked broken\n");
1414 host->flags &= ~SDHCI_USE_DMA;
1417 if (((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1418 (host->flags & SDHCI_USE_DMA)) {
1419 printk(KERN_WARNING "%s: Will use DMA "
1420 "mode even though HW doesn't fully "
1421 "claim to support it.\n", mmc_hostname(mmc));
1424 if (host->flags & SDHCI_USE_DMA) {
1425 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1426 printk(KERN_WARNING "%s: No suitable DMA available. "
1427 "Falling back to PIO.\n", mmc_hostname(mmc));
1428 host->flags &= ~SDHCI_USE_DMA;
1432 if (host->flags & SDHCI_USE_DMA)
1433 pci_set_master(pdev);
1434 else /* XXX: Hack to get MMC layer to avoid highmem */
1438 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1439 if (host->max_clk == 0) {
1440 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1441 "frequency.\n", mmc_hostname(mmc));
1445 host->max_clk *= 1000000;
1448 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1449 if (host->timeout_clk == 0) {
1450 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1451 "frequency.\n", mmc_hostname(mmc));
1455 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1456 host->timeout_clk *= 1000;
1459 * Set host parameters.
1461 mmc->ops = &sdhci_ops;
1462 mmc->f_min = host->max_clk / 256;
1463 mmc->f_max = host->max_clk;
1464 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1466 if (caps & SDHCI_CAN_DO_HISPD)
1467 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1470 if (caps & SDHCI_CAN_VDD_330)
1471 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1472 if (caps & SDHCI_CAN_VDD_300)
1473 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1474 if (caps & SDHCI_CAN_VDD_180)
1475 mmc->ocr_avail |= MMC_VDD_165_195;
1477 if (mmc->ocr_avail == 0) {
1478 printk(KERN_ERR "%s: Hardware doesn't report any "
1479 "support voltages.\n", mmc_hostname(mmc));
1484 spin_lock_init(&host->lock);
1487 * Maximum number of segments. Hardware cannot do scatter lists.
1489 if (host->flags & SDHCI_USE_DMA)
1490 mmc->max_hw_segs = 1;
1492 mmc->max_hw_segs = 16;
1493 mmc->max_phys_segs = 16;
1496 * Maximum number of sectors in one transfer. Limited by DMA boundary
1499 mmc->max_req_size = 524288;
1502 * Maximum segment size. Could be one segment with the maximum number
1505 mmc->max_seg_size = mmc->max_req_size;
1508 * Maximum block size. This varies from controller to controller and
1509 * is specified in the capabilities register.
1511 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1512 if (mmc->max_blk_size >= 3) {
1513 printk(KERN_WARNING "%s: Invalid maximum block size, "
1514 "assuming 512 bytes\n", mmc_hostname(mmc));
1515 mmc->max_blk_size = 512;
1517 mmc->max_blk_size = 512 << mmc->max_blk_size;
1520 * Maximum block count.
1522 mmc->max_blk_count = 65535;
1527 tasklet_init(&host->card_tasklet,
1528 sdhci_tasklet_card, (unsigned long)host);
1529 tasklet_init(&host->finish_tasklet,
1530 sdhci_tasklet_finish, (unsigned long)host);
1532 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1534 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1535 mmc_hostname(mmc), host);
1541 #ifdef CONFIG_MMC_DEBUG
1542 sdhci_dumpregs(host);
1545 #ifdef CONFIG_LEDS_CLASS
1546 host->led.name = mmc_hostname(mmc);
1547 host->led.brightness = LED_OFF;
1548 host->led.default_trigger = mmc_hostname(mmc);
1549 host->led.brightness_set = sdhci_led_control;
1551 ret = led_classdev_register(&pdev->dev, &host->led);
1560 printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n",
1561 mmc_hostname(mmc), host->addr, host->irq,
1562 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1566 #ifdef CONFIG_LEDS_CLASS
1568 sdhci_reset(host, SDHCI_RESET_ALL);
1569 free_irq(host->irq, host);
1572 tasklet_kill(&host->card_tasklet);
1573 tasklet_kill(&host->finish_tasklet);
1575 iounmap(host->ioaddr);
1577 pci_release_region(pdev, host->bar);
1584 static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1586 struct sdhci_chip *chip;
1587 struct mmc_host *mmc;
1588 struct sdhci_host *host;
1590 chip = pci_get_drvdata(pdev);
1591 host = chip->hosts[slot];
1594 chip->hosts[slot] = NULL;
1596 mmc_remove_host(mmc);
1598 #ifdef CONFIG_LEDS_CLASS
1599 led_classdev_unregister(&host->led);
1602 sdhci_reset(host, SDHCI_RESET_ALL);
1604 free_irq(host->irq, host);
1606 del_timer_sync(&host->timer);
1608 tasklet_kill(&host->card_tasklet);
1609 tasklet_kill(&host->finish_tasklet);
1611 iounmap(host->ioaddr);
1613 pci_release_region(pdev, host->bar);
1618 static int __devinit sdhci_probe(struct pci_dev *pdev,
1619 const struct pci_device_id *ent)
1623 struct sdhci_chip *chip;
1625 BUG_ON(pdev == NULL);
1626 BUG_ON(ent == NULL);
1628 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1630 printk(KERN_INFO DRIVER_NAME
1631 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1632 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1635 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1639 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1640 DBG("found %d slot(s)\n", slots);
1644 ret = pci_enable_device(pdev);
1648 chip = kzalloc(sizeof(struct sdhci_chip) +
1649 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1656 chip->quirks = ent->driver_data;
1659 chip->quirks = debug_quirks;
1661 chip->num_slots = slots;
1662 pci_set_drvdata(pdev, chip);
1664 for (i = 0;i < slots;i++) {
1665 ret = sdhci_probe_slot(pdev, i);
1667 for (i--;i >= 0;i--)
1668 sdhci_remove_slot(pdev, i);
1676 pci_set_drvdata(pdev, NULL);
1680 pci_disable_device(pdev);
1684 static void __devexit sdhci_remove(struct pci_dev *pdev)
1687 struct sdhci_chip *chip;
1689 chip = pci_get_drvdata(pdev);
1692 for (i = 0;i < chip->num_slots;i++)
1693 sdhci_remove_slot(pdev, i);
1695 pci_set_drvdata(pdev, NULL);
1700 pci_disable_device(pdev);
1703 static struct pci_driver sdhci_driver = {
1704 .name = DRIVER_NAME,
1705 .id_table = pci_ids,
1706 .probe = sdhci_probe,
1707 .remove = __devexit_p(sdhci_remove),
1708 .suspend = sdhci_suspend,
1709 .resume = sdhci_resume,
1712 /*****************************************************************************\
1714 * Driver init/exit *
1716 \*****************************************************************************/
1718 static int __init sdhci_drv_init(void)
1720 printk(KERN_INFO DRIVER_NAME
1721 ": Secure Digital Host Controller Interface driver\n");
1722 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1724 return pci_register_driver(&sdhci_driver);
1727 static void __exit sdhci_drv_exit(void)
1731 pci_unregister_driver(&sdhci_driver);
1734 module_init(sdhci_drv_init);
1735 module_exit(sdhci_drv_exit);
1737 module_param(debug_quirks, uint, 0444);
1739 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1740 MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
1741 MODULE_LICENSE("GPL");
1743 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");