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sdhci: highmem capable PIO routines
[linux-2.6] / drivers / mmc / host / sdhci.c
1 /*
2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3  *
4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or (at
9  * your option) any later version.
10  *
11  * Thanks to the following companies for their support:
12  *
13  *     - JMicron (hardware and technical support)
14  */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/scatterlist.h>
21
22 #include <linux/leds.h>
23
24 #include <linux/mmc/host.h>
25
26 #include "sdhci.h"
27
28 #define DRIVER_NAME "sdhci"
29
30 #define DBG(f, x...) \
31         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
32
33 static unsigned int debug_quirks = 0;
34
35 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
36 static void sdhci_finish_data(struct sdhci_host *);
37
38 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
39 static void sdhci_finish_command(struct sdhci_host *);
40
41 static void sdhci_dumpregs(struct sdhci_host *host)
42 {
43         printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
44
45         printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
46                 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
47                 readw(host->ioaddr + SDHCI_HOST_VERSION));
48         printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
49                 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
50                 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
51         printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
52                 readl(host->ioaddr + SDHCI_ARGUMENT),
53                 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
54         printk(KERN_DEBUG DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
55                 readl(host->ioaddr + SDHCI_PRESENT_STATE),
56                 readb(host->ioaddr + SDHCI_HOST_CONTROL));
57         printk(KERN_DEBUG DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
58                 readb(host->ioaddr + SDHCI_POWER_CONTROL),
59                 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
60         printk(KERN_DEBUG DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
61                 readb(host->ioaddr + SDHCI_WAKE_UP_CONTROL),
62                 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
63         printk(KERN_DEBUG DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
64                 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
65                 readl(host->ioaddr + SDHCI_INT_STATUS));
66         printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
67                 readl(host->ioaddr + SDHCI_INT_ENABLE),
68                 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
69         printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
70                 readw(host->ioaddr + SDHCI_ACMD12_ERR),
71                 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
72         printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Max curr: 0x%08x\n",
73                 readl(host->ioaddr + SDHCI_CAPABILITIES),
74                 readl(host->ioaddr + SDHCI_MAX_CURRENT));
75
76         printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
77 }
78
79 /*****************************************************************************\
80  *                                                                           *
81  * Low level functions                                                       *
82  *                                                                           *
83 \*****************************************************************************/
84
85 static void sdhci_reset(struct sdhci_host *host, u8 mask)
86 {
87         unsigned long timeout;
88
89         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
90                 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
91                         SDHCI_CARD_PRESENT))
92                         return;
93         }
94
95         writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
96
97         if (mask & SDHCI_RESET_ALL)
98                 host->clock = 0;
99
100         /* Wait max 100 ms */
101         timeout = 100;
102
103         /* hw clears the bit when it's done */
104         while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
105                 if (timeout == 0) {
106                         printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
107                                 mmc_hostname(host->mmc), (int)mask);
108                         sdhci_dumpregs(host);
109                         return;
110                 }
111                 timeout--;
112                 mdelay(1);
113         }
114 }
115
116 static void sdhci_init(struct sdhci_host *host)
117 {
118         u32 intmask;
119
120         sdhci_reset(host, SDHCI_RESET_ALL);
121
122         intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
123                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
124                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
125                 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
126                 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
127                 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
128                 SDHCI_INT_ADMA_ERROR;
129
130         writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
131         writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
132 }
133
134 static void sdhci_activate_led(struct sdhci_host *host)
135 {
136         u8 ctrl;
137
138         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
139         ctrl |= SDHCI_CTRL_LED;
140         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
141 }
142
143 static void sdhci_deactivate_led(struct sdhci_host *host)
144 {
145         u8 ctrl;
146
147         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
148         ctrl &= ~SDHCI_CTRL_LED;
149         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
150 }
151
152 #ifdef CONFIG_LEDS_CLASS
153 static void sdhci_led_control(struct led_classdev *led,
154         enum led_brightness brightness)
155 {
156         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
157         unsigned long flags;
158
159         spin_lock_irqsave(&host->lock, flags);
160
161         if (brightness == LED_OFF)
162                 sdhci_deactivate_led(host);
163         else
164                 sdhci_activate_led(host);
165
166         spin_unlock_irqrestore(&host->lock, flags);
167 }
168 #endif
169
170 /*****************************************************************************\
171  *                                                                           *
172  * Core functions                                                            *
173  *                                                                           *
174 \*****************************************************************************/
175
176 static void sdhci_read_block_pio(struct sdhci_host *host)
177 {
178         unsigned long flags;
179         size_t blksize, len, chunk;
180         u32 scratch;
181         u8 *buf;
182
183         DBG("PIO reading\n");
184
185         blksize = host->data->blksz;
186         chunk = 0;
187
188         local_irq_save(flags);
189
190         while (blksize) {
191                 if (!sg_miter_next(&host->sg_miter))
192                         BUG();
193
194                 len = min(host->sg_miter.length, blksize);
195
196                 blksize -= len;
197                 host->sg_miter.consumed = len;
198
199                 buf = host->sg_miter.addr;
200
201                 while (len) {
202                         if (chunk == 0) {
203                                 scratch = readl(host->ioaddr + SDHCI_BUFFER);
204                                 chunk = 4;
205                         }
206
207                         *buf = scratch & 0xFF;
208
209                         buf++;
210                         scratch >>= 8;
211                         chunk--;
212                         len--;
213                 }
214         }
215
216         sg_miter_stop(&host->sg_miter);
217
218         local_irq_restore(flags);
219 }
220
221 static void sdhci_write_block_pio(struct sdhci_host *host)
222 {
223         unsigned long flags;
224         size_t blksize, len, chunk;
225         u32 scratch;
226         u8 *buf;
227
228         DBG("PIO writing\n");
229
230         blksize = host->data->blksz;
231         chunk = 0;
232         scratch = 0;
233
234         local_irq_save(flags);
235
236         while (blksize) {
237                 if (!sg_miter_next(&host->sg_miter))
238                         BUG();
239
240                 len = min(host->sg_miter.length, blksize);
241
242                 blksize -= len;
243                 host->sg_miter.consumed = len;
244
245                 buf = host->sg_miter.addr;
246
247                 while (len) {
248                         scratch |= (u32)*buf << (chunk * 8);
249
250                         buf++;
251                         chunk++;
252                         len--;
253
254                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
255                                 writel(scratch, host->ioaddr + SDHCI_BUFFER);
256                                 chunk = 0;
257                                 scratch = 0;
258                         }
259                 }
260         }
261
262         sg_miter_stop(&host->sg_miter);
263
264         local_irq_restore(flags);
265 }
266
267 static void sdhci_transfer_pio(struct sdhci_host *host)
268 {
269         u32 mask;
270
271         BUG_ON(!host->data);
272
273         if (host->blocks == 0)
274                 return;
275
276         if (host->data->flags & MMC_DATA_READ)
277                 mask = SDHCI_DATA_AVAILABLE;
278         else
279                 mask = SDHCI_SPACE_AVAILABLE;
280
281         while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
282                 if (host->data->flags & MMC_DATA_READ)
283                         sdhci_read_block_pio(host);
284                 else
285                         sdhci_write_block_pio(host);
286
287                 host->blocks--;
288                 if (host->blocks == 0)
289                         break;
290         }
291
292         DBG("PIO transfer complete.\n");
293 }
294
295 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
296 {
297         local_irq_save(*flags);
298         return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
299 }
300
301 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
302 {
303         kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
304         local_irq_restore(*flags);
305 }
306
307 static int sdhci_adma_table_pre(struct sdhci_host *host,
308         struct mmc_data *data)
309 {
310         int direction;
311
312         u8 *desc;
313         u8 *align;
314         dma_addr_t addr;
315         dma_addr_t align_addr;
316         int len, offset;
317
318         struct scatterlist *sg;
319         int i;
320         char *buffer;
321         unsigned long flags;
322
323         /*
324          * The spec does not specify endianness of descriptor table.
325          * We currently guess that it is LE.
326          */
327
328         if (data->flags & MMC_DATA_READ)
329                 direction = DMA_FROM_DEVICE;
330         else
331                 direction = DMA_TO_DEVICE;
332
333         /*
334          * The ADMA descriptor table is mapped further down as we
335          * need to fill it with data first.
336          */
337
338         host->align_addr = dma_map_single(mmc_dev(host->mmc),
339                 host->align_buffer, 128 * 4, direction);
340         if (dma_mapping_error(host->align_addr))
341                 goto fail;
342         BUG_ON(host->align_addr & 0x3);
343
344         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
345                 data->sg, data->sg_len, direction);
346         if (host->sg_count == 0)
347                 goto unmap_align;
348
349         desc = host->adma_desc;
350         align = host->align_buffer;
351
352         align_addr = host->align_addr;
353
354         for_each_sg(data->sg, sg, host->sg_count, i) {
355                 addr = sg_dma_address(sg);
356                 len = sg_dma_len(sg);
357
358                 /*
359                  * The SDHCI specification states that ADMA
360                  * addresses must be 32-bit aligned. If they
361                  * aren't, then we use a bounce buffer for
362                  * the (up to three) bytes that screw up the
363                  * alignment.
364                  */
365                 offset = (4 - (addr & 0x3)) & 0x3;
366                 if (offset) {
367                         if (data->flags & MMC_DATA_WRITE) {
368                                 buffer = sdhci_kmap_atomic(sg, &flags);
369                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
370                                 memcpy(align, buffer, offset);
371                                 sdhci_kunmap_atomic(buffer, &flags);
372                         }
373
374                         desc[7] = (align_addr >> 24) & 0xff;
375                         desc[6] = (align_addr >> 16) & 0xff;
376                         desc[5] = (align_addr >> 8) & 0xff;
377                         desc[4] = (align_addr >> 0) & 0xff;
378
379                         BUG_ON(offset > 65536);
380
381                         desc[3] = (offset >> 8) & 0xff;
382                         desc[2] = (offset >> 0) & 0xff;
383
384                         desc[1] = 0x00;
385                         desc[0] = 0x21; /* tran, valid */
386
387                         align += 4;
388                         align_addr += 4;
389
390                         desc += 8;
391
392                         addr += offset;
393                         len -= offset;
394                 }
395
396                 desc[7] = (addr >> 24) & 0xff;
397                 desc[6] = (addr >> 16) & 0xff;
398                 desc[5] = (addr >> 8) & 0xff;
399                 desc[4] = (addr >> 0) & 0xff;
400
401                 BUG_ON(len > 65536);
402
403                 desc[3] = (len >> 8) & 0xff;
404                 desc[2] = (len >> 0) & 0xff;
405
406                 desc[1] = 0x00;
407                 desc[0] = 0x21; /* tran, valid */
408
409                 desc += 8;
410
411                 /*
412                  * If this triggers then we have a calculation bug
413                  * somewhere. :/
414                  */
415                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
416         }
417
418         /*
419          * Add a terminating entry.
420          */
421         desc[7] = 0;
422         desc[6] = 0;
423         desc[5] = 0;
424         desc[4] = 0;
425
426         desc[3] = 0;
427         desc[2] = 0;
428
429         desc[1] = 0x00;
430         desc[0] = 0x03; /* nop, end, valid */
431
432         /*
433          * Resync align buffer as we might have changed it.
434          */
435         if (data->flags & MMC_DATA_WRITE) {
436                 dma_sync_single_for_device(mmc_dev(host->mmc),
437                         host->align_addr, 128 * 4, direction);
438         }
439
440         host->adma_addr = dma_map_single(mmc_dev(host->mmc),
441                 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
442         if (dma_mapping_error(host->align_addr))
443                 goto unmap_entries;
444         BUG_ON(host->adma_addr & 0x3);
445
446         return 0;
447
448 unmap_entries:
449         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
450                 data->sg_len, direction);
451 unmap_align:
452         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
453                 128 * 4, direction);
454 fail:
455         return -EINVAL;
456 }
457
458 static void sdhci_adma_table_post(struct sdhci_host *host,
459         struct mmc_data *data)
460 {
461         int direction;
462
463         struct scatterlist *sg;
464         int i, size;
465         u8 *align;
466         char *buffer;
467         unsigned long flags;
468
469         if (data->flags & MMC_DATA_READ)
470                 direction = DMA_FROM_DEVICE;
471         else
472                 direction = DMA_TO_DEVICE;
473
474         dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
475                 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
476
477         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
478                 128 * 4, direction);
479
480         if (data->flags & MMC_DATA_READ) {
481                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
482                         data->sg_len, direction);
483
484                 align = host->align_buffer;
485
486                 for_each_sg(data->sg, sg, host->sg_count, i) {
487                         if (sg_dma_address(sg) & 0x3) {
488                                 size = 4 - (sg_dma_address(sg) & 0x3);
489
490                                 buffer = sdhci_kmap_atomic(sg, &flags);
491                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
492                                 memcpy(buffer, align, size);
493                                 sdhci_kunmap_atomic(buffer, &flags);
494
495                                 align += 4;
496                         }
497                 }
498         }
499
500         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
501                 data->sg_len, direction);
502 }
503
504 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
505 {
506         u8 count;
507         unsigned target_timeout, current_timeout;
508
509         /*
510          * If the host controller provides us with an incorrect timeout
511          * value, just skip the check and use 0xE.  The hardware may take
512          * longer to time out, but that's much better than having a too-short
513          * timeout value.
514          */
515         if ((host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL))
516                 return 0xE;
517
518         /* timeout in us */
519         target_timeout = data->timeout_ns / 1000 +
520                 data->timeout_clks / host->clock;
521
522         /*
523          * Figure out needed cycles.
524          * We do this in steps in order to fit inside a 32 bit int.
525          * The first step is the minimum timeout, which will have a
526          * minimum resolution of 6 bits:
527          * (1) 2^13*1000 > 2^22,
528          * (2) host->timeout_clk < 2^16
529          *     =>
530          *     (1) / (2) > 2^6
531          */
532         count = 0;
533         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
534         while (current_timeout < target_timeout) {
535                 count++;
536                 current_timeout <<= 1;
537                 if (count >= 0xF)
538                         break;
539         }
540
541         if (count >= 0xF) {
542                 printk(KERN_WARNING "%s: Too large timeout requested!\n",
543                         mmc_hostname(host->mmc));
544                 count = 0xE;
545         }
546
547         return count;
548 }
549
550 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
551 {
552         u8 count;
553         u8 ctrl;
554         int ret;
555
556         WARN_ON(host->data);
557
558         if (data == NULL)
559                 return;
560
561         /* Sanity checks */
562         BUG_ON(data->blksz * data->blocks > 524288);
563         BUG_ON(data->blksz > host->mmc->max_blk_size);
564         BUG_ON(data->blocks > 65535);
565
566         host->data = data;
567         host->data_early = 0;
568
569         count = sdhci_calc_timeout(host, data);
570         writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
571
572         if (host->flags & SDHCI_USE_DMA)
573                 host->flags |= SDHCI_REQ_USE_DMA;
574
575         /*
576          * FIXME: This doesn't account for merging when mapping the
577          * scatterlist.
578          */
579         if (host->flags & SDHCI_REQ_USE_DMA) {
580                 int broken, i;
581                 struct scatterlist *sg;
582
583                 broken = 0;
584                 if (host->flags & SDHCI_USE_ADMA) {
585                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
586                                 broken = 1;
587                 } else {
588                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
589                                 broken = 1;
590                 }
591
592                 if (unlikely(broken)) {
593                         for_each_sg(data->sg, sg, data->sg_len, i) {
594                                 if (sg->length & 0x3) {
595                                         DBG("Reverting to PIO because of "
596                                                 "transfer size (%d)\n",
597                                                 sg->length);
598                                         host->flags &= ~SDHCI_REQ_USE_DMA;
599                                         break;
600                                 }
601                         }
602                 }
603         }
604
605         /*
606          * The assumption here being that alignment is the same after
607          * translation to device address space.
608          */
609         if (host->flags & SDHCI_REQ_USE_DMA) {
610                 int broken, i;
611                 struct scatterlist *sg;
612
613                 broken = 0;
614                 if (host->flags & SDHCI_USE_ADMA) {
615                         /*
616                          * As we use 3 byte chunks to work around
617                          * alignment problems, we need to check this
618                          * quirk.
619                          */
620                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
621                                 broken = 1;
622                 } else {
623                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
624                                 broken = 1;
625                 }
626
627                 if (unlikely(broken)) {
628                         for_each_sg(data->sg, sg, data->sg_len, i) {
629                                 if (sg->offset & 0x3) {
630                                         DBG("Reverting to PIO because of "
631                                                 "bad alignment\n");
632                                         host->flags &= ~SDHCI_REQ_USE_DMA;
633                                         break;
634                                 }
635                         }
636                 }
637         }
638
639         if (host->flags & SDHCI_REQ_USE_DMA) {
640                 if (host->flags & SDHCI_USE_ADMA) {
641                         ret = sdhci_adma_table_pre(host, data);
642                         if (ret) {
643                                 /*
644                                  * This only happens when someone fed
645                                  * us an invalid request.
646                                  */
647                                 WARN_ON(1);
648                                 host->flags &= ~SDHCI_USE_DMA;
649                         } else {
650                                 writel(host->adma_addr,
651                                         host->ioaddr + SDHCI_ADMA_ADDRESS);
652                         }
653                 } else {
654                         int sg_cnt;
655
656                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
657                                         data->sg, data->sg_len,
658                                         (data->flags & MMC_DATA_READ) ?
659                                                 DMA_FROM_DEVICE :
660                                                 DMA_TO_DEVICE);
661                         if (sg_cnt == 0) {
662                                 /*
663                                  * This only happens when someone fed
664                                  * us an invalid request.
665                                  */
666                                 WARN_ON(1);
667                                 host->flags &= ~SDHCI_USE_DMA;
668                         } else {
669                                 WARN_ON(sg_cnt != 1);
670                                 writel(sg_dma_address(data->sg),
671                                         host->ioaddr + SDHCI_DMA_ADDRESS);
672                         }
673                 }
674         }
675
676         /*
677          * Always adjust the DMA selection as some controllers
678          * (e.g. JMicron) can't do PIO properly when the selection
679          * is ADMA.
680          */
681         if (host->version >= SDHCI_SPEC_200) {
682                 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
683                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
684                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
685                         (host->flags & SDHCI_USE_ADMA))
686                         ctrl |= SDHCI_CTRL_ADMA32;
687                 else
688                         ctrl |= SDHCI_CTRL_SDMA;
689                 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
690         }
691
692         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
693                 sg_miter_start(&host->sg_miter,
694                         data->sg, data->sg_len, SG_MITER_ATOMIC);
695                 host->blocks = data->blocks;
696         }
697
698         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
699         writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
700                 host->ioaddr + SDHCI_BLOCK_SIZE);
701         writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
702 }
703
704 static void sdhci_set_transfer_mode(struct sdhci_host *host,
705         struct mmc_data *data)
706 {
707         u16 mode;
708
709         if (data == NULL)
710                 return;
711
712         WARN_ON(!host->data);
713
714         mode = SDHCI_TRNS_BLK_CNT_EN;
715         if (data->blocks > 1)
716                 mode |= SDHCI_TRNS_MULTI;
717         if (data->flags & MMC_DATA_READ)
718                 mode |= SDHCI_TRNS_READ;
719         if (host->flags & SDHCI_REQ_USE_DMA)
720                 mode |= SDHCI_TRNS_DMA;
721
722         writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
723 }
724
725 static void sdhci_finish_data(struct sdhci_host *host)
726 {
727         struct mmc_data *data;
728
729         BUG_ON(!host->data);
730
731         data = host->data;
732         host->data = NULL;
733
734         if (host->flags & SDHCI_REQ_USE_DMA) {
735                 if (host->flags & SDHCI_USE_ADMA)
736                         sdhci_adma_table_post(host, data);
737                 else {
738                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
739                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
740                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
741                 }
742         }
743
744         /*
745          * The specification states that the block count register must
746          * be updated, but it does not specify at what point in the
747          * data flow. That makes the register entirely useless to read
748          * back so we have to assume that nothing made it to the card
749          * in the event of an error.
750          */
751         if (data->error)
752                 data->bytes_xfered = 0;
753         else
754                 data->bytes_xfered = data->blksz * data->blocks;
755
756         if (data->stop) {
757                 /*
758                  * The controller needs a reset of internal state machines
759                  * upon error conditions.
760                  */
761                 if (data->error) {
762                         sdhci_reset(host, SDHCI_RESET_CMD);
763                         sdhci_reset(host, SDHCI_RESET_DATA);
764                 }
765
766                 sdhci_send_command(host, data->stop);
767         } else
768                 tasklet_schedule(&host->finish_tasklet);
769 }
770
771 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
772 {
773         int flags;
774         u32 mask;
775         unsigned long timeout;
776
777         WARN_ON(host->cmd);
778
779         /* Wait max 10 ms */
780         timeout = 10;
781
782         mask = SDHCI_CMD_INHIBIT;
783         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
784                 mask |= SDHCI_DATA_INHIBIT;
785
786         /* We shouldn't wait for data inihibit for stop commands, even
787            though they might use busy signaling */
788         if (host->mrq->data && (cmd == host->mrq->data->stop))
789                 mask &= ~SDHCI_DATA_INHIBIT;
790
791         while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
792                 if (timeout == 0) {
793                         printk(KERN_ERR "%s: Controller never released "
794                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
795                         sdhci_dumpregs(host);
796                         cmd->error = -EIO;
797                         tasklet_schedule(&host->finish_tasklet);
798                         return;
799                 }
800                 timeout--;
801                 mdelay(1);
802         }
803
804         mod_timer(&host->timer, jiffies + 10 * HZ);
805
806         host->cmd = cmd;
807
808         sdhci_prepare_data(host, cmd->data);
809
810         writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
811
812         sdhci_set_transfer_mode(host, cmd->data);
813
814         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
815                 printk(KERN_ERR "%s: Unsupported response type!\n",
816                         mmc_hostname(host->mmc));
817                 cmd->error = -EINVAL;
818                 tasklet_schedule(&host->finish_tasklet);
819                 return;
820         }
821
822         if (!(cmd->flags & MMC_RSP_PRESENT))
823                 flags = SDHCI_CMD_RESP_NONE;
824         else if (cmd->flags & MMC_RSP_136)
825                 flags = SDHCI_CMD_RESP_LONG;
826         else if (cmd->flags & MMC_RSP_BUSY)
827                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
828         else
829                 flags = SDHCI_CMD_RESP_SHORT;
830
831         if (cmd->flags & MMC_RSP_CRC)
832                 flags |= SDHCI_CMD_CRC;
833         if (cmd->flags & MMC_RSP_OPCODE)
834                 flags |= SDHCI_CMD_INDEX;
835         if (cmd->data)
836                 flags |= SDHCI_CMD_DATA;
837
838         writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
839                 host->ioaddr + SDHCI_COMMAND);
840 }
841
842 static void sdhci_finish_command(struct sdhci_host *host)
843 {
844         int i;
845
846         BUG_ON(host->cmd == NULL);
847
848         if (host->cmd->flags & MMC_RSP_PRESENT) {
849                 if (host->cmd->flags & MMC_RSP_136) {
850                         /* CRC is stripped so we need to do some shifting. */
851                         for (i = 0;i < 4;i++) {
852                                 host->cmd->resp[i] = readl(host->ioaddr +
853                                         SDHCI_RESPONSE + (3-i)*4) << 8;
854                                 if (i != 3)
855                                         host->cmd->resp[i] |=
856                                                 readb(host->ioaddr +
857                                                 SDHCI_RESPONSE + (3-i)*4-1);
858                         }
859                 } else {
860                         host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
861                 }
862         }
863
864         host->cmd->error = 0;
865
866         if (host->data && host->data_early)
867                 sdhci_finish_data(host);
868
869         if (!host->cmd->data)
870                 tasklet_schedule(&host->finish_tasklet);
871
872         host->cmd = NULL;
873 }
874
875 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
876 {
877         int div;
878         u16 clk;
879         unsigned long timeout;
880
881         if (clock == host->clock)
882                 return;
883
884         writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
885
886         if (clock == 0)
887                 goto out;
888
889         for (div = 1;div < 256;div *= 2) {
890                 if ((host->max_clk / div) <= clock)
891                         break;
892         }
893         div >>= 1;
894
895         clk = div << SDHCI_DIVIDER_SHIFT;
896         clk |= SDHCI_CLOCK_INT_EN;
897         writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
898
899         /* Wait max 10 ms */
900         timeout = 10;
901         while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
902                 & SDHCI_CLOCK_INT_STABLE)) {
903                 if (timeout == 0) {
904                         printk(KERN_ERR "%s: Internal clock never "
905                                 "stabilised.\n", mmc_hostname(host->mmc));
906                         sdhci_dumpregs(host);
907                         return;
908                 }
909                 timeout--;
910                 mdelay(1);
911         }
912
913         clk |= SDHCI_CLOCK_CARD_EN;
914         writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
915
916 out:
917         host->clock = clock;
918 }
919
920 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
921 {
922         u8 pwr;
923
924         if (host->power == power)
925                 return;
926
927         if (power == (unsigned short)-1) {
928                 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
929                 goto out;
930         }
931
932         /*
933          * Spec says that we should clear the power reg before setting
934          * a new value. Some controllers don't seem to like this though.
935          */
936         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
937                 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
938
939         pwr = SDHCI_POWER_ON;
940
941         switch (1 << power) {
942         case MMC_VDD_165_195:
943                 pwr |= SDHCI_POWER_180;
944                 break;
945         case MMC_VDD_29_30:
946         case MMC_VDD_30_31:
947                 pwr |= SDHCI_POWER_300;
948                 break;
949         case MMC_VDD_32_33:
950         case MMC_VDD_33_34:
951                 pwr |= SDHCI_POWER_330;
952                 break;
953         default:
954                 BUG();
955         }
956
957         /*
958          * At least the Marvell CaFe chip gets confused if we set the voltage
959          * and set turn on power at the same time, so set the voltage first.
960          */
961         if ((host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER))
962                 writeb(pwr & ~SDHCI_POWER_ON,
963                                 host->ioaddr + SDHCI_POWER_CONTROL);
964
965         writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
966
967 out:
968         host->power = power;
969 }
970
971 /*****************************************************************************\
972  *                                                                           *
973  * MMC callbacks                                                             *
974  *                                                                           *
975 \*****************************************************************************/
976
977 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
978 {
979         struct sdhci_host *host;
980         unsigned long flags;
981
982         host = mmc_priv(mmc);
983
984         spin_lock_irqsave(&host->lock, flags);
985
986         WARN_ON(host->mrq != NULL);
987
988 #ifndef CONFIG_LEDS_CLASS
989         sdhci_activate_led(host);
990 #endif
991
992         host->mrq = mrq;
993
994         if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)
995                 || (host->flags & SDHCI_DEVICE_DEAD)) {
996                 host->mrq->cmd->error = -ENOMEDIUM;
997                 tasklet_schedule(&host->finish_tasklet);
998         } else
999                 sdhci_send_command(host, mrq->cmd);
1000
1001         mmiowb();
1002         spin_unlock_irqrestore(&host->lock, flags);
1003 }
1004
1005 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1006 {
1007         struct sdhci_host *host;
1008         unsigned long flags;
1009         u8 ctrl;
1010
1011         host = mmc_priv(mmc);
1012
1013         spin_lock_irqsave(&host->lock, flags);
1014
1015         if (host->flags & SDHCI_DEVICE_DEAD)
1016                 goto out;
1017
1018         /*
1019          * Reset the chip on each power off.
1020          * Should clear out any weird states.
1021          */
1022         if (ios->power_mode == MMC_POWER_OFF) {
1023                 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
1024                 sdhci_init(host);
1025         }
1026
1027         sdhci_set_clock(host, ios->clock);
1028
1029         if (ios->power_mode == MMC_POWER_OFF)
1030                 sdhci_set_power(host, -1);
1031         else
1032                 sdhci_set_power(host, ios->vdd);
1033
1034         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
1035
1036         if (ios->bus_width == MMC_BUS_WIDTH_4)
1037                 ctrl |= SDHCI_CTRL_4BITBUS;
1038         else
1039                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1040
1041         if (ios->timing == MMC_TIMING_SD_HS)
1042                 ctrl |= SDHCI_CTRL_HISPD;
1043         else
1044                 ctrl &= ~SDHCI_CTRL_HISPD;
1045
1046         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
1047
1048         /*
1049          * Some (ENE) controllers go apeshit on some ios operation,
1050          * signalling timeout and CRC errors even on CMD0. Resetting
1051          * it on each ios seems to solve the problem.
1052          */
1053         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1054                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1055
1056 out:
1057         mmiowb();
1058         spin_unlock_irqrestore(&host->lock, flags);
1059 }
1060
1061 static int sdhci_get_ro(struct mmc_host *mmc)
1062 {
1063         struct sdhci_host *host;
1064         unsigned long flags;
1065         int present;
1066
1067         host = mmc_priv(mmc);
1068
1069         spin_lock_irqsave(&host->lock, flags);
1070
1071         if (host->flags & SDHCI_DEVICE_DEAD)
1072                 present = 0;
1073         else
1074                 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
1075
1076         spin_unlock_irqrestore(&host->lock, flags);
1077
1078         return !(present & SDHCI_WRITE_PROTECT);
1079 }
1080
1081 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1082 {
1083         struct sdhci_host *host;
1084         unsigned long flags;
1085         u32 ier;
1086
1087         host = mmc_priv(mmc);
1088
1089         spin_lock_irqsave(&host->lock, flags);
1090
1091         if (host->flags & SDHCI_DEVICE_DEAD)
1092                 goto out;
1093
1094         ier = readl(host->ioaddr + SDHCI_INT_ENABLE);
1095
1096         ier &= ~SDHCI_INT_CARD_INT;
1097         if (enable)
1098                 ier |= SDHCI_INT_CARD_INT;
1099
1100         writel(ier, host->ioaddr + SDHCI_INT_ENABLE);
1101         writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
1102
1103 out:
1104         mmiowb();
1105
1106         spin_unlock_irqrestore(&host->lock, flags);
1107 }
1108
1109 static const struct mmc_host_ops sdhci_ops = {
1110         .request        = sdhci_request,
1111         .set_ios        = sdhci_set_ios,
1112         .get_ro         = sdhci_get_ro,
1113         .enable_sdio_irq = sdhci_enable_sdio_irq,
1114 };
1115
1116 /*****************************************************************************\
1117  *                                                                           *
1118  * Tasklets                                                                  *
1119  *                                                                           *
1120 \*****************************************************************************/
1121
1122 static void sdhci_tasklet_card(unsigned long param)
1123 {
1124         struct sdhci_host *host;
1125         unsigned long flags;
1126
1127         host = (struct sdhci_host*)param;
1128
1129         spin_lock_irqsave(&host->lock, flags);
1130
1131         if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1132                 if (host->mrq) {
1133                         printk(KERN_ERR "%s: Card removed during transfer!\n",
1134                                 mmc_hostname(host->mmc));
1135                         printk(KERN_ERR "%s: Resetting controller.\n",
1136                                 mmc_hostname(host->mmc));
1137
1138                         sdhci_reset(host, SDHCI_RESET_CMD);
1139                         sdhci_reset(host, SDHCI_RESET_DATA);
1140
1141                         host->mrq->cmd->error = -ENOMEDIUM;
1142                         tasklet_schedule(&host->finish_tasklet);
1143                 }
1144         }
1145
1146         spin_unlock_irqrestore(&host->lock, flags);
1147
1148         mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1149 }
1150
1151 static void sdhci_tasklet_finish(unsigned long param)
1152 {
1153         struct sdhci_host *host;
1154         unsigned long flags;
1155         struct mmc_request *mrq;
1156
1157         host = (struct sdhci_host*)param;
1158
1159         spin_lock_irqsave(&host->lock, flags);
1160
1161         del_timer(&host->timer);
1162
1163         mrq = host->mrq;
1164
1165         /*
1166          * The controller needs a reset of internal state machines
1167          * upon error conditions.
1168          */
1169         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1170                 (mrq->cmd->error ||
1171                  (mrq->data && (mrq->data->error ||
1172                   (mrq->data->stop && mrq->data->stop->error))) ||
1173                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1174
1175                 /* Some controllers need this kick or reset won't work here */
1176                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1177                         unsigned int clock;
1178
1179                         /* This is to force an update */
1180                         clock = host->clock;
1181                         host->clock = 0;
1182                         sdhci_set_clock(host, clock);
1183                 }
1184
1185                 /* Spec says we should do both at the same time, but Ricoh
1186                    controllers do not like that. */
1187                 sdhci_reset(host, SDHCI_RESET_CMD);
1188                 sdhci_reset(host, SDHCI_RESET_DATA);
1189         }
1190
1191         host->mrq = NULL;
1192         host->cmd = NULL;
1193         host->data = NULL;
1194
1195 #ifndef CONFIG_LEDS_CLASS
1196         sdhci_deactivate_led(host);
1197 #endif
1198
1199         mmiowb();
1200         spin_unlock_irqrestore(&host->lock, flags);
1201
1202         mmc_request_done(host->mmc, mrq);
1203 }
1204
1205 static void sdhci_timeout_timer(unsigned long data)
1206 {
1207         struct sdhci_host *host;
1208         unsigned long flags;
1209
1210         host = (struct sdhci_host*)data;
1211
1212         spin_lock_irqsave(&host->lock, flags);
1213
1214         if (host->mrq) {
1215                 printk(KERN_ERR "%s: Timeout waiting for hardware "
1216                         "interrupt.\n", mmc_hostname(host->mmc));
1217                 sdhci_dumpregs(host);
1218
1219                 if (host->data) {
1220                         host->data->error = -ETIMEDOUT;
1221                         sdhci_finish_data(host);
1222                 } else {
1223                         if (host->cmd)
1224                                 host->cmd->error = -ETIMEDOUT;
1225                         else
1226                                 host->mrq->cmd->error = -ETIMEDOUT;
1227
1228                         tasklet_schedule(&host->finish_tasklet);
1229                 }
1230         }
1231
1232         mmiowb();
1233         spin_unlock_irqrestore(&host->lock, flags);
1234 }
1235
1236 /*****************************************************************************\
1237  *                                                                           *
1238  * Interrupt handling                                                        *
1239  *                                                                           *
1240 \*****************************************************************************/
1241
1242 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1243 {
1244         BUG_ON(intmask == 0);
1245
1246         if (!host->cmd) {
1247                 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1248                         "though no command operation was in progress.\n",
1249                         mmc_hostname(host->mmc), (unsigned)intmask);
1250                 sdhci_dumpregs(host);
1251                 return;
1252         }
1253
1254         if (intmask & SDHCI_INT_TIMEOUT)
1255                 host->cmd->error = -ETIMEDOUT;
1256         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1257                         SDHCI_INT_INDEX))
1258                 host->cmd->error = -EILSEQ;
1259
1260         if (host->cmd->error)
1261                 tasklet_schedule(&host->finish_tasklet);
1262         else if (intmask & SDHCI_INT_RESPONSE)
1263                 sdhci_finish_command(host);
1264 }
1265
1266 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1267 {
1268         BUG_ON(intmask == 0);
1269
1270         if (!host->data) {
1271                 /*
1272                  * A data end interrupt is sent together with the response
1273                  * for the stop command.
1274                  */
1275                 if (intmask & SDHCI_INT_DATA_END)
1276                         return;
1277
1278                 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1279                         "though no data operation was in progress.\n",
1280                         mmc_hostname(host->mmc), (unsigned)intmask);
1281                 sdhci_dumpregs(host);
1282
1283                 return;
1284         }
1285
1286         if (intmask & SDHCI_INT_DATA_TIMEOUT)
1287                 host->data->error = -ETIMEDOUT;
1288         else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1289                 host->data->error = -EILSEQ;
1290         else if (intmask & SDHCI_INT_ADMA_ERROR)
1291                 host->data->error = -EIO;
1292
1293         if (host->data->error)
1294                 sdhci_finish_data(host);
1295         else {
1296                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1297                         sdhci_transfer_pio(host);
1298
1299                 /*
1300                  * We currently don't do anything fancy with DMA
1301                  * boundaries, but as we can't disable the feature
1302                  * we need to at least restart the transfer.
1303                  */
1304                 if (intmask & SDHCI_INT_DMA_END)
1305                         writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
1306                                 host->ioaddr + SDHCI_DMA_ADDRESS);
1307
1308                 if (intmask & SDHCI_INT_DATA_END) {
1309                         if (host->cmd) {
1310                                 /*
1311                                  * Data managed to finish before the
1312                                  * command completed. Make sure we do
1313                                  * things in the proper order.
1314                                  */
1315                                 host->data_early = 1;
1316                         } else {
1317                                 sdhci_finish_data(host);
1318                         }
1319                 }
1320         }
1321 }
1322
1323 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1324 {
1325         irqreturn_t result;
1326         struct sdhci_host* host = dev_id;
1327         u32 intmask;
1328         int cardint = 0;
1329
1330         spin_lock(&host->lock);
1331
1332         intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1333
1334         if (!intmask || intmask == 0xffffffff) {
1335                 result = IRQ_NONE;
1336                 goto out;
1337         }
1338
1339         DBG("*** %s got interrupt: 0x%08x\n",
1340                 mmc_hostname(host->mmc), intmask);
1341
1342         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1343                 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1344                         host->ioaddr + SDHCI_INT_STATUS);
1345                 tasklet_schedule(&host->card_tasklet);
1346         }
1347
1348         intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1349
1350         if (intmask & SDHCI_INT_CMD_MASK) {
1351                 writel(intmask & SDHCI_INT_CMD_MASK,
1352                         host->ioaddr + SDHCI_INT_STATUS);
1353                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1354         }
1355
1356         if (intmask & SDHCI_INT_DATA_MASK) {
1357                 writel(intmask & SDHCI_INT_DATA_MASK,
1358                         host->ioaddr + SDHCI_INT_STATUS);
1359                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1360         }
1361
1362         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1363
1364         intmask &= ~SDHCI_INT_ERROR;
1365
1366         if (intmask & SDHCI_INT_BUS_POWER) {
1367                 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1368                         mmc_hostname(host->mmc));
1369                 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
1370         }
1371
1372         intmask &= ~SDHCI_INT_BUS_POWER;
1373
1374         if (intmask & SDHCI_INT_CARD_INT)
1375                 cardint = 1;
1376
1377         intmask &= ~SDHCI_INT_CARD_INT;
1378
1379         if (intmask) {
1380                 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1381                         mmc_hostname(host->mmc), intmask);
1382                 sdhci_dumpregs(host);
1383
1384                 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
1385         }
1386
1387         result = IRQ_HANDLED;
1388
1389         mmiowb();
1390 out:
1391         spin_unlock(&host->lock);
1392
1393         /*
1394          * We have to delay this as it calls back into the driver.
1395          */
1396         if (cardint)
1397                 mmc_signal_sdio_irq(host->mmc);
1398
1399         return result;
1400 }
1401
1402 /*****************************************************************************\
1403  *                                                                           *
1404  * Suspend/resume                                                            *
1405  *                                                                           *
1406 \*****************************************************************************/
1407
1408 #ifdef CONFIG_PM
1409
1410 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
1411 {
1412         int ret;
1413
1414         ret = mmc_suspend_host(host->mmc, state);
1415         if (ret)
1416                 return ret;
1417
1418         free_irq(host->irq, host);
1419
1420         return 0;
1421 }
1422
1423 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
1424
1425 int sdhci_resume_host(struct sdhci_host *host)
1426 {
1427         int ret;
1428
1429         if (host->flags & SDHCI_USE_DMA) {
1430                 if (host->ops->enable_dma)
1431                         host->ops->enable_dma(host);
1432         }
1433
1434         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1435                           mmc_hostname(host->mmc), host);
1436         if (ret)
1437                 return ret;
1438
1439         sdhci_init(host);
1440         mmiowb();
1441
1442         ret = mmc_resume_host(host->mmc);
1443         if (ret)
1444                 return ret;
1445
1446         return 0;
1447 }
1448
1449 EXPORT_SYMBOL_GPL(sdhci_resume_host);
1450
1451 #endif /* CONFIG_PM */
1452
1453 /*****************************************************************************\
1454  *                                                                           *
1455  * Device allocation/registration                                            *
1456  *                                                                           *
1457 \*****************************************************************************/
1458
1459 struct sdhci_host *sdhci_alloc_host(struct device *dev,
1460         size_t priv_size)
1461 {
1462         struct mmc_host *mmc;
1463         struct sdhci_host *host;
1464
1465         WARN_ON(dev == NULL);
1466
1467         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
1468         if (!mmc)
1469                 return ERR_PTR(-ENOMEM);
1470
1471         host = mmc_priv(mmc);
1472         host->mmc = mmc;
1473
1474         return host;
1475 }
1476
1477 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
1478
1479 int sdhci_add_host(struct sdhci_host *host)
1480 {
1481         struct mmc_host *mmc;
1482         unsigned int caps;
1483         int ret;
1484
1485         WARN_ON(host == NULL);
1486         if (host == NULL)
1487                 return -EINVAL;
1488
1489         mmc = host->mmc;
1490
1491         if (debug_quirks)
1492                 host->quirks = debug_quirks;
1493
1494         sdhci_reset(host, SDHCI_RESET_ALL);
1495
1496         host->version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1497         host->version = (host->version & SDHCI_SPEC_VER_MASK)
1498                                 >> SDHCI_SPEC_VER_SHIFT;
1499         if (host->version > SDHCI_SPEC_200) {
1500                 printk(KERN_ERR "%s: Unknown controller version (%d). "
1501                         "You may experience problems.\n", mmc_hostname(mmc),
1502                         host->version);
1503         }
1504
1505         caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1506
1507         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
1508                 host->flags |= SDHCI_USE_DMA;
1509         else if (!(caps & SDHCI_CAN_DO_DMA))
1510                 DBG("Controller doesn't have DMA capability\n");
1511         else
1512                 host->flags |= SDHCI_USE_DMA;
1513
1514         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1515                 (host->flags & SDHCI_USE_DMA)) {
1516                 DBG("Disabling DMA as it is marked broken\n");
1517                 host->flags &= ~SDHCI_USE_DMA;
1518         }
1519
1520         if (host->flags & SDHCI_USE_DMA) {
1521                 if ((host->version >= SDHCI_SPEC_200) &&
1522                                 (caps & SDHCI_CAN_DO_ADMA2))
1523                         host->flags |= SDHCI_USE_ADMA;
1524         }
1525
1526         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1527                 (host->flags & SDHCI_USE_ADMA)) {
1528                 DBG("Disabling ADMA as it is marked broken\n");
1529                 host->flags &= ~SDHCI_USE_ADMA;
1530         }
1531
1532         if (host->flags & SDHCI_USE_DMA) {
1533                 if (host->ops->enable_dma) {
1534                         if (host->ops->enable_dma(host)) {
1535                                 printk(KERN_WARNING "%s: No suitable DMA "
1536                                         "available. Falling back to PIO.\n",
1537                                         mmc_hostname(mmc));
1538                                 host->flags &= ~(SDHCI_USE_DMA | SDHCI_USE_ADMA);
1539                         }
1540                 }
1541         }
1542
1543         if (host->flags & SDHCI_USE_ADMA) {
1544                 /*
1545                  * We need to allocate descriptors for all sg entries
1546                  * (128) and potentially one alignment transfer for
1547                  * each of those entries.
1548                  */
1549                 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1550                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1551                 if (!host->adma_desc || !host->align_buffer) {
1552                         kfree(host->adma_desc);
1553                         kfree(host->align_buffer);
1554                         printk(KERN_WARNING "%s: Unable to allocate ADMA "
1555                                 "buffers. Falling back to standard DMA.\n",
1556                                 mmc_hostname(mmc));
1557                         host->flags &= ~SDHCI_USE_ADMA;
1558                 }
1559         }
1560
1561         /*
1562          * If we use DMA, then it's up to the caller to set the DMA
1563          * mask, but PIO does not need the hw shim so we set a new
1564          * mask here in that case.
1565          */
1566         if (!(host->flags & SDHCI_USE_DMA)) {
1567                 host->dma_mask = DMA_BIT_MASK(64);
1568                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
1569         }
1570
1571         host->max_clk =
1572                 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1573         if (host->max_clk == 0) {
1574                 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1575                         "frequency.\n", mmc_hostname(mmc));
1576                 return -ENODEV;
1577         }
1578         host->max_clk *= 1000000;
1579
1580         host->timeout_clk =
1581                 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1582         if (host->timeout_clk == 0) {
1583                 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1584                         "frequency.\n", mmc_hostname(mmc));
1585                 return -ENODEV;
1586         }
1587         if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1588                 host->timeout_clk *= 1000;
1589
1590         /*
1591          * Set host parameters.
1592          */
1593         mmc->ops = &sdhci_ops;
1594         mmc->f_min = host->max_clk / 256;
1595         mmc->f_max = host->max_clk;
1596         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1597
1598         if (caps & SDHCI_CAN_DO_HISPD)
1599                 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1600
1601         mmc->ocr_avail = 0;
1602         if (caps & SDHCI_CAN_VDD_330)
1603                 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1604         if (caps & SDHCI_CAN_VDD_300)
1605                 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1606         if (caps & SDHCI_CAN_VDD_180)
1607                 mmc->ocr_avail |= MMC_VDD_165_195;
1608
1609         if (mmc->ocr_avail == 0) {
1610                 printk(KERN_ERR "%s: Hardware doesn't report any "
1611                         "support voltages.\n", mmc_hostname(mmc));
1612                 return -ENODEV;
1613         }
1614
1615         spin_lock_init(&host->lock);
1616
1617         /*
1618          * Maximum number of segments. Depends on if the hardware
1619          * can do scatter/gather or not.
1620          */
1621         if (host->flags & SDHCI_USE_ADMA)
1622                 mmc->max_hw_segs = 128;
1623         else if (host->flags & SDHCI_USE_DMA)
1624                 mmc->max_hw_segs = 1;
1625         else /* PIO */
1626                 mmc->max_hw_segs = 128;
1627         mmc->max_phys_segs = 128;
1628
1629         /*
1630          * Maximum number of sectors in one transfer. Limited by DMA boundary
1631          * size (512KiB).
1632          */
1633         mmc->max_req_size = 524288;
1634
1635         /*
1636          * Maximum segment size. Could be one segment with the maximum number
1637          * of bytes. When doing hardware scatter/gather, each entry cannot
1638          * be larger than 64 KiB though.
1639          */
1640         if (host->flags & SDHCI_USE_ADMA)
1641                 mmc->max_seg_size = 65536;
1642         else
1643                 mmc->max_seg_size = mmc->max_req_size;
1644
1645         /*
1646          * Maximum block size. This varies from controller to controller and
1647          * is specified in the capabilities register.
1648          */
1649         mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1650         if (mmc->max_blk_size >= 3) {
1651                 printk(KERN_WARNING "%s: Invalid maximum block size, "
1652                         "assuming 512 bytes\n", mmc_hostname(mmc));
1653                 mmc->max_blk_size = 512;
1654         } else
1655                 mmc->max_blk_size = 512 << mmc->max_blk_size;
1656
1657         /*
1658          * Maximum block count.
1659          */
1660         mmc->max_blk_count = 65535;
1661
1662         /*
1663          * Init tasklets.
1664          */
1665         tasklet_init(&host->card_tasklet,
1666                 sdhci_tasklet_card, (unsigned long)host);
1667         tasklet_init(&host->finish_tasklet,
1668                 sdhci_tasklet_finish, (unsigned long)host);
1669
1670         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1671
1672         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1673                 mmc_hostname(mmc), host);
1674         if (ret)
1675                 goto untasklet;
1676
1677         sdhci_init(host);
1678
1679 #ifdef CONFIG_MMC_DEBUG
1680         sdhci_dumpregs(host);
1681 #endif
1682
1683 #ifdef CONFIG_LEDS_CLASS
1684         host->led.name = mmc_hostname(mmc);
1685         host->led.brightness = LED_OFF;
1686         host->led.default_trigger = mmc_hostname(mmc);
1687         host->led.brightness_set = sdhci_led_control;
1688
1689         ret = led_classdev_register(mmc_dev(mmc), &host->led);
1690         if (ret)
1691                 goto reset;
1692 #endif
1693
1694         mmiowb();
1695
1696         mmc_add_host(mmc);
1697
1698         printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s%s\n",
1699                 mmc_hostname(mmc), host->hw_name, mmc_dev(mmc)->bus_id,
1700                 (host->flags & SDHCI_USE_ADMA)?"A":"",
1701                 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1702
1703         return 0;
1704
1705 #ifdef CONFIG_LEDS_CLASS
1706 reset:
1707         sdhci_reset(host, SDHCI_RESET_ALL);
1708         free_irq(host->irq, host);
1709 #endif
1710 untasklet:
1711         tasklet_kill(&host->card_tasklet);
1712         tasklet_kill(&host->finish_tasklet);
1713
1714         return ret;
1715 }
1716
1717 EXPORT_SYMBOL_GPL(sdhci_add_host);
1718
1719 void sdhci_remove_host(struct sdhci_host *host, int dead)
1720 {
1721         unsigned long flags;
1722
1723         if (dead) {
1724                 spin_lock_irqsave(&host->lock, flags);
1725
1726                 host->flags |= SDHCI_DEVICE_DEAD;
1727
1728                 if (host->mrq) {
1729                         printk(KERN_ERR "%s: Controller removed during "
1730                                 " transfer!\n", mmc_hostname(host->mmc));
1731
1732                         host->mrq->cmd->error = -ENOMEDIUM;
1733                         tasklet_schedule(&host->finish_tasklet);
1734                 }
1735
1736                 spin_unlock_irqrestore(&host->lock, flags);
1737         }
1738
1739         mmc_remove_host(host->mmc);
1740
1741 #ifdef CONFIG_LEDS_CLASS
1742         led_classdev_unregister(&host->led);
1743 #endif
1744
1745         if (!dead)
1746                 sdhci_reset(host, SDHCI_RESET_ALL);
1747
1748         free_irq(host->irq, host);
1749
1750         del_timer_sync(&host->timer);
1751
1752         tasklet_kill(&host->card_tasklet);
1753         tasklet_kill(&host->finish_tasklet);
1754
1755         kfree(host->adma_desc);
1756         kfree(host->align_buffer);
1757
1758         host->adma_desc = NULL;
1759         host->align_buffer = NULL;
1760 }
1761
1762 EXPORT_SYMBOL_GPL(sdhci_remove_host);
1763
1764 void sdhci_free_host(struct sdhci_host *host)
1765 {
1766         mmc_free_host(host->mmc);
1767 }
1768
1769 EXPORT_SYMBOL_GPL(sdhci_free_host);
1770
1771 /*****************************************************************************\
1772  *                                                                           *
1773  * Driver init/exit                                                          *
1774  *                                                                           *
1775 \*****************************************************************************/
1776
1777 static int __init sdhci_drv_init(void)
1778 {
1779         printk(KERN_INFO DRIVER_NAME
1780                 ": Secure Digital Host Controller Interface driver\n");
1781         printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1782
1783         return 0;
1784 }
1785
1786 static void __exit sdhci_drv_exit(void)
1787 {
1788 }
1789
1790 module_init(sdhci_drv_init);
1791 module_exit(sdhci_drv_exit);
1792
1793 module_param(debug_quirks, uint, 0444);
1794
1795 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1796 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
1797 MODULE_LICENSE("GPL");
1798
1799 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");