err.no Git - linux-2.6/blob - drivers/mmc/host/omap.c

   1 /*
   2  *  linux/drivers/mmc/host/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/delay.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/timer.h>
  24 #include <linux/mmc/host.h>
  25 #include <linux/mmc/card.h>
  26 #include <linux/clk.h>
  27 #include <linux/scatterlist.h>
  28 #include <linux/i2c/tps65010.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/mach-types.h>
  33
  34 #include <asm/arch/board.h>
  35 #include <asm/arch/mmc.h>
  36 #include <asm/arch/gpio.h>
  37 #include <asm/arch/dma.h>
  38 #include <asm/arch/mux.h>
  39 #include <asm/arch/fpga.h>
  40
  41 #define OMAP_MMC_REG_CMD        0x00
  42 #define OMAP_MMC_REG_ARGL       0x04
  43 #define OMAP_MMC_REG_ARGH       0x08
  44 #define OMAP_MMC_REG_CON        0x0c
  45 #define OMAP_MMC_REG_STAT       0x10
  46 #define OMAP_MMC_REG_IE         0x14
  47 #define OMAP_MMC_REG_CTO        0x18
  48 #define OMAP_MMC_REG_DTO        0x1c
  49 #define OMAP_MMC_REG_DATA       0x20
  50 #define OMAP_MMC_REG_BLEN       0x24
  51 #define OMAP_MMC_REG_NBLK       0x28
  52 #define OMAP_MMC_REG_BUF        0x2c
  53 #define OMAP_MMC_REG_SDIO       0x34
  54 #define OMAP_MMC_REG_REV        0x3c
  55 #define OMAP_MMC_REG_RSP0       0x40
  56 #define OMAP_MMC_REG_RSP1       0x44
  57 #define OMAP_MMC_REG_RSP2       0x48
  58 #define OMAP_MMC_REG_RSP3       0x4c
  59 #define OMAP_MMC_REG_RSP4       0x50
  60 #define OMAP_MMC_REG_RSP5       0x54
  61 #define OMAP_MMC_REG_RSP6       0x58
  62 #define OMAP_MMC_REG_RSP7       0x5c
  63 #define OMAP_MMC_REG_IOSR       0x60
  64 #define OMAP_MMC_REG_SYSC       0x64
  65 #define OMAP_MMC_REG_SYSS       0x68
  66
  67 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  68 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  69 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  70 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  71 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  72 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  73 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  74 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  75 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  76 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  77 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  78 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  79 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  80
  81 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
  82 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
  83
  84 /*
  85  * Command types
  86  */
  87 #define OMAP_MMC_CMDTYPE_BC     0
  88 #define OMAP_MMC_CMDTYPE_BCR    1
  89 #define OMAP_MMC_CMDTYPE_AC     2
  90 #define OMAP_MMC_CMDTYPE_ADTC   3
  91
  92
  93 #define DRIVER_NAME "mmci-omap"
  94
  95 /* Specifies how often in millisecs to poll for card status changes
  96  * when the cover switch is open */
  97 #define OMAP_MMC_SWITCH_POLL_DELAY      500
  98
  99 struct mmc_omap_host;
 100
 101 struct mmc_omap_slot {
 102         int                     id;
 103         unsigned int            vdd;
 104         u16                     saved_con;
 105         u16                     bus_mode;
 106         unsigned int            fclk_freq;
 107         unsigned                powered:1;
 108
 109         struct work_struct      switch_work;
 110         struct timer_list       switch_timer;
 111         unsigned                cover_open;
 112
 113         struct mmc_request      *mrq;
 114         struct mmc_omap_host    *host;
 115         struct mmc_host         *mmc;
 116         struct omap_mmc_slot_data *pdata;
 117 };
 118
 119 struct mmc_omap_host {
 120         int                     initialized;
 121         int                     suspended;
 122         struct mmc_request *    mrq;
 123         struct mmc_command *    cmd;
 124         struct mmc_data *       data;
 125         struct mmc_host *       mmc;
 126         struct device *         dev;
 127         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 128         struct clk *            iclk;
 129         struct clk *            fclk;
 130         struct resource         *mem_res;
 131         void __iomem            *virt_base;
 132         unsigned int            phys_base;
 133         int                     irq;
 134         unsigned char           bus_mode;
 135         unsigned char           hw_bus_mode;
 136
 137         struct work_struct      cmd_abort;
 138         struct timer_list       cmd_timer;
 139
 140         unsigned int            sg_len;
 141         int                     sg_idx;
 142         u16 *                   buffer;
 143         u32                     buffer_bytes_left;
 144         u32                     total_bytes_left;
 145
 146         unsigned                use_dma:1;
 147         unsigned                brs_received:1, dma_done:1;
 148         unsigned                dma_is_read:1;
 149         unsigned                dma_in_use:1;
 150         int                     dma_ch;
 151         spinlock_t              dma_lock;
 152         struct timer_list       dma_timer;
 153         unsigned                dma_len;
 154
 155         short                   power_pin;
 156
 157         struct mmc_omap_slot    *slots[OMAP_MMC_MAX_SLOTS];
 158         struct mmc_omap_slot    *current_slot;
 159         spinlock_t              slot_lock;
 160         wait_queue_head_t       slot_wq;
 161         int                     nr_slots;
 162
 163         struct omap_mmc_platform_data *pdata;
 164 };
 165
 166 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
 167 {
 168         struct mmc_omap_host *host = slot->host;
 169         unsigned long flags;
 170
 171         if (claimed)
 172                 goto no_claim;
 173         spin_lock_irqsave(&host->slot_lock, flags);
 174         while (host->mmc != NULL) {
 175                 spin_unlock_irqrestore(&host->slot_lock, flags);
 176                 wait_event(host->slot_wq, host->mmc == NULL);
 177                 spin_lock_irqsave(&host->slot_lock, flags);
 178         }
 179         host->mmc = slot->mmc;
 180         spin_unlock_irqrestore(&host->slot_lock, flags);
 181 no_claim:
 182         clk_enable(host->fclk);
 183         if (host->current_slot != slot) {
 184                 if (host->pdata->switch_slot != NULL)
 185                         host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
 186                 host->current_slot = slot;
 187         }
 188
 189         /* Doing the dummy read here seems to work around some bug
 190          * at least in OMAP24xx silicon where the command would not
 191          * start after writing the CMD register. Sigh. */
 192         OMAP_MMC_READ(host, CON);
 193
 194         OMAP_MMC_WRITE(host, CON, slot->saved_con);
 195 }
 196
 197 static void mmc_omap_start_request(struct mmc_omap_host *host,
 198                                    struct mmc_request *req);
 199
 200 static void mmc_omap_release_slot(struct mmc_omap_slot *slot)
 201 {
 202         struct mmc_omap_host *host = slot->host;
 203         unsigned long flags;
 204         int i;
 205
 206         BUG_ON(slot == NULL || host->mmc == NULL);
 207         clk_disable(host->fclk);
 208
 209         spin_lock_irqsave(&host->slot_lock, flags);
 210         /* Check for any pending requests */
 211         for (i = 0; i < host->nr_slots; i++) {
 212                 struct mmc_omap_slot *new_slot;
 213                 struct mmc_request *rq;
 214
 215                 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
 216                         continue;
 217
 218                 new_slot = host->slots[i];
 219                 /* The current slot should not have a request in queue */
 220                 BUG_ON(new_slot == host->current_slot);
 221
 222                 host->mmc = new_slot->mmc;
 223                 spin_unlock_irqrestore(&host->slot_lock, flags);
 224                 mmc_omap_select_slot(new_slot, 1);
 225                 rq = new_slot->mrq;
 226                 new_slot->mrq = NULL;
 227                 mmc_omap_start_request(host, rq);
 228                 return;
 229         }
 230
 231         host->mmc = NULL;
 232         wake_up(&host->slot_wq);
 233         spin_unlock_irqrestore(&host->slot_lock, flags);
 234 }
 235
 236 static inline
 237 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
 238 {
 239         return slot->pdata->get_cover_state(mmc_dev(slot->mmc), slot->id);
 240 }
 241
 242 static ssize_t
 243 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 244                            char *buf)
 245 {
 246         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 247         struct mmc_omap_slot *slot = mmc_priv(mmc);
 248
 249         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
 250                        "closed");
 251 }
 252
 253 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 254
 255 static ssize_t
 256 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 257                         char *buf)
 258 {
 259         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 260         struct mmc_omap_slot *slot = mmc_priv(mmc);
 261
 262         return sprintf(buf, "%s\n", slot->pdata->name);
 263 }
 264
 265 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 266
 267 static void
 268 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 269 {
 270         u32 cmdreg;
 271         u32 resptype;
 272         u32 cmdtype;
 273
 274         host->cmd = cmd;
 275
 276         resptype = 0;
 277         cmdtype = 0;
 278
 279         /* Our hardware needs to know exact type */
 280         switch (mmc_resp_type(cmd)) {
 281         case MMC_RSP_NONE:
 282                 break;
 283         case MMC_RSP_R1:
 284         case MMC_RSP_R1B:
 285                 /* resp 1, 1b, 6, 7 */
 286                 resptype = 1;
 287                 break;
 288         case MMC_RSP_R2:
 289                 resptype = 2;
 290                 break;
 291         case MMC_RSP_R3:
 292                 resptype = 3;
 293                 break;
 294         default:
 295                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 296                 break;
 297         }
 298
 299         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 300                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 301         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 302                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 303         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 304                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 305         } else {
 306                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 307         }
 308
 309         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 310
 311         if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
 312                 cmdreg |= 1 << 6;
 313
 314         if (cmd->flags & MMC_RSP_BUSY)
 315                 cmdreg |= 1 << 11;
 316
 317         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 318                 cmdreg |= 1 << 15;
 319
 320         mod_timer(&host->cmd_timer, jiffies + HZ/2);
 321
 322         OMAP_MMC_WRITE(host, CTO, 200);
 323         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 324         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 325         OMAP_MMC_WRITE(host, IE,
 326                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 327                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 328                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 329                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 330                        OMAP_MMC_STAT_END_OF_DATA);
 331         OMAP_MMC_WRITE(host, CMD, cmdreg);
 332 }
 333
 334 static void
 335 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
 336                      int abort)
 337 {
 338         enum dma_data_direction dma_data_dir;
 339
 340         BUG_ON(host->dma_ch < 0);
 341         if (data->error)
 342                 omap_stop_dma(host->dma_ch);
 343         /* Release DMA channel lazily */
 344         mod_timer(&host->dma_timer, jiffies + HZ);
 345         if (data->flags & MMC_DATA_WRITE)
 346                 dma_data_dir = DMA_TO_DEVICE;
 347         else
 348                 dma_data_dir = DMA_FROM_DEVICE;
 349         dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
 350                      dma_data_dir);
 351 }
 352
 353 static void
 354 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 355 {
 356         if (host->dma_in_use)
 357                 mmc_omap_release_dma(host, data, data->error);
 358
 359         host->data = NULL;
 360         host->sg_len = 0;
 361
 362         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 363          * dozens of requests until the card finishes writing data.
 364          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 365          */
 366
 367         if (!data->stop) {
 368                 struct mmc_host *mmc;
 369
 370                 host->mrq = NULL;
 371                 mmc = host->mmc;
 372                 mmc_omap_release_slot(host->current_slot);
 373                 mmc_request_done(mmc, data->mrq);
 374                 return;
 375         }
 376
 377         mmc_omap_start_command(host, data->stop);
 378 }
 379
 380 static void
 381 mmc_omap_send_abort(struct mmc_omap_host *host)
 382 {
 383         struct mmc_omap_slot *slot = host->current_slot;
 384         unsigned int restarts, passes, timeout;
 385         u16 stat = 0;
 386
 387         /* Sending abort takes 80 clocks. Have some extra and round up */
 388         timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq;
 389         restarts = 0;
 390         while (restarts < 10000) {
 391                 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
 392                 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
 393
 394                 passes = 0;
 395                 while (passes < timeout) {
 396                         stat = OMAP_MMC_READ(host, STAT);
 397                         if (stat & OMAP_MMC_STAT_END_OF_CMD)
 398                                 goto out;
 399                         udelay(1);
 400                         passes++;
 401                 }
 402
 403                 restarts++;
 404         }
 405 out:
 406         OMAP_MMC_WRITE(host, STAT, stat);
 407 }
 408
 409 static void
 410 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
 411 {
 412         u16 ie;
 413
 414         if (host->dma_in_use)
 415                 mmc_omap_release_dma(host, data, 1);
 416
 417         host->data = NULL;
 418         host->sg_len = 0;
 419
 420         ie = OMAP_MMC_READ(host, IE);
 421         OMAP_MMC_WRITE(host, IE, 0);
 422         OMAP_MMC_WRITE(host, IE, ie);
 423         mmc_omap_send_abort(host);
 424 }
 425
 426 static void
 427 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 428 {
 429         unsigned long flags;
 430         int done;
 431
 432         if (!host->dma_in_use) {
 433                 mmc_omap_xfer_done(host, data);
 434                 return;
 435         }
 436         done = 0;
 437         spin_lock_irqsave(&host->dma_lock, flags);
 438         if (host->dma_done)
 439                 done = 1;
 440         else
 441                 host->brs_received = 1;
 442         spin_unlock_irqrestore(&host->dma_lock, flags);
 443         if (done)
 444                 mmc_omap_xfer_done(host, data);
 445 }
 446
 447 static void
 448 mmc_omap_dma_timer(unsigned long data)
 449 {
 450         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 451
 452         BUG_ON(host->dma_ch < 0);
 453         omap_free_dma(host->dma_ch);
 454         host->dma_ch = -1;
 455 }
 456
 457 static void
 458 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 459 {
 460         unsigned long flags;
 461         int done;
 462
 463         done = 0;
 464         spin_lock_irqsave(&host->dma_lock, flags);
 465         if (host->brs_received)
 466                 done = 1;
 467         else
 468                 host->dma_done = 1;
 469         spin_unlock_irqrestore(&host->dma_lock, flags);
 470         if (done)
 471                 mmc_omap_xfer_done(host, data);
 472 }
 473
 474 static void
 475 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 476 {
 477         host->cmd = NULL;
 478
 479         del_timer(&host->cmd_timer);
 480
 481         if (cmd->flags & MMC_RSP_PRESENT) {
 482                 if (cmd->flags & MMC_RSP_136) {
 483                         /* response type 2 */
 484                         cmd->resp[3] =
 485                                 OMAP_MMC_READ(host, RSP0) |
 486                                 (OMAP_MMC_READ(host, RSP1) << 16);
 487                         cmd->resp[2] =
 488                                 OMAP_MMC_READ(host, RSP2) |
 489                                 (OMAP_MMC_READ(host, RSP3) << 16);
 490                         cmd->resp[1] =
 491                                 OMAP_MMC_READ(host, RSP4) |
 492                                 (OMAP_MMC_READ(host, RSP5) << 16);
 493                         cmd->resp[0] =
 494                                 OMAP_MMC_READ(host, RSP6) |
 495                                 (OMAP_MMC_READ(host, RSP7) << 16);
 496                 } else {
 497                         /* response types 1, 1b, 3, 4, 5, 6 */
 498                         cmd->resp[0] =
 499                                 OMAP_MMC_READ(host, RSP6) |
 500                                 (OMAP_MMC_READ(host, RSP7) << 16);
 501                 }
 502         }
 503
 504         if (host->data == NULL || cmd->error) {
 505                 struct mmc_host *mmc;
 506
 507                 if (host->data != NULL)
 508                         mmc_omap_abort_xfer(host, host->data);
 509                 host->mrq = NULL;
 510                 mmc = host->mmc;
 511                 mmc_omap_release_slot(host->current_slot);
 512                 mmc_request_done(mmc, cmd->mrq);
 513         }
 514 }
 515
 516 /*
 517  * Abort stuck command. Can occur when card is removed while it is being
 518  * read.
 519  */
 520 static void mmc_omap_abort_command(struct work_struct *work)
 521 {
 522         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 523                                                   cmd_abort);
 524         u16 ie;
 525
 526         ie = OMAP_MMC_READ(host, IE);
 527         OMAP_MMC_WRITE(host, IE, 0);
 528
 529         if (!host->cmd) {
 530                 OMAP_MMC_WRITE(host, IE, ie);
 531                 return;
 532         }
 533
 534         dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
 535                 host->cmd->opcode);
 536
 537         if (host->data && host->dma_in_use)
 538                 mmc_omap_release_dma(host, host->data, 1);
 539
 540         host->data = NULL;
 541         host->sg_len = 0;
 542
 543         mmc_omap_send_abort(host);
 544         host->cmd->error = -ETIMEDOUT;
 545         mmc_omap_cmd_done(host, host->cmd);
 546         OMAP_MMC_WRITE(host, IE, ie);
 547 }
 548
 549 static void
 550 mmc_omap_cmd_timer(unsigned long data)
 551 {
 552         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 553
 554         schedule_work(&host->cmd_abort);
 555 }
 556
 557 /* PIO only */
 558 static void
 559 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 560 {
 561         struct scatterlist *sg;
 562
 563         sg = host->data->sg + host->sg_idx;
 564         host->buffer_bytes_left = sg->length;
 565         host->buffer = sg_virt(sg);
 566         if (host->buffer_bytes_left > host->total_bytes_left)
 567                 host->buffer_bytes_left = host->total_bytes_left;
 568 }
 569
 570 /* PIO only */
 571 static void
 572 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 573 {
 574         int n;
 575
 576         if (host->buffer_bytes_left == 0) {
 577                 host->sg_idx++;
 578                 BUG_ON(host->sg_idx == host->sg_len);
 579                 mmc_omap_sg_to_buf(host);
 580         }
 581         n = 64;
 582         if (n > host->buffer_bytes_left)
 583                 n = host->buffer_bytes_left;
 584         host->buffer_bytes_left -= n;
 585         host->total_bytes_left -= n;
 586         host->data->bytes_xfered += n;
 587
 588         if (write) {
 589                 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 590         } else {
 591                 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 592         }
 593 }
 594
 595 static inline void mmc_omap_report_irq(u16 status)
 596 {
 597         static const char *mmc_omap_status_bits[] = {
 598                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 599                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 600         };
 601         int i, c = 0;
 602
 603         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 604                 if (status & (1 << i)) {
 605                         if (c)
 606                                 printk(" ");
 607                         printk("%s", mmc_omap_status_bits[i]);
 608                         c++;
 609                 }
 610 }
 611
 612 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 613 {
 614         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 615         u16 status;
 616         int end_command;
 617         int end_transfer;
 618         int transfer_error, cmd_error;
 619
 620         if (host->cmd == NULL && host->data == NULL) {
 621                 status = OMAP_MMC_READ(host, STAT);
 622                 dev_info(mmc_dev(host->slots[0]->mmc),
 623                          "Spurious IRQ 0x%04x\n", status);
 624                 if (status != 0) {
 625                         OMAP_MMC_WRITE(host, STAT, status);
 626                         OMAP_MMC_WRITE(host, IE, 0);
 627                 }
 628                 return IRQ_HANDLED;
 629         }
 630
 631         end_command = 0;
 632         end_transfer = 0;
 633         transfer_error = 0;
 634         cmd_error = 0;
 635
 636         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 637                 int cmd;
 638
 639                 OMAP_MMC_WRITE(host, STAT, status);
 640                 if (host->cmd != NULL)
 641                         cmd = host->cmd->opcode;
 642                 else
 643                         cmd = -1;
 644 #ifdef CONFIG_MMC_DEBUG
 645                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 646                         status, cmd);
 647                 mmc_omap_report_irq(status);
 648                 printk("\n");
 649 #endif
 650                 if (host->total_bytes_left) {
 651                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 652                             (status & OMAP_MMC_STAT_END_OF_DATA))
 653                                 mmc_omap_xfer_data(host, 0);
 654                         if (status & OMAP_MMC_STAT_A_EMPTY)
 655                                 mmc_omap_xfer_data(host, 1);
 656                 }
 657
 658                 if (status & OMAP_MMC_STAT_END_OF_DATA)
 659                         end_transfer = 1;
 660
 661                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 662                         dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
 663                                 cmd);
 664                         if (host->data) {
 665                                 host->data->error = -ETIMEDOUT;
 666                                 transfer_error = 1;
 667                         }
 668                 }
 669
 670                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 671                         if (host->data) {
 672                                 host->data->error = -EILSEQ;
 673                                 dev_dbg(mmc_dev(host->mmc),
 674                                          "data CRC error, bytes left %d\n",
 675                                         host->total_bytes_left);
 676                                 transfer_error = 1;
 677                         } else {
 678                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 679                         }
 680                 }
 681
 682                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 683                         /* Timeouts are routine with some commands */
 684                         if (host->cmd) {
 685                                 struct mmc_omap_slot *slot =
 686                                         host->current_slot;
 687                                 if (slot == NULL ||
 688                                     !mmc_omap_cover_is_open(slot))
 689                                         dev_err(mmc_dev(host->mmc),
 690                                                 "command timeout (CMD%d)\n",
 691                                                 cmd);
 692                                 host->cmd->error = -ETIMEDOUT;
 693                                 end_command = 1;
 694                                 cmd_error = 1;
 695                         }
 696                 }
 697
 698                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 699                         if (host->cmd) {
 700                                 dev_err(mmc_dev(host->mmc),
 701                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 702                                         cmd, host->cmd->arg);
 703                                 host->cmd->error = -EILSEQ;
 704                                 end_command = 1;
 705                                 cmd_error = 1;
 706                         } else
 707                                 dev_err(mmc_dev(host->mmc),
 708                                         "command CRC error without cmd?\n");
 709                 }
 710
 711                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 712                         dev_dbg(mmc_dev(host->mmc),
 713                                 "ignoring card status error (CMD%d)\n",
 714                                 cmd);
 715                         end_command = 1;
 716                 }
 717
 718                 /*
 719                  * NOTE: On 1610 the END_OF_CMD may come too early when
 720                  * starting a write
 721                  */
 722                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 723                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 724                         end_command = 1;
 725                 }
 726         }
 727
 728         if (end_command)
 729                 mmc_omap_cmd_done(host, host->cmd);
 730         if (host->data != NULL) {
 731                 if (transfer_error)
 732                         mmc_omap_xfer_done(host, host->data);
 733                 else if (end_transfer)
 734                         mmc_omap_end_of_data(host, host->data);
 735         }
 736
 737         return IRQ_HANDLED;
 738 }
 739
 740 void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed)
 741 {
 742         struct mmc_omap_host *host = dev_get_drvdata(dev);
 743
 744         BUG_ON(slot >= host->nr_slots);
 745
 746         /* Other subsystems can call in here before we're initialised. */
 747         if (host->nr_slots == 0 || !host->slots[slot])
 748                 return;
 749
 750         schedule_work(&host->slots[slot]->switch_work);
 751 }
 752
 753 static void mmc_omap_switch_timer(unsigned long arg)
 754 {
 755         struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
 756
 757         schedule_work(&slot->switch_work);
 758 }
 759
 760 static void mmc_omap_cover_handler(struct work_struct *work)
 761 {
 762         struct mmc_omap_slot *slot = container_of(work, struct mmc_omap_slot,
 763                                                   switch_work);
 764         int cover_open;
 765
 766         cover_open = mmc_omap_cover_is_open(slot);
 767         if (cover_open != slot->cover_open) {
 768                 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
 769                 slot->cover_open = cover_open;
 770                 dev_info(mmc_dev(slot->mmc), "cover is now %s\n",
 771                          cover_open ? "open" : "closed");
 772         }
 773         mmc_detect_change(slot->mmc, slot->id);
 774 }
 775
 776 /* Prepare to transfer the next segment of a scatterlist */
 777 static void
 778 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
 779 {
 780         int dma_ch = host->dma_ch;
 781         unsigned long data_addr;
 782         u16 buf, frame;
 783         u32 count;
 784         struct scatterlist *sg = &data->sg[host->sg_idx];
 785         int src_port = 0;
 786         int dst_port = 0;
 787         int sync_dev = 0;
 788
 789         data_addr = host->phys_base + OMAP_MMC_REG_DATA;
 790         frame = data->blksz;
 791         count = sg_dma_len(sg);
 792
 793         if ((data->blocks == 1) && (count > data->blksz))
 794                 count = frame;
 795
 796         host->dma_len = count;
 797
 798         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
 799          * Use 16 or 32 word frames when the blocksize is at least that large.
 800          * Blocksize is usually 512 bytes; but not for some SD reads.
 801          */
 802         if (cpu_is_omap15xx() && frame > 32)
 803                 frame = 32;
 804         else if (frame > 64)
 805                 frame = 64;
 806         count /= frame;
 807         frame >>= 1;
 808
 809         if (!(data->flags & MMC_DATA_WRITE)) {
 810                 buf = 0x800f | ((frame - 1) << 8);
 811
 812                 if (cpu_class_is_omap1()) {
 813                         src_port = OMAP_DMA_PORT_TIPB;
 814                         dst_port = OMAP_DMA_PORT_EMIFF;
 815                 }
 816                 if (cpu_is_omap24xx())
 817                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 818
 819                 omap_set_dma_src_params(dma_ch, src_port,
 820                                         OMAP_DMA_AMODE_CONSTANT,
 821                                         data_addr, 0, 0);
 822                 omap_set_dma_dest_params(dma_ch, dst_port,
 823                                          OMAP_DMA_AMODE_POST_INC,
 824                                          sg_dma_address(sg), 0, 0);
 825                 omap_set_dma_dest_data_pack(dma_ch, 1);
 826                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 827         } else {
 828                 buf = 0x0f80 | ((frame - 1) << 0);
 829
 830                 if (cpu_class_is_omap1()) {
 831                         src_port = OMAP_DMA_PORT_EMIFF;
 832                         dst_port = OMAP_DMA_PORT_TIPB;
 833                 }
 834                 if (cpu_is_omap24xx())
 835                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 836
 837                 omap_set_dma_dest_params(dma_ch, dst_port,
 838                                          OMAP_DMA_AMODE_CONSTANT,
 839                                          data_addr, 0, 0);
 840                 omap_set_dma_src_params(dma_ch, src_port,
 841                                         OMAP_DMA_AMODE_POST_INC,
 842                                         sg_dma_address(sg), 0, 0);
 843                 omap_set_dma_src_data_pack(dma_ch, 1);
 844                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 845         }
 846
 847         /* Max limit for DMA frame count is 0xffff */
 848         BUG_ON(count > 0xffff);
 849
 850         OMAP_MMC_WRITE(host, BUF, buf);
 851         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
 852                                      frame, count, OMAP_DMA_SYNC_FRAME,
 853                                      sync_dev, 0);
 854 }
 855
 856 /* A scatterlist segment completed */
 857 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 858 {
 859         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 860         struct mmc_data *mmcdat = host->data;
 861
 862         if (unlikely(host->dma_ch < 0)) {
 863                 dev_err(mmc_dev(host->mmc),
 864                         "DMA callback while DMA not enabled\n");
 865                 return;
 866         }
 867         /* FIXME: We really should do something to _handle_ the errors */
 868         if (ch_status & OMAP1_DMA_TOUT_IRQ) {
 869                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
 870                 return;
 871         }
 872         if (ch_status & OMAP_DMA_DROP_IRQ) {
 873                 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
 874                 return;
 875         }
 876         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
 877                 return;
 878         }
 879         mmcdat->bytes_xfered += host->dma_len;
 880         host->sg_idx++;
 881         if (host->sg_idx < host->sg_len) {
 882                 mmc_omap_prepare_dma(host, host->data);
 883                 omap_start_dma(host->dma_ch);
 884         } else
 885                 mmc_omap_dma_done(host, host->data);
 886 }
 887
 888 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
 889 {
 890         const char *dev_name;
 891         int sync_dev, dma_ch, is_read, r;
 892
 893         is_read = !(data->flags & MMC_DATA_WRITE);
 894         del_timer_sync(&host->dma_timer);
 895         if (host->dma_ch >= 0) {
 896                 if (is_read == host->dma_is_read)
 897                         return 0;
 898                 omap_free_dma(host->dma_ch);
 899                 host->dma_ch = -1;
 900         }
 901
 902         if (is_read) {
 903                 if (host->id == 1) {
 904                         sync_dev = OMAP_DMA_MMC_RX;
 905                         dev_name = "MMC1 read";
 906                 } else {
 907                         sync_dev = OMAP_DMA_MMC2_RX;
 908                         dev_name = "MMC2 read";
 909                 }
 910         } else {
 911                 if (host->id == 1) {
 912                         sync_dev = OMAP_DMA_MMC_TX;
 913                         dev_name = "MMC1 write";
 914                 } else {
 915                         sync_dev = OMAP_DMA_MMC2_TX;
 916                         dev_name = "MMC2 write";
 917                 }
 918         }
 919         r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
 920                              host, &dma_ch);
 921         if (r != 0) {
 922                 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
 923                 return r;
 924         }
 925         host->dma_ch = dma_ch;
 926         host->dma_is_read = is_read;
 927
 928         return 0;
 929 }
 930
 931 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 932 {
 933         u16 reg;
 934
 935         reg = OMAP_MMC_READ(host, SDIO);
 936         reg &= ~(1 << 5);
 937         OMAP_MMC_WRITE(host, SDIO, reg);
 938         /* Set maximum timeout */
 939         OMAP_MMC_WRITE(host, CTO, 0xff);
 940 }
 941
 942 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 943 {
 944         unsigned int timeout, cycle_ns;
 945         u16 reg;
 946
 947         cycle_ns = 1000000000 / host->current_slot->fclk_freq;
 948         timeout = req->data->timeout_ns / cycle_ns;
 949         timeout += req->data->timeout_clks;
 950
 951         /* Check if we need to use timeout multiplier register */
 952         reg = OMAP_MMC_READ(host, SDIO);
 953         if (timeout > 0xffff) {
 954                 reg |= (1 << 5);
 955                 timeout /= 1024;
 956         } else
 957                 reg &= ~(1 << 5);
 958         OMAP_MMC_WRITE(host, SDIO, reg);
 959         OMAP_MMC_WRITE(host, DTO, timeout);
 960 }
 961
 962 static void
 963 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 964 {
 965         struct mmc_data *data = req->data;
 966         int i, use_dma, block_size;
 967         unsigned sg_len;
 968
 969         host->data = data;
 970         if (data == NULL) {
 971                 OMAP_MMC_WRITE(host, BLEN, 0);
 972                 OMAP_MMC_WRITE(host, NBLK, 0);
 973                 OMAP_MMC_WRITE(host, BUF, 0);
 974                 host->dma_in_use = 0;
 975                 set_cmd_timeout(host, req);
 976                 return;
 977         }
 978
 979         block_size = data->blksz;
 980
 981         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
 982         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
 983         set_data_timeout(host, req);
 984
 985         /* cope with calling layer confusion; it issues "single
 986          * block" writes using multi-block scatterlists.
 987          */
 988         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
 989
 990         /* Only do DMA for entire blocks */
 991         use_dma = host->use_dma;
 992         if (use_dma) {
 993                 for (i = 0; i < sg_len; i++) {
 994                         if ((data->sg[i].length % block_size) != 0) {
 995                                 use_dma = 0;
 996                                 break;
 997                         }
 998                 }
 999         }
1000
1001         host->sg_idx = 0;
1002         if (use_dma) {
1003                 if (mmc_omap_get_dma_channel(host, data) == 0) {
1004                         enum dma_data_direction dma_data_dir;
1005
1006                         if (data->flags & MMC_DATA_WRITE)
1007                                 dma_data_dir = DMA_TO_DEVICE;
1008                         else
1009                                 dma_data_dir = DMA_FROM_DEVICE;
1010
1011                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1012                                                 sg_len, dma_data_dir);
1013                         host->total_bytes_left = 0;
1014                         mmc_omap_prepare_dma(host, req->data);
1015                         host->brs_received = 0;
1016                         host->dma_done = 0;
1017                         host->dma_in_use = 1;
1018                 } else
1019                         use_dma = 0;
1020         }
1021
1022         /* Revert to PIO? */
1023         if (!use_dma) {
1024                 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1025                 host->total_bytes_left = data->blocks * block_size;
1026                 host->sg_len = sg_len;
1027                 mmc_omap_sg_to_buf(host);
1028                 host->dma_in_use = 0;
1029         }
1030 }
1031
1032 static void mmc_omap_start_request(struct mmc_omap_host *host,
1033                                    struct mmc_request *req)
1034 {
1035         BUG_ON(host->mrq != NULL);
1036
1037         host->mrq = req;
1038
1039         /* only touch fifo AFTER the controller readies it */
1040         mmc_omap_prepare_data(host, req);
1041         mmc_omap_start_command(host, req->cmd);
1042         if (host->dma_in_use)
1043                 omap_start_dma(host->dma_ch);
1044         BUG_ON(irqs_disabled());
1045 }
1046
1047 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1048 {
1049         struct mmc_omap_slot *slot = mmc_priv(mmc);
1050         struct mmc_omap_host *host = slot->host;
1051         unsigned long flags;
1052
1053         spin_lock_irqsave(&host->slot_lock, flags);
1054         if (host->mmc != NULL) {
1055                 BUG_ON(slot->mrq != NULL);
1056                 slot->mrq = req;
1057                 spin_unlock_irqrestore(&host->slot_lock, flags);
1058                 return;
1059         } else
1060                 host->mmc = mmc;
1061         spin_unlock_irqrestore(&host->slot_lock, flags);
1062         mmc_omap_select_slot(slot, 1);
1063         mmc_omap_start_request(host, req);
1064 }
1065
1066 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1067                                 int vdd)
1068 {
1069         struct mmc_omap_host *host;
1070
1071         host = slot->host;
1072
1073         if (slot->pdata->set_power != NULL)
1074                 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1075                                         vdd);
1076
1077         if (cpu_is_omap24xx()) {
1078                 u16 w;
1079
1080                 if (power_on) {
1081                         w = OMAP_MMC_READ(host, CON);
1082                         OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1083                 } else {
1084                         w = OMAP_MMC_READ(host, CON);
1085                         OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1086                 }
1087         }
1088 }
1089
1090 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1091 {
1092         struct mmc_omap_slot *slot = mmc_priv(mmc);
1093         struct mmc_omap_host *host = slot->host;
1094         int func_clk_rate = clk_get_rate(host->fclk);
1095         int dsor;
1096
1097         if (ios->clock == 0)
1098                 return 0;
1099
1100         dsor = func_clk_rate / ios->clock;
1101         if (dsor < 1)
1102                 dsor = 1;
1103
1104         if (func_clk_rate / dsor > ios->clock)
1105                 dsor++;
1106
1107         if (dsor > 250)
1108                 dsor = 250;
1109
1110         slot->fclk_freq = func_clk_rate / dsor;
1111
1112         if (ios->bus_width == MMC_BUS_WIDTH_4)
1113                 dsor |= 1 << 15;
1114
1115         return dsor;
1116 }
1117
1118 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1119 {
1120         struct mmc_omap_slot *slot = mmc_priv(mmc);
1121         struct mmc_omap_host *host = slot->host;
1122         int i, dsor;
1123
1124         dsor = mmc_omap_calc_divisor(mmc, ios);
1125
1126         mmc_omap_select_slot(slot, 0);
1127
1128         if (ios->vdd != slot->vdd)
1129                 slot->vdd = ios->vdd;
1130
1131         switch (ios->power_mode) {
1132         case MMC_POWER_OFF:
1133                 mmc_omap_set_power(slot, 0, ios->vdd);
1134                 break;
1135         case MMC_POWER_UP:
1136                 /* Cannot touch dsor yet, just power up MMC */
1137                 mmc_omap_set_power(slot, 1, ios->vdd);
1138                 goto exit;
1139         case MMC_POWER_ON:
1140                 dsor |= 1 << 11;
1141                 break;
1142         }
1143
1144         if (slot->bus_mode != ios->bus_mode) {
1145                 if (slot->pdata->set_bus_mode != NULL)
1146                         slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1147                                                   ios->bus_mode);
1148                 slot->bus_mode = ios->bus_mode;
1149         }
1150
1151         /* On insanely high arm_per frequencies something sometimes
1152          * goes somehow out of sync, and the POW bit is not being set,
1153          * which results in the while loop below getting stuck.
1154          * Writing to the CON register twice seems to do the trick. */
1155         for (i = 0; i < 2; i++)
1156                 OMAP_MMC_WRITE(host, CON, dsor);
1157         slot->saved_con = dsor;
1158         if (ios->power_mode == MMC_POWER_ON) {
1159                 /* Send clock cycles, poll completion */
1160                 OMAP_MMC_WRITE(host, IE, 0);
1161                 OMAP_MMC_WRITE(host, STAT, 0xffff);
1162                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1163                 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
1164                 OMAP_MMC_WRITE(host, STAT, 1);
1165         }
1166
1167 exit:
1168         mmc_omap_release_slot(slot);
1169 }
1170
1171 static const struct mmc_host_ops mmc_omap_ops = {
1172         .request        = mmc_omap_request,
1173         .set_ios        = mmc_omap_set_ios,
1174 };
1175
1176 static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1177 {
1178         struct mmc_omap_slot *slot = NULL;
1179         struct mmc_host *mmc;
1180         int r;
1181
1182         mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1183         if (mmc == NULL)
1184                 return -ENOMEM;
1185
1186         slot = mmc_priv(mmc);
1187         slot->host = host;
1188         slot->mmc = mmc;
1189         slot->id = id;
1190         slot->pdata = &host->pdata->slots[id];
1191
1192         host->slots[id] = slot;
1193
1194         mmc->caps = MMC_CAP_MULTIWRITE;
1195         if (host->pdata->conf.wire4)
1196                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1197
1198         mmc->ops = &mmc_omap_ops;
1199         mmc->f_min = 400000;
1200
1201         if (cpu_class_is_omap2())
1202                 mmc->f_max = 48000000;
1203         else
1204                 mmc->f_max = 24000000;
1205         if (host->pdata->max_freq)
1206                 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1207         mmc->ocr_avail = slot->pdata->ocr_mask;
1208
1209         /* Use scatterlist DMA to reduce per-transfer costs.
1210          * NOTE max_seg_size assumption that small blocks aren't
1211          * normally used (except e.g. for reading SD registers).
1212          */
1213         mmc->max_phys_segs = 32;
1214         mmc->max_hw_segs = 32;
1215         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
1216         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
1217         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1218         mmc->max_seg_size = mmc->max_req_size;
1219
1220         r = mmc_add_host(mmc);
1221         if (r < 0)
1222                 goto err_remove_host;
1223
1224         if (slot->pdata->name != NULL) {
1225                 r = device_create_file(&mmc->class_dev,
1226                                         &dev_attr_slot_name);
1227                 if (r < 0)
1228                         goto err_remove_host;
1229         }
1230
1231         if (slot->pdata->get_cover_state != NULL) {
1232                 r = device_create_file(&mmc->class_dev,
1233                                         &dev_attr_cover_switch);
1234                 if (r < 0)
1235                         goto err_remove_slot_name;
1236
1237                 INIT_WORK(&slot->switch_work, mmc_omap_cover_handler);
1238                 init_timer(&slot->switch_timer);
1239                 slot->switch_timer.function = mmc_omap_switch_timer;
1240                 slot->switch_timer.data = (unsigned long) slot;
1241                 schedule_work(&slot->switch_work);
1242         }
1243
1244         return 0;
1245
1246 err_remove_slot_name:
1247         if (slot->pdata->name != NULL)
1248                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1249 err_remove_host:
1250         mmc_remove_host(mmc);
1251         mmc_free_host(mmc);
1252         return r;
1253 }
1254
1255 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1256 {
1257         struct mmc_host *mmc = slot->mmc;
1258
1259         if (slot->pdata->name != NULL)
1260                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1261         if (slot->pdata->get_cover_state != NULL)
1262                 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1263
1264         del_timer_sync(&slot->switch_timer);
1265         flush_scheduled_work();
1266
1267         mmc_remove_host(mmc);
1268         mmc_free_host(mmc);
1269 }
1270
1271 static int __init mmc_omap_probe(struct platform_device *pdev)
1272 {
1273         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1274         struct mmc_omap_host *host = NULL;
1275         struct resource *res;
1276         int i, ret = 0;
1277         int irq;
1278
1279         if (pdata == NULL) {
1280                 dev_err(&pdev->dev, "platform data missing\n");
1281                 return -ENXIO;
1282         }
1283         if (pdata->nr_slots == 0) {
1284                 dev_err(&pdev->dev, "no slots\n");
1285                 return -ENXIO;
1286         }
1287
1288         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1289         irq = platform_get_irq(pdev, 0);
1290         if (res == NULL || irq < 0)
1291                 return -ENXIO;
1292
1293         res = request_mem_region(res->start, res->end - res->start + 1,
1294                                  pdev->name);
1295         if (res == NULL)
1296                 return -EBUSY;
1297
1298         host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1299         if (host == NULL) {
1300                 ret = -ENOMEM;
1301                 goto err_free_mem_region;
1302         }
1303
1304         INIT_WORK(&host->cmd_abort, mmc_omap_abort_command);
1305         init_timer(&host->cmd_timer);
1306         host->cmd_timer.function = mmc_omap_cmd_timer;
1307         host->cmd_timer.data = (unsigned long) host;
1308
1309         spin_lock_init(&host->dma_lock);
1310         init_timer(&host->dma_timer);
1311         spin_lock_init(&host->slot_lock);
1312         init_waitqueue_head(&host->slot_wq);
1313
1314         host->dma_timer.function = mmc_omap_dma_timer;
1315         host->dma_timer.data = (unsigned long) host;
1316
1317         host->pdata = pdata;
1318         host->dev = &pdev->dev;
1319         platform_set_drvdata(pdev, host);
1320
1321         host->id = pdev->id;
1322         host->mem_res = res;
1323         host->irq = irq;
1324
1325         host->use_dma = 1;
1326         host->dma_ch = -1;
1327
1328         host->irq = irq;
1329         host->phys_base = host->mem_res->start;
1330         host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1331
1332         if (cpu_is_omap24xx()) {
1333                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1334                 if (IS_ERR(host->iclk))
1335                         goto err_free_mmc_host;
1336                 clk_enable(host->iclk);
1337         }
1338
1339         if (!cpu_is_omap24xx())
1340                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1341         else
1342                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1343
1344         if (IS_ERR(host->fclk)) {
1345                 ret = PTR_ERR(host->fclk);
1346                 goto err_free_iclk;
1347         }
1348
1349         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1350         if (ret)
1351                 goto err_free_fclk;
1352
1353         if (pdata->init != NULL) {
1354                 ret = pdata->init(&pdev->dev);
1355                 if (ret < 0)
1356                         goto err_free_irq;
1357         }
1358
1359         host->nr_slots = pdata->nr_slots;
1360         for (i = 0; i < pdata->nr_slots; i++) {
1361                 ret = mmc_omap_new_slot(host, i);
1362                 if (ret < 0) {
1363                         while (--i >= 0)
1364                                 mmc_omap_remove_slot(host->slots[i]);
1365
1366                         goto err_plat_cleanup;
1367                 }
1368         }
1369
1370         return 0;
1371
1372 err_plat_cleanup:
1373         if (pdata->cleanup)
1374                 pdata->cleanup(&pdev->dev);
1375 err_free_irq:
1376         free_irq(host->irq, host);
1377 err_free_fclk:
1378         clk_put(host->fclk);
1379 err_free_iclk:
1380         if (host->iclk != NULL) {
1381                 clk_disable(host->iclk);
1382                 clk_put(host->iclk);
1383         }
1384 err_free_mmc_host:
1385         kfree(host);
1386 err_free_mem_region:
1387         release_mem_region(res->start, res->end - res->start + 1);
1388         return ret;
1389 }
1390
1391 static int mmc_omap_remove(struct platform_device *pdev)
1392 {
1393         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1394         int i;
1395
1396         platform_set_drvdata(pdev, NULL);
1397
1398         BUG_ON(host == NULL);
1399
1400         for (i = 0; i < host->nr_slots; i++)
1401                 mmc_omap_remove_slot(host->slots[i]);
1402
1403         if (host->pdata->cleanup)
1404                 host->pdata->cleanup(&pdev->dev);
1405
1406         if (host->iclk && !IS_ERR(host->iclk))
1407                 clk_put(host->iclk);
1408         if (host->fclk && !IS_ERR(host->fclk))
1409                 clk_put(host->fclk);
1410
1411         release_mem_region(pdev->resource[0].start,
1412                            pdev->resource[0].end - pdev->resource[0].start + 1);
1413
1414         kfree(host);
1415
1416         return 0;
1417 }
1418
1419 #ifdef CONFIG_PM
1420 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1421 {
1422         int i, ret = 0;
1423         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1424
1425         if (host == NULL || host->suspended)
1426                 return 0;
1427
1428         for (i = 0; i < host->nr_slots; i++) {
1429                 struct mmc_omap_slot *slot;
1430
1431                 slot = host->slots[i];
1432                 ret = mmc_suspend_host(slot->mmc, mesg);
1433                 if (ret < 0) {
1434                         while (--i >= 0) {
1435                                 slot = host->slots[i];
1436                                 mmc_resume_host(slot->mmc);
1437                         }
1438                         return ret;
1439                 }
1440         }
1441         host->suspended = 1;
1442         return 0;
1443 }
1444
1445 static int mmc_omap_resume(struct platform_device *pdev)
1446 {
1447         int i, ret = 0;
1448         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1449
1450         if (host == NULL || !host->suspended)
1451                 return 0;
1452
1453         for (i = 0; i < host->nr_slots; i++) {
1454                 struct mmc_omap_slot *slot;
1455                 slot = host->slots[i];
1456                 ret = mmc_resume_host(slot->mmc);
1457                 if (ret < 0)
1458                         return ret;
1459
1460                 host->suspended = 0;
1461         }
1462         return 0;
1463 }
1464 #else
1465 #define mmc_omap_suspend        NULL
1466 #define mmc_omap_resume         NULL
1467 #endif
1468
1469 static struct platform_driver mmc_omap_driver = {
1470         .probe          = mmc_omap_probe,
1471         .remove         = mmc_omap_remove,
1472         .suspend        = mmc_omap_suspend,
1473         .resume         = mmc_omap_resume,
1474         .driver         = {
1475                 .name   = DRIVER_NAME,
1476                 .owner  = THIS_MODULE,
1477         },
1478 };
1479
1480 static int __init mmc_omap_init(void)
1481 {
1482         return platform_driver_register(&mmc_omap_driver);
1483 }
1484
1485 static void __exit mmc_omap_exit(void)
1486 {
1487         platform_driver_unregister(&mmc_omap_driver);
1488 }
1489
1490 module_init(mmc_omap_init);
1491 module_exit(mmc_omap_exit);
1492
1493 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1494 MODULE_LICENSE("GPL");
1495 MODULE_ALIAS("platform:" DRIVER_NAME);
1496 MODULE_AUTHOR("Juha Yrjölä");