2 * linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver
4 * Copyright (c) 2005, Advanced Micro Devices, Inc.
6 * Developed with help from the 2.4.30 MMC AU1XXX controller including
7 * the following copyright notices:
8 * Copyright (c) 2003-2004 Embedded Edge, LLC.
9 * Portions Copyright (C) 2002 Embedix, Inc
10 * Copyright 2002 Hewlett-Packard Company
12 * 2.6 version of this driver inspired by:
13 * (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
14 * All Rights Reserved.
15 * (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
16 * All Rights Reserved.
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
24 /* Why is a timer used to detect insert events?
26 * From the AU1100 MMC application guide:
27 * If the Au1100-based design is intended to support both MultiMediaCards
28 * and 1- or 4-data bit SecureDigital cards, then the solution is to
29 * connect a weak (560KOhm) pull-up resistor to connector pin 1.
30 * In doing so, a MMC card never enters SPI-mode communications,
31 * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
32 * (the low to high transition will not occur).
34 * So we use the timer to check the status manually.
37 #include <linux/module.h>
38 #include <linux/init.h>
39 #include <linux/platform_device.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/scatterlist.h>
44 #include <linux/leds.h>
45 #include <linux/mmc/host.h>
48 #include <asm/mach-au1x00/au1000.h>
49 #include <asm/mach-au1x00/au1xxx_dbdma.h>
50 #include <asm/mach-au1x00/au1100_mmc.h>
52 #define DRIVER_NAME "au1xxx-mmc"
54 /* Set this to enable special debugging macros */
58 #define DBG(fmt, idx, args...) \
59 printk(KERN_DEBUG "au1xmmc(%d): DEBUG: " fmt, idx, ##args)
61 #define DBG(fmt, idx, args...) do {} while (0)
64 /* Hardware definitions */
65 #define AU1XMMC_DESCRIPTOR_COUNT 1
66 #define AU1XMMC_DESCRIPTOR_SIZE 2048
68 #define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \
69 MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \
70 MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)
72 /* This gives us a hard value for the stop command that we can write directly
73 * to the command register.
76 (SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO)
78 /* This is the set of interrupts that we configure by default. */
79 #define AU1XMMC_INTERRUPTS \
80 (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_RAT | \
81 SD_CONFIG_CR | SD_CONFIG_I)
83 /* The poll event (looking for insert/remove events runs twice a second. */
84 #define AU1XMMC_DETECT_TIMEOUT (HZ/2)
88 struct mmc_request *mrq;
114 struct timer_list timer;
115 struct tasklet_struct finish_task;
116 struct tasklet_struct data_task;
117 struct au1xmmc_platform_data *platdata;
118 struct platform_device *pdev;
119 struct resource *ioarea;
122 /* Status flags used by the host structure */
123 #define HOST_F_XMIT 0x0001
124 #define HOST_F_RECV 0x0002
125 #define HOST_F_DMA 0x0010
126 #define HOST_F_ACTIVE 0x0100
127 #define HOST_F_STOP 0x1000
129 #define HOST_S_IDLE 0x0001
130 #define HOST_S_CMD 0x0002
131 #define HOST_S_DATA 0x0003
132 #define HOST_S_STOP 0x0004
134 /* Easy access macros */
135 #define HOST_STATUS(h) ((h)->iobase + SD_STATUS)
136 #define HOST_CONFIG(h) ((h)->iobase + SD_CONFIG)
137 #define HOST_ENABLE(h) ((h)->iobase + SD_ENABLE)
138 #define HOST_TXPORT(h) ((h)->iobase + SD_TXPORT)
139 #define HOST_RXPORT(h) ((h)->iobase + SD_RXPORT)
140 #define HOST_CMDARG(h) ((h)->iobase + SD_CMDARG)
141 #define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE)
142 #define HOST_CMD(h) ((h)->iobase + SD_CMD)
143 #define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2)
144 #define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT)
145 #define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG)
147 #define DMA_CHANNEL(h) \
148 (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan)
150 static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
152 u32 val = au_readl(HOST_CONFIG(host));
154 au_writel(val, HOST_CONFIG(host));
158 static inline void FLUSH_FIFO(struct au1xmmc_host *host)
160 u32 val = au_readl(HOST_CONFIG2(host));
162 au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
165 /* SEND_STOP will turn off clock control - this re-enables it */
166 val &= ~SD_CONFIG2_DF;
168 au_writel(val, HOST_CONFIG2(host));
172 static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
174 u32 val = au_readl(HOST_CONFIG(host));
176 au_writel(val, HOST_CONFIG(host));
180 static inline void SEND_STOP(struct au1xmmc_host *host)
184 WARN_ON(host->status != HOST_S_DATA);
185 host->status = HOST_S_STOP;
187 config2 = au_readl(HOST_CONFIG2(host));
188 au_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host));
191 /* Send the stop commmand */
192 au_writel(STOP_CMD, HOST_CMD(host));
195 static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
197 if (host->platdata && host->platdata->set_power)
198 host->platdata->set_power(host->mmc, state);
201 static int au1xmmc_card_inserted(struct au1xmmc_host *host)
205 if (host->platdata && host->platdata->card_inserted)
206 ret = host->platdata->card_inserted(host->mmc);
208 ret = 1; /* assume there is a card */
213 static int au1xmmc_card_readonly(struct mmc_host *mmc)
215 struct au1xmmc_host *host = mmc_priv(mmc);
218 if (host->platdata && host->platdata->card_readonly)
219 ret = host->platdata->card_readonly(mmc);
221 ret = 0; /* assume card is read-write */
226 static void au1xmmc_finish_request(struct au1xmmc_host *host)
228 struct mmc_request *mrq = host->mrq;
231 host->flags &= HOST_F_ACTIVE | HOST_F_DMA;
237 host->pio.offset = 0;
240 host->status = HOST_S_IDLE;
242 mmc_request_done(host->mmc, mrq);
245 static void au1xmmc_tasklet_finish(unsigned long param)
247 struct au1xmmc_host *host = (struct au1xmmc_host *) param;
248 au1xmmc_finish_request(host);
251 static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
252 struct mmc_command *cmd, struct mmc_data *data)
254 u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
256 switch (mmc_resp_type(cmd)) {
260 mmccmd |= SD_CMD_RT_1;
263 mmccmd |= SD_CMD_RT_1B;
266 mmccmd |= SD_CMD_RT_2;
269 mmccmd |= SD_CMD_RT_3;
272 printk(KERN_INFO "au1xmmc: unhandled response type %02x\n",
278 if (data->flags & MMC_DATA_READ) {
279 if (data->blocks > 1)
280 mmccmd |= SD_CMD_CT_4;
282 mmccmd |= SD_CMD_CT_2;
283 } else if (data->flags & MMC_DATA_WRITE) {
284 if (data->blocks > 1)
285 mmccmd |= SD_CMD_CT_3;
287 mmccmd |= SD_CMD_CT_1;
291 au_writel(cmd->arg, HOST_CMDARG(host));
295 IRQ_OFF(host, SD_CONFIG_CR);
297 au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
300 /* Wait for the command to go on the line */
301 while (au_readl(HOST_CMD(host)) & SD_CMD_GO)
304 /* Wait for the command to come back */
306 u32 status = au_readl(HOST_STATUS(host));
308 while (!(status & SD_STATUS_CR))
309 status = au_readl(HOST_STATUS(host));
311 /* Clear the CR status */
312 au_writel(SD_STATUS_CR, HOST_STATUS(host));
314 IRQ_ON(host, SD_CONFIG_CR);
320 static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
322 struct mmc_request *mrq = host->mrq;
323 struct mmc_data *data;
326 WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP));
328 if (host->mrq == NULL)
331 data = mrq->cmd->data;
334 status = au_readl(HOST_STATUS(host));
336 /* The transaction is really over when the SD_STATUS_DB bit is clear */
337 while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
338 status = au_readl(HOST_STATUS(host));
341 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
343 /* Process any errors */
344 crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
345 if (host->flags & HOST_F_XMIT)
346 crc |= ((status & 0x07) == 0x02) ? 0 : 1;
349 data->error = -EILSEQ;
351 /* Clear the CRC bits */
352 au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
354 data->bytes_xfered = 0;
357 if (host->flags & HOST_F_DMA) {
358 #ifdef CONFIG_SOC_AU1200 /* DBDMA */
359 u32 chan = DMA_CHANNEL(host);
361 chan_tab_t *c = *((chan_tab_t **)chan);
362 au1x_dma_chan_t *cp = c->chan_ptr;
363 data->bytes_xfered = cp->ddma_bytecnt;
367 (data->blocks * data->blksz) - host->pio.len;
370 au1xmmc_finish_request(host);
373 static void au1xmmc_tasklet_data(unsigned long param)
375 struct au1xmmc_host *host = (struct au1xmmc_host *)param;
377 u32 status = au_readl(HOST_STATUS(host));
378 au1xmmc_data_complete(host, status);
381 #define AU1XMMC_MAX_TRANSFER 8
383 static void au1xmmc_send_pio(struct au1xmmc_host *host)
385 struct mmc_data *data;
386 int sg_len, max, count;
387 unsigned char *sg_ptr, val;
389 struct scatterlist *sg;
391 data = host->mrq->data;
393 if (!(host->flags & HOST_F_XMIT))
396 /* This is the pointer to the data buffer */
397 sg = &data->sg[host->pio.index];
398 sg_ptr = sg_virt(sg) + host->pio.offset;
400 /* This is the space left inside the buffer */
401 sg_len = data->sg[host->pio.index].length - host->pio.offset;
403 /* Check if we need less than the size of the sg_buffer */
404 max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
405 if (max > AU1XMMC_MAX_TRANSFER)
406 max = AU1XMMC_MAX_TRANSFER;
408 for (count = 0; count < max; count++) {
409 status = au_readl(HOST_STATUS(host));
411 if (!(status & SD_STATUS_TH))
416 au_writel((unsigned long)val, HOST_TXPORT(host));
420 host->pio.len -= count;
421 host->pio.offset += count;
423 if (count == sg_len) {
425 host->pio.offset = 0;
428 if (host->pio.len == 0) {
429 IRQ_OFF(host, SD_CONFIG_TH);
431 if (host->flags & HOST_F_STOP)
434 tasklet_schedule(&host->data_task);
438 static void au1xmmc_receive_pio(struct au1xmmc_host *host)
440 struct mmc_data *data;
441 int max, count, sg_len = 0;
442 unsigned char *sg_ptr = NULL;
444 struct scatterlist *sg;
446 data = host->mrq->data;
448 if (!(host->flags & HOST_F_RECV))
453 if (host->pio.index < host->dma.len) {
454 sg = &data->sg[host->pio.index];
455 sg_ptr = sg_virt(sg) + host->pio.offset;
457 /* This is the space left inside the buffer */
458 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
460 /* Check if we need less than the size of the sg_buffer */
465 if (max > AU1XMMC_MAX_TRANSFER)
466 max = AU1XMMC_MAX_TRANSFER;
468 for (count = 0; count < max; count++) {
469 status = au_readl(HOST_STATUS(host));
471 if (!(status & SD_STATUS_NE))
474 if (status & SD_STATUS_RC) {
475 DBG("RX CRC Error [%d + %d].\n", host->pdev->id,
476 host->pio.len, count);
480 if (status & SD_STATUS_RO) {
481 DBG("RX Overrun [%d + %d]\n", host->pdev->id,
482 host->pio.len, count);
485 else if (status & SD_STATUS_RU) {
486 DBG("RX Underrun [%d + %d]\n", host->pdev->id,
487 host->pio.len, count);
491 val = au_readl(HOST_RXPORT(host));
494 *sg_ptr++ = (unsigned char)(val & 0xFF);
497 host->pio.len -= count;
498 host->pio.offset += count;
500 if (sg_len && count == sg_len) {
502 host->pio.offset = 0;
505 if (host->pio.len == 0) {
506 /* IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); */
507 IRQ_OFF(host, SD_CONFIG_NE);
509 if (host->flags & HOST_F_STOP)
512 tasklet_schedule(&host->data_task);
516 /* This is called when a command has been completed - grab the response
517 * and check for errors. Then start the data transfer if it is indicated.
519 static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
521 struct mmc_request *mrq = host->mrq;
522 struct mmc_command *cmd;
532 if (cmd->flags & MMC_RSP_PRESENT) {
533 if (cmd->flags & MMC_RSP_136) {
534 r[0] = au_readl(host->iobase + SD_RESP3);
535 r[1] = au_readl(host->iobase + SD_RESP2);
536 r[2] = au_readl(host->iobase + SD_RESP1);
537 r[3] = au_readl(host->iobase + SD_RESP0);
539 /* The CRC is omitted from the response, so really
540 * we only got 120 bytes, but the engine expects
541 * 128 bits, so we have to shift things up.
543 for (i = 0; i < 4; i++) {
544 cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
546 cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
549 /* Techincally, we should be getting all 48 bits of
550 * the response (SD_RESP1 + SD_RESP2), but because
551 * our response omits the CRC, our data ends up
552 * being shifted 8 bits to the right. In this case,
553 * that means that the OSR data starts at bit 31,
554 * so we can just read RESP0 and return that.
556 cmd->resp[0] = au_readl(host->iobase + SD_RESP0);
560 /* Figure out errors */
561 if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
562 cmd->error = -EILSEQ;
564 trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
566 if (!trans || cmd->error) {
567 IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF);
568 tasklet_schedule(&host->finish_task);
572 host->status = HOST_S_DATA;
574 if (host->flags & HOST_F_DMA) {
575 #ifdef CONFIG_SOC_AU1200 /* DBDMA */
576 u32 channel = DMA_CHANNEL(host);
578 /* Start the DMA as soon as the buffer gets something in it */
580 if (host->flags & HOST_F_RECV) {
581 u32 mask = SD_STATUS_DB | SD_STATUS_NE;
583 while((status & mask) != mask)
584 status = au_readl(HOST_STATUS(host));
587 au1xxx_dbdma_start(channel);
592 static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
594 unsigned int pbus = get_au1x00_speed();
595 unsigned int divisor;
599 * divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
601 pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2);
603 divisor = ((pbus / rate) / 2) - 1;
605 config = au_readl(HOST_CONFIG(host));
607 config &= ~(SD_CONFIG_DIV);
608 config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
610 au_writel(config, HOST_CONFIG(host));
614 static int au1xmmc_prepare_data(struct au1xmmc_host *host,
615 struct mmc_data *data)
617 int datalen = data->blocks * data->blksz;
619 if (data->flags & MMC_DATA_READ)
620 host->flags |= HOST_F_RECV;
622 host->flags |= HOST_F_XMIT;
625 host->flags |= HOST_F_STOP;
627 host->dma.dir = DMA_BIDIRECTIONAL;
629 host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
630 data->sg_len, host->dma.dir);
632 if (host->dma.len == 0)
635 au_writel(data->blksz - 1, HOST_BLKSIZE(host));
637 if (host->flags & HOST_F_DMA) {
638 #ifdef CONFIG_SOC_AU1200 /* DBDMA */
640 u32 channel = DMA_CHANNEL(host);
642 au1xxx_dbdma_stop(channel);
644 for (i = 0; i < host->dma.len; i++) {
645 u32 ret = 0, flags = DDMA_FLAGS_NOIE;
646 struct scatterlist *sg = &data->sg[i];
647 int sg_len = sg->length;
649 int len = (datalen > sg_len) ? sg_len : datalen;
651 if (i == host->dma.len - 1)
652 flags = DDMA_FLAGS_IE;
654 if (host->flags & HOST_F_XMIT) {
655 ret = au1xxx_dbdma_put_source_flags(channel,
656 (void *)sg_virt(sg), len, flags);
658 ret = au1xxx_dbdma_put_dest_flags(channel,
659 (void *)sg_virt(sg), len, flags);
670 host->pio.offset = 0;
671 host->pio.len = datalen;
673 if (host->flags & HOST_F_XMIT)
674 IRQ_ON(host, SD_CONFIG_TH);
676 IRQ_ON(host, SD_CONFIG_NE);
677 /* IRQ_ON(host, SD_CONFIG_RA | SD_CONFIG_RF); */
683 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
688 /* This actually starts a command or data transaction */
689 static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
691 struct au1xmmc_host *host = mmc_priv(mmc);
694 WARN_ON(irqs_disabled());
695 WARN_ON(host->status != HOST_S_IDLE);
698 host->status = HOST_S_CMD;
702 ret = au1xmmc_prepare_data(host, mrq->data);
706 ret = au1xmmc_send_command(host, 0, mrq->cmd, mrq->data);
709 mrq->cmd->error = ret;
710 au1xmmc_finish_request(host);
714 static void au1xmmc_reset_controller(struct au1xmmc_host *host)
716 /* Apply the clock */
717 au_writel(SD_ENABLE_CE, HOST_ENABLE(host));
720 au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
723 au_writel(~0, HOST_STATUS(host));
726 au_writel(0, HOST_BLKSIZE(host));
727 au_writel(0x001fffff, HOST_TIMEOUT(host));
730 au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
733 au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
736 au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
739 /* Configure interrupts */
740 au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
745 static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
747 struct au1xmmc_host *host = mmc_priv(mmc);
750 if (ios->power_mode == MMC_POWER_OFF)
751 au1xmmc_set_power(host, 0);
752 else if (ios->power_mode == MMC_POWER_ON) {
753 au1xmmc_set_power(host, 1);
756 if (ios->clock && ios->clock != host->clock) {
757 au1xmmc_set_clock(host, ios->clock);
758 host->clock = ios->clock;
761 config2 = au_readl(HOST_CONFIG2(host));
762 switch (ios->bus_width) {
763 case MMC_BUS_WIDTH_4:
764 config2 |= SD_CONFIG2_WB;
766 case MMC_BUS_WIDTH_1:
767 config2 &= ~SD_CONFIG2_WB;
770 au_writel(config2, HOST_CONFIG2(host));
774 #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
775 #define STATUS_DATA_IN (SD_STATUS_NE)
776 #define STATUS_DATA_OUT (SD_STATUS_TH)
778 static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
780 struct au1xmmc_host *host = dev_id;
783 status = au_readl(HOST_STATUS(host));
785 if (!(status & SD_STATUS_I))
786 return IRQ_NONE; /* not ours */
788 if (status & SD_STATUS_SI) /* SDIO */
789 mmc_signal_sdio_irq(host->mmc);
791 if (host->mrq && (status & STATUS_TIMEOUT)) {
792 if (status & SD_STATUS_RAT)
793 host->mrq->cmd->error = -ETIMEDOUT;
794 else if (status & SD_STATUS_DT)
795 host->mrq->data->error = -ETIMEDOUT;
797 /* In PIO mode, interrupts might still be enabled */
798 IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
800 /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */
801 tasklet_schedule(&host->finish_task);
804 else if (status & SD_STATUS_DD) {
805 /* Sometimes we get a DD before a NE in PIO mode */
806 if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE))
807 au1xmmc_receive_pio(host);
809 au1xmmc_data_complete(host, status);
810 /* tasklet_schedule(&host->data_task); */
814 else if (status & SD_STATUS_CR) {
815 if (host->status == HOST_S_CMD)
816 au1xmmc_cmd_complete(host, status);
818 } else if (!(host->flags & HOST_F_DMA)) {
819 if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT))
820 au1xmmc_send_pio(host);
821 else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN))
822 au1xmmc_receive_pio(host);
824 } else if (status & 0x203F3C70) {
825 DBG("Unhandled status %8.8x\n", host->pdev->id,
829 au_writel(status, HOST_STATUS(host));
835 #ifdef CONFIG_SOC_AU1200
836 /* 8bit memory DMA device */
837 static dbdev_tab_t au1xmmc_mem_dbdev = {
838 .dev_id = DSCR_CMD0_ALWAYS,
839 .dev_flags = DEV_FLAGS_ANYUSE,
842 .dev_physaddr = 0x00000000,
844 .dev_intpolarity = 0,
848 static void au1xmmc_dbdma_callback(int irq, void *dev_id)
850 struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id;
852 /* Avoid spurious interrupts */
856 if (host->flags & HOST_F_STOP)
859 tasklet_schedule(&host->data_task);
862 static int au1xmmc_dbdma_init(struct au1xmmc_host *host)
864 struct resource *res;
867 res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0);
872 res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1);
880 host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid,
881 au1xmmc_dbdma_callback, (void *)host);
882 if (!host->tx_chan) {
883 dev_err(&host->pdev->dev, "cannot allocate TX DMA\n");
887 host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid,
888 au1xmmc_dbdma_callback, (void *)host);
889 if (!host->rx_chan) {
890 dev_err(&host->pdev->dev, "cannot allocate RX DMA\n");
891 au1xxx_dbdma_chan_free(host->tx_chan);
895 au1xxx_dbdma_set_devwidth(host->tx_chan, 8);
896 au1xxx_dbdma_set_devwidth(host->rx_chan, 8);
898 au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT);
899 au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT);
901 /* DBDMA is good to go */
902 host->flags |= HOST_F_DMA;
907 static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host)
909 if (host->flags & HOST_F_DMA) {
910 host->flags &= ~HOST_F_DMA;
911 au1xxx_dbdma_chan_free(host->tx_chan);
912 au1xxx_dbdma_chan_free(host->rx_chan);
917 static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en)
919 struct au1xmmc_host *host = mmc_priv(mmc);
922 IRQ_ON(host, SD_CONFIG_SI);
924 IRQ_OFF(host, SD_CONFIG_SI);
927 static const struct mmc_host_ops au1xmmc_ops = {
928 .request = au1xmmc_request,
929 .set_ios = au1xmmc_set_ios,
930 .get_ro = au1xmmc_card_readonly,
931 .enable_sdio_irq = au1xmmc_enable_sdio_irq,
934 static void au1xmmc_poll_event(unsigned long arg)
936 struct au1xmmc_host *host = (struct au1xmmc_host *)arg;
937 int card = au1xmmc_card_inserted(host);
938 int controller = (host->flags & HOST_F_ACTIVE) ? 1 : 0;
940 if (card != controller) {
941 host->flags &= ~HOST_F_ACTIVE;
943 host->flags |= HOST_F_ACTIVE;
944 mmc_detect_change(host->mmc, 0);
948 if (host->mrq != NULL) {
949 u32 status = au_readl(HOST_STATUS(host));
950 DBG("PENDING - %8.8x\n", host->pdev->id, status);
953 mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT);
956 static void au1xmmc_init_cd_poll_timer(struct au1xmmc_host *host)
958 init_timer(&host->timer);
959 host->timer.function = au1xmmc_poll_event;
960 host->timer.data = (unsigned long)host;
961 host->timer.expires = jiffies + AU1XMMC_DETECT_TIMEOUT;
964 static int __devinit au1xmmc_probe(struct platform_device *pdev)
966 struct mmc_host *mmc;
967 struct au1xmmc_host *host;
971 mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
973 dev_err(&pdev->dev, "no memory for mmc_host\n");
978 host = mmc_priv(mmc);
980 host->platdata = pdev->dev.platform_data;
984 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
986 dev_err(&pdev->dev, "no mmio defined\n");
990 host->ioarea = request_mem_region(r->start, r->end - r->start + 1,
993 dev_err(&pdev->dev, "mmio already in use\n");
997 host->iobase = (unsigned long)ioremap(r->start, 0x3c);
999 dev_err(&pdev->dev, "cannot remap mmio\n");
1003 r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1005 dev_err(&pdev->dev, "no IRQ defined\n");
1009 host->irq = r->start;
1010 /* IRQ is shared among both SD controllers */
1011 ret = request_irq(host->irq, au1xmmc_irq, IRQF_SHARED,
1014 dev_err(&pdev->dev, "cannot grab IRQ\n");
1018 mmc->ops = &au1xmmc_ops;
1020 mmc->f_min = 450000;
1021 mmc->f_max = 24000000;
1023 mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE;
1024 mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT;
1026 mmc->max_blk_size = 2048;
1027 mmc->max_blk_count = 512;
1029 mmc->ocr_avail = AU1XMMC_OCR;
1030 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1032 host->status = HOST_S_IDLE;
1034 /* board-specific carddetect setup, if any */
1035 if (host->platdata && host->platdata->cd_setup) {
1036 ret = host->platdata->cd_setup(mmc, 1);
1038 dev_err(&pdev->dev, "board CD setup failed\n");
1042 /* poll the board-specific is-card-in-socket-? method */
1043 au1xmmc_init_cd_poll_timer(host);
1046 tasklet_init(&host->data_task, au1xmmc_tasklet_data,
1047 (unsigned long)host);
1049 tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
1050 (unsigned long)host);
1052 #ifdef CONFIG_SOC_AU1200
1053 ret = au1xmmc_dbdma_init(host);
1055 printk(KERN_INFO DRIVER_NAME ": DBDMA init failed; using PIO\n");
1058 #ifdef CONFIG_LEDS_CLASS
1059 if (host->platdata && host->platdata->led) {
1060 struct led_classdev *led = host->platdata->led;
1061 led->name = mmc_hostname(mmc);
1062 led->brightness = LED_OFF;
1063 led->default_trigger = mmc_hostname(mmc);
1064 ret = led_classdev_register(mmc_dev(mmc), led);
1070 au1xmmc_reset_controller(host);
1072 ret = mmc_add_host(mmc);
1074 dev_err(&pdev->dev, "cannot add mmc host\n");
1078 platform_set_drvdata(pdev, mmc);
1080 /* start the carddetect poll timer if necessary */
1081 if (!(host->platdata && host->platdata->cd_setup))
1082 add_timer(&host->timer);
1084 printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X"
1085 " (mode=%s)\n", pdev->id, host->iobase,
1086 host->flags & HOST_F_DMA ? "dma" : "pio");
1088 return 0; /* all ok */
1091 #ifdef CONFIG_LEDS_CLASS
1092 if (host->platdata && host->platdata->led)
1093 led_classdev_unregister(host->platdata->led);
1096 au_writel(0, HOST_ENABLE(host));
1097 au_writel(0, HOST_CONFIG(host));
1098 au_writel(0, HOST_CONFIG2(host));
1101 #ifdef CONFIG_SOC_AU1200
1102 au1xmmc_dbdma_shutdown(host);
1105 tasklet_kill(&host->data_task);
1106 tasklet_kill(&host->finish_task);
1108 if (host->platdata && host->platdata->cd_setup)
1109 host->platdata->cd_setup(mmc, 0);
1111 free_irq(host->irq, host);
1113 iounmap((void *)host->iobase);
1115 release_resource(host->ioarea);
1116 kfree(host->ioarea);
1123 static int __devexit au1xmmc_remove(struct platform_device *pdev)
1125 struct mmc_host *mmc = platform_get_drvdata(pdev);
1126 struct au1xmmc_host *host;
1129 host = mmc_priv(mmc);
1131 mmc_remove_host(mmc);
1133 #ifdef CONFIG_LEDS_CLASS
1134 if (host->platdata && host->platdata->led)
1135 led_classdev_unregister(host->platdata->led);
1138 if (host->platdata && host->platdata->cd_setup)
1139 host->platdata->cd_setup(mmc, 0);
1141 del_timer_sync(&host->timer);
1143 au_writel(0, HOST_ENABLE(host));
1144 au_writel(0, HOST_CONFIG(host));
1145 au_writel(0, HOST_CONFIG2(host));
1148 tasklet_kill(&host->data_task);
1149 tasklet_kill(&host->finish_task);
1151 #ifdef CONFIG_SOC_AU1200
1152 au1xmmc_dbdma_shutdown(host);
1154 au1xmmc_set_power(host, 0);
1156 free_irq(host->irq, host);
1157 iounmap((void *)host->iobase);
1158 release_resource(host->ioarea);
1159 kfree(host->ioarea);
1166 static struct platform_driver au1xmmc_driver = {
1167 .probe = au1xmmc_probe,
1168 .remove = au1xmmc_remove,
1172 .name = DRIVER_NAME,
1173 .owner = THIS_MODULE,
1177 static int __init au1xmmc_init(void)
1179 #ifdef CONFIG_SOC_AU1200
1180 /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
1181 * of 8 bits. And since devices are shared, we need to create
1182 * our own to avoid freaking out other devices.
1184 memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
1186 printk(KERN_ERR "au1xmmc: cannot add memory dbdma dev\n");
1188 return platform_driver_register(&au1xmmc_driver);
1191 static void __exit au1xmmc_exit(void)
1193 #ifdef CONFIG_SOC_AU1200
1195 au1xxx_ddma_del_device(memid);
1197 platform_driver_unregister(&au1xmmc_driver);
1200 module_init(au1xmmc_init);
1201 module_exit(au1xmmc_exit);
1203 MODULE_AUTHOR("Advanced Micro Devices, Inc");
1204 MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1205 MODULE_LICENSE("GPL");
1206 MODULE_ALIAS("platform:au1xxx-mmc");