2 * linux/drivers/mmc/at91_mci.c - ATMEL AT91RM9200 MCI Driver
4 * Copyright (C) 2005 Cougar Creek Computing Devices Ltd, All Rights Reserved
6 * Copyright (C) 2006 Malcolm Noyes
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 This is the AT91RM9200 MCI driver that has been tested with both MMC cards
15 and SD-cards. Boards that support write protect are now supported.
16 The CCAT91SBC001 board does not support SD cards.
18 The three entry points are at91_mci_request, at91_mci_set_ios
22 This configures the device to put it into the correct mode and clock speed
26 MCI request processes the commands sent in the mmc_request structure. This
27 can consist of a processing command and a stop command in the case of
28 multiple block transfers.
30 There are three main types of request, commands, reads and writes.
32 Commands are straight forward. The command is submitted to the controller and
33 the request function returns. When the controller generates an interrupt to indicate
34 the command is finished, the response to the command are read and the mmc_request_done
35 function called to end the request.
37 Reads and writes work in a similar manner to normal commands but involve the PDC (DMA)
38 controller to manage the transfers.
40 A read is done from the controller directly to the scatterlist passed in from the request.
41 Due to a bug in the controller, when a read is completed, all the words are byte
42 swapped in the scatterlist buffers.
44 The sequence of read interrupts is: ENDRX, RXBUFF, CMDRDY
46 A write is slightly different in that the bytes to write are read from the scatterlist
47 into a dma memory buffer (this is in case the source buffer should be read only). The
48 entire write buffer is then done from this single dma memory buffer.
50 The sequence of write interrupts is: ENDTX, TXBUFE, NOTBUSY, CMDRDY
53 Gets the status of the write protect pin, if available.
56 #include <linux/config.h>
57 #include <linux/module.h>
58 #include <linux/moduleparam.h>
59 #include <linux/init.h>
60 #include <linux/ioport.h>
61 #include <linux/platform_device.h>
62 #include <linux/interrupt.h>
63 #include <linux/blkdev.h>
64 #include <linux/delay.h>
65 #include <linux/err.h>
66 #include <linux/dma-mapping.h>
67 #include <linux/clk.h>
69 #include <linux/mmc/host.h>
70 #include <linux/mmc/protocol.h>
74 #include <asm/mach/mmc.h>
75 #include <asm/arch/board.h>
76 #include <asm/arch/gpio.h>
77 #include <asm/arch/at91rm9200_mci.h>
78 #include <asm/arch/at91rm9200_pdc.h>
80 #define DRIVER_NAME "at91_mci"
84 #ifdef CONFIG_MMC_DEBUG
88 #define DBG(fmt...) do { } while (0)
91 static struct clk *mci_clk;
93 #define FL_SENT_COMMAND (1 << 0)
94 #define FL_SENT_STOP (1 << 1)
99 * Read from a MCI register.
101 static inline unsigned long at91_mci_read(unsigned int reg)
103 void __iomem *mci_base = (void __iomem *)AT91_VA_BASE_MCI;
105 return __raw_readl(mci_base + reg);
109 * Write to a MCI register.
111 static inline void at91_mci_write(unsigned int reg, unsigned long value)
113 void __iomem *mci_base = (void __iomem *)AT91_VA_BASE_MCI;
115 __raw_writel(value, mci_base + reg);
119 * Low level type for this driver
123 struct mmc_host *mmc;
124 struct mmc_command *cmd;
125 struct mmc_request *request;
127 struct at91_mmc_data *board;
131 * Flag indicating when the command has been sent. This is used to
132 * work out whether or not to send the stop
135 /* flag for current bus settings */
138 /* DMA buffer used for transmitting */
139 unsigned int* buffer;
140 dma_addr_t physical_address;
141 unsigned int total_length;
143 /* Latest in the scatterlist that has been enabled for transfer, but not freed */
146 /* Latest in the scatterlist that has been enabled for transfer */
151 * Copy from sg to a dma block - used for transfers
153 static inline void at91mci_sg_to_dma(struct at91mci_host *host, struct mmc_data *data)
155 unsigned int len, i, size;
156 unsigned *dmabuf = host->buffer;
158 size = host->total_length;
162 * Just loop through all entries. Size might not
163 * be the entire list though so make sure that
164 * we do not transfer too much.
166 for (i = 0; i < len; i++) {
167 struct scatterlist *sg;
170 unsigned int *sgbuffer;
174 sgbuffer = kmap_atomic(sg->page, KM_BIO_SRC_IRQ) + sg->offset;
175 amount = min(size, sg->length);
179 for (index = 0; index < amount; index++)
180 *dmabuf++ = swab32(sgbuffer[index]);
182 kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ);
189 * Check that we didn't get a request to transfer
190 * more data than can fit into the SG list.
198 static void at91mci_pre_dma_read(struct at91mci_host *host)
201 struct scatterlist *sg;
202 struct mmc_command *cmd;
203 struct mmc_data *data;
205 DBG("pre dma read\n");
219 for (i = 0; i < 2; i++) {
220 /* nothing left to transfer */
221 if (host->transfer_index >= data->sg_len) {
222 DBG("Nothing left to transfer (index = %d)\n", host->transfer_index);
226 /* Check to see if this needs filling */
228 if (at91_mci_read(AT91_PDC_RCR) != 0) {
229 DBG("Transfer active in current\n");
234 if (at91_mci_read(AT91_PDC_RNCR) != 0) {
235 DBG("Transfer active in next\n");
240 /* Setup the next transfer */
241 DBG("Using transfer index %d\n", host->transfer_index);
243 sg = &data->sg[host->transfer_index++];
244 DBG("sg = %p\n", sg);
246 sg->dma_address = dma_map_page(NULL, sg->page, sg->offset, sg->length, DMA_FROM_DEVICE);
248 DBG("dma address = %08X, length = %d\n", sg->dma_address, sg->length);
251 at91_mci_write(AT91_PDC_RPR, sg->dma_address);
252 at91_mci_write(AT91_PDC_RCR, sg->length / 4);
255 at91_mci_write(AT91_PDC_RNPR, sg->dma_address);
256 at91_mci_write(AT91_PDC_RNCR, sg->length / 4);
260 DBG("pre dma read done\n");
264 * Handle after a dma read
266 static void at91mci_post_dma_read(struct at91mci_host *host)
268 struct mmc_command *cmd;
269 struct mmc_data *data;
271 DBG("post dma read\n");
285 while (host->in_use_index < host->transfer_index) {
286 unsigned int *buffer;
290 struct scatterlist *sg;
292 DBG("finishing index %d\n", host->in_use_index);
294 sg = &data->sg[host->in_use_index++];
296 DBG("Unmapping page %08X\n", sg->dma_address);
298 dma_unmap_page(NULL, sg->dma_address, sg->length, DMA_FROM_DEVICE);
300 /* Swap the contents of the buffer */
301 buffer = kmap_atomic(sg->page, KM_BIO_SRC_IRQ) + sg->offset;
302 DBG("buffer = %p, length = %d\n", buffer, sg->length);
304 data->bytes_xfered += sg->length;
306 len = sg->length / 4;
308 for (index = 0; index < len; index++) {
309 buffer[index] = swab32(buffer[index]);
311 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
312 flush_dcache_page(sg->page);
315 /* Is there another transfer to trigger? */
316 if (host->transfer_index < data->sg_len)
317 at91mci_pre_dma_read(host);
319 at91_mci_write(AT91_MCI_IER, AT91_MCI_RXBUFF);
320 at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
323 DBG("post dma read done\n");
327 * Handle transmitted data
329 static void at91_mci_handle_transmitted(struct at91mci_host *host)
331 struct mmc_command *cmd;
332 struct mmc_data *data;
334 DBG("Handling the transmit\n");
336 /* Disable the transfer */
337 at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
339 /* Now wait for cmd ready */
340 at91_mci_write(AT91_MCI_IDR, AT91_MCI_TXBUFE);
341 at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY);
349 data->bytes_xfered = host->total_length;
353 * Enable the controller
355 static void at91_mci_enable(void)
357 at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
358 at91_mci_write(AT91_MCI_IDR, 0xFFFFFFFF);
359 at91_mci_write(AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC);
360 at91_mci_write(AT91_MCI_MR, 0x834A);
361 at91_mci_write(AT91_MCI_SDCR, 0x0);
365 * Disable the controller
367 static void at91_mci_disable(void)
369 at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
374 * return the interrupts to enable
376 static unsigned int at91_mci_send_command(struct at91mci_host *host, struct mmc_command *cmd)
378 unsigned int cmdr, mr;
379 unsigned int block_length;
380 struct mmc_data *data = cmd->data;
383 unsigned int ier = 0;
387 /* Not sure if this is needed */
389 if ((at91_mci_read(AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) {
390 DBG("Clearing timeout\n");
391 at91_mci_write(AT91_MCI_ARGR, 0);
392 at91_mci_write(AT91_MCI_CMDR, AT91_MCI_OPDCMD);
393 while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY)) {
395 DBG("Clearing: SR = %08X\n", at91_mci_read(AT91_MCI_SR));
401 if (mmc_resp_type(cmd) == MMC_RSP_NONE)
402 cmdr |= AT91_MCI_RSPTYP_NONE;
404 /* if a response is expected then allow maximum response latancy */
405 cmdr |= AT91_MCI_MAXLAT;
406 /* set 136 bit response for R2, 48 bit response otherwise */
407 if (mmc_resp_type(cmd) == MMC_RSP_R2)
408 cmdr |= AT91_MCI_RSPTYP_136;
410 cmdr |= AT91_MCI_RSPTYP_48;
414 block_length = 1 << data->blksz_bits;
415 blocks = data->blocks;
417 /* always set data start - also set direction flag for read */
418 if (data->flags & MMC_DATA_READ)
419 cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START);
420 else if (data->flags & MMC_DATA_WRITE)
421 cmdr |= AT91_MCI_TRCMD_START;
423 if (data->flags & MMC_DATA_STREAM)
424 cmdr |= AT91_MCI_TRTYP_STREAM;
425 if (data->flags & MMC_DATA_MULTI)
426 cmdr |= AT91_MCI_TRTYP_MULTIPLE;
433 if (cmd->opcode == MMC_STOP_TRANSMISSION)
434 cmdr |= AT91_MCI_TRCMD_STOP;
436 if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
437 cmdr |= AT91_MCI_OPDCMD;
440 * Set the arguments and send the command
442 DBG("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08lX)\n",
443 cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91_MCI_MR));
446 at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTDIS | AT91_PDC_RXTDIS);
447 at91_mci_write(AT91_PDC_RPR, 0);
448 at91_mci_write(AT91_PDC_RCR, 0);
449 at91_mci_write(AT91_PDC_RNPR, 0);
450 at91_mci_write(AT91_PDC_RNCR, 0);
451 at91_mci_write(AT91_PDC_TPR, 0);
452 at91_mci_write(AT91_PDC_TCR, 0);
453 at91_mci_write(AT91_PDC_TNPR, 0);
454 at91_mci_write(AT91_PDC_TNCR, 0);
456 at91_mci_write(AT91_MCI_ARGR, cmd->arg);
457 at91_mci_write(AT91_MCI_CMDR, cmdr);
458 return AT91_MCI_CMDRDY;
461 mr = at91_mci_read(AT91_MCI_MR) & 0x7fff; /* zero block length and PDC mode */
462 at91_mci_write(AT91_MCI_MR, mr | (block_length << 16) | AT91_MCI_PDCMODE);
465 * Disable the PDC controller
467 at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
469 if (cmdr & AT91_MCI_TRCMD_START) {
470 data->bytes_xfered = 0;
471 host->transfer_index = 0;
472 host->in_use_index = 0;
473 if (cmdr & AT91_MCI_TRDIR) {
478 host->total_length = 0;
480 at91mci_pre_dma_read(host);
481 ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */;
487 host->total_length = block_length * blocks;
488 host->buffer = dma_alloc_coherent(NULL,
490 &host->physical_address, GFP_KERNEL);
492 at91mci_sg_to_dma(host, data);
494 DBG("Transmitting %d bytes\n", host->total_length);
496 at91_mci_write(AT91_PDC_TPR, host->physical_address);
497 at91_mci_write(AT91_PDC_TCR, host->total_length / 4);
498 ier = AT91_MCI_TXBUFE;
503 * Send the command and then enable the PDC - not the other way round as
504 * the data sheet says
507 at91_mci_write(AT91_MCI_ARGR, cmd->arg);
508 at91_mci_write(AT91_MCI_CMDR, cmdr);
510 if (cmdr & AT91_MCI_TRCMD_START) {
511 if (cmdr & AT91_MCI_TRDIR)
512 at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTEN);
514 at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTEN);
520 * Wait for a command to complete
522 static void at91mci_process_command(struct at91mci_host *host, struct mmc_command *cmd)
526 ier = at91_mci_send_command(host, cmd);
528 DBG("setting ier to %08X\n", ier);
530 /* Stop on errors or the required value */
531 at91_mci_write(AT91_MCI_IER, 0xffff0000 | ier);
535 * Process the next step in the request
537 static void at91mci_process_next(struct at91mci_host *host)
539 if (!(host->flags & FL_SENT_COMMAND)) {
540 host->flags |= FL_SENT_COMMAND;
541 at91mci_process_command(host, host->request->cmd);
543 else if ((!(host->flags & FL_SENT_STOP)) && host->request->stop) {
544 host->flags |= FL_SENT_STOP;
545 at91mci_process_command(host, host->request->stop);
548 mmc_request_done(host->mmc, host->request);
552 * Handle a command that has been completed
554 static void at91mci_completed_command(struct at91mci_host *host)
556 struct mmc_command *cmd = host->cmd;
559 at91_mci_write(AT91_MCI_IDR, 0xffffffff);
561 cmd->resp[0] = at91_mci_read(AT91_MCI_RSPR(0));
562 cmd->resp[1] = at91_mci_read(AT91_MCI_RSPR(1));
563 cmd->resp[2] = at91_mci_read(AT91_MCI_RSPR(2));
564 cmd->resp[3] = at91_mci_read(AT91_MCI_RSPR(3));
567 dma_free_coherent(NULL, host->total_length, host->buffer, host->physical_address);
571 status = at91_mci_read(AT91_MCI_SR);
573 DBG("Status = %08X [%08X %08X %08X %08X]\n",
574 status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
576 if (status & (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE |
577 AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE |
578 AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)) {
579 if ((status & AT91_MCI_RCRCE) &&
580 ((cmd->opcode == MMC_SEND_OP_COND) || (cmd->opcode == SD_APP_OP_COND))) {
581 cmd->error = MMC_ERR_NONE;
584 if (status & (AT91_MCI_RTOE | AT91_MCI_DTOE))
585 cmd->error = MMC_ERR_TIMEOUT;
586 else if (status & (AT91_MCI_RCRCE | AT91_MCI_DCRCE))
587 cmd->error = MMC_ERR_BADCRC;
588 else if (status & (AT91_MCI_OVRE | AT91_MCI_UNRE))
589 cmd->error = MMC_ERR_FIFO;
591 cmd->error = MMC_ERR_FAILED;
593 DBG("Error detected and set to %d (cmd = %d, retries = %d)\n",
594 cmd->error, cmd->opcode, cmd->retries);
598 cmd->error = MMC_ERR_NONE;
600 at91mci_process_next(host);
604 * Handle an MMC request
606 static void at91_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
608 struct at91mci_host *host = mmc_priv(mmc);
612 at91mci_process_next(host);
618 static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
621 struct at91mci_host *host = mmc_priv(mmc);
622 unsigned long at91_master_clock = clk_get_rate(mci_clk);
624 DBG("Clock %uHz, busmode %u, powermode %u, Vdd %u\n",
625 ios->clock, ios->bus_mode, ios->power_mode, ios->vdd);
628 host->bus_mode = ios->bus_mode;
630 printk("MMC: No host for bus_mode\n");
632 if (ios->clock == 0) {
633 /* Disable the MCI controller */
634 at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS);
638 /* Enable the MCI controller */
639 at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
641 if ((at91_master_clock % (ios->clock * 2)) == 0)
642 clkdiv = ((at91_master_clock / ios->clock) / 2) - 1;
644 clkdiv = (at91_master_clock / ios->clock) / 2;
646 DBG("clkdiv = %d. mcck = %ld\n", clkdiv,
647 at91_master_clock / (2 * (clkdiv + 1)));
649 if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) {
650 DBG("MMC: Setting controller bus width to 4\n");
651 at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) | AT91_MCI_SDCBUS);
654 DBG("MMC: Setting controller bus width to 1\n");
655 at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
658 /* Set the clock divider */
659 at91_mci_write(AT91_MCI_MR, (at91_mci_read(AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv);
661 /* maybe switch power to the card */
662 if (host && host->board->vcc_pin) {
663 switch (ios->power_mode) {
665 at91_set_gpio_output(host->board->vcc_pin, 0);
669 at91_set_gpio_output(host->board->vcc_pin, 1);
676 * Handle an interrupt
678 static irqreturn_t at91_mci_irq(int irq, void *devid, struct pt_regs *regs)
680 struct at91mci_host *host = devid;
683 unsigned int int_status;
688 int_status = at91_mci_read(AT91_MCI_SR);
689 DBG("MCI irq: status = %08X, %08lX, %08lX\n", int_status, at91_mci_read(AT91_MCI_IMR),
690 int_status & at91_mci_read(AT91_MCI_IMR));
692 if ((int_status & at91_mci_read(AT91_MCI_IMR)) & 0xffff0000)
695 int_status &= at91_mci_read(AT91_MCI_IMR);
697 if (int_status & AT91_MCI_UNRE)
698 DBG("MMC: Underrun error\n");
699 if (int_status & AT91_MCI_OVRE)
700 DBG("MMC: Overrun error\n");
701 if (int_status & AT91_MCI_DTOE)
702 DBG("MMC: Data timeout\n");
703 if (int_status & AT91_MCI_DCRCE)
704 DBG("MMC: CRC error in data\n");
705 if (int_status & AT91_MCI_RTOE)
706 DBG("MMC: Response timeout\n");
707 if (int_status & AT91_MCI_RENDE)
708 DBG("MMC: Response end bit error\n");
709 if (int_status & AT91_MCI_RCRCE)
710 DBG("MMC: Response CRC error\n");
711 if (int_status & AT91_MCI_RDIRE)
712 DBG("MMC: Response direction error\n");
713 if (int_status & AT91_MCI_RINDE)
714 DBG("MMC: Response index error\n");
716 /* Only continue processing if no errors */
718 if (int_status & AT91_MCI_TXBUFE) {
719 DBG("TX buffer empty\n");
720 at91_mci_handle_transmitted(host);
723 if (int_status & AT91_MCI_RXBUFF) {
724 DBG("RX buffer full\n");
725 at91_mci_write(AT91_MCI_IER, AT91_MCI_CMDRDY);
728 if (int_status & AT91_MCI_ENDTX) {
729 DBG("Transmit has ended\n");
732 if (int_status & AT91_MCI_ENDRX) {
733 DBG("Receive has ended\n");
734 at91mci_post_dma_read(host);
737 if (int_status & AT91_MCI_NOTBUSY) {
738 DBG("Card is ready\n");
739 at91_mci_write(AT91_MCI_IER, AT91_MCI_CMDRDY);
742 if (int_status & AT91_MCI_DTIP) {
743 DBG("Data transfer in progress\n");
746 if (int_status & AT91_MCI_BLKE) {
747 DBG("Block transfer has ended\n");
750 if (int_status & AT91_MCI_TXRDY) {
751 DBG("Ready to transmit\n");
754 if (int_status & AT91_MCI_RXRDY) {
755 DBG("Ready to receive\n");
758 if (int_status & AT91_MCI_CMDRDY) {
759 DBG("Command ready\n");
763 at91_mci_write(AT91_MCI_IDR, int_status);
766 DBG("Completed command\n");
767 at91_mci_write(AT91_MCI_IDR, 0xffffffff);
768 at91mci_completed_command(host);
774 static irqreturn_t at91_mmc_det_irq(int irq, void *_host, struct pt_regs *regs)
776 struct at91mci_host *host = _host;
777 int present = !at91_get_gpio_value(irq);
780 * we expect this irq on both insert and remove,
781 * and use a short delay to debounce.
783 if (present != host->present) {
784 host->present = present;
785 DBG("%s: card %s\n", mmc_hostname(host->mmc),
786 present ? "insert" : "remove");
788 DBG("****** Resetting SD-card bus width ******\n");
789 at91_mci_write(AT91_MCI_SDCR, 0);
791 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
796 int at91_mci_get_ro(struct mmc_host *mmc)
799 struct at91mci_host *host = mmc_priv(mmc);
801 if (host->board->wp_pin) {
802 read_only = at91_get_gpio_value(host->board->wp_pin);
803 printk(KERN_WARNING "%s: card is %s\n", mmc_hostname(mmc),
804 (read_only ? "read-only" : "read-write") );
807 printk(KERN_WARNING "%s: host does not support reading read-only "
808 "switch. Assuming write-enable.\n", mmc_hostname(mmc));
813 static struct mmc_host_ops at91_mci_ops = {
814 .request = at91_mci_request,
815 .set_ios = at91_mci_set_ios,
816 .get_ro = at91_mci_get_ro,
820 * Probe for the device
822 static int at91_mci_probe(struct platform_device *pdev)
824 struct mmc_host *mmc;
825 struct at91mci_host *host;
828 DBG("Probe MCI devices\n");
832 mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev);
834 DBG("Failed to allocate mmc host\n");
838 mmc->ops = &at91_mci_ops;
840 mmc->f_max = 25000000;
841 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
843 host = mmc_priv(mmc);
847 host->board = pdev->dev.platform_data;
848 if (host->board->wire4) {
850 mmc->caps |= MMC_CAP_4_BIT_DATA;
852 printk("MMC: 4 wire bus mode not supported by this driver - using 1 wire\n");
859 mci_clk = clk_get(&pdev->dev, "mci_clk");
861 printk(KERN_ERR "AT91 MMC: no clock defined.\n");
864 clk_enable(mci_clk); /* Enable the peripheral clock */
867 * Allocate the MCI interrupt
869 ret = request_irq(AT91_ID_MCI, at91_mci_irq, SA_SHIRQ, DRIVER_NAME, host);
871 DBG("Failed to request MCI interrupt\n");
875 platform_set_drvdata(pdev, mmc);
878 * Add host to MMC layer
880 if (host->board->det_pin)
881 host->present = !at91_get_gpio_value(host->board->det_pin);
888 * monitor card insertion/removal if we can
890 if (host->board->det_pin) {
891 ret = request_irq(host->board->det_pin, at91_mmc_det_irq,
892 SA_SAMPLE_RANDOM, DRIVER_NAME, host);
894 DBG("couldn't allocate MMC detect irq\n");
897 DBG(KERN_INFO "Added MCI driver\n");
905 static int at91_mci_remove(struct platform_device *pdev)
907 struct mmc_host *mmc = platform_get_drvdata(pdev);
908 struct at91mci_host *host;
913 host = mmc_priv(mmc);
915 if (host->present != -1) {
916 free_irq(host->board->det_pin, host);
917 cancel_delayed_work(&host->mmc->detect);
920 mmc_remove_host(mmc);
922 free_irq(AT91_ID_MCI, host);
925 clk_disable(mci_clk); /* Disable the peripheral clock */
928 platform_set_drvdata(pdev, NULL);
936 static int at91_mci_suspend(struct platform_device *pdev, pm_message_t state)
938 struct mmc_host *mmc = platform_get_drvdata(pdev);
942 ret = mmc_suspend_host(mmc, state);
947 static int at91_mci_resume(struct platform_device *pdev)
949 struct mmc_host *mmc = platform_get_drvdata(pdev);
953 ret = mmc_resume_host(mmc);
958 #define at91_mci_suspend NULL
959 #define at91_mci_resume NULL
962 static struct platform_driver at91_mci_driver = {
963 .probe = at91_mci_probe,
964 .remove = at91_mci_remove,
965 .suspend = at91_mci_suspend,
966 .resume = at91_mci_resume,
969 .owner = THIS_MODULE,
973 static int __init at91_mci_init(void)
975 return platform_driver_register(&at91_mci_driver);
978 static void __exit at91_mci_exit(void)
980 platform_driver_unregister(&at91_mci_driver);
983 module_init(at91_mci_init);
984 module_exit(at91_mci_exit);
986 MODULE_DESCRIPTION("AT91 Multimedia Card Interface driver");
987 MODULE_AUTHOR("Nick Randell");
988 MODULE_LICENSE("GPL");