2 * jmb38x_ms.c - JMicron jmb38x MemoryStick card reader
4 * Copyright (C) 2008 Alex Dubov <oakad@yahoo.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
12 #include <linux/spinlock.h>
13 #include <linux/interrupt.h>
14 #include <linux/pci.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/memstick.h>
20 #define DRIVER_NAME "jmb38x_ms"
23 module_param(no_dma, bool, 0644);
36 INT_STATUS_ENABLE = 0x28,
37 INT_SIGNAL_ENABLE = 0x2c,
40 PAD_OUTPUT_ENABLE = 0x38,
49 struct jmb38x_ms_host {
50 struct jmb38x_ms *chip;
56 unsigned int block_pos;
57 unsigned long timeout_jiffies;
58 struct timer_list timer;
59 struct memstick_request *req;
60 unsigned char cmd_flags;
62 unsigned int io_word[2];
68 struct memstick_host *hosts[];
71 #define BLOCK_COUNT_MASK 0xffff0000
72 #define BLOCK_SIZE_MASK 0x00000fff
74 #define DMA_CONTROL_ENABLE 0x00000001
76 #define TPC_DATA_SEL 0x00008000
77 #define TPC_DIR 0x00004000
78 #define TPC_WAIT_INT 0x00002000
79 #define TPC_GET_INT 0x00000800
80 #define TPC_CODE_SZ_MASK 0x00000700
81 #define TPC_DATA_SZ_MASK 0x00000007
83 #define HOST_CONTROL_RESET_REQ 0x00008000
84 #define HOST_CONTROL_REI 0x00004000
85 #define HOST_CONTROL_LED 0x00000400
86 #define HOST_CONTROL_FAST_CLK 0x00000200
87 #define HOST_CONTROL_RESET 0x00000100
88 #define HOST_CONTROL_POWER_EN 0x00000080
89 #define HOST_CONTROL_CLOCK_EN 0x00000040
90 #define HOST_CONTROL_IF_SHIFT 4
92 #define HOST_CONTROL_IF_SERIAL 0x0
93 #define HOST_CONTROL_IF_PAR4 0x1
94 #define HOST_CONTROL_IF_PAR8 0x3
96 #define STATUS_BUSY 0x00080000
97 #define STATUS_MS_DAT7 0x00040000
98 #define STATUS_MS_DAT6 0x00020000
99 #define STATUS_MS_DAT5 0x00010000
100 #define STATUS_MS_DAT4 0x00008000
101 #define STATUS_MS_DAT3 0x00004000
102 #define STATUS_MS_DAT2 0x00002000
103 #define STATUS_MS_DAT1 0x00001000
104 #define STATUS_MS_DAT0 0x00000800
105 #define STATUS_HAS_MEDIA 0x00000400
106 #define STATUS_FIFO_EMPTY 0x00000200
107 #define STATUS_FIFO_FULL 0x00000100
108 #define STATUS_MS_CED 0x00000080
109 #define STATUS_MS_ERR 0x00000040
110 #define STATUS_MS_BRQ 0x00000020
111 #define STATUS_MS_CNK 0x00000001
113 #define INT_STATUS_TPC_ERR 0x00080000
114 #define INT_STATUS_CRC_ERR 0x00040000
115 #define INT_STATUS_TIMER_TO 0x00020000
116 #define INT_STATUS_HSK_TO 0x00010000
117 #define INT_STATUS_ANY_ERR 0x00008000
118 #define INT_STATUS_FIFO_WRDY 0x00000080
119 #define INT_STATUS_FIFO_RRDY 0x00000040
120 #define INT_STATUS_MEDIA_OUT 0x00000010
121 #define INT_STATUS_MEDIA_IN 0x00000008
122 #define INT_STATUS_DMA_BOUNDARY 0x00000004
123 #define INT_STATUS_EOTRAN 0x00000002
124 #define INT_STATUS_EOTPC 0x00000001
126 #define INT_STATUS_ALL 0x000f801f
128 #define PAD_OUTPUT_ENABLE_MS 0x0F3F
130 #define PAD_PU_PD_OFF 0x7FFF0000
131 #define PAD_PU_PD_ON_MS_SOCK0 0x5f8f0000
132 #define PAD_PU_PD_ON_MS_SOCK1 0x0f0f0000
134 #define CLOCK_CONTROL_40MHZ 0x00000001
135 #define CLOCK_CONTROL_50MHZ 0x00000002
136 #define CLOCK_CONTROL_60MHZ 0x00000008
137 #define CLOCK_CONTROL_62_5MHZ 0x0000000c
138 #define CLOCK_CONTROL_OFF 0x00000000
147 static unsigned int jmb38x_ms_read_data(struct jmb38x_ms_host *host,
148 unsigned char *buf, unsigned int length)
150 unsigned int off = 0;
152 while (host->io_pos && length) {
153 buf[off++] = host->io_word[0] & 0xff;
154 host->io_word[0] >>= 8;
162 while (!(STATUS_FIFO_EMPTY & readl(host->addr + STATUS))) {
165 *(unsigned int *)(buf + off) = __raw_readl(host->addr + DATA);
171 && !(STATUS_FIFO_EMPTY & readl(host->addr + STATUS))) {
172 host->io_word[0] = readl(host->addr + DATA);
173 for (host->io_pos = 4; host->io_pos; --host->io_pos) {
174 buf[off++] = host->io_word[0] & 0xff;
175 host->io_word[0] >>= 8;
185 static unsigned int jmb38x_ms_read_reg_data(struct jmb38x_ms_host *host,
189 unsigned int off = 0;
191 while (host->io_pos > 4 && length) {
192 buf[off++] = host->io_word[0] & 0xff;
193 host->io_word[0] >>= 8;
201 while (host->io_pos && length) {
202 buf[off++] = host->io_word[1] & 0xff;
203 host->io_word[1] >>= 8;
211 static unsigned int jmb38x_ms_write_data(struct jmb38x_ms_host *host,
215 unsigned int off = 0;
218 while (host->io_pos < 4 && length) {
219 host->io_word[0] |= buf[off++] << (host->io_pos * 8);
225 if (host->io_pos == 4
226 && !(STATUS_FIFO_FULL & readl(host->addr + STATUS))) {
227 writel(host->io_word[0], host->addr + DATA);
229 host->io_word[0] = 0;
230 } else if (host->io_pos) {
237 while (!(STATUS_FIFO_FULL & readl(host->addr + STATUS))) {
241 __raw_writel(*(unsigned int *)(buf + off),
249 host->io_word[0] |= buf[off + 2] << 16;
252 host->io_word[0] |= buf[off + 1] << 8;
255 host->io_word[0] |= buf[off];
264 static unsigned int jmb38x_ms_write_reg_data(struct jmb38x_ms_host *host,
268 unsigned int off = 0;
270 while (host->io_pos < 4 && length) {
271 host->io_word[0] &= ~(0xff << (host->io_pos * 8));
272 host->io_word[0] |= buf[off++] << (host->io_pos * 8);
280 while (host->io_pos < 8 && length) {
281 host->io_word[1] &= ~(0xff << (host->io_pos * 8));
282 host->io_word[1] |= buf[off++] << (host->io_pos * 8);
290 static int jmb38x_ms_transfer_data(struct jmb38x_ms_host *host)
294 unsigned int t_size, p_cnt;
297 unsigned long flags = 0;
299 if (host->req->long_data) {
300 length = host->req->sg.length - host->block_pos;
301 off = host->req->sg.offset + host->block_pos;
303 length = host->req->data_len - host->block_pos;
308 unsigned int uninitialized_var(p_off);
310 if (host->req->long_data) {
311 pg = nth_page(sg_page(&host->req->sg),
313 p_off = offset_in_page(off);
314 p_cnt = PAGE_SIZE - p_off;
315 p_cnt = min(p_cnt, length);
317 local_irq_save(flags);
318 buf = kmap_atomic(pg, KM_BIO_SRC_IRQ) + p_off;
320 buf = host->req->data + host->block_pos;
321 p_cnt = host->req->data_len - host->block_pos;
324 if (host->req->data_dir == WRITE)
325 t_size = !(host->cmd_flags & REG_DATA)
326 ? jmb38x_ms_write_data(host, buf, p_cnt)
327 : jmb38x_ms_write_reg_data(host, buf, p_cnt);
329 t_size = !(host->cmd_flags & REG_DATA)
330 ? jmb38x_ms_read_data(host, buf, p_cnt)
331 : jmb38x_ms_read_reg_data(host, buf, p_cnt);
333 if (host->req->long_data) {
334 kunmap_atomic(buf - p_off, KM_BIO_SRC_IRQ);
335 local_irq_restore(flags);
340 host->block_pos += t_size;
345 if (!length && host->req->data_dir == WRITE) {
346 if (host->cmd_flags & REG_DATA) {
347 writel(host->io_word[0], host->addr + TPC_P0);
348 writel(host->io_word[1], host->addr + TPC_P1);
349 } else if (host->io_pos) {
350 writel(host->io_word[0], host->addr + DATA);
357 static int jmb38x_ms_issue_cmd(struct memstick_host *msh)
359 struct jmb38x_ms_host *host = memstick_priv(msh);
361 unsigned int data_len, cmd, t_val;
363 if (!(STATUS_HAS_MEDIA & readl(host->addr + STATUS))) {
364 dev_dbg(&msh->dev, "no media status\n");
365 host->req->error = -ETIME;
366 return host->req->error;
369 dev_dbg(&msh->dev, "control %08x\n",
370 readl(host->addr + HOST_CONTROL));
371 dev_dbg(&msh->dev, "status %08x\n", readl(host->addr + INT_STATUS));
372 dev_dbg(&msh->dev, "hstatus %08x\n", readl(host->addr + STATUS));
377 host->io_word[0] = 0;
378 host->io_word[1] = 0;
380 cmd = host->req->tpc << 16;
383 if (host->req->data_dir == READ)
385 if (host->req->need_card_int)
388 data = host->req->data;
391 host->cmd_flags |= DMA_DATA;
393 if (host->req->long_data) {
394 data_len = host->req->sg.length;
396 data_len = host->req->data_len;
397 host->cmd_flags &= ~DMA_DATA;
401 cmd &= ~(TPC_DATA_SEL | 0xf);
402 host->cmd_flags |= REG_DATA;
403 cmd |= data_len & 0xf;
404 host->cmd_flags &= ~DMA_DATA;
407 if (host->cmd_flags & DMA_DATA) {
408 if (1 != pci_map_sg(host->chip->pdev, &host->req->sg, 1,
409 host->req->data_dir == READ
411 : PCI_DMA_TODEVICE)) {
412 host->req->error = -ENOMEM;
413 return host->req->error;
415 data_len = sg_dma_len(&host->req->sg);
416 writel(sg_dma_address(&host->req->sg),
417 host->addr + DMA_ADDRESS);
418 writel(((1 << 16) & BLOCK_COUNT_MASK)
419 | (data_len & BLOCK_SIZE_MASK),
421 writel(DMA_CONTROL_ENABLE, host->addr + DMA_CONTROL);
422 } else if (!(host->cmd_flags & REG_DATA)) {
423 writel(((1 << 16) & BLOCK_COUNT_MASK)
424 | (data_len & BLOCK_SIZE_MASK),
426 t_val = readl(host->addr + INT_STATUS_ENABLE);
427 t_val |= host->req->data_dir == READ
428 ? INT_STATUS_FIFO_RRDY
429 : INT_STATUS_FIFO_WRDY;
431 writel(t_val, host->addr + INT_STATUS_ENABLE);
432 writel(t_val, host->addr + INT_SIGNAL_ENABLE);
434 cmd &= ~(TPC_DATA_SEL | 0xf);
435 host->cmd_flags |= REG_DATA;
436 cmd |= data_len & 0xf;
438 if (host->req->data_dir == WRITE) {
439 jmb38x_ms_transfer_data(host);
440 writel(host->io_word[0], host->addr + TPC_P0);
441 writel(host->io_word[1], host->addr + TPC_P1);
445 mod_timer(&host->timer, jiffies + host->timeout_jiffies);
446 writel(HOST_CONTROL_LED | readl(host->addr + HOST_CONTROL),
447 host->addr + HOST_CONTROL);
448 host->req->error = 0;
450 writel(cmd, host->addr + TPC);
451 dev_dbg(&msh->dev, "executing TPC %08x, len %x\n", cmd, data_len);
456 static void jmb38x_ms_complete_cmd(struct memstick_host *msh, int last)
458 struct jmb38x_ms_host *host = memstick_priv(msh);
459 unsigned int t_val = 0;
462 del_timer(&host->timer);
464 dev_dbg(&msh->dev, "c control %08x\n",
465 readl(host->addr + HOST_CONTROL));
466 dev_dbg(&msh->dev, "c status %08x\n",
467 readl(host->addr + INT_STATUS));
468 dev_dbg(&msh->dev, "c hstatus %08x\n", readl(host->addr + STATUS));
470 host->req->int_reg = readl(host->addr + STATUS) & 0xff;
472 writel(0, host->addr + BLOCK);
473 writel(0, host->addr + DMA_CONTROL);
475 if (host->cmd_flags & DMA_DATA) {
476 pci_unmap_sg(host->chip->pdev, &host->req->sg, 1,
477 host->req->data_dir == READ
478 ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE);
480 t_val = readl(host->addr + INT_STATUS_ENABLE);
481 if (host->req->data_dir == READ)
482 t_val &= ~INT_STATUS_FIFO_RRDY;
484 t_val &= ~INT_STATUS_FIFO_WRDY;
486 writel(t_val, host->addr + INT_STATUS_ENABLE);
487 writel(t_val, host->addr + INT_SIGNAL_ENABLE);
490 writel((~HOST_CONTROL_LED) & readl(host->addr + HOST_CONTROL),
491 host->addr + HOST_CONTROL);
495 rc = memstick_next_req(msh, &host->req);
496 } while (!rc && jmb38x_ms_issue_cmd(msh));
499 rc = memstick_next_req(msh, &host->req);
501 host->req->error = -ETIME;
506 static irqreturn_t jmb38x_ms_isr(int irq, void *dev_id)
508 struct memstick_host *msh = dev_id;
509 struct jmb38x_ms_host *host = memstick_priv(msh);
510 unsigned int irq_status;
512 spin_lock(&host->lock);
513 irq_status = readl(host->addr + INT_STATUS);
514 dev_dbg(&host->chip->pdev->dev, "irq_status = %08x\n", irq_status);
515 if (irq_status == 0 || irq_status == (~0)) {
516 spin_unlock(&host->lock);
521 if (irq_status & INT_STATUS_ANY_ERR) {
522 if (irq_status & INT_STATUS_CRC_ERR)
523 host->req->error = -EILSEQ;
525 host->req->error = -ETIME;
527 if (host->cmd_flags & DMA_DATA) {
528 if (irq_status & INT_STATUS_EOTRAN)
529 host->cmd_flags |= FIFO_READY;
531 if (irq_status & (INT_STATUS_FIFO_RRDY
532 | INT_STATUS_FIFO_WRDY))
533 jmb38x_ms_transfer_data(host);
535 if (irq_status & INT_STATUS_EOTRAN) {
536 jmb38x_ms_transfer_data(host);
537 host->cmd_flags |= FIFO_READY;
541 if (irq_status & INT_STATUS_EOTPC) {
542 host->cmd_flags |= CMD_READY;
543 if (host->cmd_flags & REG_DATA) {
544 if (host->req->data_dir == READ) {
553 jmb38x_ms_transfer_data(host);
555 host->cmd_flags |= FIFO_READY;
561 if (irq_status & (INT_STATUS_MEDIA_IN | INT_STATUS_MEDIA_OUT)) {
562 dev_dbg(&host->chip->pdev->dev, "media changed\n");
563 memstick_detect_change(msh);
566 writel(irq_status, host->addr + INT_STATUS);
569 && (((host->cmd_flags & CMD_READY)
570 && (host->cmd_flags & FIFO_READY))
571 || host->req->error))
572 jmb38x_ms_complete_cmd(msh, 0);
574 spin_unlock(&host->lock);
578 static void jmb38x_ms_abort(unsigned long data)
580 struct memstick_host *msh = (struct memstick_host *)data;
581 struct jmb38x_ms_host *host = memstick_priv(msh);
584 dev_dbg(&host->chip->pdev->dev, "abort\n");
585 spin_lock_irqsave(&host->lock, flags);
587 host->req->error = -ETIME;
588 jmb38x_ms_complete_cmd(msh, 0);
590 spin_unlock_irqrestore(&host->lock, flags);
593 static void jmb38x_ms_request(struct memstick_host *msh)
595 struct jmb38x_ms_host *host = memstick_priv(msh);
599 spin_lock_irqsave(&host->lock, flags);
601 spin_unlock_irqrestore(&host->lock, flags);
607 rc = memstick_next_req(msh, &host->req);
608 } while (!rc && jmb38x_ms_issue_cmd(msh));
609 spin_unlock_irqrestore(&host->lock, flags);
612 static int jmb38x_ms_reset(struct jmb38x_ms_host *host)
616 writel(HOST_CONTROL_RESET_REQ | HOST_CONTROL_CLOCK_EN
617 | readl(host->addr + HOST_CONTROL),
618 host->addr + HOST_CONTROL);
621 for (cnt = 0; cnt < 20; ++cnt) {
622 if (!(HOST_CONTROL_RESET_REQ
623 & readl(host->addr + HOST_CONTROL)))
628 dev_dbg(&host->chip->pdev->dev, "reset_req timeout\n");
632 writel(HOST_CONTROL_RESET | HOST_CONTROL_CLOCK_EN
633 | readl(host->addr + HOST_CONTROL),
634 host->addr + HOST_CONTROL);
637 for (cnt = 0; cnt < 20; ++cnt) {
638 if (!(HOST_CONTROL_RESET
639 & readl(host->addr + HOST_CONTROL)))
644 dev_dbg(&host->chip->pdev->dev, "reset timeout\n");
649 writel(INT_STATUS_ALL, host->addr + INT_SIGNAL_ENABLE);
650 writel(INT_STATUS_ALL, host->addr + INT_STATUS_ENABLE);
654 static int jmb38x_ms_set_param(struct memstick_host *msh,
655 enum memstick_param param,
658 struct jmb38x_ms_host *host = memstick_priv(msh);
659 unsigned int host_ctl = readl(host->addr + HOST_CONTROL);
660 unsigned int clock_ctl = CLOCK_CONTROL_40MHZ, clock_delay = 0;
665 if (value == MEMSTICK_POWER_ON) {
666 rc = jmb38x_ms_reset(host);
671 host_ctl |= HOST_CONTROL_POWER_EN
672 | HOST_CONTROL_CLOCK_EN;
673 writel(host_ctl, host->addr + HOST_CONTROL);
675 writel(host->id ? PAD_PU_PD_ON_MS_SOCK1
676 : PAD_PU_PD_ON_MS_SOCK0,
677 host->addr + PAD_PU_PD);
679 writel(PAD_OUTPUT_ENABLE_MS,
680 host->addr + PAD_OUTPUT_ENABLE);
683 dev_dbg(&host->chip->pdev->dev, "power on\n");
684 } else if (value == MEMSTICK_POWER_OFF) {
685 host_ctl &= ~(HOST_CONTROL_POWER_EN
686 | HOST_CONTROL_CLOCK_EN);
687 writel(host_ctl, host->addr + HOST_CONTROL);
688 writel(0, host->addr + PAD_OUTPUT_ENABLE);
689 writel(PAD_PU_PD_OFF, host->addr + PAD_PU_PD);
690 dev_dbg(&host->chip->pdev->dev, "power off\n");
694 case MEMSTICK_INTERFACE:
695 host_ctl &= ~(3 << HOST_CONTROL_IF_SHIFT);
697 if (value == MEMSTICK_SERIAL) {
698 host_ctl &= ~HOST_CONTROL_FAST_CLK;
699 host_ctl |= HOST_CONTROL_IF_SERIAL
700 << HOST_CONTROL_IF_SHIFT;
701 host_ctl |= HOST_CONTROL_REI;
702 clock_ctl = CLOCK_CONTROL_40MHZ;
704 } else if (value == MEMSTICK_PAR4) {
705 host_ctl |= HOST_CONTROL_FAST_CLK;
706 host_ctl |= HOST_CONTROL_IF_PAR4
707 << HOST_CONTROL_IF_SHIFT;
708 host_ctl &= ~HOST_CONTROL_REI;
709 clock_ctl = CLOCK_CONTROL_40MHZ;
711 } else if (value == MEMSTICK_PAR8) {
712 host_ctl |= HOST_CONTROL_FAST_CLK;
713 host_ctl |= HOST_CONTROL_IF_PAR8
714 << HOST_CONTROL_IF_SHIFT;
715 host_ctl &= ~HOST_CONTROL_REI;
716 clock_ctl = CLOCK_CONTROL_60MHZ;
720 writel(host_ctl, host->addr + HOST_CONTROL);
721 writel(clock_ctl, host->addr + CLOCK_CONTROL);
722 writel(clock_delay, host->addr + CLOCK_DELAY);
730 static int jmb38x_ms_suspend(struct pci_dev *dev, pm_message_t state)
732 struct jmb38x_ms *jm = pci_get_drvdata(dev);
735 for (cnt = 0; cnt < jm->host_cnt; ++cnt) {
738 memstick_suspend_host(jm->hosts[cnt]);
742 pci_enable_wake(dev, pci_choose_state(dev, state), 0);
743 pci_disable_device(dev);
744 pci_set_power_state(dev, pci_choose_state(dev, state));
748 static int jmb38x_ms_resume(struct pci_dev *dev)
750 struct jmb38x_ms *jm = pci_get_drvdata(dev);
753 pci_set_power_state(dev, PCI_D0);
754 pci_restore_state(dev);
755 rc = pci_enable_device(dev);
760 pci_read_config_dword(dev, 0xac, &rc);
761 pci_write_config_dword(dev, 0xac, rc | 0x00470000);
763 for (rc = 0; rc < jm->host_cnt; ++rc) {
766 memstick_resume_host(jm->hosts[rc]);
767 memstick_detect_change(jm->hosts[rc]);
775 #define jmb38x_ms_suspend NULL
776 #define jmb38x_ms_resume NULL
778 #endif /* CONFIG_PM */
780 static int jmb38x_ms_count_slots(struct pci_dev *pdev)
784 for (cnt = 0; cnt < PCI_ROM_RESOURCE; ++cnt) {
785 if (!(IORESOURCE_MEM & pci_resource_flags(pdev, cnt)))
788 if (256 != pci_resource_len(pdev, cnt))
796 static struct memstick_host *jmb38x_ms_alloc_host(struct jmb38x_ms *jm, int cnt)
798 struct memstick_host *msh;
799 struct jmb38x_ms_host *host;
801 msh = memstick_alloc_host(sizeof(struct jmb38x_ms_host),
806 host = memstick_priv(msh);
808 host->addr = ioremap(pci_resource_start(jm->pdev, cnt),
809 pci_resource_len(jm->pdev, cnt));
813 spin_lock_init(&host->lock);
815 snprintf(host->host_id, sizeof(host->host_id), DRIVER_NAME ":slot%d",
817 host->irq = jm->pdev->irq;
818 host->timeout_jiffies = msecs_to_jiffies(1000);
819 msh->request = jmb38x_ms_request;
820 msh->set_param = jmb38x_ms_set_param;
822 msh->caps = MEMSTICK_CAP_PAR4 | MEMSTICK_CAP_PAR8;
824 setup_timer(&host->timer, jmb38x_ms_abort, (unsigned long)msh);
826 if (!request_irq(host->irq, jmb38x_ms_isr, IRQF_SHARED, host->host_id,
836 static void jmb38x_ms_free_host(struct memstick_host *msh)
838 struct jmb38x_ms_host *host = memstick_priv(msh);
840 free_irq(host->irq, msh);
842 memstick_free_host(msh);
845 static int jmb38x_ms_probe(struct pci_dev *pdev,
846 const struct pci_device_id *dev_id)
848 struct jmb38x_ms *jm;
849 int pci_dev_busy = 0;
852 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
856 rc = pci_enable_device(pdev);
860 pci_set_master(pdev);
862 rc = pci_request_regions(pdev, DRIVER_NAME);
868 pci_read_config_dword(pdev, 0xac, &rc);
869 pci_write_config_dword(pdev, 0xac, rc | 0x00470000);
871 cnt = jmb38x_ms_count_slots(pdev);
878 jm = kzalloc(sizeof(struct jmb38x_ms)
879 + cnt * sizeof(struct memstick_host *), GFP_KERNEL);
887 pci_set_drvdata(pdev, jm);
889 for (cnt = 0; cnt < jm->host_cnt; ++cnt) {
890 jm->hosts[cnt] = jmb38x_ms_alloc_host(jm, cnt);
894 rc = memstick_add_host(jm->hosts[cnt]);
897 jmb38x_ms_free_host(jm->hosts[cnt]);
898 jm->hosts[cnt] = NULL;
908 pci_set_drvdata(pdev, NULL);
911 pci_release_regions(pdev);
914 pci_disable_device(pdev);
918 static void jmb38x_ms_remove(struct pci_dev *dev)
920 struct jmb38x_ms *jm = pci_get_drvdata(dev);
921 struct jmb38x_ms_host *host;
925 for (cnt = 0; cnt < jm->host_cnt; ++cnt) {
929 host = memstick_priv(jm->hosts[cnt]);
931 writel(0, host->addr + INT_SIGNAL_ENABLE);
932 writel(0, host->addr + INT_STATUS_ENABLE);
934 dev_dbg(&jm->pdev->dev, "interrupts off\n");
935 spin_lock_irqsave(&host->lock, flags);
937 host->req->error = -ETIME;
938 jmb38x_ms_complete_cmd(jm->hosts[cnt], 1);
940 spin_unlock_irqrestore(&host->lock, flags);
942 memstick_remove_host(jm->hosts[cnt]);
943 dev_dbg(&jm->pdev->dev, "host removed\n");
945 jmb38x_ms_free_host(jm->hosts[cnt]);
948 pci_set_drvdata(dev, NULL);
949 pci_release_regions(dev);
950 pci_disable_device(dev);
954 static struct pci_device_id jmb38x_ms_id_tbl [] = {
955 { PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_MS, PCI_ANY_ID,
956 PCI_ANY_ID, 0, 0, 0 },
960 static struct pci_driver jmb38x_ms_driver = {
962 .id_table = jmb38x_ms_id_tbl,
963 .probe = jmb38x_ms_probe,
964 .remove = jmb38x_ms_remove,
965 .suspend = jmb38x_ms_suspend,
966 .resume = jmb38x_ms_resume
969 static int __init jmb38x_ms_init(void)
971 return pci_register_driver(&jmb38x_ms_driver);
974 static void __exit jmb38x_ms_exit(void)
976 pci_unregister_driver(&jmb38x_ms_driver);
979 MODULE_AUTHOR("Alex Dubov");
980 MODULE_DESCRIPTION("JMicron jmb38x MemoryStick driver");
981 MODULE_LICENSE("GPL");
982 MODULE_DEVICE_TABLE(pci, jmb38x_ms_id_tbl);
984 module_init(jmb38x_ms_init);
985 module_exit(jmb38x_ms_exit);