5 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/errno.h>
23 #include <linux/string.h>
24 #include <linux/slab.h>
25 #include <linux/firmware.h>
26 #include <linux/videodev2.h>
27 #include <media/v4l2-common.h>
29 #include "pvrusb2-std.h"
30 #include "pvrusb2-util.h"
31 #include "pvrusb2-hdw.h"
32 #include "pvrusb2-i2c-core.h"
33 #include "pvrusb2-tuner.h"
34 #include "pvrusb2-eeprom.h"
35 #include "pvrusb2-hdw-internal.h"
36 #include "pvrusb2-encoder.h"
37 #include "pvrusb2-debug.h"
38 #include "pvrusb2-fx2-cmd.h"
40 #define TV_MIN_FREQ 55250000L
41 #define TV_MAX_FREQ 850000000L
43 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
44 static DEFINE_MUTEX(pvr2_unit_mtx);
47 static int initusbreset = 1;
48 static int procreload;
49 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
50 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
51 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
52 static int init_pause_msec;
54 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
55 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
56 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
57 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
58 module_param(initusbreset, int, S_IRUGO|S_IWUSR);
59 MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
60 module_param(procreload, int, S_IRUGO|S_IWUSR);
61 MODULE_PARM_DESC(procreload,
62 "Attempt init failure recovery with firmware reload");
63 module_param_array(tuner, int, NULL, 0444);
64 MODULE_PARM_DESC(tuner,"specify installed tuner type");
65 module_param_array(video_std, int, NULL, 0444);
66 MODULE_PARM_DESC(video_std,"specify initial video standard");
67 module_param_array(tolerance, int, NULL, 0444);
68 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
70 #define PVR2_CTL_WRITE_ENDPOINT 0x01
71 #define PVR2_CTL_READ_ENDPOINT 0x81
73 #define PVR2_GPIO_IN 0x9008
74 #define PVR2_GPIO_OUT 0x900c
75 #define PVR2_GPIO_DIR 0x9020
77 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
79 #define PVR2_FIRMWARE_ENDPOINT 0x02
81 /* size of a firmware chunk */
82 #define FIRMWARE_CHUNK_SIZE 0x2000
84 /* Define the list of additional controls we'll dynamically construct based
85 on query of the cx2341x module. */
86 struct pvr2_mpeg_ids {
90 static const struct pvr2_mpeg_ids mpeg_ids[] = {
92 .strid = "audio_layer",
93 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
95 .strid = "audio_bitrate",
96 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
98 /* Already using audio_mode elsewhere :-( */
99 .strid = "mpeg_audio_mode",
100 .id = V4L2_CID_MPEG_AUDIO_MODE,
102 .strid = "mpeg_audio_mode_extension",
103 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
105 .strid = "audio_emphasis",
106 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
108 .strid = "audio_crc",
109 .id = V4L2_CID_MPEG_AUDIO_CRC,
111 .strid = "video_aspect",
112 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
114 .strid = "video_b_frames",
115 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
117 .strid = "video_gop_size",
118 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
120 .strid = "video_gop_closure",
121 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
123 .strid = "video_bitrate_mode",
124 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
126 .strid = "video_bitrate",
127 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
129 .strid = "video_bitrate_peak",
130 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
132 .strid = "video_temporal_decimation",
133 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
135 .strid = "stream_type",
136 .id = V4L2_CID_MPEG_STREAM_TYPE,
138 .strid = "video_spatial_filter_mode",
139 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
141 .strid = "video_spatial_filter",
142 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
144 .strid = "video_luma_spatial_filter_type",
145 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
147 .strid = "video_chroma_spatial_filter_type",
148 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
150 .strid = "video_temporal_filter_mode",
151 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
153 .strid = "video_temporal_filter",
154 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
156 .strid = "video_median_filter_type",
157 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
159 .strid = "video_luma_median_filter_top",
160 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
162 .strid = "video_luma_median_filter_bottom",
163 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
165 .strid = "video_chroma_median_filter_top",
166 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
168 .strid = "video_chroma_median_filter_bottom",
169 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
172 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
175 static const char *control_values_srate[] = {
176 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
177 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
178 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
183 static const char *control_values_input[] = {
184 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
185 [PVR2_CVAL_INPUT_DTV] = "dtv",
186 [PVR2_CVAL_INPUT_RADIO] = "radio",
187 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
188 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
192 static const char *control_values_audiomode[] = {
193 [V4L2_TUNER_MODE_MONO] = "Mono",
194 [V4L2_TUNER_MODE_STEREO] = "Stereo",
195 [V4L2_TUNER_MODE_LANG1] = "Lang1",
196 [V4L2_TUNER_MODE_LANG2] = "Lang2",
197 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
201 static const char *control_values_hsm[] = {
202 [PVR2_CVAL_HSM_FAIL] = "Fail",
203 [PVR2_CVAL_HSM_HIGH] = "High",
204 [PVR2_CVAL_HSM_FULL] = "Full",
208 static const char *pvr2_state_names[] = {
209 [PVR2_STATE_NONE] = "none",
210 [PVR2_STATE_DEAD] = "dead",
211 [PVR2_STATE_COLD] = "cold",
212 [PVR2_STATE_WARM] = "warm",
213 [PVR2_STATE_ERROR] = "error",
214 [PVR2_STATE_READY] = "ready",
215 [PVR2_STATE_RUN] = "run",
219 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
220 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
221 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
222 static void pvr2_hdw_worker_i2c(struct work_struct *work);
223 static void pvr2_hdw_worker_poll(struct work_struct *work);
224 static void pvr2_hdw_worker_init(struct work_struct *work);
225 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
226 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
227 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
228 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
229 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
230 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
231 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
232 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
233 static void pvr2_hdw_quiescent_timeout(unsigned long);
234 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
235 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
236 unsigned int timeout,int probe_fl,
237 void *write_data,unsigned int write_len,
238 void *read_data,unsigned int read_len);
241 static void trace_stbit(const char *name,int val)
243 pvr2_trace(PVR2_TRACE_STBITS,
244 "State bit %s <-- %s",
245 name,(val ? "true" : "false"));
248 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
250 struct pvr2_hdw *hdw = cptr->hdw;
251 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
252 *vp = hdw->freqTable[hdw->freqProgSlot-1];
259 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
261 struct pvr2_hdw *hdw = cptr->hdw;
262 unsigned int slotId = hdw->freqProgSlot;
263 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
264 hdw->freqTable[slotId-1] = v;
265 /* Handle side effects correctly - if we're tuned to this
266 slot, then forgot the slot id relation since the stored
267 frequency has been changed. */
268 if (hdw->freqSelector) {
269 if (hdw->freqSlotRadio == slotId) {
270 hdw->freqSlotRadio = 0;
273 if (hdw->freqSlotTelevision == slotId) {
274 hdw->freqSlotTelevision = 0;
281 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
283 *vp = cptr->hdw->freqProgSlot;
287 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
289 struct pvr2_hdw *hdw = cptr->hdw;
290 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
291 hdw->freqProgSlot = v;
296 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
298 struct pvr2_hdw *hdw = cptr->hdw;
299 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
303 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
306 struct pvr2_hdw *hdw = cptr->hdw;
307 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
309 freq = hdw->freqTable[slotId-1];
311 pvr2_hdw_set_cur_freq(hdw,freq);
313 if (hdw->freqSelector) {
314 hdw->freqSlotRadio = slotId;
316 hdw->freqSlotTelevision = slotId;
321 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
323 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
327 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
329 return cptr->hdw->freqDirty != 0;
332 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
334 cptr->hdw->freqDirty = 0;
337 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
339 pvr2_hdw_set_cur_freq(cptr->hdw,v);
343 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
345 /* Actual maximum depends on the video standard in effect. */
346 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
354 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
356 /* Actual minimum depends on device digitizer type. */
357 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
365 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
367 *vp = cptr->hdw->input_val;
371 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
373 return ((1 << v) & cptr->hdw->input_avail_mask) != 0;
376 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
378 struct pvr2_hdw *hdw = cptr->hdw;
380 if (hdw->input_val != v) {
382 hdw->input_dirty = !0;
385 /* Handle side effects - if we switch to a mode that needs the RF
386 tuner, then select the right frequency choice as well and mark
388 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
389 hdw->freqSelector = 0;
391 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
392 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
393 hdw->freqSelector = 1;
399 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
401 return cptr->hdw->input_dirty != 0;
404 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
406 cptr->hdw->input_dirty = 0;
410 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
413 struct pvr2_hdw *hdw = cptr->hdw;
414 if (hdw->tuner_signal_stale) {
415 pvr2_i2c_core_status_poll(hdw);
417 fv = hdw->tuner_signal_info.rangehigh;
419 /* Safety fallback */
423 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
432 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
435 struct pvr2_hdw *hdw = cptr->hdw;
436 if (hdw->tuner_signal_stale) {
437 pvr2_i2c_core_status_poll(hdw);
439 fv = hdw->tuner_signal_info.rangelow;
441 /* Safety fallback */
445 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
454 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
456 return cptr->hdw->enc_stale != 0;
459 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
461 cptr->hdw->enc_stale = 0;
462 cptr->hdw->enc_unsafe_stale = 0;
465 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
468 struct v4l2_ext_controls cs;
469 struct v4l2_ext_control c1;
470 memset(&cs,0,sizeof(cs));
471 memset(&c1,0,sizeof(c1));
474 c1.id = cptr->info->v4l_id;
475 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
482 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
485 struct pvr2_hdw *hdw = cptr->hdw;
486 struct v4l2_ext_controls cs;
487 struct v4l2_ext_control c1;
488 memset(&cs,0,sizeof(cs));
489 memset(&c1,0,sizeof(c1));
492 c1.id = cptr->info->v4l_id;
494 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
495 hdw->state_encoder_run, &cs,
498 /* Oops. cx2341x is telling us it's not safe to change
499 this control while we're capturing. Make a note of this
500 fact so that the pipeline will be stopped the next time
501 controls are committed. Then go on ahead and store this
503 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
506 if (!ret) hdw->enc_unsafe_stale = !0;
513 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
515 struct v4l2_queryctrl qctrl;
516 struct pvr2_ctl_info *info;
517 qctrl.id = cptr->info->v4l_id;
518 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
519 /* Strip out the const so we can adjust a function pointer. It's
520 OK to do this here because we know this is a dynamically created
521 control, so the underlying storage for the info pointer is (a)
522 private to us, and (b) not in read-only storage. Either we do
523 this or we significantly complicate the underlying control
525 info = (struct pvr2_ctl_info *)(cptr->info);
526 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
527 if (info->set_value) {
528 info->set_value = NULL;
531 if (!(info->set_value)) {
532 info->set_value = ctrl_cx2341x_set;
538 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
540 *vp = cptr->hdw->state_pipeline_req;
544 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
546 *vp = cptr->hdw->master_state;
550 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
552 int result = pvr2_hdw_is_hsm(cptr->hdw);
553 *vp = PVR2_CVAL_HSM_FULL;
554 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
555 if (result) *vp = PVR2_CVAL_HSM_HIGH;
559 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
561 *vp = cptr->hdw->std_mask_avail;
565 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
567 struct pvr2_hdw *hdw = cptr->hdw;
569 ns = hdw->std_mask_avail;
570 ns = (ns & ~m) | (v & m);
571 if (ns == hdw->std_mask_avail) return 0;
572 hdw->std_mask_avail = ns;
573 pvr2_hdw_internal_set_std_avail(hdw);
574 pvr2_hdw_internal_find_stdenum(hdw);
578 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
579 char *bufPtr,unsigned int bufSize,
582 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
586 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
587 const char *bufPtr,unsigned int bufSize,
592 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
593 if (ret < 0) return ret;
594 if (mskp) *mskp = id;
595 if (valp) *valp = id;
599 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
601 *vp = cptr->hdw->std_mask_cur;
605 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
607 struct pvr2_hdw *hdw = cptr->hdw;
609 ns = hdw->std_mask_cur;
610 ns = (ns & ~m) | (v & m);
611 if (ns == hdw->std_mask_cur) return 0;
612 hdw->std_mask_cur = ns;
614 pvr2_hdw_internal_find_stdenum(hdw);
618 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
620 return cptr->hdw->std_dirty != 0;
623 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
625 cptr->hdw->std_dirty = 0;
628 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
630 struct pvr2_hdw *hdw = cptr->hdw;
631 pvr2_i2c_core_status_poll(hdw);
632 *vp = hdw->tuner_signal_info.signal;
636 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
639 unsigned int subchan;
640 struct pvr2_hdw *hdw = cptr->hdw;
641 pvr2_i2c_core_status_poll(hdw);
642 subchan = hdw->tuner_signal_info.rxsubchans;
643 if (subchan & V4L2_TUNER_SUB_MONO) {
644 val |= (1 << V4L2_TUNER_MODE_MONO);
646 if (subchan & V4L2_TUNER_SUB_STEREO) {
647 val |= (1 << V4L2_TUNER_MODE_STEREO);
649 if (subchan & V4L2_TUNER_SUB_LANG1) {
650 val |= (1 << V4L2_TUNER_MODE_LANG1);
652 if (subchan & V4L2_TUNER_SUB_LANG2) {
653 val |= (1 << V4L2_TUNER_MODE_LANG2);
660 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
662 struct pvr2_hdw *hdw = cptr->hdw;
663 if (v < 0) return -EINVAL;
664 if (v > hdw->std_enum_cnt) return -EINVAL;
665 hdw->std_enum_cur = v;
668 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
669 hdw->std_mask_cur = hdw->std_defs[v].id;
675 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
677 *vp = cptr->hdw->std_enum_cur;
682 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
684 return cptr->hdw->std_dirty != 0;
688 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
690 cptr->hdw->std_dirty = 0;
694 #define DEFINT(vmin,vmax) \
695 .type = pvr2_ctl_int, \
696 .def.type_int.min_value = vmin, \
697 .def.type_int.max_value = vmax
699 #define DEFENUM(tab) \
700 .type = pvr2_ctl_enum, \
701 .def.type_enum.count = ARRAY_SIZE(tab), \
702 .def.type_enum.value_names = tab
705 .type = pvr2_ctl_bool
707 #define DEFMASK(msk,tab) \
708 .type = pvr2_ctl_bitmask, \
709 .def.type_bitmask.valid_bits = msk, \
710 .def.type_bitmask.bit_names = tab
712 #define DEFREF(vname) \
713 .set_value = ctrl_set_##vname, \
714 .get_value = ctrl_get_##vname, \
715 .is_dirty = ctrl_isdirty_##vname, \
716 .clear_dirty = ctrl_cleardirty_##vname
719 #define VCREATE_FUNCS(vname) \
720 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
721 {*vp = cptr->hdw->vname##_val; return 0;} \
722 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
723 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
724 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
725 {return cptr->hdw->vname##_dirty != 0;} \
726 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
727 {cptr->hdw->vname##_dirty = 0;}
729 VCREATE_FUNCS(brightness)
730 VCREATE_FUNCS(contrast)
731 VCREATE_FUNCS(saturation)
733 VCREATE_FUNCS(volume)
734 VCREATE_FUNCS(balance)
736 VCREATE_FUNCS(treble)
738 VCREATE_FUNCS(audiomode)
739 VCREATE_FUNCS(res_hor)
740 VCREATE_FUNCS(res_ver)
743 /* Table definition of all controls which can be manipulated */
744 static const struct pvr2_ctl_info control_defs[] = {
746 .v4l_id = V4L2_CID_BRIGHTNESS,
747 .desc = "Brightness",
748 .name = "brightness",
749 .default_value = 128,
753 .v4l_id = V4L2_CID_CONTRAST,
760 .v4l_id = V4L2_CID_SATURATION,
761 .desc = "Saturation",
762 .name = "saturation",
767 .v4l_id = V4L2_CID_HUE,
774 .v4l_id = V4L2_CID_AUDIO_VOLUME,
777 .default_value = 62000,
781 .v4l_id = V4L2_CID_AUDIO_BALANCE,
786 DEFINT(-32768,32767),
788 .v4l_id = V4L2_CID_AUDIO_BASS,
793 DEFINT(-32768,32767),
795 .v4l_id = V4L2_CID_AUDIO_TREBLE,
800 DEFINT(-32768,32767),
802 .v4l_id = V4L2_CID_AUDIO_MUTE,
809 .desc = "Video Source",
811 .internal_id = PVR2_CID_INPUT,
812 .default_value = PVR2_CVAL_INPUT_TV,
813 .check_value = ctrl_check_input,
815 DEFENUM(control_values_input),
817 .desc = "Audio Mode",
818 .name = "audio_mode",
819 .internal_id = PVR2_CID_AUDIOMODE,
820 .default_value = V4L2_TUNER_MODE_STEREO,
822 DEFENUM(control_values_audiomode),
824 .desc = "Horizontal capture resolution",
825 .name = "resolution_hor",
826 .internal_id = PVR2_CID_HRES,
827 .default_value = 720,
831 .desc = "Vertical capture resolution",
832 .name = "resolution_ver",
833 .internal_id = PVR2_CID_VRES,
834 .default_value = 480,
837 /* Hook in check for video standard and adjust maximum
838 depending on the standard. */
839 .get_max_value = ctrl_vres_max_get,
840 .get_min_value = ctrl_vres_min_get,
842 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
843 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
844 .desc = "Audio Sampling Frequency",
847 DEFENUM(control_values_srate),
849 .desc = "Tuner Frequency (Hz)",
851 .internal_id = PVR2_CID_FREQUENCY,
853 .set_value = ctrl_freq_set,
854 .get_value = ctrl_freq_get,
855 .is_dirty = ctrl_freq_is_dirty,
856 .clear_dirty = ctrl_freq_clear_dirty,
858 /* Hook in check for input value (tv/radio) and adjust
859 max/min values accordingly */
860 .get_max_value = ctrl_freq_max_get,
861 .get_min_value = ctrl_freq_min_get,
865 .set_value = ctrl_channel_set,
866 .get_value = ctrl_channel_get,
867 DEFINT(0,FREQTABLE_SIZE),
869 .desc = "Channel Program Frequency",
870 .name = "freq_table_value",
871 .set_value = ctrl_channelfreq_set,
872 .get_value = ctrl_channelfreq_get,
874 /* Hook in check for input value (tv/radio) and adjust
875 max/min values accordingly */
876 .get_max_value = ctrl_freq_max_get,
877 .get_min_value = ctrl_freq_min_get,
879 .desc = "Channel Program ID",
880 .name = "freq_table_channel",
881 .set_value = ctrl_channelprog_set,
882 .get_value = ctrl_channelprog_get,
883 DEFINT(0,FREQTABLE_SIZE),
885 .desc = "Streaming Enabled",
886 .name = "streaming_enabled",
887 .get_value = ctrl_streamingenabled_get,
892 .get_value = ctrl_hsm_get,
893 DEFENUM(control_values_hsm),
895 .desc = "Master State",
896 .name = "master_state",
897 .get_value = ctrl_masterstate_get,
898 DEFENUM(pvr2_state_names),
900 .desc = "Signal Present",
901 .name = "signal_present",
902 .get_value = ctrl_signal_get,
905 .desc = "Audio Modes Present",
906 .name = "audio_modes_present",
907 .get_value = ctrl_audio_modes_present_get,
908 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
909 v4l. Nothing outside of this module cares about this,
910 but I reuse it in order to also reuse the
911 control_values_audiomode string table. */
912 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
913 (1 << V4L2_TUNER_MODE_STEREO)|
914 (1 << V4L2_TUNER_MODE_LANG1)|
915 (1 << V4L2_TUNER_MODE_LANG2)),
916 control_values_audiomode),
918 .desc = "Video Standards Available Mask",
919 .name = "video_standard_mask_available",
920 .internal_id = PVR2_CID_STDAVAIL,
922 .get_value = ctrl_stdavail_get,
923 .set_value = ctrl_stdavail_set,
924 .val_to_sym = ctrl_std_val_to_sym,
925 .sym_to_val = ctrl_std_sym_to_val,
926 .type = pvr2_ctl_bitmask,
928 .desc = "Video Standards In Use Mask",
929 .name = "video_standard_mask_active",
930 .internal_id = PVR2_CID_STDCUR,
932 .get_value = ctrl_stdcur_get,
933 .set_value = ctrl_stdcur_set,
934 .is_dirty = ctrl_stdcur_is_dirty,
935 .clear_dirty = ctrl_stdcur_clear_dirty,
936 .val_to_sym = ctrl_std_val_to_sym,
937 .sym_to_val = ctrl_std_sym_to_val,
938 .type = pvr2_ctl_bitmask,
940 .desc = "Video Standard Name",
941 .name = "video_standard",
942 .internal_id = PVR2_CID_STDENUM,
944 .get_value = ctrl_stdenumcur_get,
945 .set_value = ctrl_stdenumcur_set,
946 .is_dirty = ctrl_stdenumcur_is_dirty,
947 .clear_dirty = ctrl_stdenumcur_clear_dirty,
948 .type = pvr2_ctl_enum,
952 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
955 const char *pvr2_config_get_name(enum pvr2_config cfg)
958 case pvr2_config_empty: return "empty";
959 case pvr2_config_mpeg: return "mpeg";
960 case pvr2_config_vbi: return "vbi";
961 case pvr2_config_pcm: return "pcm";
962 case pvr2_config_rawvideo: return "raw video";
968 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
974 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
976 return hdw->serial_number;
980 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
982 return hdw->bus_info;
986 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
988 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
991 /* Set the currently tuned frequency and account for all possible
992 driver-core side effects of this action. */
993 void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
995 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
996 if (hdw->freqSelector) {
997 /* Swing over to radio frequency selection */
998 hdw->freqSelector = 0;
1001 if (hdw->freqValRadio != val) {
1002 hdw->freqValRadio = val;
1003 hdw->freqSlotRadio = 0;
1004 hdw->freqDirty = !0;
1007 if (!(hdw->freqSelector)) {
1008 /* Swing over to television frequency selection */
1009 hdw->freqSelector = 1;
1010 hdw->freqDirty = !0;
1012 if (hdw->freqValTelevision != val) {
1013 hdw->freqValTelevision = val;
1014 hdw->freqSlotTelevision = 0;
1015 hdw->freqDirty = !0;
1020 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1022 return hdw->unit_number;
1026 /* Attempt to locate one of the given set of files. Messages are logged
1027 appropriate to what has been found. The return value will be 0 or
1028 greater on success (it will be the index of the file name found) and
1029 fw_entry will be filled in. Otherwise a negative error is returned on
1030 failure. If the return value is -ENOENT then no viable firmware file
1031 could be located. */
1032 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1033 const struct firmware **fw_entry,
1034 const char *fwtypename,
1035 unsigned int fwcount,
1036 const char *fwnames[])
1040 for (idx = 0; idx < fwcount; idx++) {
1041 ret = request_firmware(fw_entry,
1043 &hdw->usb_dev->dev);
1045 trace_firmware("Located %s firmware: %s;"
1051 if (ret == -ENOENT) continue;
1052 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1053 "request_firmware fatal error with code=%d",ret);
1056 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1058 " Device %s firmware"
1059 " seems to be missing.",
1061 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1062 "Did you install the pvrusb2 firmware files"
1063 " in their proper location?");
1065 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1066 "request_firmware unable to locate %s file %s",
1067 fwtypename,fwnames[0]);
1069 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1070 "request_firmware unable to locate"
1071 " one of the following %s files:",
1073 for (idx = 0; idx < fwcount; idx++) {
1074 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1075 "request_firmware: Failed to find %s",
1084 * pvr2_upload_firmware1().
1086 * Send the 8051 firmware to the device. After the upload, arrange for
1087 * device to re-enumerate.
1089 * NOTE : the pointer to the firmware data given by request_firmware()
1090 * is not suitable for an usb transaction.
1093 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1095 const struct firmware *fw_entry = NULL;
1101 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1102 hdw->fw1_state = FW1_STATE_OK;
1103 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1104 "Connected device type defines"
1105 " no firmware to upload; ignoring firmware");
1109 hdw->fw1_state = FW1_STATE_FAILED; // default result
1111 trace_firmware("pvr2_upload_firmware1");
1113 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1114 hdw->hdw_desc->fx2_firmware.cnt,
1115 hdw->hdw_desc->fx2_firmware.lst);
1117 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1121 usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1122 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1124 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1126 if (fw_entry->size != 0x2000){
1127 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1128 release_firmware(fw_entry);
1132 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1133 if (fw_ptr == NULL){
1134 release_firmware(fw_entry);
1138 /* We have to hold the CPU during firmware upload. */
1139 pvr2_hdw_cpureset_assert(hdw,1);
1141 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1145 for(address = 0; address < fw_entry->size; address += 0x800) {
1146 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1147 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1148 0, fw_ptr, 0x800, HZ);
1151 trace_firmware("Upload done, releasing device's CPU");
1153 /* Now release the CPU. It will disconnect and reconnect later. */
1154 pvr2_hdw_cpureset_assert(hdw,0);
1157 release_firmware(fw_entry);
1159 trace_firmware("Upload done (%d bytes sent)",ret);
1161 /* We should have written 8192 bytes */
1163 hdw->fw1_state = FW1_STATE_RELOAD;
1172 * pvr2_upload_firmware2()
1174 * This uploads encoder firmware on endpoint 2.
1178 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1180 const struct firmware *fw_entry = NULL;
1182 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1186 static const char *fw_files[] = {
1187 CX2341X_FIRM_ENC_FILENAME,
1190 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1194 trace_firmware("pvr2_upload_firmware2");
1196 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1197 ARRAY_SIZE(fw_files), fw_files);
1198 if (ret < 0) return ret;
1201 /* Since we're about to completely reinitialize the encoder,
1202 invalidate our cached copy of its configuration state. Next
1203 time we configure the encoder, then we'll fully configure it. */
1204 hdw->enc_cur_valid = 0;
1206 /* First prepare firmware loading */
1207 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1208 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1209 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1210 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1211 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1212 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1213 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1214 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1215 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1216 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1217 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1218 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1219 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1220 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1221 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1222 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1223 LOCK_TAKE(hdw->ctl_lock); do {
1224 hdw->cmd_buffer[0] = FX2CMD_FWPOST1;
1225 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
1226 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1227 hdw->cmd_buffer[1] = 0;
1228 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0);
1229 } while (0); LOCK_GIVE(hdw->ctl_lock);
1232 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1233 "firmware2 upload prep failed, ret=%d",ret);
1234 release_firmware(fw_entry);
1238 /* Now send firmware */
1240 fw_len = fw_entry->size;
1242 if (fw_len % sizeof(u32)) {
1243 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1244 "size of %s firmware"
1245 " must be a multiple of %zu bytes",
1246 fw_files[fwidx],sizeof(u32));
1247 release_firmware(fw_entry);
1251 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1252 if (fw_ptr == NULL){
1253 release_firmware(fw_entry);
1254 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1255 "failed to allocate memory for firmware2 upload");
1259 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1262 for (fw_done = 0; fw_done < fw_len;) {
1263 bcnt = fw_len - fw_done;
1264 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1265 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1266 /* Usbsnoop log shows that we must swap bytes... */
1267 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1268 ((u32 *)fw_ptr)[icnt] =
1269 ___swab32(((u32 *)fw_ptr)[icnt]);
1271 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1272 &actual_length, HZ);
1273 ret |= (actual_length != bcnt);
1278 trace_firmware("upload of %s : %i / %i ",
1279 fw_files[fwidx],fw_done,fw_len);
1282 release_firmware(fw_entry);
1285 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1286 "firmware2 upload transfer failure");
1292 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1293 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1294 LOCK_TAKE(hdw->ctl_lock); do {
1295 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1296 hdw->cmd_buffer[1] = 0;
1297 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0);
1298 } while (0); LOCK_GIVE(hdw->ctl_lock);
1301 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1302 "firmware2 upload post-proc failure");
1308 static const char *pvr2_get_state_name(unsigned int st)
1310 if (st < ARRAY_SIZE(pvr2_state_names)) {
1311 return pvr2_state_names[st];
1316 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1318 if (!hdw->decoder_ctrl) {
1319 if (!hdw->flag_decoder_missed) {
1320 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1321 "WARNING: No decoder present");
1322 hdw->flag_decoder_missed = !0;
1323 trace_stbit("flag_decoder_missed",
1324 hdw->flag_decoder_missed);
1328 hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt,enablefl);
1333 void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
1335 if (hdw->decoder_ctrl == ptr) return;
1336 hdw->decoder_ctrl = ptr;
1337 if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1338 hdw->flag_decoder_missed = 0;
1339 trace_stbit("flag_decoder_missed",
1340 hdw->flag_decoder_missed);
1341 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1342 "Decoder has appeared");
1343 pvr2_hdw_state_sched(hdw);
1348 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1350 return hdw->master_state;
1354 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1356 if (!hdw->flag_tripped) return 0;
1357 hdw->flag_tripped = 0;
1358 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1359 "Clearing driver error statuss");
1364 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1367 LOCK_TAKE(hdw->big_lock); do {
1368 fl = pvr2_hdw_untrip_unlocked(hdw);
1369 } while (0); LOCK_GIVE(hdw->big_lock);
1370 if (fl) pvr2_hdw_state_sched(hdw);
1375 const char *pvr2_hdw_get_state_name(unsigned int id)
1377 if (id >= ARRAY_SIZE(pvr2_state_names)) return NULL;
1378 return pvr2_state_names[id];
1382 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1384 return hdw->state_pipeline_req != 0;
1388 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1391 LOCK_TAKE(hdw->big_lock); do {
1392 pvr2_hdw_untrip_unlocked(hdw);
1393 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1394 hdw->state_pipeline_req = enable_flag != 0;
1395 pvr2_trace(PVR2_TRACE_START_STOP,
1396 "/*--TRACE_STREAM--*/ %s",
1397 enable_flag ? "enable" : "disable");
1399 pvr2_hdw_state_sched(hdw);
1400 } while (0); LOCK_GIVE(hdw->big_lock);
1401 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1403 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1404 if (st != PVR2_STATE_READY) return -EIO;
1405 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1412 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1415 LOCK_TAKE(hdw->big_lock);
1416 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1417 hdw->desired_stream_type = config;
1418 hdw->state_pipeline_config = 0;
1419 trace_stbit("state_pipeline_config",
1420 hdw->state_pipeline_config);
1421 pvr2_hdw_state_sched(hdw);
1423 LOCK_GIVE(hdw->big_lock);
1425 return pvr2_hdw_wait(hdw,0);
1429 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1431 int unit_number = hdw->unit_number;
1433 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1434 tp = tuner[unit_number];
1436 if (tp < 0) return -EINVAL;
1437 hdw->tuner_type = tp;
1438 hdw->tuner_updated = !0;
1443 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1445 int unit_number = hdw->unit_number;
1447 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1448 tp = video_std[unit_number];
1455 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1457 int unit_number = hdw->unit_number;
1459 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1460 tp = tolerance[unit_number];
1466 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1468 /* Try a harmless request to fetch the eeprom's address over
1469 endpoint 1. See what happens. Only the full FX2 image can
1470 respond to this. If this probe fails then likely the FX2
1471 firmware needs be loaded. */
1473 LOCK_TAKE(hdw->ctl_lock); do {
1474 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1475 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1478 if (result < 0) break;
1479 } while(0); LOCK_GIVE(hdw->ctl_lock);
1481 pvr2_trace(PVR2_TRACE_INIT,
1482 "Probe of device endpoint 1 result status %d",
1485 pvr2_trace(PVR2_TRACE_INIT,
1486 "Probe of device endpoint 1 succeeded");
1491 struct pvr2_std_hack {
1492 v4l2_std_id pat; /* Pattern to match */
1493 v4l2_std_id msk; /* Which bits we care about */
1494 v4l2_std_id std; /* What additional standards or default to set */
1497 /* This data structure labels specific combinations of standards from
1498 tveeprom that we'll try to recognize. If we recognize one, then assume
1499 a specified default standard to use. This is here because tveeprom only
1500 tells us about available standards not the intended default standard (if
1501 any) for the device in question. We guess the default based on what has
1502 been reported as available. Note that this is only for guessing a
1503 default - which can always be overridden explicitly - and if the user
1504 has otherwise named a default then that default will always be used in
1505 place of this table. */
1506 const static struct pvr2_std_hack std_eeprom_maps[] = {
1508 .pat = V4L2_STD_B|V4L2_STD_GH,
1509 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1513 .std = V4L2_STD_NTSC_M,
1516 .pat = V4L2_STD_PAL_I,
1517 .std = V4L2_STD_PAL_I,
1520 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1521 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1525 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1529 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1533 v4l2_std_id std1,std2,std3;
1535 std1 = get_default_standard(hdw);
1536 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1538 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1539 pvr2_trace(PVR2_TRACE_STD,
1540 "Supported video standard(s) reported available"
1541 " in hardware: %.*s",
1544 hdw->std_mask_avail = hdw->std_mask_eeprom;
1546 std2 = (std1|std3) & ~hdw->std_mask_avail;
1548 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1549 pvr2_trace(PVR2_TRACE_STD,
1550 "Expanding supported video standards"
1551 " to include: %.*s",
1553 hdw->std_mask_avail |= std2;
1556 pvr2_hdw_internal_set_std_avail(hdw);
1559 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1560 pvr2_trace(PVR2_TRACE_STD,
1561 "Initial video standard forced to %.*s",
1563 hdw->std_mask_cur = std1;
1564 hdw->std_dirty = !0;
1565 pvr2_hdw_internal_find_stdenum(hdw);
1569 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1570 pvr2_trace(PVR2_TRACE_STD,
1571 "Initial video standard"
1572 " (determined by device type): %.*s",bcnt,buf);
1573 hdw->std_mask_cur = std3;
1574 hdw->std_dirty = !0;
1575 pvr2_hdw_internal_find_stdenum(hdw);
1581 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1582 if (std_eeprom_maps[idx].msk ?
1583 ((std_eeprom_maps[idx].pat ^
1584 hdw->std_mask_eeprom) &
1585 std_eeprom_maps[idx].msk) :
1586 (std_eeprom_maps[idx].pat !=
1587 hdw->std_mask_eeprom)) continue;
1588 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1589 std_eeprom_maps[idx].std);
1590 pvr2_trace(PVR2_TRACE_STD,
1591 "Initial video standard guessed as %.*s",
1593 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1594 hdw->std_dirty = !0;
1595 pvr2_hdw_internal_find_stdenum(hdw);
1600 if (hdw->std_enum_cnt > 1) {
1601 // Autoselect the first listed standard
1602 hdw->std_enum_cur = 1;
1603 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1604 hdw->std_dirty = !0;
1605 pvr2_trace(PVR2_TRACE_STD,
1606 "Initial video standard auto-selected to %s",
1607 hdw->std_defs[hdw->std_enum_cur-1].name);
1611 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1612 "Unable to select a viable initial video standard");
1616 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1620 struct pvr2_ctrl *cptr;
1622 if (hdw->hdw_desc->fx2_firmware.cnt) {
1625 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1628 pvr2_trace(PVR2_TRACE_INIT,
1629 "USB endpoint config looks strange"
1630 "; possibly firmware needs to be"
1635 reloadFl = !pvr2_hdw_check_firmware(hdw);
1637 pvr2_trace(PVR2_TRACE_INIT,
1638 "Check for FX2 firmware failed"
1639 "; possibly firmware needs to be"
1644 if (pvr2_upload_firmware1(hdw) != 0) {
1645 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1646 "Failure uploading firmware1");
1651 hdw->fw1_state = FW1_STATE_OK;
1654 pvr2_hdw_device_reset(hdw);
1656 if (!pvr2_hdw_dev_ok(hdw)) return;
1658 for (idx = 0; idx < hdw->hdw_desc->client_modules.cnt; idx++) {
1659 request_module(hdw->hdw_desc->client_modules.lst[idx]);
1662 if (!hdw->hdw_desc->flag_no_powerup) {
1663 pvr2_hdw_cmd_powerup(hdw);
1664 if (!pvr2_hdw_dev_ok(hdw)) return;
1667 // This step MUST happen after the earlier powerup step.
1668 pvr2_i2c_core_init(hdw);
1669 if (!pvr2_hdw_dev_ok(hdw)) return;
1671 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1672 cptr = hdw->controls + idx;
1673 if (cptr->info->skip_init) continue;
1674 if (!cptr->info->set_value) continue;
1675 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1678 /* Set up special default values for the television and radio
1679 frequencies here. It's not really important what these defaults
1680 are, but I set them to something usable in the Chicago area just
1681 to make driver testing a little easier. */
1683 /* US Broadcast channel 7 (175.25 MHz) */
1684 hdw->freqValTelevision = 175250000L;
1685 /* 104.3 MHz, a usable FM station for my area */
1686 hdw->freqValRadio = 104300000L;
1688 // Do not use pvr2_reset_ctl_endpoints() here. It is not
1689 // thread-safe against the normal pvr2_send_request() mechanism.
1690 // (We should make it thread safe).
1692 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
1693 ret = pvr2_hdw_get_eeprom_addr(hdw);
1694 if (!pvr2_hdw_dev_ok(hdw)) return;
1696 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1697 "Unable to determine location of eeprom,"
1700 hdw->eeprom_addr = ret;
1701 pvr2_eeprom_analyze(hdw);
1702 if (!pvr2_hdw_dev_ok(hdw)) return;
1705 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
1706 hdw->tuner_updated = !0;
1707 hdw->std_mask_eeprom = V4L2_STD_ALL;
1710 pvr2_hdw_setup_std(hdw);
1712 if (!get_default_tuner_type(hdw)) {
1713 pvr2_trace(PVR2_TRACE_INIT,
1714 "pvr2_hdw_setup: Tuner type overridden to %d",
1718 pvr2_i2c_core_check_stale(hdw);
1719 hdw->tuner_updated = 0;
1721 if (!pvr2_hdw_dev_ok(hdw)) return;
1723 pvr2_hdw_commit_setup(hdw);
1725 hdw->vid_stream = pvr2_stream_create();
1726 if (!pvr2_hdw_dev_ok(hdw)) return;
1727 pvr2_trace(PVR2_TRACE_INIT,
1728 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1729 if (hdw->vid_stream) {
1730 idx = get_default_error_tolerance(hdw);
1732 pvr2_trace(PVR2_TRACE_INIT,
1733 "pvr2_hdw_setup: video stream %p"
1734 " setting tolerance %u",
1735 hdw->vid_stream,idx);
1737 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1738 PVR2_VID_ENDPOINT,idx);
1741 if (!pvr2_hdw_dev_ok(hdw)) return;
1743 hdw->flag_init_ok = !0;
1745 pvr2_hdw_state_sched(hdw);
1749 /* Set up the structure and attempt to put the device into a usable state.
1750 This can be a time-consuming operation, which is why it is not done
1751 internally as part of the create() step. */
1752 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
1754 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1756 pvr2_hdw_setup_low(hdw);
1757 pvr2_trace(PVR2_TRACE_INIT,
1758 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1759 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
1760 if (pvr2_hdw_dev_ok(hdw)) {
1761 if (hdw->flag_init_ok) {
1764 "Device initialization"
1765 " completed successfully.");
1768 if (hdw->fw1_state == FW1_STATE_RELOAD) {
1771 "Device microcontroller firmware"
1772 " (re)loaded; it should now reset"
1777 PVR2_TRACE_ERROR_LEGS,
1778 "Device initialization was not successful.");
1779 if (hdw->fw1_state == FW1_STATE_MISSING) {
1781 PVR2_TRACE_ERROR_LEGS,
1782 "Giving up since device"
1783 " microcontroller firmware"
1784 " appears to be missing.");
1790 PVR2_TRACE_ERROR_LEGS,
1791 "Attempting pvrusb2 recovery by reloading"
1792 " primary firmware.");
1794 PVR2_TRACE_ERROR_LEGS,
1795 "If this works, device should disconnect"
1796 " and reconnect in a sane state.");
1797 hdw->fw1_state = FW1_STATE_UNKNOWN;
1798 pvr2_upload_firmware1(hdw);
1801 PVR2_TRACE_ERROR_LEGS,
1802 "***WARNING*** pvrusb2 device hardware"
1803 " appears to be jammed"
1804 " and I can't clear it.");
1806 PVR2_TRACE_ERROR_LEGS,
1807 "You might need to power cycle"
1808 " the pvrusb2 device"
1809 " in order to recover.");
1812 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
1816 /* Perform second stage initialization. Set callback pointer first so that
1817 we can avoid a possible initialization race (if the kernel thread runs
1818 before the callback has been set). */
1819 void pvr2_hdw_initialize(struct pvr2_hdw *hdw,
1820 void (*callback_func)(void *),
1821 void *callback_data)
1823 LOCK_TAKE(hdw->big_lock); do {
1824 hdw->state_data = callback_data;
1825 hdw->state_func = callback_func;
1826 } while (0); LOCK_GIVE(hdw->big_lock);
1827 queue_work(hdw->workqueue,&hdw->workinit);
1831 /* Create, set up, and return a structure for interacting with the
1832 underlying hardware. */
1833 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1834 const struct usb_device_id *devid)
1836 unsigned int idx,cnt1,cnt2,m;
1837 struct pvr2_hdw *hdw;
1839 struct pvr2_ctrl *cptr;
1840 const struct pvr2_device_desc *hdw_desc;
1842 struct v4l2_queryctrl qctrl;
1843 struct pvr2_ctl_info *ciptr;
1845 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
1847 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
1848 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
1849 hdw,hdw_desc->description);
1850 if (!hdw) goto fail;
1852 init_timer(&hdw->quiescent_timer);
1853 hdw->quiescent_timer.data = (unsigned long)hdw;
1854 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
1856 init_timer(&hdw->encoder_wait_timer);
1857 hdw->encoder_wait_timer.data = (unsigned long)hdw;
1858 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
1860 hdw->master_state = PVR2_STATE_DEAD;
1862 init_waitqueue_head(&hdw->state_wait_data);
1864 hdw->tuner_signal_stale = !0;
1865 cx2341x_fill_defaults(&hdw->enc_ctl_state);
1867 /* Calculate which inputs are OK */
1869 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
1870 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
1871 m |= 1 << PVR2_CVAL_INPUT_DTV;
1873 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
1874 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
1875 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
1876 hdw->input_avail_mask = m;
1878 /* If not a hybrid device, pathway_state never changes. So
1879 initialize it here to what it should forever be. */
1880 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
1881 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
1882 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
1883 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
1886 hdw->control_cnt = CTRLDEF_COUNT;
1887 hdw->control_cnt += MPEGDEF_COUNT;
1888 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
1890 if (!hdw->controls) goto fail;
1891 hdw->hdw_desc = hdw_desc;
1892 for (idx = 0; idx < hdw->control_cnt; idx++) {
1893 cptr = hdw->controls + idx;
1896 for (idx = 0; idx < 32; idx++) {
1897 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1899 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1900 cptr = hdw->controls + idx;
1901 cptr->info = control_defs+idx;
1904 /* Ensure that default input choice is a valid one. */
1905 m = hdw->input_avail_mask;
1906 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
1907 if (!((1 << idx) & m)) continue;
1908 hdw->input_val = idx;
1912 /* Define and configure additional controls from cx2341x module. */
1913 hdw->mpeg_ctrl_info = kzalloc(
1914 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
1915 if (!hdw->mpeg_ctrl_info) goto fail;
1916 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
1917 cptr = hdw->controls + idx + CTRLDEF_COUNT;
1918 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
1919 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
1920 ciptr->name = mpeg_ids[idx].strid;
1921 ciptr->v4l_id = mpeg_ids[idx].id;
1922 ciptr->skip_init = !0;
1923 ciptr->get_value = ctrl_cx2341x_get;
1924 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
1925 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
1926 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
1927 qctrl.id = ciptr->v4l_id;
1928 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
1929 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
1930 ciptr->set_value = ctrl_cx2341x_set;
1932 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
1933 PVR2_CTLD_INFO_DESC_SIZE);
1934 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
1935 ciptr->default_value = qctrl.default_value;
1936 switch (qctrl.type) {
1938 case V4L2_CTRL_TYPE_INTEGER:
1939 ciptr->type = pvr2_ctl_int;
1940 ciptr->def.type_int.min_value = qctrl.minimum;
1941 ciptr->def.type_int.max_value = qctrl.maximum;
1943 case V4L2_CTRL_TYPE_BOOLEAN:
1944 ciptr->type = pvr2_ctl_bool;
1946 case V4L2_CTRL_TYPE_MENU:
1947 ciptr->type = pvr2_ctl_enum;
1948 ciptr->def.type_enum.value_names =
1949 cx2341x_ctrl_get_menu(ciptr->v4l_id);
1951 ciptr->def.type_enum.value_names[cnt1] != NULL;
1953 ciptr->def.type_enum.count = cnt1;
1959 // Initialize video standard enum dynamic control
1960 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
1962 memcpy(&hdw->std_info_enum,cptr->info,
1963 sizeof(hdw->std_info_enum));
1964 cptr->info = &hdw->std_info_enum;
1967 // Initialize control data regarding video standard masks
1968 valid_std_mask = pvr2_std_get_usable();
1969 for (idx = 0; idx < 32; idx++) {
1970 if (!(valid_std_mask & (1 << idx))) continue;
1971 cnt1 = pvr2_std_id_to_str(
1972 hdw->std_mask_names[idx],
1973 sizeof(hdw->std_mask_names[idx])-1,
1975 hdw->std_mask_names[idx][cnt1] = 0;
1977 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
1979 memcpy(&hdw->std_info_avail,cptr->info,
1980 sizeof(hdw->std_info_avail));
1981 cptr->info = &hdw->std_info_avail;
1982 hdw->std_info_avail.def.type_bitmask.bit_names =
1984 hdw->std_info_avail.def.type_bitmask.valid_bits =
1987 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
1989 memcpy(&hdw->std_info_cur,cptr->info,
1990 sizeof(hdw->std_info_cur));
1991 cptr->info = &hdw->std_info_cur;
1992 hdw->std_info_cur.def.type_bitmask.bit_names =
1994 hdw->std_info_avail.def.type_bitmask.valid_bits =
1998 hdw->eeprom_addr = -1;
1999 hdw->unit_number = -1;
2000 hdw->v4l_minor_number_video = -1;
2001 hdw->v4l_minor_number_vbi = -1;
2002 hdw->v4l_minor_number_radio = -1;
2003 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2004 if (!hdw->ctl_write_buffer) goto fail;
2005 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2006 if (!hdw->ctl_read_buffer) goto fail;
2007 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2008 if (!hdw->ctl_write_urb) goto fail;
2009 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2010 if (!hdw->ctl_read_urb) goto fail;
2012 mutex_lock(&pvr2_unit_mtx); do {
2013 for (idx = 0; idx < PVR_NUM; idx++) {
2014 if (unit_pointers[idx]) continue;
2015 hdw->unit_number = idx;
2016 unit_pointers[idx] = hdw;
2019 } while (0); mutex_unlock(&pvr2_unit_mtx);
2022 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2024 if (hdw->unit_number >= 0) {
2025 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2026 ('a' + hdw->unit_number));
2029 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2030 hdw->name[cnt1] = 0;
2032 hdw->workqueue = create_singlethread_workqueue(hdw->name);
2033 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2034 INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
2035 INIT_WORK(&hdw->workinit,pvr2_hdw_worker_init);
2037 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2038 hdw->unit_number,hdw->name);
2040 hdw->tuner_type = -1;
2043 hdw->usb_intf = intf;
2044 hdw->usb_dev = interface_to_usbdev(intf);
2046 scnprintf(hdw->bus_info,sizeof(hdw->bus_info),
2047 "usb %s address %d",
2048 hdw->usb_dev->dev.bus_id,
2049 hdw->usb_dev->devnum);
2051 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2052 usb_set_interface(hdw->usb_dev,ifnum,0);
2054 mutex_init(&hdw->ctl_lock_mutex);
2055 mutex_init(&hdw->big_lock_mutex);
2060 del_timer_sync(&hdw->quiescent_timer);
2061 del_timer_sync(&hdw->encoder_wait_timer);
2062 if (hdw->workqueue) {
2063 flush_workqueue(hdw->workqueue);
2064 destroy_workqueue(hdw->workqueue);
2065 hdw->workqueue = NULL;
2067 usb_free_urb(hdw->ctl_read_urb);
2068 usb_free_urb(hdw->ctl_write_urb);
2069 kfree(hdw->ctl_read_buffer);
2070 kfree(hdw->ctl_write_buffer);
2071 kfree(hdw->controls);
2072 kfree(hdw->mpeg_ctrl_info);
2073 kfree(hdw->std_defs);
2074 kfree(hdw->std_enum_names);
2081 /* Remove _all_ associations between this driver and the underlying USB
2083 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2085 if (hdw->flag_disconnected) return;
2086 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2087 if (hdw->ctl_read_urb) {
2088 usb_kill_urb(hdw->ctl_read_urb);
2089 usb_free_urb(hdw->ctl_read_urb);
2090 hdw->ctl_read_urb = NULL;
2092 if (hdw->ctl_write_urb) {
2093 usb_kill_urb(hdw->ctl_write_urb);
2094 usb_free_urb(hdw->ctl_write_urb);
2095 hdw->ctl_write_urb = NULL;
2097 if (hdw->ctl_read_buffer) {
2098 kfree(hdw->ctl_read_buffer);
2099 hdw->ctl_read_buffer = NULL;
2101 if (hdw->ctl_write_buffer) {
2102 kfree(hdw->ctl_write_buffer);
2103 hdw->ctl_write_buffer = NULL;
2105 hdw->flag_disconnected = !0;
2106 hdw->usb_dev = NULL;
2107 hdw->usb_intf = NULL;
2108 pvr2_hdw_render_useless(hdw);
2112 /* Destroy hardware interaction structure */
2113 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2116 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2117 del_timer_sync(&hdw->quiescent_timer);
2118 del_timer_sync(&hdw->encoder_wait_timer);
2119 if (hdw->workqueue) {
2120 flush_workqueue(hdw->workqueue);
2121 destroy_workqueue(hdw->workqueue);
2122 hdw->workqueue = NULL;
2124 if (hdw->fw_buffer) {
2125 kfree(hdw->fw_buffer);
2126 hdw->fw_buffer = NULL;
2128 if (hdw->vid_stream) {
2129 pvr2_stream_destroy(hdw->vid_stream);
2130 hdw->vid_stream = NULL;
2132 if (hdw->decoder_ctrl) {
2133 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2135 pvr2_i2c_core_done(hdw);
2136 pvr2_hdw_remove_usb_stuff(hdw);
2137 mutex_lock(&pvr2_unit_mtx); do {
2138 if ((hdw->unit_number >= 0) &&
2139 (hdw->unit_number < PVR_NUM) &&
2140 (unit_pointers[hdw->unit_number] == hdw)) {
2141 unit_pointers[hdw->unit_number] = NULL;
2143 } while (0); mutex_unlock(&pvr2_unit_mtx);
2144 kfree(hdw->controls);
2145 kfree(hdw->mpeg_ctrl_info);
2146 kfree(hdw->std_defs);
2147 kfree(hdw->std_enum_names);
2152 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2154 return (hdw && hdw->flag_ok);
2158 /* Called when hardware has been unplugged */
2159 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2161 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2162 LOCK_TAKE(hdw->big_lock);
2163 LOCK_TAKE(hdw->ctl_lock);
2164 pvr2_hdw_remove_usb_stuff(hdw);
2165 LOCK_GIVE(hdw->ctl_lock);
2166 LOCK_GIVE(hdw->big_lock);
2170 // Attempt to autoselect an appropriate value for std_enum_cur given
2171 // whatever is currently in std_mask_cur
2172 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2175 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2176 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2177 hdw->std_enum_cur = idx;
2181 hdw->std_enum_cur = 0;
2185 // Calculate correct set of enumerated standards based on currently known
2186 // set of available standards bits.
2187 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2189 struct v4l2_standard *newstd;
2190 unsigned int std_cnt;
2193 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2195 if (hdw->std_defs) {
2196 kfree(hdw->std_defs);
2197 hdw->std_defs = NULL;
2199 hdw->std_enum_cnt = 0;
2200 if (hdw->std_enum_names) {
2201 kfree(hdw->std_enum_names);
2202 hdw->std_enum_names = NULL;
2207 PVR2_TRACE_ERROR_LEGS,
2208 "WARNING: Failed to identify any viable standards");
2210 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2211 hdw->std_enum_names[0] = "none";
2212 for (idx = 0; idx < std_cnt; idx++) {
2213 hdw->std_enum_names[idx+1] =
2216 // Set up the dynamic control for this standard
2217 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2218 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2219 hdw->std_defs = newstd;
2220 hdw->std_enum_cnt = std_cnt+1;
2221 hdw->std_enum_cur = 0;
2222 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2226 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2227 struct v4l2_standard *std,
2231 if (!idx) return ret;
2232 LOCK_TAKE(hdw->big_lock); do {
2233 if (idx >= hdw->std_enum_cnt) break;
2235 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2237 } while (0); LOCK_GIVE(hdw->big_lock);
2242 /* Get the number of defined controls */
2243 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2245 return hdw->control_cnt;
2249 /* Retrieve a control handle given its index (0..count-1) */
2250 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2253 if (idx >= hdw->control_cnt) return NULL;
2254 return hdw->controls + idx;
2258 /* Retrieve a control handle given its index (0..count-1) */
2259 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2260 unsigned int ctl_id)
2262 struct pvr2_ctrl *cptr;
2266 /* This could be made a lot more efficient, but for now... */
2267 for (idx = 0; idx < hdw->control_cnt; idx++) {
2268 cptr = hdw->controls + idx;
2269 i = cptr->info->internal_id;
2270 if (i && (i == ctl_id)) return cptr;
2276 /* Given a V4L ID, retrieve the control structure associated with it. */
2277 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2279 struct pvr2_ctrl *cptr;
2283 /* This could be made a lot more efficient, but for now... */
2284 for (idx = 0; idx < hdw->control_cnt; idx++) {
2285 cptr = hdw->controls + idx;
2286 i = cptr->info->v4l_id;
2287 if (i && (i == ctl_id)) return cptr;
2293 /* Given a V4L ID for its immediate predecessor, retrieve the control
2294 structure associated with it. */
2295 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2296 unsigned int ctl_id)
2298 struct pvr2_ctrl *cptr,*cp2;
2302 /* This could be made a lot more efficient, but for now... */
2304 for (idx = 0; idx < hdw->control_cnt; idx++) {
2305 cptr = hdw->controls + idx;
2306 i = cptr->info->v4l_id;
2308 if (i <= ctl_id) continue;
2309 if (cp2 && (cp2->info->v4l_id < i)) continue;
2317 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2320 case pvr2_ctl_int: return "integer";
2321 case pvr2_ctl_enum: return "enum";
2322 case pvr2_ctl_bool: return "boolean";
2323 case pvr2_ctl_bitmask: return "bitmask";
2329 /* Figure out if we need to commit control changes. If so, mark internal
2330 state flags to indicate this fact and return true. Otherwise do nothing
2331 else and return false. */
2332 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
2335 struct pvr2_ctrl *cptr;
2337 int commit_flag = 0;
2339 unsigned int bcnt,ccnt;
2341 for (idx = 0; idx < hdw->control_cnt; idx++) {
2342 cptr = hdw->controls + idx;
2343 if (!cptr->info->is_dirty) continue;
2344 if (!cptr->info->is_dirty(cptr)) continue;
2347 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
2348 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2351 cptr->info->get_value(cptr,&value);
2352 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2354 sizeof(buf)-bcnt,&ccnt);
2356 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2357 get_ctrl_typename(cptr->info->type));
2358 pvr2_trace(PVR2_TRACE_CTL,
2359 "/*--TRACE_COMMIT--*/ %.*s",
2364 /* Nothing has changed */
2368 hdw->state_pipeline_config = 0;
2369 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2370 pvr2_hdw_state_sched(hdw);
2376 /* Perform all operations needed to commit all control changes. This must
2377 be performed in synchronization with the pipeline state and is thus
2378 expected to be called as part of the driver's worker thread. Return
2379 true if commit successful, otherwise return false to indicate that
2380 commit isn't possible at this time. */
2381 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
2384 struct pvr2_ctrl *cptr;
2385 int disruptive_change;
2387 /* When video standard changes, reset the hres and vres values -
2388 but if the user has pending changes there, then let the changes
2390 if (hdw->std_dirty) {
2391 /* Rewrite the vertical resolution to be appropriate to the
2392 video standard that has been selected. */
2394 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2399 if (nvres != hdw->res_ver_val) {
2400 hdw->res_ver_val = nvres;
2401 hdw->res_ver_dirty = !0;
2405 if (hdw->input_dirty &&
2406 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
2407 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
2408 hdw->pathway_state)) {
2409 /* Change of mode being asked for... */
2410 hdw->state_pathway_ok = 0;
2411 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
2413 if (!hdw->state_pathway_ok) {
2414 /* Can't commit anything until pathway is ok. */
2417 /* If any of the below has changed, then we can't do the update
2418 while the pipeline is running. Pipeline must be paused first
2419 and decoder -> encoder connection be made quiescent before we
2423 hdw->enc_unsafe_stale ||
2425 hdw->res_ver_dirty ||
2426 hdw->res_hor_dirty ||
2428 (hdw->active_stream_type != hdw->desired_stream_type));
2429 if (disruptive_change && !hdw->state_pipeline_idle) {
2430 /* Pipeline is not idle; we can't proceed. Arrange to
2431 cause pipeline to stop so that we can try this again
2433 hdw->state_pipeline_pause = !0;
2437 if (hdw->srate_dirty) {
2438 /* Write new sample rate into control structure since
2439 * the master copy is stale. We must track srate
2440 * separate from the mpeg control structure because
2441 * other logic also uses this value. */
2442 struct v4l2_ext_controls cs;
2443 struct v4l2_ext_control c1;
2444 memset(&cs,0,sizeof(cs));
2445 memset(&c1,0,sizeof(c1));
2448 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2449 c1.value = hdw->srate_val;
2450 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
2453 /* Scan i2c core at this point - before we clear all the dirty
2454 bits. Various parts of the i2c core will notice dirty bits as
2455 appropriate and arrange to broadcast or directly send updates to
2456 the client drivers in order to keep everything in sync */
2457 pvr2_i2c_core_check_stale(hdw);
2459 for (idx = 0; idx < hdw->control_cnt; idx++) {
2460 cptr = hdw->controls + idx;
2461 if (!cptr->info->clear_dirty) continue;
2462 cptr->info->clear_dirty(cptr);
2465 if (hdw->active_stream_type != hdw->desired_stream_type) {
2466 /* Handle any side effects of stream config here */
2467 hdw->active_stream_type = hdw->desired_stream_type;
2470 /* Now execute i2c core update */
2471 pvr2_i2c_core_sync(hdw);
2473 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
2474 hdw->state_encoder_run) {
2475 /* If encoder isn't running or it can't be touched, then
2476 this will get worked out later when we start the
2478 if (pvr2_encoder_adjust(hdw) < 0) return !0;
2481 hdw->state_pipeline_config = !0;
2482 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2487 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2490 LOCK_TAKE(hdw->big_lock);
2491 fl = pvr2_hdw_commit_setup(hdw);
2492 LOCK_GIVE(hdw->big_lock);
2494 return pvr2_hdw_wait(hdw,0);
2498 static void pvr2_hdw_worker_i2c(struct work_struct *work)
2500 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
2501 LOCK_TAKE(hdw->big_lock); do {
2502 pvr2_i2c_core_sync(hdw);
2503 } while (0); LOCK_GIVE(hdw->big_lock);
2507 static void pvr2_hdw_worker_poll(struct work_struct *work)
2510 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
2511 LOCK_TAKE(hdw->big_lock); do {
2512 fl = pvr2_hdw_state_eval(hdw);
2513 } while (0); LOCK_GIVE(hdw->big_lock);
2514 if (fl && hdw->state_func) {
2515 hdw->state_func(hdw->state_data);
2520 static void pvr2_hdw_worker_init(struct work_struct *work)
2522 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workinit);
2523 LOCK_TAKE(hdw->big_lock); do {
2524 pvr2_hdw_setup(hdw);
2525 } while (0); LOCK_GIVE(hdw->big_lock);
2529 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
2531 return wait_event_interruptible(
2532 hdw->state_wait_data,
2533 (hdw->state_stale == 0) &&
2534 (!state || (hdw->master_state != state)));
2538 /* Return name for this driver instance */
2539 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2545 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
2547 return hdw->hdw_desc->description;
2551 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
2553 return hdw->hdw_desc->shortname;
2557 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2560 LOCK_TAKE(hdw->ctl_lock); do {
2561 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
2562 result = pvr2_send_request(hdw,
2565 if (result < 0) break;
2566 result = (hdw->cmd_buffer[0] != 0);
2567 } while(0); LOCK_GIVE(hdw->ctl_lock);
2572 /* Execute poll of tuner status */
2573 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
2575 LOCK_TAKE(hdw->big_lock); do {
2576 pvr2_i2c_core_status_poll(hdw);
2577 } while (0); LOCK_GIVE(hdw->big_lock);
2581 /* Return information about the tuner */
2582 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
2584 LOCK_TAKE(hdw->big_lock); do {
2585 if (hdw->tuner_signal_stale) {
2586 pvr2_i2c_core_status_poll(hdw);
2588 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
2589 } while (0); LOCK_GIVE(hdw->big_lock);
2594 /* Get handle to video output stream */
2595 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2597 return hp->vid_stream;
2601 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2603 int nr = pvr2_hdw_get_unit_number(hdw);
2604 LOCK_TAKE(hdw->big_lock); do {
2605 hdw->log_requested = !0;
2606 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
2607 pvr2_i2c_core_check_stale(hdw);
2608 hdw->log_requested = 0;
2609 pvr2_i2c_core_sync(hdw);
2610 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
2611 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
2612 pvr2_hdw_state_log_state(hdw);
2613 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
2614 } while (0); LOCK_GIVE(hdw->big_lock);
2618 /* Grab EEPROM contents, needed for direct method. */
2619 #define EEPROM_SIZE 8192
2620 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
2621 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
2623 struct i2c_msg msg[2];
2632 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
2634 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2635 "Failed to allocate memory"
2636 " required to read eeprom");
2640 trace_eeprom("Value for eeprom addr from controller was 0x%x",
2642 addr = hdw->eeprom_addr;
2643 /* Seems that if the high bit is set, then the *real* eeprom
2644 address is shifted right now bit position (noticed this in
2645 newer PVR USB2 hardware) */
2646 if (addr & 0x80) addr >>= 1;
2648 /* FX2 documentation states that a 16bit-addressed eeprom is
2649 expected if the I2C address is an odd number (yeah, this is
2650 strange but it's what they do) */
2651 mode16 = (addr & 1);
2652 eepromSize = (mode16 ? EEPROM_SIZE : 256);
2653 trace_eeprom("Examining %d byte eeprom at location 0x%x"
2654 " using %d bit addressing",eepromSize,addr,
2659 msg[0].len = mode16 ? 2 : 1;
2662 msg[1].flags = I2C_M_RD;
2664 /* We have to do the actual eeprom data fetch ourselves, because
2665 (1) we're only fetching part of the eeprom, and (2) if we were
2666 getting the whole thing our I2C driver can't grab it in one
2667 pass - which is what tveeprom is otherwise going to attempt */
2668 memset(eeprom,0,EEPROM_SIZE);
2669 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
2671 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
2672 offs = tcnt + (eepromSize - EEPROM_SIZE);
2674 iadd[0] = offs >> 8;
2680 msg[1].buf = eeprom+tcnt;
2681 if ((ret = i2c_transfer(&hdw->i2c_adap,
2682 msg,ARRAY_SIZE(msg))) != 2) {
2683 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2684 "eeprom fetch set offs err=%d",ret);
2693 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
2700 LOCK_TAKE(hdw->big_lock); do {
2701 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
2704 pvr2_trace(PVR2_TRACE_FIRMWARE,
2705 "Cleaning up after CPU firmware fetch");
2706 kfree(hdw->fw_buffer);
2707 hdw->fw_buffer = NULL;
2709 if (hdw->fw_cpu_flag) {
2710 /* Now release the CPU. It will disconnect
2711 and reconnect later. */
2712 pvr2_hdw_cpureset_assert(hdw,0);
2717 hdw->fw_cpu_flag = (prom_flag == 0);
2718 if (hdw->fw_cpu_flag) {
2719 pvr2_trace(PVR2_TRACE_FIRMWARE,
2720 "Preparing to suck out CPU firmware");
2721 hdw->fw_size = 0x2000;
2722 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
2723 if (!hdw->fw_buffer) {
2728 /* We have to hold the CPU during firmware upload. */
2729 pvr2_hdw_cpureset_assert(hdw,1);
2731 /* download the firmware from address 0000-1fff in 2048
2732 (=0x800) bytes chunk. */
2734 pvr2_trace(PVR2_TRACE_FIRMWARE,
2735 "Grabbing CPU firmware");
2736 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2737 for(address = 0; address < hdw->fw_size;
2739 ret = usb_control_msg(hdw->usb_dev,pipe,
2742 hdw->fw_buffer+address,
2747 pvr2_trace(PVR2_TRACE_FIRMWARE,
2748 "Done grabbing CPU firmware");
2750 pvr2_trace(PVR2_TRACE_FIRMWARE,
2751 "Sucking down EEPROM contents");
2752 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
2753 if (!hdw->fw_buffer) {
2754 pvr2_trace(PVR2_TRACE_FIRMWARE,
2755 "EEPROM content suck failed.");
2758 hdw->fw_size = EEPROM_SIZE;
2759 pvr2_trace(PVR2_TRACE_FIRMWARE,
2760 "Done sucking down EEPROM contents");
2763 } while (0); LOCK_GIVE(hdw->big_lock);
2767 /* Return true if we're in a mode for retrieval CPU firmware */
2768 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2770 return hdw->fw_buffer != NULL;
2774 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2775 char *buf,unsigned int cnt)
2778 LOCK_TAKE(hdw->big_lock); do {
2782 if (!hdw->fw_buffer) {
2787 if (offs >= hdw->fw_size) {
2788 pvr2_trace(PVR2_TRACE_FIRMWARE,
2789 "Read firmware data offs=%d EOF",
2795 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2797 memcpy(buf,hdw->fw_buffer+offs,cnt);
2799 pvr2_trace(PVR2_TRACE_FIRMWARE,
2800 "Read firmware data offs=%d cnt=%d",
2803 } while (0); LOCK_GIVE(hdw->big_lock);
2809 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
2810 enum pvr2_v4l_type index)
2813 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
2814 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
2815 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
2821 /* Store a v4l minor device number */
2822 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
2823 enum pvr2_v4l_type index,int v)
2826 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
2827 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
2828 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
2834 static void pvr2_ctl_write_complete(struct urb *urb)
2836 struct pvr2_hdw *hdw = urb->context;
2837 hdw->ctl_write_pend_flag = 0;
2838 if (hdw->ctl_read_pend_flag) return;
2839 complete(&hdw->ctl_done);
2843 static void pvr2_ctl_read_complete(struct urb *urb)
2845 struct pvr2_hdw *hdw = urb->context;
2846 hdw->ctl_read_pend_flag = 0;
2847 if (hdw->ctl_write_pend_flag) return;
2848 complete(&hdw->ctl_done);
2852 static void pvr2_ctl_timeout(unsigned long data)
2854 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2855 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2856 hdw->ctl_timeout_flag = !0;
2857 if (hdw->ctl_write_pend_flag)
2858 usb_unlink_urb(hdw->ctl_write_urb);
2859 if (hdw->ctl_read_pend_flag)
2860 usb_unlink_urb(hdw->ctl_read_urb);
2865 /* Issue a command and get a response from the device. This extended
2866 version includes a probe flag (which if set means that device errors
2867 should not be logged or treated as fatal) and a timeout in jiffies.
2868 This can be used to non-lethally probe the health of endpoint 1. */
2869 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2870 unsigned int timeout,int probe_fl,
2871 void *write_data,unsigned int write_len,
2872 void *read_data,unsigned int read_len)
2876 struct timer_list timer;
2877 if (!hdw->ctl_lock_held) {
2878 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2879 "Attempted to execute control transfer"
2883 if (!hdw->flag_ok && !probe_fl) {
2884 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2885 "Attempted to execute control transfer"
2886 " when device not ok");
2889 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2891 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2892 "Attempted to execute control transfer"
2893 " when USB is disconnected");
2898 /* Ensure that we have sane parameters */
2899 if (!write_data) write_len = 0;
2900 if (!read_data) read_len = 0;
2901 if (write_len > PVR2_CTL_BUFFSIZE) {
2903 PVR2_TRACE_ERROR_LEGS,
2904 "Attempted to execute %d byte"
2905 " control-write transfer (limit=%d)",
2906 write_len,PVR2_CTL_BUFFSIZE);
2909 if (read_len > PVR2_CTL_BUFFSIZE) {
2911 PVR2_TRACE_ERROR_LEGS,
2912 "Attempted to execute %d byte"
2913 " control-read transfer (limit=%d)",
2914 write_len,PVR2_CTL_BUFFSIZE);
2917 if ((!write_len) && (!read_len)) {
2919 PVR2_TRACE_ERROR_LEGS,
2920 "Attempted to execute null control transfer?");
2925 hdw->cmd_debug_state = 1;
2927 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2929 hdw->cmd_debug_code = 0;
2931 hdw->cmd_debug_write_len = write_len;
2932 hdw->cmd_debug_read_len = read_len;
2934 /* Initialize common stuff */
2935 init_completion(&hdw->ctl_done);
2936 hdw->ctl_timeout_flag = 0;
2937 hdw->ctl_write_pend_flag = 0;
2938 hdw->ctl_read_pend_flag = 0;
2940 timer.expires = jiffies + timeout;
2941 timer.data = (unsigned long)hdw;
2942 timer.function = pvr2_ctl_timeout;
2945 hdw->cmd_debug_state = 2;
2946 /* Transfer write data to internal buffer */
2947 for (idx = 0; idx < write_len; idx++) {
2948 hdw->ctl_write_buffer[idx] =
2949 ((unsigned char *)write_data)[idx];
2951 /* Initiate a write request */
2952 usb_fill_bulk_urb(hdw->ctl_write_urb,
2954 usb_sndbulkpipe(hdw->usb_dev,
2955 PVR2_CTL_WRITE_ENDPOINT),
2956 hdw->ctl_write_buffer,
2958 pvr2_ctl_write_complete,
2960 hdw->ctl_write_urb->actual_length = 0;
2961 hdw->ctl_write_pend_flag = !0;
2962 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2964 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2965 "Failed to submit write-control"
2966 " URB status=%d",status);
2967 hdw->ctl_write_pend_flag = 0;
2973 hdw->cmd_debug_state = 3;
2974 memset(hdw->ctl_read_buffer,0x43,read_len);
2975 /* Initiate a read request */
2976 usb_fill_bulk_urb(hdw->ctl_read_urb,
2978 usb_rcvbulkpipe(hdw->usb_dev,
2979 PVR2_CTL_READ_ENDPOINT),
2980 hdw->ctl_read_buffer,
2982 pvr2_ctl_read_complete,
2984 hdw->ctl_read_urb->actual_length = 0;
2985 hdw->ctl_read_pend_flag = !0;
2986 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
2988 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2989 "Failed to submit read-control"
2990 " URB status=%d",status);
2991 hdw->ctl_read_pend_flag = 0;
2999 /* Now wait for all I/O to complete */
3000 hdw->cmd_debug_state = 4;
3001 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3002 wait_for_completion(&hdw->ctl_done);
3004 hdw->cmd_debug_state = 5;
3007 del_timer_sync(&timer);
3009 hdw->cmd_debug_state = 6;
3012 if (hdw->ctl_timeout_flag) {
3013 status = -ETIMEDOUT;
3015 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3016 "Timed out control-write");
3022 /* Validate results of write request */
3023 if ((hdw->ctl_write_urb->status != 0) &&
3024 (hdw->ctl_write_urb->status != -ENOENT) &&
3025 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3026 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3027 /* USB subsystem is reporting some kind of failure
3029 status = hdw->ctl_write_urb->status;
3031 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3032 "control-write URB failure,"
3038 if (hdw->ctl_write_urb->actual_length < write_len) {
3039 /* Failed to write enough data */
3042 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3043 "control-write URB short,"
3044 " expected=%d got=%d",
3046 hdw->ctl_write_urb->actual_length);
3052 /* Validate results of read request */
3053 if ((hdw->ctl_read_urb->status != 0) &&
3054 (hdw->ctl_read_urb->status != -ENOENT) &&
3055 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3056 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3057 /* USB subsystem is reporting some kind of failure
3059 status = hdw->ctl_read_urb->status;
3061 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3062 "control-read URB failure,"
3068 if (hdw->ctl_read_urb->actual_length < read_len) {
3069 /* Failed to read enough data */
3072 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3073 "control-read URB short,"
3074 " expected=%d got=%d",
3076 hdw->ctl_read_urb->actual_length);
3080 /* Transfer retrieved data out from internal buffer */
3081 for (idx = 0; idx < read_len; idx++) {
3082 ((unsigned char *)read_data)[idx] =
3083 hdw->ctl_read_buffer[idx];
3089 hdw->cmd_debug_state = 0;
3090 if ((status < 0) && (!probe_fl)) {
3091 pvr2_hdw_render_useless(hdw);
3097 int pvr2_send_request(struct pvr2_hdw *hdw,
3098 void *write_data,unsigned int write_len,
3099 void *read_data,unsigned int read_len)
3101 return pvr2_send_request_ex(hdw,HZ*4,0,
3102 write_data,write_len,
3103 read_data,read_len);
3106 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3110 LOCK_TAKE(hdw->ctl_lock);
3112 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
3113 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3114 hdw->cmd_buffer[5] = 0;
3115 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3116 hdw->cmd_buffer[7] = reg & 0xff;
3119 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3121 LOCK_GIVE(hdw->ctl_lock);
3127 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3131 LOCK_TAKE(hdw->ctl_lock);
3133 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
3134 hdw->cmd_buffer[1] = 0;
3135 hdw->cmd_buffer[2] = 0;
3136 hdw->cmd_buffer[3] = 0;
3137 hdw->cmd_buffer[4] = 0;
3138 hdw->cmd_buffer[5] = 0;
3139 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3140 hdw->cmd_buffer[7] = reg & 0xff;
3142 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3143 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3145 LOCK_GIVE(hdw->ctl_lock);
3151 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3153 if (!hdw->flag_ok) return;
3154 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3155 "Device being rendered inoperable");
3156 if (hdw->vid_stream) {
3157 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3160 trace_stbit("flag_ok",hdw->flag_ok);
3161 pvr2_hdw_state_sched(hdw);
3165 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3168 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3169 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3171 ret = usb_reset_device(hdw->usb_dev);
3172 usb_unlock_device(hdw->usb_dev);
3174 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3175 "Failed to lock USB device ret=%d",ret);
3177 if (init_pause_msec) {
3178 pvr2_trace(PVR2_TRACE_INFO,
3179 "Waiting %u msec for hardware to settle",
3181 msleep(init_pause_msec);
3187 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3193 if (!hdw->usb_dev) return;
3195 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3197 da[0] = val ? 0x01 : 0x00;
3199 /* Write the CPUCS register on the 8051. The lsb of the register
3200 is the reset bit; a 1 asserts reset while a 0 clears it. */
3201 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3202 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3204 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3205 "cpureset_assert(%d) error=%d",val,ret);
3206 pvr2_hdw_render_useless(hdw);
3211 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3214 LOCK_TAKE(hdw->ctl_lock); do {
3215 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
3216 hdw->cmd_buffer[0] = FX2CMD_DEEP_RESET;
3217 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
3218 } while (0); LOCK_GIVE(hdw->ctl_lock);
3223 static int pvr2_hdw_cmd_power_ctrl(struct pvr2_hdw *hdw, int onoff)
3226 LOCK_TAKE(hdw->ctl_lock); do {
3228 pvr2_trace(PVR2_TRACE_INIT, "Requesting powerup");
3229 hdw->cmd_buffer[0] = FX2CMD_POWER_ON;
3231 pvr2_trace(PVR2_TRACE_INIT, "Requesting powerdown");
3232 hdw->cmd_buffer[0] = FX2CMD_POWER_OFF;
3234 status = pvr2_send_request(hdw, hdw->cmd_buffer, 1, NULL, 0);
3235 } while (0); LOCK_GIVE(hdw->ctl_lock);
3239 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3241 return pvr2_hdw_cmd_power_ctrl(hdw, 1);
3244 int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
3246 return pvr2_hdw_cmd_power_ctrl(hdw, 0);
3250 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3252 if (!hdw->decoder_ctrl) {
3253 pvr2_trace(PVR2_TRACE_INIT,
3254 "Unable to reset decoder: nothing attached");
3258 if (!hdw->decoder_ctrl->force_reset) {
3259 pvr2_trace(PVR2_TRACE_INIT,
3260 "Unable to reset decoder: not implemented");
3264 pvr2_trace(PVR2_TRACE_INIT,
3265 "Requesting decoder reset");
3266 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3271 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
3275 LOCK_TAKE(hdw->ctl_lock); do {
3276 pvr2_trace(PVR2_TRACE_INIT,
3277 "Issuing fe demod wake command (%s)",
3278 (onoff ? "on" : "off"));
3280 hdw->cmd_buffer[0] = FX2CMD_HCW_DEMOD_RESETIN;
3281 hdw->cmd_buffer[1] = onoff;
3282 status = pvr2_send_request(hdw, hdw->cmd_buffer, 2, NULL, 0);
3283 } while (0); LOCK_GIVE(hdw->ctl_lock);
3289 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
3293 LOCK_TAKE(hdw->ctl_lock); do {
3294 pvr2_trace(PVR2_TRACE_INIT,
3295 "Issuing fe power command to CPLD (%s)",
3296 (onoff ? "on" : "off"));
3298 hdw->cmd_buffer[0] =
3299 (onoff ? FX2CMD_ONAIR_DTV_POWER_ON :
3300 FX2CMD_ONAIR_DTV_POWER_OFF);
3301 status = pvr2_send_request(hdw, hdw->cmd_buffer, 1, NULL, 0);
3302 } while (0); LOCK_GIVE(hdw->ctl_lock);
3308 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
3312 LOCK_TAKE(hdw->ctl_lock); do {
3313 pvr2_trace(PVR2_TRACE_INIT,
3314 "Issuing onair digital setup command (%s)",
3315 (onoff ? "on" : "off"));
3316 hdw->cmd_buffer[0] =
3317 (onoff ? FX2CMD_ONAIR_DTV_STREAMING_ON :
3318 FX2CMD_ONAIR_DTV_STREAMING_OFF);
3319 status = pvr2_send_request(hdw, hdw->cmd_buffer, 1, NULL, 0);
3320 } while (0); LOCK_GIVE(hdw->ctl_lock);
3325 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
3328 /* Compare digital/analog desired setting with current setting. If
3329 they don't match, fix it... */
3330 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
3331 if (cmode == hdw->pathway_state) {
3332 /* They match; nothing to do */
3336 switch (hdw->hdw_desc->digital_control_scheme) {
3337 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
3338 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
3339 if (cmode == PVR2_PATHWAY_ANALOG) {
3340 /* If moving to analog mode, also force the decoder
3341 to reset. If no decoder is attached, then it's
3342 ok to ignore this because if/when the decoder
3343 attaches, it will reset itself at that time. */
3344 pvr2_hdw_cmd_decoder_reset(hdw);
3347 case PVR2_DIGITAL_SCHEME_ONAIR:
3348 /* Supposedly we should always have the power on whether in
3349 digital or analog mode. But for now do what appears to
3351 if (digitalFl) pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,!0);
3352 pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,digitalFl);
3353 if (!digitalFl) pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,0);
3358 pvr2_hdw_untrip_unlocked(hdw);
3359 hdw->pathway_state = cmode;
3363 void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
3365 /* change some GPIO data
3367 * note: bit d7 of dir appears to control the LED,
3368 * so we shut it off here.
3372 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
3374 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
3376 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
3380 typedef void (*led_method_func)(struct pvr2_hdw *,int);
3382 static led_method_func led_methods[] = {
3383 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
3388 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
3390 unsigned int scheme_id;
3393 if ((!onoff) == (!hdw->led_on)) return;
3395 hdw->led_on = onoff != 0;
3397 scheme_id = hdw->hdw_desc->led_scheme;
3398 if (scheme_id < ARRAY_SIZE(led_methods)) {
3399 fp = led_methods[scheme_id];
3404 if (fp) (*fp)(hdw,onoff);
3408 /* Stop / start video stream transport */
3409 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
3412 if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
3413 hdw->hdw_desc->digital_control_scheme ==
3414 PVR2_DIGITAL_SCHEME_HAUPPAUGE) {
3416 FX2CMD_HCW_DTV_STREAMING_ON :
3417 FX2CMD_HCW_DTV_STREAMING_OFF);
3420 FX2CMD_STREAMING_ON :
3421 FX2CMD_STREAMING_OFF);
3424 LOCK_TAKE(hdw->ctl_lock); do {
3425 hdw->cmd_buffer[0] = cc;
3426 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
3427 } while (0); LOCK_GIVE(hdw->ctl_lock);
3432 /* Evaluate whether or not state_pathway_ok can change */
3433 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
3435 if (hdw->state_pathway_ok) {
3436 /* Nothing to do if pathway is already ok */
3439 if (!hdw->state_pipeline_idle) {
3440 /* Not allowed to change anything if pipeline is not idle */
3443 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
3444 hdw->state_pathway_ok = !0;
3445 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
3450 /* Evaluate whether or not state_encoder_ok can change */
3451 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
3453 if (hdw->state_encoder_ok) return 0;
3454 if (hdw->flag_tripped) return 0;
3455 if (hdw->state_encoder_run) return 0;
3456 if (hdw->state_encoder_config) return 0;
3457 if (hdw->state_decoder_run) return 0;
3458 if (hdw->state_usbstream_run) return 0;
3459 if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) return 0;
3460 if (pvr2_upload_firmware2(hdw) < 0) {
3461 hdw->flag_tripped = !0;
3462 trace_stbit("flag_tripped",hdw->flag_tripped);
3465 hdw->state_encoder_ok = !0;
3466 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
3471 /* Evaluate whether or not state_encoder_config can change */
3472 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
3474 if (hdw->state_encoder_config) {
3475 if (hdw->state_encoder_ok) {
3476 if (hdw->state_pipeline_req &&
3477 !hdw->state_pipeline_pause) return 0;
3479 hdw->state_encoder_config = 0;
3480 hdw->state_encoder_waitok = 0;
3481 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3482 /* paranoia - solve race if timer just completed */
3483 del_timer_sync(&hdw->encoder_wait_timer);
3485 if (!hdw->state_pathway_ok ||
3486 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
3487 !hdw->state_encoder_ok ||
3488 !hdw->state_pipeline_idle ||
3489 hdw->state_pipeline_pause ||
3490 !hdw->state_pipeline_req ||
3491 !hdw->state_pipeline_config) {
3492 /* We must reset the enforced wait interval if
3493 anything has happened that might have disturbed
3494 the encoder. This should be a rare case. */
3495 if (timer_pending(&hdw->encoder_wait_timer)) {
3496 del_timer_sync(&hdw->encoder_wait_timer);
3498 if (hdw->state_encoder_waitok) {
3499 /* Must clear the state - therefore we did
3500 something to a state bit and must also
3502 hdw->state_encoder_waitok = 0;
3503 trace_stbit("state_encoder_waitok",
3504 hdw->state_encoder_waitok);
3509 if (!hdw->state_encoder_waitok) {
3510 if (!timer_pending(&hdw->encoder_wait_timer)) {
3511 /* waitok flag wasn't set and timer isn't
3512 running. Check flag once more to avoid
3513 a race then start the timer. This is
3514 the point when we measure out a minimal
3515 quiet interval before doing something to
3517 if (!hdw->state_encoder_waitok) {
3518 hdw->encoder_wait_timer.expires =
3519 jiffies + (HZ*50/1000);
3520 add_timer(&hdw->encoder_wait_timer);
3523 /* We can't continue until we know we have been
3524 quiet for the interval measured by this
3528 pvr2_encoder_configure(hdw);
3529 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
3531 trace_stbit("state_encoder_config",hdw->state_encoder_config);
3536 /* Evaluate whether or not state_encoder_run can change */
3537 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
3539 if (hdw->state_encoder_run) {
3540 if (hdw->state_encoder_ok) {
3541 if (hdw->state_decoder_run &&
3542 hdw->state_pathway_ok) return 0;
3543 if (pvr2_encoder_stop(hdw) < 0) return !0;
3545 hdw->state_encoder_run = 0;
3547 if (!hdw->state_encoder_ok) return 0;
3548 if (!hdw->state_decoder_run) return 0;
3549 if (!hdw->state_pathway_ok) return 0;
3550 if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) return 0;
3551 if (pvr2_encoder_start(hdw) < 0) return !0;
3552 hdw->state_encoder_run = !0;
3554 trace_stbit("state_encoder_run",hdw->state_encoder_run);
3559 /* Timeout function for quiescent timer. */
3560 static void pvr2_hdw_quiescent_timeout(unsigned long data)
3562 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3563 hdw->state_decoder_quiescent = !0;
3564 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3565 hdw->state_stale = !0;
3566 queue_work(hdw->workqueue,&hdw->workpoll);
3570 /* Timeout function for encoder wait timer. */
3571 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
3573 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3574 hdw->state_encoder_waitok = !0;
3575 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3576 hdw->state_stale = !0;
3577 queue_work(hdw->workqueue,&hdw->workpoll);
3581 /* Evaluate whether or not state_decoder_run can change */
3582 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
3584 if (hdw->state_decoder_run) {
3585 if (hdw->state_encoder_ok) {
3586 if (hdw->state_pipeline_req &&
3587 !hdw->state_pipeline_pause &&
3588 hdw->state_pathway_ok) return 0;
3590 if (!hdw->flag_decoder_missed) {
3591 pvr2_decoder_enable(hdw,0);
3593 hdw->state_decoder_quiescent = 0;
3594 hdw->state_decoder_run = 0;
3595 /* paranoia - solve race if timer just completed */
3596 del_timer_sync(&hdw->quiescent_timer);
3598 if (!hdw->state_decoder_quiescent) {
3599 if (!timer_pending(&hdw->quiescent_timer)) {
3600 /* We don't do something about the
3601 quiescent timer until right here because
3602 we also want to catch cases where the
3603 decoder was already not running (like
3604 after initialization) as opposed to
3605 knowing that we had just stopped it.
3606 The second flag check is here to cover a
3607 race - the timer could have run and set
3608 this flag just after the previous check
3609 but before we did the pending check. */
3610 if (!hdw->state_decoder_quiescent) {
3611 hdw->quiescent_timer.expires =
3612 jiffies + (HZ*50/1000);
3613 add_timer(&hdw->quiescent_timer);
3616 /* Don't allow decoder to start again until it has
3617 been quiesced first. This little detail should
3618 hopefully further stabilize the encoder. */
3621 if (!hdw->state_pathway_ok ||
3622 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
3623 !hdw->state_pipeline_req ||
3624 hdw->state_pipeline_pause ||
3625 !hdw->state_pipeline_config ||
3626 !hdw->state_encoder_config ||
3627 !hdw->state_encoder_ok) return 0;
3628 del_timer_sync(&hdw->quiescent_timer);
3629 if (hdw->flag_decoder_missed) return 0;
3630 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
3631 hdw->state_decoder_quiescent = 0;
3632 hdw->state_decoder_run = !0;
3634 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3635 trace_stbit("state_decoder_run",hdw->state_decoder_run);
3640 /* Evaluate whether or not state_usbstream_run can change */
3641 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
3643 if (hdw->state_usbstream_run) {
3644 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
3645 if (hdw->state_encoder_ok &&
3646 hdw->state_encoder_run &&
3647 hdw->state_pathway_ok) return 0;
3649 if (hdw->state_pipeline_req &&
3650 !hdw->state_pipeline_pause &&
3651 hdw->state_pathway_ok) return 0;
3653 pvr2_hdw_cmd_usbstream(hdw,0);
3654 hdw->state_usbstream_run = 0;
3656 if (!hdw->state_pipeline_req ||
3657 hdw->state_pipeline_pause ||
3658 !hdw->state_pathway_ok) return 0;
3659 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
3660 if (!hdw->state_encoder_ok ||
3661 !hdw->state_encoder_run) return 0;
3663 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
3664 hdw->state_usbstream_run = !0;
3666 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
3671 /* Attempt to configure pipeline, if needed */
3672 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
3674 if (hdw->state_pipeline_config ||
3675 hdw->state_pipeline_pause) return 0;
3676 pvr2_hdw_commit_execute(hdw);
3681 /* Update pipeline idle and pipeline pause tracking states based on other
3682 inputs. This must be called whenever the other relevant inputs have
3684 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
3688 /* Update pipeline state */
3689 st = !(hdw->state_encoder_run ||
3690 hdw->state_decoder_run ||
3691 hdw->state_usbstream_run ||
3692 (!hdw->state_decoder_quiescent));
3693 if (!st != !hdw->state_pipeline_idle) {
3694 hdw->state_pipeline_idle = st;
3697 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
3698 hdw->state_pipeline_pause = 0;
3705 typedef int (*state_eval_func)(struct pvr2_hdw *);
3707 /* Set of functions to be run to evaluate various states in the driver. */
3708 const static state_eval_func eval_funcs[] = {
3709 state_eval_pathway_ok,
3710 state_eval_pipeline_config,
3711 state_eval_encoder_ok,
3712 state_eval_encoder_config,
3713 state_eval_decoder_run,
3714 state_eval_encoder_run,
3715 state_eval_usbstream_run,
3719 /* Process various states and return true if we did anything interesting. */
3720 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
3723 int state_updated = 0;
3726 if (!hdw->state_stale) return 0;
3727 if ((hdw->fw1_state != FW1_STATE_OK) ||
3729 hdw->state_stale = 0;
3732 /* This loop is the heart of the entire driver. It keeps trying to
3733 evaluate various bits of driver state until nothing changes for
3734 one full iteration. Each "bit of state" tracks some global
3735 aspect of the driver, e.g. whether decoder should run, if
3736 pipeline is configured, usb streaming is on, etc. We separately
3737 evaluate each of those questions based on other driver state to
3738 arrive at the correct running configuration. */
3741 state_update_pipeline_state(hdw);
3742 /* Iterate over each bit of state */
3743 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
3744 if ((*eval_funcs[i])(hdw)) {
3747 state_update_pipeline_state(hdw);
3750 } while (check_flag && hdw->flag_ok);
3751 hdw->state_stale = 0;
3752 trace_stbit("state_stale",hdw->state_stale);
3753 return state_updated;
3757 static const char *pvr2_pathway_state_name(int id)
3760 case PVR2_PATHWAY_ANALOG: return "analog";
3761 case PVR2_PATHWAY_DIGITAL: return "digital";
3762 default: return "unknown";
3767 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
3768 char *buf,unsigned int acnt)
3774 "driver:%s%s%s%s%s <mode=%s>",
3775 (hdw->flag_ok ? " <ok>" : " <fail>"),
3776 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
3777 (hdw->flag_disconnected ? " <disconnected>" :
3779 (hdw->flag_tripped ? " <tripped>" : ""),
3780 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
3781 pvr2_pathway_state_name(hdw->pathway_state));
3786 "pipeline:%s%s%s%s",
3787 (hdw->state_pipeline_idle ? " <idle>" : ""),
3788 (hdw->state_pipeline_config ?
3789 " <configok>" : " <stale>"),
3790 (hdw->state_pipeline_req ? " <req>" : ""),
3791 (hdw->state_pipeline_pause ? " <pause>" : ""));
3795 "worker:%s%s%s%s%s%s%s",
3796 (hdw->state_decoder_run ?
3798 (hdw->state_decoder_quiescent ?
3799 "" : " <decode:stop>")),
3800 (hdw->state_decoder_quiescent ?
3801 " <decode:quiescent>" : ""),
3802 (hdw->state_encoder_ok ?
3803 "" : " <encode:init>"),
3804 (hdw->state_encoder_run ?
3805 " <encode:run>" : " <encode:stop>"),
3806 (hdw->state_encoder_config ?
3807 " <encode:configok>" :
3808 (hdw->state_encoder_waitok ?
3809 "" : " <encode:wait>")),
3810 (hdw->state_usbstream_run ?
3811 " <usb:run>" : " <usb:stop>"),
3812 (hdw->state_pathway_ok ?
3813 " <pathway:ok>" : ""));
3819 pvr2_get_state_name(hdw->master_state));
3827 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
3828 char *buf,unsigned int acnt)
3830 unsigned int bcnt,ccnt,idx;
3832 LOCK_TAKE(hdw->big_lock);
3833 for (idx = 0; ; idx++) {
3834 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
3836 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
3838 buf[0] = '\n'; ccnt = 1;
3839 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
3841 LOCK_GIVE(hdw->big_lock);
3846 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
3849 unsigned int idx,ccnt;
3851 for (idx = 0; ; idx++) {
3852 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
3854 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
3859 /* Evaluate and update the driver's current state, taking various actions
3860 as appropriate for the update. */
3861 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
3864 int state_updated = 0;
3865 int callback_flag = 0;
3868 pvr2_trace(PVR2_TRACE_STBITS,
3869 "Drive state check START");
3870 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
3871 pvr2_hdw_state_log_state(hdw);
3874 /* Process all state and get back over disposition */
3875 state_updated = pvr2_hdw_state_update(hdw);
3877 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
3879 /* Update master state based upon all other states. */
3880 if (!hdw->flag_ok) {
3881 st = PVR2_STATE_DEAD;
3882 } else if (hdw->fw1_state != FW1_STATE_OK) {
3883 st = PVR2_STATE_COLD;
3884 } else if (analog_mode && !hdw->state_encoder_ok) {
3885 st = PVR2_STATE_WARM;
3886 } else if (hdw->flag_tripped ||
3887 (analog_mode && hdw->flag_decoder_missed)) {
3888 st = PVR2_STATE_ERROR;
3889 } else if (hdw->state_usbstream_run &&
3891 (hdw->state_encoder_run && hdw->state_decoder_run))) {
3892 st = PVR2_STATE_RUN;
3894 st = PVR2_STATE_READY;
3896 if (hdw->master_state != st) {
3897 pvr2_trace(PVR2_TRACE_STATE,
3898 "Device state change from %s to %s",
3899 pvr2_get_state_name(hdw->master_state),
3900 pvr2_get_state_name(st));
3901 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
3902 hdw->master_state = st;
3906 if (state_updated) {
3907 /* Trigger anyone waiting on any state changes here. */
3908 wake_up(&hdw->state_wait_data);
3911 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
3912 pvr2_hdw_state_log_state(hdw);
3914 pvr2_trace(PVR2_TRACE_STBITS,
3915 "Drive state check DONE callback=%d",callback_flag);
3917 return callback_flag;
3921 /* Cause kernel thread to check / update driver state */
3922 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
3924 if (hdw->state_stale) return;
3925 hdw->state_stale = !0;
3926 trace_stbit("state_stale",hdw->state_stale);
3927 queue_work(hdw->workqueue,&hdw->workpoll);
3931 void pvr2_hdw_get_debug_info_unlocked(const struct pvr2_hdw *hdw,
3932 struct pvr2_hdw_debug_info *ptr)
3934 ptr->big_lock_held = hdw->big_lock_held;
3935 ptr->ctl_lock_held = hdw->ctl_lock_held;
3936 ptr->flag_disconnected = hdw->flag_disconnected;
3937 ptr->flag_init_ok = hdw->flag_init_ok;
3938 ptr->flag_ok = hdw->flag_ok;
3939 ptr->fw1_state = hdw->fw1_state;
3940 ptr->flag_decoder_missed = hdw->flag_decoder_missed;
3941 ptr->flag_tripped = hdw->flag_tripped;
3942 ptr->state_encoder_ok = hdw->state_encoder_ok;
3943 ptr->state_encoder_run = hdw->state_encoder_run;
3944 ptr->state_decoder_run = hdw->state_decoder_run;
3945 ptr->state_usbstream_run = hdw->state_usbstream_run;
3946 ptr->state_decoder_quiescent = hdw->state_decoder_quiescent;
3947 ptr->state_pipeline_config = hdw->state_pipeline_config;
3948 ptr->state_pipeline_req = hdw->state_pipeline_req;
3949 ptr->state_pipeline_pause = hdw->state_pipeline_pause;
3950 ptr->state_pipeline_idle = hdw->state_pipeline_idle;
3951 ptr->cmd_debug_state = hdw->cmd_debug_state;
3952 ptr->cmd_code = hdw->cmd_debug_code;
3953 ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
3954 ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
3955 ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
3956 ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
3957 ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
3958 ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
3959 ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
3963 void pvr2_hdw_get_debug_info_locked(struct pvr2_hdw *hdw,
3964 struct pvr2_hdw_debug_info *ptr)
3966 LOCK_TAKE(hdw->ctl_lock); do {
3967 pvr2_hdw_get_debug_info_unlocked(hdw,ptr);
3968 } while(0); LOCK_GIVE(hdw->ctl_lock);
3972 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
3974 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
3978 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
3980 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
3984 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
3986 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
3990 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
3995 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
3996 if (ret) return ret;
3997 nval = (cval & ~msk) | (val & msk);
3998 pvr2_trace(PVR2_TRACE_GPIO,
3999 "GPIO direction changing 0x%x:0x%x"
4000 " from 0x%x to 0x%x",
4004 pvr2_trace(PVR2_TRACE_GPIO,
4005 "GPIO direction changing to 0x%x",nval);
4007 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
4011 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
4016 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
4017 if (ret) return ret;
4018 nval = (cval & ~msk) | (val & msk);
4019 pvr2_trace(PVR2_TRACE_GPIO,
4020 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
4024 pvr2_trace(PVR2_TRACE_GPIO,
4025 "GPIO output changing to 0x%x",nval);
4027 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
4031 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
4033 return hdw->input_avail_mask;
4037 /* Find I2C address of eeprom */
4038 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
4041 LOCK_TAKE(hdw->ctl_lock); do {
4042 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
4043 result = pvr2_send_request(hdw,
4046 if (result < 0) break;
4047 result = hdw->cmd_buffer[0];
4048 } while(0); LOCK_GIVE(hdw->ctl_lock);
4053 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
4054 u32 match_type, u32 match_chip, u64 reg_id,
4055 int setFl,u64 *val_ptr)
4057 #ifdef CONFIG_VIDEO_ADV_DEBUG
4058 struct pvr2_i2c_client *cp;
4059 struct v4l2_register req;
4063 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
4065 req.match_type = match_type;
4066 req.match_chip = match_chip;
4068 if (setFl) req.val = *val_ptr;
4069 mutex_lock(&hdw->i2c_list_lock); do {
4070 list_for_each_entry(cp, &hdw->i2c_clients, list) {
4071 if (!v4l2_chip_match_i2c_client(
4073 req.match_type, req.match_chip)) {
4076 stat = pvr2_i2c_client_cmd(
4077 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
4078 VIDIOC_DBG_G_REGISTER),&req);
4079 if (!setFl) *val_ptr = req.val;
4083 } while (0); mutex_unlock(&hdw->i2c_list_lock);
4095 Stuff for Emacs to see, in order to encourage consistent editing style:
4096 *** Local Variables: ***
4098 *** fill-column: 75 ***
4099 *** tab-width: 8 ***
4100 *** c-basic-offset: 8 ***