err.no Git - linux-2.6/blob - drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *  $Id$
   4  *
   5  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  *
  20  */
  21
  22 #include <linux/errno.h>
  23 #include <linux/string.h>
  24 #include <linux/slab.h>
  25 #include <linux/firmware.h>
  26 #include <linux/videodev2.h>
  27 #include <media/v4l2-common.h>
  28 #include "pvrusb2.h"
  29 #include "pvrusb2-std.h"
  30 #include "pvrusb2-util.h"
  31 #include "pvrusb2-hdw.h"
  32 #include "pvrusb2-i2c-core.h"
  33 #include "pvrusb2-tuner.h"
  34 #include "pvrusb2-eeprom.h"
  35 #include "pvrusb2-hdw-internal.h"
  36 #include "pvrusb2-encoder.h"
  37 #include "pvrusb2-debug.h"
  38 #include "pvrusb2-fx2-cmd.h"
  39
  40 #define TV_MIN_FREQ     55250000L
  41 #define TV_MAX_FREQ    850000000L
  42
  43 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  44 static DEFINE_MUTEX(pvr2_unit_mtx);
  45
  46 static int ctlchg;
  47 static int initusbreset = 1;
  48 static int procreload;
  49 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  50 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  51 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  52 static int init_pause_msec;
  53
  54 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  55 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  56 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  57 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  58 module_param(initusbreset, int, S_IRUGO|S_IWUSR);
  59 MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
  60 module_param(procreload, int, S_IRUGO|S_IWUSR);
  61 MODULE_PARM_DESC(procreload,
  62                  "Attempt init failure recovery with firmware reload");
  63 module_param_array(tuner,    int, NULL, 0444);
  64 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  65 module_param_array(video_std,    int, NULL, 0444);
  66 MODULE_PARM_DESC(video_std,"specify initial video standard");
  67 module_param_array(tolerance,    int, NULL, 0444);
  68 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  69
  70 #define PVR2_CTL_WRITE_ENDPOINT  0x01
  71 #define PVR2_CTL_READ_ENDPOINT   0x81
  72
  73 #define PVR2_GPIO_IN 0x9008
  74 #define PVR2_GPIO_OUT 0x900c
  75 #define PVR2_GPIO_DIR 0x9020
  76
  77 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
  78
  79 #define PVR2_FIRMWARE_ENDPOINT   0x02
  80
  81 /* size of a firmware chunk */
  82 #define FIRMWARE_CHUNK_SIZE 0x2000
  83
  84 /* Define the list of additional controls we'll dynamically construct based
  85    on query of the cx2341x module. */
  86 struct pvr2_mpeg_ids {
  87         const char *strid;
  88         int id;
  89 };
  90 static const struct pvr2_mpeg_ids mpeg_ids[] = {
  91         {
  92                 .strid = "audio_layer",
  93                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
  94         },{
  95                 .strid = "audio_bitrate",
  96                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
  97         },{
  98                 /* Already using audio_mode elsewhere :-( */
  99                 .strid = "mpeg_audio_mode",
 100                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 101         },{
 102                 .strid = "mpeg_audio_mode_extension",
 103                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 104         },{
 105                 .strid = "audio_emphasis",
 106                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 107         },{
 108                 .strid = "audio_crc",
 109                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 110         },{
 111                 .strid = "video_aspect",
 112                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 113         },{
 114                 .strid = "video_b_frames",
 115                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 116         },{
 117                 .strid = "video_gop_size",
 118                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 119         },{
 120                 .strid = "video_gop_closure",
 121                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 122         },{
 123                 .strid = "video_bitrate_mode",
 124                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 125         },{
 126                 .strid = "video_bitrate",
 127                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 128         },{
 129                 .strid = "video_bitrate_peak",
 130                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 131         },{
 132                 .strid = "video_temporal_decimation",
 133                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 134         },{
 135                 .strid = "stream_type",
 136                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 137         },{
 138                 .strid = "video_spatial_filter_mode",
 139                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 140         },{
 141                 .strid = "video_spatial_filter",
 142                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 143         },{
 144                 .strid = "video_luma_spatial_filter_type",
 145                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 146         },{
 147                 .strid = "video_chroma_spatial_filter_type",
 148                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 149         },{
 150                 .strid = "video_temporal_filter_mode",
 151                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 152         },{
 153                 .strid = "video_temporal_filter",
 154                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 155         },{
 156                 .strid = "video_median_filter_type",
 157                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 158         },{
 159                 .strid = "video_luma_median_filter_top",
 160                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 161         },{
 162                 .strid = "video_luma_median_filter_bottom",
 163                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 164         },{
 165                 .strid = "video_chroma_median_filter_top",
 166                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 167         },{
 168                 .strid = "video_chroma_median_filter_bottom",
 169                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 170         }
 171 };
 172 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 173
 174
 175 static const char *control_values_srate[] = {
 176         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 177         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 178         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 179 };
 180
 181
 182
 183 static const char *control_values_input[] = {
 184         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 185         [PVR2_CVAL_INPUT_DTV]       = "dtv",
 186         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 187         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 188         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 189 };
 190
 191
 192 static const char *control_values_audiomode[] = {
 193         [V4L2_TUNER_MODE_MONO]   = "Mono",
 194         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 195         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 196         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 197         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 198 };
 199
 200
 201 static const char *control_values_hsm[] = {
 202         [PVR2_CVAL_HSM_FAIL] = "Fail",
 203         [PVR2_CVAL_HSM_HIGH] = "High",
 204         [PVR2_CVAL_HSM_FULL] = "Full",
 205 };
 206
 207
 208 static const char *pvr2_state_names[] = {
 209         [PVR2_STATE_NONE] =    "none",
 210         [PVR2_STATE_DEAD] =    "dead",
 211         [PVR2_STATE_COLD] =    "cold",
 212         [PVR2_STATE_WARM] =    "warm",
 213         [PVR2_STATE_ERROR] =   "error",
 214         [PVR2_STATE_READY] =   "ready",
 215         [PVR2_STATE_RUN] =     "run",
 216 };
 217
 218
 219 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 220 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 221 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 222 static void pvr2_hdw_worker_i2c(struct work_struct *work);
 223 static void pvr2_hdw_worker_poll(struct work_struct *work);
 224 static void pvr2_hdw_worker_init(struct work_struct *work);
 225 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 226 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 227 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 228 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 229 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 230 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 231 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 232 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 233 static void pvr2_hdw_quiescent_timeout(unsigned long);
 234 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 235 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 236                                 unsigned int timeout,int probe_fl,
 237                                 void *write_data,unsigned int write_len,
 238                                 void *read_data,unsigned int read_len);
 239
 240
 241 static void trace_stbit(const char *name,int val)
 242 {
 243         pvr2_trace(PVR2_TRACE_STBITS,
 244                    "State bit %s <-- %s",
 245                    name,(val ? "true" : "false"));
 246 }
 247
 248 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 249 {
 250         struct pvr2_hdw *hdw = cptr->hdw;
 251         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 252                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 253         } else {
 254                 *vp = 0;
 255         }
 256         return 0;
 257 }
 258
 259 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 260 {
 261         struct pvr2_hdw *hdw = cptr->hdw;
 262         unsigned int slotId = hdw->freqProgSlot;
 263         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 264                 hdw->freqTable[slotId-1] = v;
 265                 /* Handle side effects correctly - if we're tuned to this
 266                    slot, then forgot the slot id relation since the stored
 267                    frequency has been changed. */
 268                 if (hdw->freqSelector) {
 269                         if (hdw->freqSlotRadio == slotId) {
 270                                 hdw->freqSlotRadio = 0;
 271                         }
 272                 } else {
 273                         if (hdw->freqSlotTelevision == slotId) {
 274                                 hdw->freqSlotTelevision = 0;
 275                         }
 276                 }
 277         }
 278         return 0;
 279 }
 280
 281 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 282 {
 283         *vp = cptr->hdw->freqProgSlot;
 284         return 0;
 285 }
 286
 287 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 288 {
 289         struct pvr2_hdw *hdw = cptr->hdw;
 290         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 291                 hdw->freqProgSlot = v;
 292         }
 293         return 0;
 294 }
 295
 296 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 297 {
 298         struct pvr2_hdw *hdw = cptr->hdw;
 299         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 300         return 0;
 301 }
 302
 303 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 304 {
 305         unsigned freq = 0;
 306         struct pvr2_hdw *hdw = cptr->hdw;
 307         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 308         if (slotId > 0) {
 309                 freq = hdw->freqTable[slotId-1];
 310                 if (!freq) return 0;
 311                 pvr2_hdw_set_cur_freq(hdw,freq);
 312         }
 313         if (hdw->freqSelector) {
 314                 hdw->freqSlotRadio = slotId;
 315         } else {
 316                 hdw->freqSlotTelevision = slotId;
 317         }
 318         return 0;
 319 }
 320
 321 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 322 {
 323         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 324         return 0;
 325 }
 326
 327 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 328 {
 329         return cptr->hdw->freqDirty != 0;
 330 }
 331
 332 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 333 {
 334         cptr->hdw->freqDirty = 0;
 335 }
 336
 337 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 338 {
 339         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 340         return 0;
 341 }
 342
 343 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 344 {
 345         /* Actual maximum depends on the video standard in effect. */
 346         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 347                 *vp = 480;
 348         } else {
 349                 *vp = 576;
 350         }
 351         return 0;
 352 }
 353
 354 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 355 {
 356         /* Actual minimum depends on device digitizer type. */
 357         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 358                 *vp = 75;
 359         } else {
 360                 *vp = 17;
 361         }
 362         return 0;
 363 }
 364
 365 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 366 {
 367         *vp = cptr->hdw->input_val;
 368         return 0;
 369 }
 370
 371 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 372 {
 373         return ((1 << v) & cptr->hdw->input_avail_mask) != 0;
 374 }
 375
 376 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 377 {
 378         struct pvr2_hdw *hdw = cptr->hdw;
 379
 380         if (hdw->input_val != v) {
 381                 hdw->input_val = v;
 382                 hdw->input_dirty = !0;
 383         }
 384
 385         /* Handle side effects - if we switch to a mode that needs the RF
 386            tuner, then select the right frequency choice as well and mark
 387            it dirty. */
 388         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
 389                 hdw->freqSelector = 0;
 390                 hdw->freqDirty = !0;
 391         } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
 392                    (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
 393                 hdw->freqSelector = 1;
 394                 hdw->freqDirty = !0;
 395         }
 396         return 0;
 397 }
 398
 399 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 400 {
 401         return cptr->hdw->input_dirty != 0;
 402 }
 403
 404 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 405 {
 406         cptr->hdw->input_dirty = 0;
 407 }
 408
 409
 410 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 411 {
 412         unsigned long fv;
 413         struct pvr2_hdw *hdw = cptr->hdw;
 414         if (hdw->tuner_signal_stale) {
 415                 pvr2_i2c_core_status_poll(hdw);
 416         }
 417         fv = hdw->tuner_signal_info.rangehigh;
 418         if (!fv) {
 419                 /* Safety fallback */
 420                 *vp = TV_MAX_FREQ;
 421                 return 0;
 422         }
 423         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 424                 fv = (fv * 125) / 2;
 425         } else {
 426                 fv = fv * 62500;
 427         }
 428         *vp = fv;
 429         return 0;
 430 }
 431
 432 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 433 {
 434         unsigned long fv;
 435         struct pvr2_hdw *hdw = cptr->hdw;
 436         if (hdw->tuner_signal_stale) {
 437                 pvr2_i2c_core_status_poll(hdw);
 438         }
 439         fv = hdw->tuner_signal_info.rangelow;
 440         if (!fv) {
 441                 /* Safety fallback */
 442                 *vp = TV_MIN_FREQ;
 443                 return 0;
 444         }
 445         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 446                 fv = (fv * 125) / 2;
 447         } else {
 448                 fv = fv * 62500;
 449         }
 450         *vp = fv;
 451         return 0;
 452 }
 453
 454 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 455 {
 456         return cptr->hdw->enc_stale != 0;
 457 }
 458
 459 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 460 {
 461         cptr->hdw->enc_stale = 0;
 462         cptr->hdw->enc_unsafe_stale = 0;
 463 }
 464
 465 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 466 {
 467         int ret;
 468         struct v4l2_ext_controls cs;
 469         struct v4l2_ext_control c1;
 470         memset(&cs,0,sizeof(cs));
 471         memset(&c1,0,sizeof(c1));
 472         cs.controls = &c1;
 473         cs.count = 1;
 474         c1.id = cptr->info->v4l_id;
 475         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 476                                 VIDIOC_G_EXT_CTRLS);
 477         if (ret) return ret;
 478         *vp = c1.value;
 479         return 0;
 480 }
 481
 482 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 483 {
 484         int ret;
 485         struct pvr2_hdw *hdw = cptr->hdw;
 486         struct v4l2_ext_controls cs;
 487         struct v4l2_ext_control c1;
 488         memset(&cs,0,sizeof(cs));
 489         memset(&c1,0,sizeof(c1));
 490         cs.controls = &c1;
 491         cs.count = 1;
 492         c1.id = cptr->info->v4l_id;
 493         c1.value = v;
 494         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 495                                 hdw->state_encoder_run, &cs,
 496                                 VIDIOC_S_EXT_CTRLS);
 497         if (ret == -EBUSY) {
 498                 /* Oops.  cx2341x is telling us it's not safe to change
 499                    this control while we're capturing.  Make a note of this
 500                    fact so that the pipeline will be stopped the next time
 501                    controls are committed.  Then go on ahead and store this
 502                    change anyway. */
 503                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 504                                         0, &cs,
 505                                         VIDIOC_S_EXT_CTRLS);
 506                 if (!ret) hdw->enc_unsafe_stale = !0;
 507         }
 508         if (ret) return ret;
 509         hdw->enc_stale = !0;
 510         return 0;
 511 }
 512
 513 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 514 {
 515         struct v4l2_queryctrl qctrl;
 516         struct pvr2_ctl_info *info;
 517         qctrl.id = cptr->info->v4l_id;
 518         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 519         /* Strip out the const so we can adjust a function pointer.  It's
 520            OK to do this here because we know this is a dynamically created
 521            control, so the underlying storage for the info pointer is (a)
 522            private to us, and (b) not in read-only storage.  Either we do
 523            this or we significantly complicate the underlying control
 524            implementation. */
 525         info = (struct pvr2_ctl_info *)(cptr->info);
 526         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 527                 if (info->set_value) {
 528                         info->set_value = NULL;
 529                 }
 530         } else {
 531                 if (!(info->set_value)) {
 532                         info->set_value = ctrl_cx2341x_set;
 533                 }
 534         }
 535         return qctrl.flags;
 536 }
 537
 538 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 539 {
 540         *vp = cptr->hdw->state_pipeline_req;
 541         return 0;
 542 }
 543
 544 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 545 {
 546         *vp = cptr->hdw->master_state;
 547         return 0;
 548 }
 549
 550 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 551 {
 552         int result = pvr2_hdw_is_hsm(cptr->hdw);
 553         *vp = PVR2_CVAL_HSM_FULL;
 554         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 555         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 556         return 0;
 557 }
 558
 559 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 560 {
 561         *vp = cptr->hdw->std_mask_avail;
 562         return 0;
 563 }
 564
 565 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 566 {
 567         struct pvr2_hdw *hdw = cptr->hdw;
 568         v4l2_std_id ns;
 569         ns = hdw->std_mask_avail;
 570         ns = (ns & ~m) | (v & m);
 571         if (ns == hdw->std_mask_avail) return 0;
 572         hdw->std_mask_avail = ns;
 573         pvr2_hdw_internal_set_std_avail(hdw);
 574         pvr2_hdw_internal_find_stdenum(hdw);
 575         return 0;
 576 }
 577
 578 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 579                                char *bufPtr,unsigned int bufSize,
 580                                unsigned int *len)
 581 {
 582         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 583         return 0;
 584 }
 585
 586 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 587                                const char *bufPtr,unsigned int bufSize,
 588                                int *mskp,int *valp)
 589 {
 590         int ret;
 591         v4l2_std_id id;
 592         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 593         if (ret < 0) return ret;
 594         if (mskp) *mskp = id;
 595         if (valp) *valp = id;
 596         return 0;
 597 }
 598
 599 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 600 {
 601         *vp = cptr->hdw->std_mask_cur;
 602         return 0;
 603 }
 604
 605 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 606 {
 607         struct pvr2_hdw *hdw = cptr->hdw;
 608         v4l2_std_id ns;
 609         ns = hdw->std_mask_cur;
 610         ns = (ns & ~m) | (v & m);
 611         if (ns == hdw->std_mask_cur) return 0;
 612         hdw->std_mask_cur = ns;
 613         hdw->std_dirty = !0;
 614         pvr2_hdw_internal_find_stdenum(hdw);
 615         return 0;
 616 }
 617
 618 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 619 {
 620         return cptr->hdw->std_dirty != 0;
 621 }
 622
 623 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 624 {
 625         cptr->hdw->std_dirty = 0;
 626 }
 627
 628 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 629 {
 630         struct pvr2_hdw *hdw = cptr->hdw;
 631         pvr2_i2c_core_status_poll(hdw);
 632         *vp = hdw->tuner_signal_info.signal;
 633         return 0;
 634 }
 635
 636 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 637 {
 638         int val = 0;
 639         unsigned int subchan;
 640         struct pvr2_hdw *hdw = cptr->hdw;
 641         pvr2_i2c_core_status_poll(hdw);
 642         subchan = hdw->tuner_signal_info.rxsubchans;
 643         if (subchan & V4L2_TUNER_SUB_MONO) {
 644                 val |= (1 << V4L2_TUNER_MODE_MONO);
 645         }
 646         if (subchan & V4L2_TUNER_SUB_STEREO) {
 647                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 648         }
 649         if (subchan & V4L2_TUNER_SUB_LANG1) {
 650                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 651         }
 652         if (subchan & V4L2_TUNER_SUB_LANG2) {
 653                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 654         }
 655         *vp = val;
 656         return 0;
 657 }
 658
 659
 660 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 661 {
 662         struct pvr2_hdw *hdw = cptr->hdw;
 663         if (v < 0) return -EINVAL;
 664         if (v > hdw->std_enum_cnt) return -EINVAL;
 665         hdw->std_enum_cur = v;
 666         if (!v) return 0;
 667         v--;
 668         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 669         hdw->std_mask_cur = hdw->std_defs[v].id;
 670         hdw->std_dirty = !0;
 671         return 0;
 672 }
 673
 674
 675 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 676 {
 677         *vp = cptr->hdw->std_enum_cur;
 678         return 0;
 679 }
 680
 681
 682 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 683 {
 684         return cptr->hdw->std_dirty != 0;
 685 }
 686
 687
 688 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 689 {
 690         cptr->hdw->std_dirty = 0;
 691 }
 692
 693
 694 #define DEFINT(vmin,vmax) \
 695         .type = pvr2_ctl_int, \
 696         .def.type_int.min_value = vmin, \
 697         .def.type_int.max_value = vmax
 698
 699 #define DEFENUM(tab) \
 700         .type = pvr2_ctl_enum, \
 701         .def.type_enum.count = ARRAY_SIZE(tab), \
 702         .def.type_enum.value_names = tab
 703
 704 #define DEFBOOL \
 705         .type = pvr2_ctl_bool
 706
 707 #define DEFMASK(msk,tab) \
 708         .type = pvr2_ctl_bitmask, \
 709         .def.type_bitmask.valid_bits = msk, \
 710         .def.type_bitmask.bit_names = tab
 711
 712 #define DEFREF(vname) \
 713         .set_value = ctrl_set_##vname, \
 714         .get_value = ctrl_get_##vname, \
 715         .is_dirty = ctrl_isdirty_##vname, \
 716         .clear_dirty = ctrl_cleardirty_##vname
 717
 718
 719 #define VCREATE_FUNCS(vname) \
 720 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 721 {*vp = cptr->hdw->vname##_val; return 0;} \
 722 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 723 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 724 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 725 {return cptr->hdw->vname##_dirty != 0;} \
 726 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 727 {cptr->hdw->vname##_dirty = 0;}
 728
 729 VCREATE_FUNCS(brightness)
 730 VCREATE_FUNCS(contrast)
 731 VCREATE_FUNCS(saturation)
 732 VCREATE_FUNCS(hue)
 733 VCREATE_FUNCS(volume)
 734 VCREATE_FUNCS(balance)
 735 VCREATE_FUNCS(bass)
 736 VCREATE_FUNCS(treble)
 737 VCREATE_FUNCS(mute)
 738 VCREATE_FUNCS(audiomode)
 739 VCREATE_FUNCS(res_hor)
 740 VCREATE_FUNCS(res_ver)
 741 VCREATE_FUNCS(srate)
 742
 743 /* Table definition of all controls which can be manipulated */
 744 static const struct pvr2_ctl_info control_defs[] = {
 745         {
 746                 .v4l_id = V4L2_CID_BRIGHTNESS,
 747                 .desc = "Brightness",
 748                 .name = "brightness",
 749                 .default_value = 128,
 750                 DEFREF(brightness),
 751                 DEFINT(0,255),
 752         },{
 753                 .v4l_id = V4L2_CID_CONTRAST,
 754                 .desc = "Contrast",
 755                 .name = "contrast",
 756                 .default_value = 68,
 757                 DEFREF(contrast),
 758                 DEFINT(0,127),
 759         },{
 760                 .v4l_id = V4L2_CID_SATURATION,
 761                 .desc = "Saturation",
 762                 .name = "saturation",
 763                 .default_value = 64,
 764                 DEFREF(saturation),
 765                 DEFINT(0,127),
 766         },{
 767                 .v4l_id = V4L2_CID_HUE,
 768                 .desc = "Hue",
 769                 .name = "hue",
 770                 .default_value = 0,
 771                 DEFREF(hue),
 772                 DEFINT(-128,127),
 773         },{
 774                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
 775                 .desc = "Volume",
 776                 .name = "volume",
 777                 .default_value = 62000,
 778                 DEFREF(volume),
 779                 DEFINT(0,65535),
 780         },{
 781                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
 782                 .desc = "Balance",
 783                 .name = "balance",
 784                 .default_value = 0,
 785                 DEFREF(balance),
 786                 DEFINT(-32768,32767),
 787         },{
 788                 .v4l_id = V4L2_CID_AUDIO_BASS,
 789                 .desc = "Bass",
 790                 .name = "bass",
 791                 .default_value = 0,
 792                 DEFREF(bass),
 793                 DEFINT(-32768,32767),
 794         },{
 795                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
 796                 .desc = "Treble",
 797                 .name = "treble",
 798                 .default_value = 0,
 799                 DEFREF(treble),
 800                 DEFINT(-32768,32767),
 801         },{
 802                 .v4l_id = V4L2_CID_AUDIO_MUTE,
 803                 .desc = "Mute",
 804                 .name = "mute",
 805                 .default_value = 0,
 806                 DEFREF(mute),
 807                 DEFBOOL,
 808         },{
 809                 .desc = "Video Source",
 810                 .name = "input",
 811                 .internal_id = PVR2_CID_INPUT,
 812                 .default_value = PVR2_CVAL_INPUT_TV,
 813                 .check_value = ctrl_check_input,
 814                 DEFREF(input),
 815                 DEFENUM(control_values_input),
 816         },{
 817                 .desc = "Audio Mode",
 818                 .name = "audio_mode",
 819                 .internal_id = PVR2_CID_AUDIOMODE,
 820                 .default_value = V4L2_TUNER_MODE_STEREO,
 821                 DEFREF(audiomode),
 822                 DEFENUM(control_values_audiomode),
 823         },{
 824                 .desc = "Horizontal capture resolution",
 825                 .name = "resolution_hor",
 826                 .internal_id = PVR2_CID_HRES,
 827                 .default_value = 720,
 828                 DEFREF(res_hor),
 829                 DEFINT(19,720),
 830         },{
 831                 .desc = "Vertical capture resolution",
 832                 .name = "resolution_ver",
 833                 .internal_id = PVR2_CID_VRES,
 834                 .default_value = 480,
 835                 DEFREF(res_ver),
 836                 DEFINT(17,576),
 837                 /* Hook in check for video standard and adjust maximum
 838                    depending on the standard. */
 839                 .get_max_value = ctrl_vres_max_get,
 840                 .get_min_value = ctrl_vres_min_get,
 841         },{
 842                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
 843                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
 844                 .desc = "Audio Sampling Frequency",
 845                 .name = "srate",
 846                 DEFREF(srate),
 847                 DEFENUM(control_values_srate),
 848         },{
 849                 .desc = "Tuner Frequency (Hz)",
 850                 .name = "frequency",
 851                 .internal_id = PVR2_CID_FREQUENCY,
 852                 .default_value = 0,
 853                 .set_value = ctrl_freq_set,
 854                 .get_value = ctrl_freq_get,
 855                 .is_dirty = ctrl_freq_is_dirty,
 856                 .clear_dirty = ctrl_freq_clear_dirty,
 857                 DEFINT(0,0),
 858                 /* Hook in check for input value (tv/radio) and adjust
 859                    max/min values accordingly */
 860                 .get_max_value = ctrl_freq_max_get,
 861                 .get_min_value = ctrl_freq_min_get,
 862         },{
 863                 .desc = "Channel",
 864                 .name = "channel",
 865                 .set_value = ctrl_channel_set,
 866                 .get_value = ctrl_channel_get,
 867                 DEFINT(0,FREQTABLE_SIZE),
 868         },{
 869                 .desc = "Channel Program Frequency",
 870                 .name = "freq_table_value",
 871                 .set_value = ctrl_channelfreq_set,
 872                 .get_value = ctrl_channelfreq_get,
 873                 DEFINT(0,0),
 874                 /* Hook in check for input value (tv/radio) and adjust
 875                    max/min values accordingly */
 876                 .get_max_value = ctrl_freq_max_get,
 877                 .get_min_value = ctrl_freq_min_get,
 878         },{
 879                 .desc = "Channel Program ID",
 880                 .name = "freq_table_channel",
 881                 .set_value = ctrl_channelprog_set,
 882                 .get_value = ctrl_channelprog_get,
 883                 DEFINT(0,FREQTABLE_SIZE),
 884         },{
 885                 .desc = "Streaming Enabled",
 886                 .name = "streaming_enabled",
 887                 .get_value = ctrl_streamingenabled_get,
 888                 DEFBOOL,
 889         },{
 890                 .desc = "USB Speed",
 891                 .name = "usb_speed",
 892                 .get_value = ctrl_hsm_get,
 893                 DEFENUM(control_values_hsm),
 894         },{
 895                 .desc = "Master State",
 896                 .name = "master_state",
 897                 .get_value = ctrl_masterstate_get,
 898                 DEFENUM(pvr2_state_names),
 899         },{
 900                 .desc = "Signal Present",
 901                 .name = "signal_present",
 902                 .get_value = ctrl_signal_get,
 903                 DEFINT(0,65535),
 904         },{
 905                 .desc = "Audio Modes Present",
 906                 .name = "audio_modes_present",
 907                 .get_value = ctrl_audio_modes_present_get,
 908                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
 909                    v4l.  Nothing outside of this module cares about this,
 910                    but I reuse it in order to also reuse the
 911                    control_values_audiomode string table. */
 912                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
 913                          (1 << V4L2_TUNER_MODE_STEREO)|
 914                          (1 << V4L2_TUNER_MODE_LANG1)|
 915                          (1 << V4L2_TUNER_MODE_LANG2)),
 916                         control_values_audiomode),
 917         },{
 918                 .desc = "Video Standards Available Mask",
 919                 .name = "video_standard_mask_available",
 920                 .internal_id = PVR2_CID_STDAVAIL,
 921                 .skip_init = !0,
 922                 .get_value = ctrl_stdavail_get,
 923                 .set_value = ctrl_stdavail_set,
 924                 .val_to_sym = ctrl_std_val_to_sym,
 925                 .sym_to_val = ctrl_std_sym_to_val,
 926                 .type = pvr2_ctl_bitmask,
 927         },{
 928                 .desc = "Video Standards In Use Mask",
 929                 .name = "video_standard_mask_active",
 930                 .internal_id = PVR2_CID_STDCUR,
 931                 .skip_init = !0,
 932                 .get_value = ctrl_stdcur_get,
 933                 .set_value = ctrl_stdcur_set,
 934                 .is_dirty = ctrl_stdcur_is_dirty,
 935                 .clear_dirty = ctrl_stdcur_clear_dirty,
 936                 .val_to_sym = ctrl_std_val_to_sym,
 937                 .sym_to_val = ctrl_std_sym_to_val,
 938                 .type = pvr2_ctl_bitmask,
 939         },{
 940                 .desc = "Video Standard Name",
 941                 .name = "video_standard",
 942                 .internal_id = PVR2_CID_STDENUM,
 943                 .skip_init = !0,
 944                 .get_value = ctrl_stdenumcur_get,
 945                 .set_value = ctrl_stdenumcur_set,
 946                 .is_dirty = ctrl_stdenumcur_is_dirty,
 947                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
 948                 .type = pvr2_ctl_enum,
 949         }
 950 };
 951
 952 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
 953
 954
 955 const char *pvr2_config_get_name(enum pvr2_config cfg)
 956 {
 957         switch (cfg) {
 958         case pvr2_config_empty: return "empty";
 959         case pvr2_config_mpeg: return "mpeg";
 960         case pvr2_config_vbi: return "vbi";
 961         case pvr2_config_pcm: return "pcm";
 962         case pvr2_config_rawvideo: return "raw video";
 963         }
 964         return "<unknown>";
 965 }
 966
 967
 968 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
 969 {
 970         return hdw->usb_dev;
 971 }
 972
 973
 974 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
 975 {
 976         return hdw->serial_number;
 977 }
 978
 979
 980 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
 981 {
 982         return hdw->bus_info;
 983 }
 984
 985
 986 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
 987 {
 988         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
 989 }
 990
 991 /* Set the currently tuned frequency and account for all possible
 992    driver-core side effects of this action. */
 993 void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
 994 {
 995         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
 996                 if (hdw->freqSelector) {
 997                         /* Swing over to radio frequency selection */
 998                         hdw->freqSelector = 0;
 999                         hdw->freqDirty = !0;
1000                 }
1001                 if (hdw->freqValRadio != val) {
1002                         hdw->freqValRadio = val;
1003                         hdw->freqSlotRadio = 0;
1004                         hdw->freqDirty = !0;
1005                 }
1006         } else {
1007                 if (!(hdw->freqSelector)) {
1008                         /* Swing over to television frequency selection */
1009                         hdw->freqSelector = 1;
1010                         hdw->freqDirty = !0;
1011                 }
1012                 if (hdw->freqValTelevision != val) {
1013                         hdw->freqValTelevision = val;
1014                         hdw->freqSlotTelevision = 0;
1015                         hdw->freqDirty = !0;
1016                 }
1017         }
1018 }
1019
1020 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1021 {
1022         return hdw->unit_number;
1023 }
1024
1025
1026 /* Attempt to locate one of the given set of files.  Messages are logged
1027    appropriate to what has been found.  The return value will be 0 or
1028    greater on success (it will be the index of the file name found) and
1029    fw_entry will be filled in.  Otherwise a negative error is returned on
1030    failure.  If the return value is -ENOENT then no viable firmware file
1031    could be located. */
1032 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1033                                 const struct firmware **fw_entry,
1034                                 const char *fwtypename,
1035                                 unsigned int fwcount,
1036                                 const char *fwnames[])
1037 {
1038         unsigned int idx;
1039         int ret = -EINVAL;
1040         for (idx = 0; idx < fwcount; idx++) {
1041                 ret = request_firmware(fw_entry,
1042                                        fwnames[idx],
1043                                        &hdw->usb_dev->dev);
1044                 if (!ret) {
1045                         trace_firmware("Located %s firmware: %s;"
1046                                        " uploading...",
1047                                        fwtypename,
1048                                        fwnames[idx]);
1049                         return idx;
1050                 }
1051                 if (ret == -ENOENT) continue;
1052                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1053                            "request_firmware fatal error with code=%d",ret);
1054                 return ret;
1055         }
1056         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1057                    "***WARNING***"
1058                    " Device %s firmware"
1059                    " seems to be missing.",
1060                    fwtypename);
1061         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1062                    "Did you install the pvrusb2 firmware files"
1063                    " in their proper location?");
1064         if (fwcount == 1) {
1065                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1066                            "request_firmware unable to locate %s file %s",
1067                            fwtypename,fwnames[0]);
1068         } else {
1069                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1070                            "request_firmware unable to locate"
1071                            " one of the following %s files:",
1072                            fwtypename);
1073                 for (idx = 0; idx < fwcount; idx++) {
1074                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1075                                    "request_firmware: Failed to find %s",
1076                                    fwnames[idx]);
1077                 }
1078         }
1079         return ret;
1080 }
1081
1082
1083 /*
1084  * pvr2_upload_firmware1().
1085  *
1086  * Send the 8051 firmware to the device.  After the upload, arrange for
1087  * device to re-enumerate.
1088  *
1089  * NOTE : the pointer to the firmware data given by request_firmware()
1090  * is not suitable for an usb transaction.
1091  *
1092  */
1093 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1094 {
1095         const struct firmware *fw_entry = NULL;
1096         void  *fw_ptr;
1097         unsigned int pipe;
1098         int ret;
1099         u16 address;
1100
1101         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1102                 hdw->fw1_state = FW1_STATE_OK;
1103                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1104                            "Connected device type defines"
1105                            " no firmware to upload; ignoring firmware");
1106                 return -ENOTTY;
1107         }
1108
1109         hdw->fw1_state = FW1_STATE_FAILED; // default result
1110
1111         trace_firmware("pvr2_upload_firmware1");
1112
1113         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1114                                    hdw->hdw_desc->fx2_firmware.cnt,
1115                                    hdw->hdw_desc->fx2_firmware.lst);
1116         if (ret < 0) {
1117                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1118                 return ret;
1119         }
1120
1121         usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1122         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1123
1124         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1125
1126         if (fw_entry->size != 0x2000){
1127                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1128                 release_firmware(fw_entry);
1129                 return -ENOMEM;
1130         }
1131
1132         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1133         if (fw_ptr == NULL){
1134                 release_firmware(fw_entry);
1135                 return -ENOMEM;
1136         }
1137
1138         /* We have to hold the CPU during firmware upload. */
1139         pvr2_hdw_cpureset_assert(hdw,1);
1140
1141         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1142            chunk. */
1143
1144         ret = 0;
1145         for(address = 0; address < fw_entry->size; address += 0x800) {
1146                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1147                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1148                                        0, fw_ptr, 0x800, HZ);
1149         }
1150
1151         trace_firmware("Upload done, releasing device's CPU");
1152
1153         /* Now release the CPU.  It will disconnect and reconnect later. */
1154         pvr2_hdw_cpureset_assert(hdw,0);
1155
1156         kfree(fw_ptr);
1157         release_firmware(fw_entry);
1158
1159         trace_firmware("Upload done (%d bytes sent)",ret);
1160
1161         /* We should have written 8192 bytes */
1162         if (ret == 8192) {
1163                 hdw->fw1_state = FW1_STATE_RELOAD;
1164                 return 0;
1165         }
1166
1167         return -EIO;
1168 }
1169
1170
1171 /*
1172  * pvr2_upload_firmware2()
1173  *
1174  * This uploads encoder firmware on endpoint 2.
1175  *
1176  */
1177
1178 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1179 {
1180         const struct firmware *fw_entry = NULL;
1181         void  *fw_ptr;
1182         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1183         int actual_length;
1184         int ret = 0;
1185         int fwidx;
1186         static const char *fw_files[] = {
1187                 CX2341X_FIRM_ENC_FILENAME,
1188         };
1189
1190         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1191                 return 0;
1192         }
1193
1194         trace_firmware("pvr2_upload_firmware2");
1195
1196         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1197                                    ARRAY_SIZE(fw_files), fw_files);
1198         if (ret < 0) return ret;
1199         fwidx = ret;
1200         ret = 0;
1201         /* Since we're about to completely reinitialize the encoder,
1202            invalidate our cached copy of its configuration state.  Next
1203            time we configure the encoder, then we'll fully configure it. */
1204         hdw->enc_cur_valid = 0;
1205
1206         /* First prepare firmware loading */
1207         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1208         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1209         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1210         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1211         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1212         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1213         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1214         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1215         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1216         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1217         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1218         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1219         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1220         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1221         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1222         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1223         LOCK_TAKE(hdw->ctl_lock); do {
1224                 hdw->cmd_buffer[0] = FX2CMD_FWPOST1;
1225                 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
1226                 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1227                 hdw->cmd_buffer[1] = 0;
1228                 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0);
1229         } while (0); LOCK_GIVE(hdw->ctl_lock);
1230
1231         if (ret) {
1232                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1233                            "firmware2 upload prep failed, ret=%d",ret);
1234                 release_firmware(fw_entry);
1235                 return ret;
1236         }
1237
1238         /* Now send firmware */
1239
1240         fw_len = fw_entry->size;
1241
1242         if (fw_len % sizeof(u32)) {
1243                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1244                            "size of %s firmware"
1245                            " must be a multiple of %zu bytes",
1246                            fw_files[fwidx],sizeof(u32));
1247                 release_firmware(fw_entry);
1248                 return -1;
1249         }
1250
1251         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1252         if (fw_ptr == NULL){
1253                 release_firmware(fw_entry);
1254                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1255                            "failed to allocate memory for firmware2 upload");
1256                 return -ENOMEM;
1257         }
1258
1259         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1260
1261         fw_done = 0;
1262         for (fw_done = 0; fw_done < fw_len;) {
1263                 bcnt = fw_len - fw_done;
1264                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1265                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1266                 /* Usbsnoop log shows that we must swap bytes... */
1267                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1268                         ((u32 *)fw_ptr)[icnt] =
1269                                 ___swab32(((u32 *)fw_ptr)[icnt]);
1270
1271                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1272                                     &actual_length, HZ);
1273                 ret |= (actual_length != bcnt);
1274                 if (ret) break;
1275                 fw_done += bcnt;
1276         }
1277
1278         trace_firmware("upload of %s : %i / %i ",
1279                        fw_files[fwidx],fw_done,fw_len);
1280
1281         kfree(fw_ptr);
1282         release_firmware(fw_entry);
1283
1284         if (ret) {
1285                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1286                            "firmware2 upload transfer failure");
1287                 return ret;
1288         }
1289
1290         /* Finish upload */
1291
1292         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1293         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1294         LOCK_TAKE(hdw->ctl_lock); do {
1295                 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1296                 hdw->cmd_buffer[1] = 0;
1297                 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0);
1298         } while (0); LOCK_GIVE(hdw->ctl_lock);
1299
1300         if (ret) {
1301                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1302                            "firmware2 upload post-proc failure");
1303         }
1304         return ret;
1305 }
1306
1307
1308 static const char *pvr2_get_state_name(unsigned int st)
1309 {
1310         if (st < ARRAY_SIZE(pvr2_state_names)) {
1311                 return pvr2_state_names[st];
1312         }
1313         return "???";
1314 }
1315
1316 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1317 {
1318         if (!hdw->decoder_ctrl) {
1319                 if (!hdw->flag_decoder_missed) {
1320                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1321                                    "WARNING: No decoder present");
1322                         hdw->flag_decoder_missed = !0;
1323                         trace_stbit("flag_decoder_missed",
1324                                     hdw->flag_decoder_missed);
1325                 }
1326                 return -EIO;
1327         }
1328         hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt,enablefl);
1329         return 0;
1330 }
1331
1332
1333 void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
1334 {
1335         if (hdw->decoder_ctrl == ptr) return;
1336         hdw->decoder_ctrl = ptr;
1337         if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1338                 hdw->flag_decoder_missed = 0;
1339                 trace_stbit("flag_decoder_missed",
1340                             hdw->flag_decoder_missed);
1341                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1342                            "Decoder has appeared");
1343                 pvr2_hdw_state_sched(hdw);
1344         }
1345 }
1346
1347
1348 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1349 {
1350         return hdw->master_state;
1351 }
1352
1353
1354 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1355 {
1356         if (!hdw->flag_tripped) return 0;
1357         hdw->flag_tripped = 0;
1358         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1359                    "Clearing driver error statuss");
1360         return !0;
1361 }
1362
1363
1364 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1365 {
1366         int fl;
1367         LOCK_TAKE(hdw->big_lock); do {
1368                 fl = pvr2_hdw_untrip_unlocked(hdw);
1369         } while (0); LOCK_GIVE(hdw->big_lock);
1370         if (fl) pvr2_hdw_state_sched(hdw);
1371         return 0;
1372 }
1373
1374
1375 const char *pvr2_hdw_get_state_name(unsigned int id)
1376 {
1377         if (id >= ARRAY_SIZE(pvr2_state_names)) return NULL;
1378         return pvr2_state_names[id];
1379 }
1380
1381
1382 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1383 {
1384         return hdw->state_pipeline_req != 0;
1385 }
1386
1387
1388 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1389 {
1390         int ret,st;
1391         LOCK_TAKE(hdw->big_lock); do {
1392                 pvr2_hdw_untrip_unlocked(hdw);
1393                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1394                         hdw->state_pipeline_req = enable_flag != 0;
1395                         pvr2_trace(PVR2_TRACE_START_STOP,
1396                                    "/*--TRACE_STREAM--*/ %s",
1397                                    enable_flag ? "enable" : "disable");
1398                 }
1399                 pvr2_hdw_state_sched(hdw);
1400         } while (0); LOCK_GIVE(hdw->big_lock);
1401         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1402         if (enable_flag) {
1403                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1404                         if (st != PVR2_STATE_READY) return -EIO;
1405                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1406                 }
1407         }
1408         return 0;
1409 }
1410
1411
1412 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1413 {
1414         int fl;
1415         LOCK_TAKE(hdw->big_lock);
1416         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1417                 hdw->desired_stream_type = config;
1418                 hdw->state_pipeline_config = 0;
1419                 trace_stbit("state_pipeline_config",
1420                             hdw->state_pipeline_config);
1421                 pvr2_hdw_state_sched(hdw);
1422         }
1423         LOCK_GIVE(hdw->big_lock);
1424         if (fl) return 0;
1425         return pvr2_hdw_wait(hdw,0);
1426 }
1427
1428
1429 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1430 {
1431         int unit_number = hdw->unit_number;
1432         int tp = -1;
1433         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1434                 tp = tuner[unit_number];
1435         }
1436         if (tp < 0) return -EINVAL;
1437         hdw->tuner_type = tp;
1438         hdw->tuner_updated = !0;
1439         return 0;
1440 }
1441
1442
1443 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1444 {
1445         int unit_number = hdw->unit_number;
1446         int tp = 0;
1447         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1448                 tp = video_std[unit_number];
1449                 if (tp) return tp;
1450         }
1451         return 0;
1452 }
1453
1454
1455 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1456 {
1457         int unit_number = hdw->unit_number;
1458         int tp = 0;
1459         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1460                 tp = tolerance[unit_number];
1461         }
1462         return tp;
1463 }
1464
1465
1466 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1467 {
1468         /* Try a harmless request to fetch the eeprom's address over
1469            endpoint 1.  See what happens.  Only the full FX2 image can
1470            respond to this.  If this probe fails then likely the FX2
1471            firmware needs be loaded. */
1472         int result;
1473         LOCK_TAKE(hdw->ctl_lock); do {
1474                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1475                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1476                                            hdw->cmd_buffer,1,
1477                                            hdw->cmd_buffer,1);
1478                 if (result < 0) break;
1479         } while(0); LOCK_GIVE(hdw->ctl_lock);
1480         if (result) {
1481                 pvr2_trace(PVR2_TRACE_INIT,
1482                            "Probe of device endpoint 1 result status %d",
1483                            result);
1484         } else {
1485                 pvr2_trace(PVR2_TRACE_INIT,
1486                            "Probe of device endpoint 1 succeeded");
1487         }
1488         return result == 0;
1489 }
1490
1491 struct pvr2_std_hack {
1492         v4l2_std_id pat;  /* Pattern to match */
1493         v4l2_std_id msk;  /* Which bits we care about */
1494         v4l2_std_id std;  /* What additional standards or default to set */
1495 };
1496
1497 /* This data structure labels specific combinations of standards from
1498    tveeprom that we'll try to recognize.  If we recognize one, then assume
1499    a specified default standard to use.  This is here because tveeprom only
1500    tells us about available standards not the intended default standard (if
1501    any) for the device in question.  We guess the default based on what has
1502    been reported as available.  Note that this is only for guessing a
1503    default - which can always be overridden explicitly - and if the user
1504    has otherwise named a default then that default will always be used in
1505    place of this table. */
1506 const static struct pvr2_std_hack std_eeprom_maps[] = {
1507         {       /* PAL(B/G) */
1508                 .pat = V4L2_STD_B|V4L2_STD_GH,
1509                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1510         },
1511         {       /* NTSC(M) */
1512                 .pat = V4L2_STD_MN,
1513                 .std = V4L2_STD_NTSC_M,
1514         },
1515         {       /* PAL(I) */
1516                 .pat = V4L2_STD_PAL_I,
1517                 .std = V4L2_STD_PAL_I,
1518         },
1519         {       /* SECAM(L/L') */
1520                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1521                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1522         },
1523         {       /* PAL(D/D1/K) */
1524                 .pat = V4L2_STD_DK,
1525                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1526         },
1527 };
1528
1529 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1530 {
1531         char buf[40];
1532         unsigned int bcnt;
1533         v4l2_std_id std1,std2,std3;
1534
1535         std1 = get_default_standard(hdw);
1536         std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1537
1538         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1539         pvr2_trace(PVR2_TRACE_STD,
1540                    "Supported video standard(s) reported available"
1541                    " in hardware: %.*s",
1542                    bcnt,buf);
1543
1544         hdw->std_mask_avail = hdw->std_mask_eeprom;
1545
1546         std2 = (std1|std3) & ~hdw->std_mask_avail;
1547         if (std2) {
1548                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1549                 pvr2_trace(PVR2_TRACE_STD,
1550                            "Expanding supported video standards"
1551                            " to include: %.*s",
1552                            bcnt,buf);
1553                 hdw->std_mask_avail |= std2;
1554         }
1555
1556         pvr2_hdw_internal_set_std_avail(hdw);
1557
1558         if (std1) {
1559                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1560                 pvr2_trace(PVR2_TRACE_STD,
1561                            "Initial video standard forced to %.*s",
1562                            bcnt,buf);
1563                 hdw->std_mask_cur = std1;
1564                 hdw->std_dirty = !0;
1565                 pvr2_hdw_internal_find_stdenum(hdw);
1566                 return;
1567         }
1568         if (std3) {
1569                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1570                 pvr2_trace(PVR2_TRACE_STD,
1571                            "Initial video standard"
1572                            " (determined by device type): %.*s",bcnt,buf);
1573                 hdw->std_mask_cur = std3;
1574                 hdw->std_dirty = !0;
1575                 pvr2_hdw_internal_find_stdenum(hdw);
1576                 return;
1577         }
1578
1579         {
1580                 unsigned int idx;
1581                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1582                         if (std_eeprom_maps[idx].msk ?
1583                             ((std_eeprom_maps[idx].pat ^
1584                              hdw->std_mask_eeprom) &
1585                              std_eeprom_maps[idx].msk) :
1586                             (std_eeprom_maps[idx].pat !=
1587                              hdw->std_mask_eeprom)) continue;
1588                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1589                                                   std_eeprom_maps[idx].std);
1590                         pvr2_trace(PVR2_TRACE_STD,
1591                                    "Initial video standard guessed as %.*s",
1592                                    bcnt,buf);
1593                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1594                         hdw->std_dirty = !0;
1595                         pvr2_hdw_internal_find_stdenum(hdw);
1596                         return;
1597                 }
1598         }
1599
1600         if (hdw->std_enum_cnt > 1) {
1601                 // Autoselect the first listed standard
1602                 hdw->std_enum_cur = 1;
1603                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1604                 hdw->std_dirty = !0;
1605                 pvr2_trace(PVR2_TRACE_STD,
1606                            "Initial video standard auto-selected to %s",
1607                            hdw->std_defs[hdw->std_enum_cur-1].name);
1608                 return;
1609         }
1610
1611         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1612                    "Unable to select a viable initial video standard");
1613 }
1614
1615
1616 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1617 {
1618         int ret;
1619         unsigned int idx;
1620         struct pvr2_ctrl *cptr;
1621         int reloadFl = 0;
1622         if (hdw->hdw_desc->fx2_firmware.cnt) {
1623                 if (!reloadFl) {
1624                         reloadFl =
1625                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1626                                  == 0);
1627                         if (reloadFl) {
1628                                 pvr2_trace(PVR2_TRACE_INIT,
1629                                            "USB endpoint config looks strange"
1630                                            "; possibly firmware needs to be"
1631                                            " loaded");
1632                         }
1633                 }
1634                 if (!reloadFl) {
1635                         reloadFl = !pvr2_hdw_check_firmware(hdw);
1636                         if (reloadFl) {
1637                                 pvr2_trace(PVR2_TRACE_INIT,
1638                                            "Check for FX2 firmware failed"
1639                                            "; possibly firmware needs to be"
1640                                            " loaded");
1641                         }
1642                 }
1643                 if (reloadFl) {
1644                         if (pvr2_upload_firmware1(hdw) != 0) {
1645                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1646                                            "Failure uploading firmware1");
1647                         }
1648                         return;
1649                 }
1650         }
1651         hdw->fw1_state = FW1_STATE_OK;
1652
1653         if (initusbreset) {
1654                 pvr2_hdw_device_reset(hdw);
1655         }
1656         if (!pvr2_hdw_dev_ok(hdw)) return;
1657
1658         for (idx = 0; idx < hdw->hdw_desc->client_modules.cnt; idx++) {
1659                 request_module(hdw->hdw_desc->client_modules.lst[idx]);
1660         }
1661
1662         if (!hdw->hdw_desc->flag_no_powerup) {
1663                 pvr2_hdw_cmd_powerup(hdw);
1664                 if (!pvr2_hdw_dev_ok(hdw)) return;
1665         }
1666
1667         // This step MUST happen after the earlier powerup step.
1668         pvr2_i2c_core_init(hdw);
1669         if (!pvr2_hdw_dev_ok(hdw)) return;
1670
1671         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1672                 cptr = hdw->controls + idx;
1673                 if (cptr->info->skip_init) continue;
1674                 if (!cptr->info->set_value) continue;
1675                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1676         }
1677
1678         /* Set up special default values for the television and radio
1679            frequencies here.  It's not really important what these defaults
1680            are, but I set them to something usable in the Chicago area just
1681            to make driver testing a little easier. */
1682
1683         /* US Broadcast channel 7 (175.25 MHz) */
1684         hdw->freqValTelevision = 175250000L;
1685         /* 104.3 MHz, a usable FM station for my area */
1686         hdw->freqValRadio = 104300000L;
1687
1688         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
1689         // thread-safe against the normal pvr2_send_request() mechanism.
1690         // (We should make it thread safe).
1691
1692         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
1693                 ret = pvr2_hdw_get_eeprom_addr(hdw);
1694                 if (!pvr2_hdw_dev_ok(hdw)) return;
1695                 if (ret < 0) {
1696                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1697                                    "Unable to determine location of eeprom,"
1698                                    " skipping");
1699                 } else {
1700                         hdw->eeprom_addr = ret;
1701                         pvr2_eeprom_analyze(hdw);
1702                         if (!pvr2_hdw_dev_ok(hdw)) return;
1703                 }
1704         } else {
1705                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
1706                 hdw->tuner_updated = !0;
1707                 hdw->std_mask_eeprom = V4L2_STD_ALL;
1708         }
1709
1710         pvr2_hdw_setup_std(hdw);
1711
1712         if (!get_default_tuner_type(hdw)) {
1713                 pvr2_trace(PVR2_TRACE_INIT,
1714                            "pvr2_hdw_setup: Tuner type overridden to %d",
1715                            hdw->tuner_type);
1716         }
1717
1718         pvr2_i2c_core_check_stale(hdw);
1719         hdw->tuner_updated = 0;
1720
1721         if (!pvr2_hdw_dev_ok(hdw)) return;
1722
1723         pvr2_hdw_commit_setup(hdw);
1724
1725         hdw->vid_stream = pvr2_stream_create();
1726         if (!pvr2_hdw_dev_ok(hdw)) return;
1727         pvr2_trace(PVR2_TRACE_INIT,
1728                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1729         if (hdw->vid_stream) {
1730                 idx = get_default_error_tolerance(hdw);
1731                 if (idx) {
1732                         pvr2_trace(PVR2_TRACE_INIT,
1733                                    "pvr2_hdw_setup: video stream %p"
1734                                    " setting tolerance %u",
1735                                    hdw->vid_stream,idx);
1736                 }
1737                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1738                                   PVR2_VID_ENDPOINT,idx);
1739         }
1740
1741         if (!pvr2_hdw_dev_ok(hdw)) return;
1742
1743         hdw->flag_init_ok = !0;
1744
1745         pvr2_hdw_state_sched(hdw);
1746 }
1747
1748
1749 /* Set up the structure and attempt to put the device into a usable state.
1750    This can be a time-consuming operation, which is why it is not done
1751    internally as part of the create() step. */
1752 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
1753 {
1754         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1755         do {
1756                 pvr2_hdw_setup_low(hdw);
1757                 pvr2_trace(PVR2_TRACE_INIT,
1758                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1759                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
1760                 if (pvr2_hdw_dev_ok(hdw)) {
1761                         if (hdw->flag_init_ok) {
1762                                 pvr2_trace(
1763                                         PVR2_TRACE_INFO,
1764                                         "Device initialization"
1765                                         " completed successfully.");
1766                                 break;
1767                         }
1768                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
1769                                 pvr2_trace(
1770                                         PVR2_TRACE_INFO,
1771                                         "Device microcontroller firmware"
1772                                         " (re)loaded; it should now reset"
1773                                         " and reconnect.");
1774                                 break;
1775                         }
1776                         pvr2_trace(
1777                                 PVR2_TRACE_ERROR_LEGS,
1778                                 "Device initialization was not successful.");
1779                         if (hdw->fw1_state == FW1_STATE_MISSING) {
1780                                 pvr2_trace(
1781                                         PVR2_TRACE_ERROR_LEGS,
1782                                         "Giving up since device"
1783                                         " microcontroller firmware"
1784                                         " appears to be missing.");
1785                                 break;
1786                         }
1787                 }
1788                 if (procreload) {
1789                         pvr2_trace(
1790                                 PVR2_TRACE_ERROR_LEGS,
1791                                 "Attempting pvrusb2 recovery by reloading"
1792                                 " primary firmware.");
1793                         pvr2_trace(
1794                                 PVR2_TRACE_ERROR_LEGS,
1795                                 "If this works, device should disconnect"
1796                                 " and reconnect in a sane state.");
1797                         hdw->fw1_state = FW1_STATE_UNKNOWN;
1798                         pvr2_upload_firmware1(hdw);
1799                 } else {
1800                         pvr2_trace(
1801                                 PVR2_TRACE_ERROR_LEGS,
1802                                 "***WARNING*** pvrusb2 device hardware"
1803                                 " appears to be jammed"
1804                                 " and I can't clear it.");
1805                         pvr2_trace(
1806                                 PVR2_TRACE_ERROR_LEGS,
1807                                 "You might need to power cycle"
1808                                 " the pvrusb2 device"
1809                                 " in order to recover.");
1810                 }
1811         } while (0);
1812         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
1813 }
1814
1815
1816 /* Perform second stage initialization.  Set callback pointer first so that
1817    we can avoid a possible initialization race (if the kernel thread runs
1818    before the callback has been set). */
1819 void pvr2_hdw_initialize(struct pvr2_hdw *hdw,
1820                          void (*callback_func)(void *),
1821                          void *callback_data)
1822 {
1823         LOCK_TAKE(hdw->big_lock); do {
1824                 hdw->state_data = callback_data;
1825                 hdw->state_func = callback_func;
1826         } while (0); LOCK_GIVE(hdw->big_lock);
1827         queue_work(hdw->workqueue,&hdw->workinit);
1828 }
1829
1830
1831 /* Create, set up, and return a structure for interacting with the
1832    underlying hardware.  */
1833 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1834                                  const struct usb_device_id *devid)
1835 {
1836         unsigned int idx,cnt1,cnt2,m;
1837         struct pvr2_hdw *hdw;
1838         int valid_std_mask;
1839         struct pvr2_ctrl *cptr;
1840         const struct pvr2_device_desc *hdw_desc;
1841         __u8 ifnum;
1842         struct v4l2_queryctrl qctrl;
1843         struct pvr2_ctl_info *ciptr;
1844
1845         hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
1846
1847         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
1848         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
1849                    hdw,hdw_desc->description);
1850         if (!hdw) goto fail;
1851
1852         init_timer(&hdw->quiescent_timer);
1853         hdw->quiescent_timer.data = (unsigned long)hdw;
1854         hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
1855
1856         init_timer(&hdw->encoder_wait_timer);
1857         hdw->encoder_wait_timer.data = (unsigned long)hdw;
1858         hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
1859
1860         hdw->master_state = PVR2_STATE_DEAD;
1861
1862         init_waitqueue_head(&hdw->state_wait_data);
1863
1864         hdw->tuner_signal_stale = !0;
1865         cx2341x_fill_defaults(&hdw->enc_ctl_state);
1866
1867         /* Calculate which inputs are OK */
1868         m = 0;
1869         if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
1870         if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
1871                 m |= 1 << PVR2_CVAL_INPUT_DTV;
1872         }
1873         if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
1874         if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
1875         if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
1876         hdw->input_avail_mask = m;
1877
1878         /* If not a hybrid device, pathway_state never changes.  So
1879            initialize it here to what it should forever be. */
1880         if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
1881                 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
1882         } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
1883                 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
1884         }
1885
1886         hdw->control_cnt = CTRLDEF_COUNT;
1887         hdw->control_cnt += MPEGDEF_COUNT;
1888         hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
1889                                 GFP_KERNEL);
1890         if (!hdw->controls) goto fail;
1891         hdw->hdw_desc = hdw_desc;
1892         for (idx = 0; idx < hdw->control_cnt; idx++) {
1893                 cptr = hdw->controls + idx;
1894                 cptr->hdw = hdw;
1895         }
1896         for (idx = 0; idx < 32; idx++) {
1897                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1898         }
1899         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1900                 cptr = hdw->controls + idx;
1901                 cptr->info = control_defs+idx;
1902         }
1903
1904         /* Ensure that default input choice is a valid one. */
1905         m = hdw->input_avail_mask;
1906         if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
1907                 if (!((1 << idx) & m)) continue;
1908                 hdw->input_val = idx;
1909                 break;
1910         }
1911
1912         /* Define and configure additional controls from cx2341x module. */
1913         hdw->mpeg_ctrl_info = kzalloc(
1914                 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
1915         if (!hdw->mpeg_ctrl_info) goto fail;
1916         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
1917                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
1918                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
1919                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
1920                 ciptr->name = mpeg_ids[idx].strid;
1921                 ciptr->v4l_id = mpeg_ids[idx].id;
1922                 ciptr->skip_init = !0;
1923                 ciptr->get_value = ctrl_cx2341x_get;
1924                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
1925                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
1926                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
1927                 qctrl.id = ciptr->v4l_id;
1928                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
1929                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
1930                         ciptr->set_value = ctrl_cx2341x_set;
1931                 }
1932                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
1933                         PVR2_CTLD_INFO_DESC_SIZE);
1934                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
1935                 ciptr->default_value = qctrl.default_value;
1936                 switch (qctrl.type) {
1937                 default:
1938                 case V4L2_CTRL_TYPE_INTEGER:
1939                         ciptr->type = pvr2_ctl_int;
1940                         ciptr->def.type_int.min_value = qctrl.minimum;
1941                         ciptr->def.type_int.max_value = qctrl.maximum;
1942                         break;
1943                 case V4L2_CTRL_TYPE_BOOLEAN:
1944                         ciptr->type = pvr2_ctl_bool;
1945                         break;
1946                 case V4L2_CTRL_TYPE_MENU:
1947                         ciptr->type = pvr2_ctl_enum;
1948                         ciptr->def.type_enum.value_names =
1949                                 cx2341x_ctrl_get_menu(ciptr->v4l_id);
1950                         for (cnt1 = 0;
1951                              ciptr->def.type_enum.value_names[cnt1] != NULL;
1952                              cnt1++) { }
1953                         ciptr->def.type_enum.count = cnt1;
1954                         break;
1955                 }
1956                 cptr->info = ciptr;
1957         }
1958
1959         // Initialize video standard enum dynamic control
1960         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
1961         if (cptr) {
1962                 memcpy(&hdw->std_info_enum,cptr->info,
1963                        sizeof(hdw->std_info_enum));
1964                 cptr->info = &hdw->std_info_enum;
1965
1966         }
1967         // Initialize control data regarding video standard masks
1968         valid_std_mask = pvr2_std_get_usable();
1969         for (idx = 0; idx < 32; idx++) {
1970                 if (!(valid_std_mask & (1 << idx))) continue;
1971                 cnt1 = pvr2_std_id_to_str(
1972                         hdw->std_mask_names[idx],
1973                         sizeof(hdw->std_mask_names[idx])-1,
1974                         1 << idx);
1975                 hdw->std_mask_names[idx][cnt1] = 0;
1976         }
1977         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
1978         if (cptr) {
1979                 memcpy(&hdw->std_info_avail,cptr->info,
1980                        sizeof(hdw->std_info_avail));
1981                 cptr->info = &hdw->std_info_avail;
1982                 hdw->std_info_avail.def.type_bitmask.bit_names =
1983                         hdw->std_mask_ptrs;
1984                 hdw->std_info_avail.def.type_bitmask.valid_bits =
1985                         valid_std_mask;
1986         }
1987         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
1988         if (cptr) {
1989                 memcpy(&hdw->std_info_cur,cptr->info,
1990                        sizeof(hdw->std_info_cur));
1991                 cptr->info = &hdw->std_info_cur;
1992                 hdw->std_info_cur.def.type_bitmask.bit_names =
1993                         hdw->std_mask_ptrs;
1994                 hdw->std_info_avail.def.type_bitmask.valid_bits =
1995                         valid_std_mask;
1996         }
1997
1998         hdw->eeprom_addr = -1;
1999         hdw->unit_number = -1;
2000         hdw->v4l_minor_number_video = -1;
2001         hdw->v4l_minor_number_vbi = -1;
2002         hdw->v4l_minor_number_radio = -1;
2003         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2004         if (!hdw->ctl_write_buffer) goto fail;
2005         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2006         if (!hdw->ctl_read_buffer) goto fail;
2007         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2008         if (!hdw->ctl_write_urb) goto fail;
2009         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2010         if (!hdw->ctl_read_urb) goto fail;
2011
2012         mutex_lock(&pvr2_unit_mtx); do {
2013                 for (idx = 0; idx < PVR_NUM; idx++) {
2014                         if (unit_pointers[idx]) continue;
2015                         hdw->unit_number = idx;
2016                         unit_pointers[idx] = hdw;
2017                         break;
2018                 }
2019         } while (0); mutex_unlock(&pvr2_unit_mtx);
2020
2021         cnt1 = 0;
2022         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2023         cnt1 += cnt2;
2024         if (hdw->unit_number >= 0) {
2025                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2026                                  ('a' + hdw->unit_number));
2027                 cnt1 += cnt2;
2028         }
2029         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2030         hdw->name[cnt1] = 0;
2031
2032         hdw->workqueue = create_singlethread_workqueue(hdw->name);
2033         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2034         INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
2035         INIT_WORK(&hdw->workinit,pvr2_hdw_worker_init);
2036
2037         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2038                    hdw->unit_number,hdw->name);
2039
2040         hdw->tuner_type = -1;
2041         hdw->flag_ok = !0;
2042
2043         hdw->usb_intf = intf;
2044         hdw->usb_dev = interface_to_usbdev(intf);
2045
2046         scnprintf(hdw->bus_info,sizeof(hdw->bus_info),
2047                   "usb %s address %d",
2048                   hdw->usb_dev->dev.bus_id,
2049                   hdw->usb_dev->devnum);
2050
2051         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2052         usb_set_interface(hdw->usb_dev,ifnum,0);
2053
2054         mutex_init(&hdw->ctl_lock_mutex);
2055         mutex_init(&hdw->big_lock_mutex);
2056
2057         return hdw;
2058  fail:
2059         if (hdw) {
2060                 del_timer_sync(&hdw->quiescent_timer);
2061                 del_timer_sync(&hdw->encoder_wait_timer);
2062                 if (hdw->workqueue) {
2063                         flush_workqueue(hdw->workqueue);
2064                         destroy_workqueue(hdw->workqueue);
2065                         hdw->workqueue = NULL;
2066                 }
2067                 usb_free_urb(hdw->ctl_read_urb);
2068                 usb_free_urb(hdw->ctl_write_urb);
2069                 kfree(hdw->ctl_read_buffer);
2070                 kfree(hdw->ctl_write_buffer);
2071                 kfree(hdw->controls);
2072                 kfree(hdw->mpeg_ctrl_info);
2073                 kfree(hdw->std_defs);
2074                 kfree(hdw->std_enum_names);
2075                 kfree(hdw);
2076         }
2077         return NULL;
2078 }
2079
2080
2081 /* Remove _all_ associations between this driver and the underlying USB
2082    layer. */
2083 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2084 {
2085         if (hdw->flag_disconnected) return;
2086         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2087         if (hdw->ctl_read_urb) {
2088                 usb_kill_urb(hdw->ctl_read_urb);
2089                 usb_free_urb(hdw->ctl_read_urb);
2090                 hdw->ctl_read_urb = NULL;
2091         }
2092         if (hdw->ctl_write_urb) {
2093                 usb_kill_urb(hdw->ctl_write_urb);
2094                 usb_free_urb(hdw->ctl_write_urb);
2095                 hdw->ctl_write_urb = NULL;
2096         }
2097         if (hdw->ctl_read_buffer) {
2098                 kfree(hdw->ctl_read_buffer);
2099                 hdw->ctl_read_buffer = NULL;
2100         }
2101         if (hdw->ctl_write_buffer) {
2102                 kfree(hdw->ctl_write_buffer);
2103                 hdw->ctl_write_buffer = NULL;
2104         }
2105         hdw->flag_disconnected = !0;
2106         hdw->usb_dev = NULL;
2107         hdw->usb_intf = NULL;
2108         pvr2_hdw_render_useless(hdw);
2109 }
2110
2111
2112 /* Destroy hardware interaction structure */
2113 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2114 {
2115         if (!hdw) return;
2116         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2117         if (hdw->workqueue) {
2118                 flush_workqueue(hdw->workqueue);
2119                 destroy_workqueue(hdw->workqueue);
2120                 hdw->workqueue = NULL;
2121         }
2122         del_timer_sync(&hdw->quiescent_timer);
2123         del_timer_sync(&hdw->encoder_wait_timer);
2124         if (hdw->fw_buffer) {
2125                 kfree(hdw->fw_buffer);
2126                 hdw->fw_buffer = NULL;
2127         }
2128         if (hdw->vid_stream) {
2129                 pvr2_stream_destroy(hdw->vid_stream);
2130                 hdw->vid_stream = NULL;
2131         }
2132         if (hdw->decoder_ctrl) {
2133                 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2134         }
2135         pvr2_i2c_core_done(hdw);
2136         pvr2_hdw_remove_usb_stuff(hdw);
2137         mutex_lock(&pvr2_unit_mtx); do {
2138                 if ((hdw->unit_number >= 0) &&
2139                     (hdw->unit_number < PVR_NUM) &&
2140                     (unit_pointers[hdw->unit_number] == hdw)) {
2141                         unit_pointers[hdw->unit_number] = NULL;
2142                 }
2143         } while (0); mutex_unlock(&pvr2_unit_mtx);
2144         kfree(hdw->controls);
2145         kfree(hdw->mpeg_ctrl_info);
2146         kfree(hdw->std_defs);
2147         kfree(hdw->std_enum_names);
2148         kfree(hdw);
2149 }
2150
2151
2152 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2153 {
2154         return (hdw && hdw->flag_ok);
2155 }
2156
2157
2158 /* Called when hardware has been unplugged */
2159 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2160 {
2161         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2162         LOCK_TAKE(hdw->big_lock);
2163         LOCK_TAKE(hdw->ctl_lock);
2164         pvr2_hdw_remove_usb_stuff(hdw);
2165         LOCK_GIVE(hdw->ctl_lock);
2166         LOCK_GIVE(hdw->big_lock);
2167 }
2168
2169
2170 // Attempt to autoselect an appropriate value for std_enum_cur given
2171 // whatever is currently in std_mask_cur
2172 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2173 {
2174         unsigned int idx;
2175         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2176                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2177                         hdw->std_enum_cur = idx;
2178                         return;
2179                 }
2180         }
2181         hdw->std_enum_cur = 0;
2182 }
2183
2184
2185 // Calculate correct set of enumerated standards based on currently known
2186 // set of available standards bits.
2187 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2188 {
2189         struct v4l2_standard *newstd;
2190         unsigned int std_cnt;
2191         unsigned int idx;
2192
2193         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2194
2195         if (hdw->std_defs) {
2196                 kfree(hdw->std_defs);
2197                 hdw->std_defs = NULL;
2198         }
2199         hdw->std_enum_cnt = 0;
2200         if (hdw->std_enum_names) {
2201                 kfree(hdw->std_enum_names);
2202                 hdw->std_enum_names = NULL;
2203         }
2204
2205         if (!std_cnt) {
2206                 pvr2_trace(
2207                         PVR2_TRACE_ERROR_LEGS,
2208                         "WARNING: Failed to identify any viable standards");
2209         }
2210         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2211         hdw->std_enum_names[0] = "none";
2212         for (idx = 0; idx < std_cnt; idx++) {
2213                 hdw->std_enum_names[idx+1] =
2214                         newstd[idx].name;
2215         }
2216         // Set up the dynamic control for this standard
2217         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2218         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2219         hdw->std_defs = newstd;
2220         hdw->std_enum_cnt = std_cnt+1;
2221         hdw->std_enum_cur = 0;
2222         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2223 }
2224
2225
2226 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2227                                struct v4l2_standard *std,
2228                                unsigned int idx)
2229 {
2230         int ret = -EINVAL;
2231         if (!idx) return ret;
2232         LOCK_TAKE(hdw->big_lock); do {
2233                 if (idx >= hdw->std_enum_cnt) break;
2234                 idx--;
2235                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2236                 ret = 0;
2237         } while (0); LOCK_GIVE(hdw->big_lock);
2238         return ret;
2239 }
2240
2241
2242 /* Get the number of defined controls */
2243 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2244 {
2245         return hdw->control_cnt;
2246 }
2247
2248
2249 /* Retrieve a control handle given its index (0..count-1) */
2250 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2251                                              unsigned int idx)
2252 {
2253         if (idx >= hdw->control_cnt) return NULL;
2254         return hdw->controls + idx;
2255 }
2256
2257
2258 /* Retrieve a control handle given its index (0..count-1) */
2259 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2260                                           unsigned int ctl_id)
2261 {
2262         struct pvr2_ctrl *cptr;
2263         unsigned int idx;
2264         int i;
2265
2266         /* This could be made a lot more efficient, but for now... */
2267         for (idx = 0; idx < hdw->control_cnt; idx++) {
2268                 cptr = hdw->controls + idx;
2269                 i = cptr->info->internal_id;
2270                 if (i && (i == ctl_id)) return cptr;
2271         }
2272         return NULL;
2273 }
2274
2275
2276 /* Given a V4L ID, retrieve the control structure associated with it. */
2277 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2278 {
2279         struct pvr2_ctrl *cptr;
2280         unsigned int idx;
2281         int i;
2282
2283         /* This could be made a lot more efficient, but for now... */
2284         for (idx = 0; idx < hdw->control_cnt; idx++) {
2285                 cptr = hdw->controls + idx;
2286                 i = cptr->info->v4l_id;
2287                 if (i && (i == ctl_id)) return cptr;
2288         }
2289         return NULL;
2290 }
2291
2292
2293 /* Given a V4L ID for its immediate predecessor, retrieve the control
2294    structure associated with it. */
2295 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2296                                             unsigned int ctl_id)
2297 {
2298         struct pvr2_ctrl *cptr,*cp2;
2299         unsigned int idx;
2300         int i;
2301
2302         /* This could be made a lot more efficient, but for now... */
2303         cp2 = NULL;
2304         for (idx = 0; idx < hdw->control_cnt; idx++) {
2305                 cptr = hdw->controls + idx;
2306                 i = cptr->info->v4l_id;
2307                 if (!i) continue;
2308                 if (i <= ctl_id) continue;
2309                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2310                 cp2 = cptr;
2311         }
2312         return cp2;
2313         return NULL;
2314 }
2315
2316
2317 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2318 {
2319         switch (tp) {
2320         case pvr2_ctl_int: return "integer";
2321         case pvr2_ctl_enum: return "enum";
2322         case pvr2_ctl_bool: return "boolean";
2323         case pvr2_ctl_bitmask: return "bitmask";
2324         }
2325         return "";
2326 }
2327
2328
2329 /* Figure out if we need to commit control changes.  If so, mark internal
2330    state flags to indicate this fact and return true.  Otherwise do nothing
2331    else and return false. */
2332 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
2333 {
2334         unsigned int idx;
2335         struct pvr2_ctrl *cptr;
2336         int value;
2337         int commit_flag = 0;
2338         char buf[100];
2339         unsigned int bcnt,ccnt;
2340
2341         for (idx = 0; idx < hdw->control_cnt; idx++) {
2342                 cptr = hdw->controls + idx;
2343                 if (!cptr->info->is_dirty) continue;
2344                 if (!cptr->info->is_dirty(cptr)) continue;
2345                 commit_flag = !0;
2346
2347                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
2348                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2349                                  cptr->info->name);
2350                 value = 0;
2351                 cptr->info->get_value(cptr,&value);
2352                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2353                                                 buf+bcnt,
2354                                                 sizeof(buf)-bcnt,&ccnt);
2355                 bcnt += ccnt;
2356                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2357                                   get_ctrl_typename(cptr->info->type));
2358                 pvr2_trace(PVR2_TRACE_CTL,
2359                            "/*--TRACE_COMMIT--*/ %.*s",
2360                            bcnt,buf);
2361         }
2362
2363         if (!commit_flag) {
2364                 /* Nothing has changed */
2365                 return 0;
2366         }
2367
2368         hdw->state_pipeline_config = 0;
2369         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2370         pvr2_hdw_state_sched(hdw);
2371
2372         return !0;
2373 }
2374
2375
2376 /* Perform all operations needed to commit all control changes.  This must
2377    be performed in synchronization with the pipeline state and is thus
2378    expected to be called as part of the driver's worker thread.  Return
2379    true if commit successful, otherwise return false to indicate that
2380    commit isn't possible at this time. */
2381 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
2382 {
2383         unsigned int idx;
2384         struct pvr2_ctrl *cptr;
2385         int disruptive_change;
2386
2387         /* When video standard changes, reset the hres and vres values -
2388            but if the user has pending changes there, then let the changes
2389            take priority. */
2390         if (hdw->std_dirty) {
2391                 /* Rewrite the vertical resolution to be appropriate to the
2392                    video standard that has been selected. */
2393                 int nvres;
2394                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2395                         nvres = 480;
2396                 } else {
2397                         nvres = 576;
2398                 }
2399                 if (nvres != hdw->res_ver_val) {
2400                         hdw->res_ver_val = nvres;
2401                         hdw->res_ver_dirty = !0;
2402                 }
2403         }
2404
2405         if (hdw->input_dirty &&
2406             (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
2407               PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
2408              hdw->pathway_state)) {
2409                 /* Change of mode being asked for... */
2410                 hdw->state_pathway_ok = 0;
2411                 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
2412         }
2413         if (!hdw->state_pathway_ok) {
2414                 /* Can't commit anything until pathway is ok. */
2415                 return 0;
2416         }
2417         /* If any of the below has changed, then we can't do the update
2418            while the pipeline is running.  Pipeline must be paused first
2419            and decoder -> encoder connection be made quiescent before we
2420            can proceed. */
2421         disruptive_change =
2422                 (hdw->std_dirty ||
2423                  hdw->enc_unsafe_stale ||
2424                  hdw->srate_dirty ||
2425                  hdw->res_ver_dirty ||
2426                  hdw->res_hor_dirty ||
2427                  hdw->input_dirty ||
2428                  (hdw->active_stream_type != hdw->desired_stream_type));
2429         if (disruptive_change && !hdw->state_pipeline_idle) {
2430                 /* Pipeline is not idle; we can't proceed.  Arrange to
2431                    cause pipeline to stop so that we can try this again
2432                    later.... */
2433                 hdw->state_pipeline_pause = !0;
2434                 return 0;
2435         }
2436
2437         if (hdw->srate_dirty) {
2438                 /* Write new sample rate into control structure since
2439                  * the master copy is stale.  We must track srate
2440                  * separate from the mpeg control structure because
2441                  * other logic also uses this value. */
2442                 struct v4l2_ext_controls cs;
2443                 struct v4l2_ext_control c1;
2444                 memset(&cs,0,sizeof(cs));
2445                 memset(&c1,0,sizeof(c1));
2446                 cs.controls = &c1;
2447                 cs.count = 1;
2448                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2449                 c1.value = hdw->srate_val;
2450                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
2451         }
2452
2453         /* Scan i2c core at this point - before we clear all the dirty
2454            bits.  Various parts of the i2c core will notice dirty bits as
2455            appropriate and arrange to broadcast or directly send updates to
2456            the client drivers in order to keep everything in sync */
2457         pvr2_i2c_core_check_stale(hdw);
2458
2459         for (idx = 0; idx < hdw->control_cnt; idx++) {
2460                 cptr = hdw->controls + idx;
2461                 if (!cptr->info->clear_dirty) continue;
2462                 cptr->info->clear_dirty(cptr);
2463         }
2464
2465         if (hdw->active_stream_type != hdw->desired_stream_type) {
2466                 /* Handle any side effects of stream config here */
2467                 hdw->active_stream_type = hdw->desired_stream_type;
2468         }
2469
2470         /* Now execute i2c core update */
2471         pvr2_i2c_core_sync(hdw);
2472
2473         if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
2474             hdw->state_encoder_run) {
2475                 /* If encoder isn't running or it can't be touched, then
2476                    this will get worked out later when we start the
2477                    encoder. */
2478                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
2479         }
2480
2481         hdw->state_pipeline_config = !0;
2482         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2483         return !0;
2484 }
2485
2486
2487 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2488 {
2489         int fl;
2490         LOCK_TAKE(hdw->big_lock);
2491         fl = pvr2_hdw_commit_setup(hdw);
2492         LOCK_GIVE(hdw->big_lock);
2493         if (!fl) return 0;
2494         return pvr2_hdw_wait(hdw,0);
2495 }
2496
2497
2498 static void pvr2_hdw_worker_i2c(struct work_struct *work)
2499 {
2500         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
2501         LOCK_TAKE(hdw->big_lock); do {
2502                 pvr2_i2c_core_sync(hdw);
2503         } while (0); LOCK_GIVE(hdw->big_lock);
2504 }
2505
2506
2507 static void pvr2_hdw_worker_poll(struct work_struct *work)
2508 {
2509         int fl = 0;
2510         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
2511         LOCK_TAKE(hdw->big_lock); do {
2512                 fl = pvr2_hdw_state_eval(hdw);
2513         } while (0); LOCK_GIVE(hdw->big_lock);
2514         if (fl && hdw->state_func) {
2515                 hdw->state_func(hdw->state_data);
2516         }
2517 }
2518
2519
2520 static void pvr2_hdw_worker_init(struct work_struct *work)
2521 {
2522         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workinit);
2523         LOCK_TAKE(hdw->big_lock); do {
2524                 pvr2_hdw_setup(hdw);
2525         } while (0); LOCK_GIVE(hdw->big_lock);
2526 }
2527
2528
2529 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
2530 {
2531         return wait_event_interruptible(
2532                 hdw->state_wait_data,
2533                 (hdw->state_stale == 0) &&
2534                 (!state || (hdw->master_state != state)));
2535 }
2536
2537
2538 /* Return name for this driver instance */
2539 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2540 {
2541         return hdw->name;
2542 }
2543
2544
2545 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
2546 {
2547         return hdw->hdw_desc->description;
2548 }
2549
2550
2551 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
2552 {
2553         return hdw->hdw_desc->shortname;
2554 }
2555
2556
2557 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2558 {
2559         int result;
2560         LOCK_TAKE(hdw->ctl_lock); do {
2561                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
2562                 result = pvr2_send_request(hdw,
2563                                            hdw->cmd_buffer,1,
2564                                            hdw->cmd_buffer,1);
2565                 if (result < 0) break;
2566                 result = (hdw->cmd_buffer[0] != 0);
2567         } while(0); LOCK_GIVE(hdw->ctl_lock);
2568         return result;
2569 }
2570
2571
2572 /* Execute poll of tuner status */
2573 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
2574 {
2575         LOCK_TAKE(hdw->big_lock); do {
2576                 pvr2_i2c_core_status_poll(hdw);
2577         } while (0); LOCK_GIVE(hdw->big_lock);
2578 }
2579
2580
2581 /* Return information about the tuner */
2582 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
2583 {
2584         LOCK_TAKE(hdw->big_lock); do {
2585                 if (hdw->tuner_signal_stale) {
2586                         pvr2_i2c_core_status_poll(hdw);
2587                 }
2588                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
2589         } while (0); LOCK_GIVE(hdw->big_lock);
2590         return 0;
2591 }
2592
2593
2594 /* Get handle to video output stream */
2595 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2596 {
2597         return hp->vid_stream;
2598 }
2599
2600
2601 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2602 {
2603         int nr = pvr2_hdw_get_unit_number(hdw);
2604         LOCK_TAKE(hdw->big_lock); do {
2605                 hdw->log_requested = !0;
2606                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
2607                 pvr2_i2c_core_check_stale(hdw);
2608                 hdw->log_requested = 0;
2609                 pvr2_i2c_core_sync(hdw);
2610                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
2611                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
2612                 pvr2_hdw_state_log_state(hdw);
2613                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
2614         } while (0); LOCK_GIVE(hdw->big_lock);
2615 }
2616
2617
2618 /* Grab EEPROM contents, needed for direct method. */
2619 #define EEPROM_SIZE 8192
2620 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
2621 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
2622 {
2623         struct i2c_msg msg[2];
2624         u8 *eeprom;
2625         u8 iadd[2];
2626         u8 addr;
2627         u16 eepromSize;
2628         unsigned int offs;
2629         int ret;
2630         int mode16 = 0;
2631         unsigned pcnt,tcnt;
2632         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
2633         if (!eeprom) {
2634                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2635                            "Failed to allocate memory"
2636                            " required to read eeprom");
2637                 return NULL;
2638         }
2639
2640         trace_eeprom("Value for eeprom addr from controller was 0x%x",
2641                      hdw->eeprom_addr);
2642         addr = hdw->eeprom_addr;
2643         /* Seems that if the high bit is set, then the *real* eeprom
2644            address is shifted right now bit position (noticed this in
2645            newer PVR USB2 hardware) */
2646         if (addr & 0x80) addr >>= 1;
2647
2648         /* FX2 documentation states that a 16bit-addressed eeprom is
2649            expected if the I2C address is an odd number (yeah, this is
2650            strange but it's what they do) */
2651         mode16 = (addr & 1);
2652         eepromSize = (mode16 ? EEPROM_SIZE : 256);
2653         trace_eeprom("Examining %d byte eeprom at location 0x%x"
2654                      " using %d bit addressing",eepromSize,addr,
2655                      mode16 ? 16 : 8);
2656
2657         msg[0].addr = addr;
2658         msg[0].flags = 0;
2659         msg[0].len = mode16 ? 2 : 1;
2660         msg[0].buf = iadd;
2661         msg[1].addr = addr;
2662         msg[1].flags = I2C_M_RD;
2663
2664         /* We have to do the actual eeprom data fetch ourselves, because
2665            (1) we're only fetching part of the eeprom, and (2) if we were
2666            getting the whole thing our I2C driver can't grab it in one
2667            pass - which is what tveeprom is otherwise going to attempt */
2668         memset(eeprom,0,EEPROM_SIZE);
2669         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
2670                 pcnt = 16;
2671                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
2672                 offs = tcnt + (eepromSize - EEPROM_SIZE);
2673                 if (mode16) {
2674                         iadd[0] = offs >> 8;
2675                         iadd[1] = offs;
2676                 } else {
2677                         iadd[0] = offs;
2678                 }
2679                 msg[1].len = pcnt;
2680                 msg[1].buf = eeprom+tcnt;
2681                 if ((ret = i2c_transfer(&hdw->i2c_adap,
2682                                         msg,ARRAY_SIZE(msg))) != 2) {
2683                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2684                                    "eeprom fetch set offs err=%d",ret);
2685                         kfree(eeprom);
2686                         return NULL;
2687                 }
2688         }
2689         return eeprom;
2690 }
2691
2692
2693 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
2694                                 int prom_flag,
2695                                 int enable_flag)
2696 {
2697         int ret;
2698         u16 address;
2699         unsigned int pipe;
2700         LOCK_TAKE(hdw->big_lock); do {
2701                 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
2702
2703                 if (!enable_flag) {
2704                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2705                                    "Cleaning up after CPU firmware fetch");
2706                         kfree(hdw->fw_buffer);
2707                         hdw->fw_buffer = NULL;
2708                         hdw->fw_size = 0;
2709                         if (hdw->fw_cpu_flag) {
2710                                 /* Now release the CPU.  It will disconnect
2711                                    and reconnect later. */
2712                                 pvr2_hdw_cpureset_assert(hdw,0);
2713                         }
2714                         break;
2715                 }
2716
2717                 hdw->fw_cpu_flag = (prom_flag == 0);
2718                 if (hdw->fw_cpu_flag) {
2719                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2720                                    "Preparing to suck out CPU firmware");
2721                         hdw->fw_size = 0x2000;
2722                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
2723                         if (!hdw->fw_buffer) {
2724                                 hdw->fw_size = 0;
2725                                 break;
2726                         }
2727
2728                         /* We have to hold the CPU during firmware upload. */
2729                         pvr2_hdw_cpureset_assert(hdw,1);
2730
2731                         /* download the firmware from address 0000-1fff in 2048
2732                            (=0x800) bytes chunk. */
2733
2734                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2735                                    "Grabbing CPU firmware");
2736                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2737                         for(address = 0; address < hdw->fw_size;
2738                             address += 0x800) {
2739                                 ret = usb_control_msg(hdw->usb_dev,pipe,
2740                                                       0xa0,0xc0,
2741                                                       address,0,
2742                                                       hdw->fw_buffer+address,
2743                                                       0x800,HZ);
2744                                 if (ret < 0) break;
2745                         }
2746
2747                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2748                                    "Done grabbing CPU firmware");
2749                 } else {
2750                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2751                                    "Sucking down EEPROM contents");
2752                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
2753                         if (!hdw->fw_buffer) {
2754                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2755                                            "EEPROM content suck failed.");
2756                                 break;
2757                         }
2758                         hdw->fw_size = EEPROM_SIZE;
2759                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2760                                    "Done sucking down EEPROM contents");
2761                 }
2762
2763         } while (0); LOCK_GIVE(hdw->big_lock);
2764 }
2765
2766
2767 /* Return true if we're in a mode for retrieval CPU firmware */
2768 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2769 {
2770         return hdw->fw_buffer != NULL;
2771 }
2772
2773
2774 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2775                        char *buf,unsigned int cnt)
2776 {
2777         int ret = -EINVAL;
2778         LOCK_TAKE(hdw->big_lock); do {
2779                 if (!buf) break;
2780                 if (!cnt) break;
2781
2782                 if (!hdw->fw_buffer) {
2783                         ret = -EIO;
2784                         break;
2785                 }
2786
2787                 if (offs >= hdw->fw_size) {
2788                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2789                                    "Read firmware data offs=%d EOF",
2790                                    offs);
2791                         ret = 0;
2792                         break;
2793                 }
2794
2795                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2796
2797                 memcpy(buf,hdw->fw_buffer+offs,cnt);
2798
2799                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2800                            "Read firmware data offs=%d cnt=%d",
2801                            offs,cnt);
2802                 ret = cnt;
2803         } while (0); LOCK_GIVE(hdw->big_lock);
2804
2805         return ret;
2806 }
2807
2808
2809 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
2810                                   enum pvr2_v4l_type index)
2811 {
2812         switch (index) {
2813         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
2814         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
2815         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
2816         default: return -1;
2817         }
2818 }
2819
2820
2821 /* Store a v4l minor device number */
2822 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
2823                                      enum pvr2_v4l_type index,int v)
2824 {
2825         switch (index) {
2826         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
2827         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
2828         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
2829         default: break;
2830         }
2831 }
2832
2833
2834 static void pvr2_ctl_write_complete(struct urb *urb)
2835 {
2836         struct pvr2_hdw *hdw = urb->context;
2837         hdw->ctl_write_pend_flag = 0;
2838         if (hdw->ctl_read_pend_flag) return;
2839         complete(&hdw->ctl_done);
2840 }
2841
2842
2843 static void pvr2_ctl_read_complete(struct urb *urb)
2844 {
2845         struct pvr2_hdw *hdw = urb->context;
2846         hdw->ctl_read_pend_flag = 0;
2847         if (hdw->ctl_write_pend_flag) return;
2848         complete(&hdw->ctl_done);
2849 }
2850
2851
2852 static void pvr2_ctl_timeout(unsigned long data)
2853 {
2854         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2855         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2856                 hdw->ctl_timeout_flag = !0;
2857                 if (hdw->ctl_write_pend_flag)
2858                         usb_unlink_urb(hdw->ctl_write_urb);
2859                 if (hdw->ctl_read_pend_flag)
2860                         usb_unlink_urb(hdw->ctl_read_urb);
2861         }
2862 }
2863
2864
2865 /* Issue a command and get a response from the device.  This extended
2866    version includes a probe flag (which if set means that device errors
2867    should not be logged or treated as fatal) and a timeout in jiffies.
2868    This can be used to non-lethally probe the health of endpoint 1. */
2869 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2870                                 unsigned int timeout,int probe_fl,
2871                                 void *write_data,unsigned int write_len,
2872                                 void *read_data,unsigned int read_len)
2873 {
2874         unsigned int idx;
2875         int status = 0;
2876         struct timer_list timer;
2877         if (!hdw->ctl_lock_held) {
2878                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2879                            "Attempted to execute control transfer"
2880                            " without lock!!");
2881                 return -EDEADLK;
2882         }
2883         if (!hdw->flag_ok && !probe_fl) {
2884                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2885                            "Attempted to execute control transfer"
2886                            " when device not ok");
2887                 return -EIO;
2888         }
2889         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2890                 if (!probe_fl) {
2891                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2892                                    "Attempted to execute control transfer"
2893                                    " when USB is disconnected");
2894                 }
2895                 return -ENOTTY;
2896         }
2897
2898         /* Ensure that we have sane parameters */
2899         if (!write_data) write_len = 0;
2900         if (!read_data) read_len = 0;
2901         if (write_len > PVR2_CTL_BUFFSIZE) {
2902                 pvr2_trace(
2903                         PVR2_TRACE_ERROR_LEGS,
2904                         "Attempted to execute %d byte"
2905                         " control-write transfer (limit=%d)",
2906                         write_len,PVR2_CTL_BUFFSIZE);
2907                 return -EINVAL;
2908         }
2909         if (read_len > PVR2_CTL_BUFFSIZE) {
2910                 pvr2_trace(
2911                         PVR2_TRACE_ERROR_LEGS,
2912                         "Attempted to execute %d byte"
2913                         " control-read transfer (limit=%d)",
2914                         write_len,PVR2_CTL_BUFFSIZE);
2915                 return -EINVAL;
2916         }
2917         if ((!write_len) && (!read_len)) {
2918                 pvr2_trace(
2919                         PVR2_TRACE_ERROR_LEGS,
2920                         "Attempted to execute null control transfer?");
2921                 return -EINVAL;
2922         }
2923
2924
2925         hdw->cmd_debug_state = 1;
2926         if (write_len) {
2927                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2928         } else {
2929                 hdw->cmd_debug_code = 0;
2930         }
2931         hdw->cmd_debug_write_len = write_len;
2932         hdw->cmd_debug_read_len = read_len;
2933
2934         /* Initialize common stuff */
2935         init_completion(&hdw->ctl_done);
2936         hdw->ctl_timeout_flag = 0;
2937         hdw->ctl_write_pend_flag = 0;
2938         hdw->ctl_read_pend_flag = 0;
2939         init_timer(&timer);
2940         timer.expires = jiffies + timeout;
2941         timer.data = (unsigned long)hdw;
2942         timer.function = pvr2_ctl_timeout;
2943
2944         if (write_len) {
2945                 hdw->cmd_debug_state = 2;
2946                 /* Transfer write data to internal buffer */
2947                 for (idx = 0; idx < write_len; idx++) {
2948                         hdw->ctl_write_buffer[idx] =
2949                                 ((unsigned char *)write_data)[idx];
2950                 }
2951                 /* Initiate a write request */
2952                 usb_fill_bulk_urb(hdw->ctl_write_urb,
2953                                   hdw->usb_dev,
2954                                   usb_sndbulkpipe(hdw->usb_dev,
2955                                                   PVR2_CTL_WRITE_ENDPOINT),
2956                                   hdw->ctl_write_buffer,
2957                                   write_len,
2958                                   pvr2_ctl_write_complete,
2959                                   hdw);
2960                 hdw->ctl_write_urb->actual_length = 0;
2961                 hdw->ctl_write_pend_flag = !0;
2962                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2963                 if (status < 0) {
2964                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2965                                    "Failed to submit write-control"
2966                                    " URB status=%d",status);
2967                         hdw->ctl_write_pend_flag = 0;
2968                         goto done;
2969                 }
2970         }
2971
2972         if (read_len) {
2973                 hdw->cmd_debug_state = 3;
2974                 memset(hdw->ctl_read_buffer,0x43,read_len);
2975                 /* Initiate a read request */
2976                 usb_fill_bulk_urb(hdw->ctl_read_urb,
2977                                   hdw->usb_dev,
2978                                   usb_rcvbulkpipe(hdw->usb_dev,
2979                                                   PVR2_CTL_READ_ENDPOINT),
2980                                   hdw->ctl_read_buffer,
2981                                   read_len,
2982                                   pvr2_ctl_read_complete,
2983                                   hdw);
2984                 hdw->ctl_read_urb->actual_length = 0;
2985                 hdw->ctl_read_pend_flag = !0;
2986                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
2987                 if (status < 0) {
2988                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2989                                    "Failed to submit read-control"
2990                                    " URB status=%d",status);
2991                         hdw->ctl_read_pend_flag = 0;
2992                         goto done;
2993                 }
2994         }
2995
2996         /* Start timer */
2997         add_timer(&timer);
2998
2999         /* Now wait for all I/O to complete */
3000         hdw->cmd_debug_state = 4;
3001         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3002                 wait_for_completion(&hdw->ctl_done);
3003         }
3004         hdw->cmd_debug_state = 5;
3005
3006         /* Stop timer */
3007         del_timer_sync(&timer);
3008
3009         hdw->cmd_debug_state = 6;
3010         status = 0;
3011
3012         if (hdw->ctl_timeout_flag) {
3013                 status = -ETIMEDOUT;
3014                 if (!probe_fl) {
3015                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3016                                    "Timed out control-write");
3017                 }
3018                 goto done;
3019         }
3020
3021         if (write_len) {
3022                 /* Validate results of write request */
3023                 if ((hdw->ctl_write_urb->status != 0) &&
3024                     (hdw->ctl_write_urb->status != -ENOENT) &&
3025                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3026                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
3027                         /* USB subsystem is reporting some kind of failure
3028                            on the write */
3029                         status = hdw->ctl_write_urb->status;
3030                         if (!probe_fl) {
3031                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3032                                            "control-write URB failure,"
3033                                            " status=%d",
3034                                            status);
3035                         }
3036                         goto done;
3037                 }
3038                 if (hdw->ctl_write_urb->actual_length < write_len) {
3039                         /* Failed to write enough data */
3040                         status = -EIO;
3041                         if (!probe_fl) {
3042                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3043                                            "control-write URB short,"
3044                                            " expected=%d got=%d",
3045                                            write_len,
3046                                            hdw->ctl_write_urb->actual_length);
3047                         }
3048                         goto done;
3049                 }
3050         }
3051         if (read_len) {
3052                 /* Validate results of read request */
3053                 if ((hdw->ctl_read_urb->status != 0) &&
3054                     (hdw->ctl_read_urb->status != -ENOENT) &&
3055                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3056                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3057                         /* USB subsystem is reporting some kind of failure
3058                            on the read */
3059                         status = hdw->ctl_read_urb->status;
3060                         if (!probe_fl) {
3061                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3062                                            "control-read URB failure,"
3063                                            " status=%d",
3064                                            status);
3065                         }
3066                         goto done;
3067                 }
3068                 if (hdw->ctl_read_urb->actual_length < read_len) {
3069                         /* Failed to read enough data */
3070                         status = -EIO;
3071                         if (!probe_fl) {
3072                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3073                                            "control-read URB short,"
3074                                            " expected=%d got=%d",
3075                                            read_len,
3076                                            hdw->ctl_read_urb->actual_length);
3077                         }
3078                         goto done;
3079                 }
3080                 /* Transfer retrieved data out from internal buffer */
3081                 for (idx = 0; idx < read_len; idx++) {
3082                         ((unsigned char *)read_data)[idx] =
3083                                 hdw->ctl_read_buffer[idx];
3084                 }
3085         }
3086
3087  done:
3088
3089         hdw->cmd_debug_state = 0;
3090         if ((status < 0) && (!probe_fl)) {
3091                 pvr2_hdw_render_useless(hdw);
3092         }
3093         return status;
3094 }
3095
3096
3097 int pvr2_send_request(struct pvr2_hdw *hdw,
3098                       void *write_data,unsigned int write_len,
3099                       void *read_data,unsigned int read_len)
3100 {
3101         return pvr2_send_request_ex(hdw,HZ*4,0,
3102                                     write_data,write_len,
3103                                     read_data,read_len);
3104 }
3105
3106 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3107 {
3108         int ret;
3109
3110         LOCK_TAKE(hdw->ctl_lock);
3111
3112         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3113         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3114         hdw->cmd_buffer[5] = 0;
3115         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3116         hdw->cmd_buffer[7] = reg & 0xff;
3117
3118
3119         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3120
3121         LOCK_GIVE(hdw->ctl_lock);
3122
3123         return ret;
3124 }
3125
3126
3127 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3128 {
3129         int ret = 0;
3130
3131         LOCK_TAKE(hdw->ctl_lock);
3132
3133         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3134         hdw->cmd_buffer[1] = 0;
3135         hdw->cmd_buffer[2] = 0;
3136         hdw->cmd_buffer[3] = 0;
3137         hdw->cmd_buffer[4] = 0;
3138         hdw->cmd_buffer[5] = 0;
3139         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3140         hdw->cmd_buffer[7] = reg & 0xff;
3141
3142         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3143         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3144
3145         LOCK_GIVE(hdw->ctl_lock);
3146
3147         return ret;
3148 }
3149
3150
3151 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3152 {
3153         if (!hdw->flag_ok) return;
3154         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3155                    "Device being rendered inoperable");
3156         if (hdw->vid_stream) {
3157                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3158         }
3159         hdw->flag_ok = 0;
3160         trace_stbit("flag_ok",hdw->flag_ok);
3161         pvr2_hdw_state_sched(hdw);
3162 }
3163
3164
3165 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3166 {
3167         int ret;
3168         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3169         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3170         if (ret == 1) {
3171                 ret = usb_reset_device(hdw->usb_dev);
3172                 usb_unlock_device(hdw->usb_dev);
3173         } else {
3174                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3175                            "Failed to lock USB device ret=%d",ret);
3176         }
3177         if (init_pause_msec) {
3178                 pvr2_trace(PVR2_TRACE_INFO,
3179                            "Waiting %u msec for hardware to settle",
3180                            init_pause_msec);
3181                 msleep(init_pause_msec);
3182         }
3183
3184 }
3185
3186
3187 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3188 {
3189         char da[1];
3190         unsigned int pipe;
3191         int ret;
3192
3193         if (!hdw->usb_dev) return;
3194
3195         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3196
3197         da[0] = val ? 0x01 : 0x00;
3198
3199         /* Write the CPUCS register on the 8051.  The lsb of the register
3200            is the reset bit; a 1 asserts reset while a 0 clears it. */
3201         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3202         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3203         if (ret < 0) {
3204                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3205                            "cpureset_assert(%d) error=%d",val,ret);
3206                 pvr2_hdw_render_useless(hdw);
3207         }
3208 }
3209
3210
3211 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3212 {
3213         int status;
3214         LOCK_TAKE(hdw->ctl_lock); do {
3215                 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
3216                 hdw->cmd_buffer[0] = FX2CMD_DEEP_RESET;
3217                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
3218         } while (0); LOCK_GIVE(hdw->ctl_lock);
3219         return status;
3220 }
3221
3222
3223 static int pvr2_hdw_cmd_power_ctrl(struct pvr2_hdw *hdw, int onoff)
3224 {
3225         int status;
3226         LOCK_TAKE(hdw->ctl_lock); do {
3227                 if (onoff) {
3228                         pvr2_trace(PVR2_TRACE_INIT, "Requesting powerup");
3229                         hdw->cmd_buffer[0] = FX2CMD_POWER_ON;
3230                 } else {
3231                         pvr2_trace(PVR2_TRACE_INIT, "Requesting powerdown");
3232                         hdw->cmd_buffer[0] = FX2CMD_POWER_OFF;
3233                 }
3234                 status = pvr2_send_request(hdw, hdw->cmd_buffer, 1, NULL, 0);
3235         } while (0); LOCK_GIVE(hdw->ctl_lock);
3236         return status;
3237 }
3238
3239 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3240 {
3241         return pvr2_hdw_cmd_power_ctrl(hdw, 1);
3242 }
3243
3244 int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
3245 {
3246         return pvr2_hdw_cmd_power_ctrl(hdw, 0);
3247 }
3248
3249
3250 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3251 {
3252         if (!hdw->decoder_ctrl) {
3253                 pvr2_trace(PVR2_TRACE_INIT,
3254                            "Unable to reset decoder: nothing attached");
3255                 return -ENOTTY;
3256         }
3257
3258         if (!hdw->decoder_ctrl->force_reset) {
3259                 pvr2_trace(PVR2_TRACE_INIT,
3260                            "Unable to reset decoder: not implemented");
3261                 return -ENOTTY;
3262         }
3263
3264         pvr2_trace(PVR2_TRACE_INIT,
3265                    "Requesting decoder reset");
3266         hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3267         return 0;
3268 }
3269
3270
3271 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
3272 {
3273         int status;
3274
3275         LOCK_TAKE(hdw->ctl_lock); do {
3276                 pvr2_trace(PVR2_TRACE_INIT,
3277                            "Issuing fe demod wake command (%s)",
3278                            (onoff ? "on" : "off"));
3279                 hdw->flag_ok = !0;
3280                 hdw->cmd_buffer[0] = FX2CMD_HCW_DEMOD_RESETIN;
3281                 hdw->cmd_buffer[1] = onoff;
3282                 status = pvr2_send_request(hdw, hdw->cmd_buffer, 2, NULL, 0);
3283         } while (0); LOCK_GIVE(hdw->ctl_lock);
3284
3285         return status;
3286 }
3287
3288
3289 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
3290 {
3291         int status;
3292
3293         LOCK_TAKE(hdw->ctl_lock); do {
3294                 pvr2_trace(PVR2_TRACE_INIT,
3295                            "Issuing fe power command to CPLD (%s)",
3296                            (onoff ? "on" : "off"));
3297                 hdw->flag_ok = !0;
3298                 hdw->cmd_buffer[0] =
3299                         (onoff ? FX2CMD_ONAIR_DTV_POWER_ON :
3300                                  FX2CMD_ONAIR_DTV_POWER_OFF);
3301                 status = pvr2_send_request(hdw, hdw->cmd_buffer, 1, NULL, 0);
3302         } while (0); LOCK_GIVE(hdw->ctl_lock);
3303
3304         return status;
3305 }
3306
3307
3308 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
3309                                                 int onoff)
3310 {
3311         int status;
3312         LOCK_TAKE(hdw->ctl_lock); do {
3313                 pvr2_trace(PVR2_TRACE_INIT,
3314                            "Issuing onair digital setup command (%s)",
3315                            (onoff ? "on" : "off"));
3316                 hdw->cmd_buffer[0] =
3317                         (onoff ? FX2CMD_ONAIR_DTV_STREAMING_ON :
3318                                  FX2CMD_ONAIR_DTV_STREAMING_OFF);
3319                 status = pvr2_send_request(hdw, hdw->cmd_buffer, 1, NULL, 0);
3320         } while (0); LOCK_GIVE(hdw->ctl_lock);
3321         return status;
3322 }
3323
3324
3325 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
3326 {
3327         int cmode;
3328         /* Compare digital/analog desired setting with current setting.  If
3329            they don't match, fix it... */
3330         cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
3331         if (cmode == hdw->pathway_state) {
3332                 /* They match; nothing to do */
3333                 return;
3334         }
3335
3336         switch (hdw->hdw_desc->digital_control_scheme) {
3337         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
3338                 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
3339                 if (cmode == PVR2_PATHWAY_ANALOG) {
3340                         /* If moving to analog mode, also force the decoder
3341                            to reset.  If no decoder is attached, then it's
3342                            ok to ignore this because if/when the decoder
3343                            attaches, it will reset itself at that time. */
3344                         pvr2_hdw_cmd_decoder_reset(hdw);
3345                 }
3346                 break;
3347         case PVR2_DIGITAL_SCHEME_ONAIR:
3348                 /* Supposedly we should always have the power on whether in
3349                    digital or analog mode.  But for now do what appears to
3350                    work... */
3351                 if (digitalFl) pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,!0);
3352                 pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,digitalFl);
3353                 if (!digitalFl) pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,0);
3354                 break;
3355         default: break;
3356         }
3357
3358         pvr2_hdw_untrip_unlocked(hdw);
3359         hdw->pathway_state = cmode;
3360 }
3361
3362
3363 void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
3364 {
3365         /* change some GPIO data
3366          *
3367          * note: bit d7 of dir appears to control the LED,
3368          * so we shut it off here.
3369          *
3370          */
3371         if (onoff) {
3372                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
3373         } else {
3374                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
3375         }
3376         pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
3377 }
3378
3379
3380 typedef void (*led_method_func)(struct pvr2_hdw *,int);
3381
3382 static led_method_func led_methods[] = {
3383         [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
3384 };
3385
3386
3387 /* Toggle LED */
3388 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
3389 {
3390         unsigned int scheme_id;
3391         led_method_func fp;
3392
3393         if ((!onoff) == (!hdw->led_on)) return;
3394
3395         hdw->led_on = onoff != 0;
3396
3397         scheme_id = hdw->hdw_desc->led_scheme;
3398         if (scheme_id < ARRAY_SIZE(led_methods)) {
3399                 fp = led_methods[scheme_id];
3400         } else {
3401                 fp = NULL;
3402         }
3403
3404         if (fp) (*fp)(hdw,onoff);
3405 }
3406
3407
3408 /* Stop / start video stream transport */
3409 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
3410 {
3411         int status,cc;
3412         if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
3413             hdw->hdw_desc->digital_control_scheme ==
3414             PVR2_DIGITAL_SCHEME_HAUPPAUGE) {
3415                 cc = (runFl ?
3416                       FX2CMD_HCW_DTV_STREAMING_ON :
3417                       FX2CMD_HCW_DTV_STREAMING_OFF);
3418         } else {
3419                 cc = (runFl ?
3420                       FX2CMD_STREAMING_ON :
3421                       FX2CMD_STREAMING_OFF);
3422         }
3423
3424         LOCK_TAKE(hdw->ctl_lock); do {
3425                 hdw->cmd_buffer[0] = cc;
3426                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
3427         } while (0); LOCK_GIVE(hdw->ctl_lock);
3428         return status;
3429 }
3430
3431
3432 /* Evaluate whether or not state_pathway_ok can change */
3433 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
3434 {
3435         if (hdw->state_pathway_ok) {
3436                 /* Nothing to do if pathway is already ok */
3437                 return 0;
3438         }
3439         if (!hdw->state_pipeline_idle) {
3440                 /* Not allowed to change anything if pipeline is not idle */
3441                 return 0;
3442         }
3443         pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
3444         hdw->state_pathway_ok = !0;
3445         trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
3446         return !0;
3447 }
3448
3449
3450 /* Evaluate whether or not state_encoder_ok can change */
3451 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
3452 {
3453         if (hdw->state_encoder_ok) return 0;
3454         if (hdw->flag_tripped) return 0;
3455         if (hdw->state_encoder_run) return 0;
3456         if (hdw->state_encoder_config) return 0;
3457         if (hdw->state_decoder_run) return 0;
3458         if (hdw->state_usbstream_run) return 0;
3459         if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) return 0;
3460         if (pvr2_upload_firmware2(hdw) < 0) {
3461                 hdw->flag_tripped = !0;
3462                 trace_stbit("flag_tripped",hdw->flag_tripped);
3463                 return !0;
3464         }
3465         hdw->state_encoder_ok = !0;
3466         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
3467         return !0;
3468 }
3469
3470
3471 /* Evaluate whether or not state_encoder_config can change */
3472 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
3473 {
3474         if (hdw->state_encoder_config) {
3475                 if (hdw->state_encoder_ok) {
3476                         if (hdw->state_pipeline_req &&
3477                             !hdw->state_pipeline_pause) return 0;
3478                 }
3479                 hdw->state_encoder_config = 0;
3480                 hdw->state_encoder_waitok = 0;
3481                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3482                 /* paranoia - solve race if timer just completed */
3483                 del_timer_sync(&hdw->encoder_wait_timer);
3484         } else {
3485                 if (!hdw->state_pathway_ok ||
3486                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
3487                     !hdw->state_encoder_ok ||
3488                     !hdw->state_pipeline_idle ||
3489                     hdw->state_pipeline_pause ||
3490                     !hdw->state_pipeline_req ||
3491                     !hdw->state_pipeline_config) {
3492                         /* We must reset the enforced wait interval if
3493                            anything has happened that might have disturbed
3494                            the encoder.  This should be a rare case. */
3495                         if (timer_pending(&hdw->encoder_wait_timer)) {
3496                                 del_timer_sync(&hdw->encoder_wait_timer);
3497                         }
3498                         if (hdw->state_encoder_waitok) {
3499                                 /* Must clear the state - therefore we did
3500                                    something to a state bit and must also
3501                                    return true. */
3502                                 hdw->state_encoder_waitok = 0;
3503                                 trace_stbit("state_encoder_waitok",
3504                                             hdw->state_encoder_waitok);
3505                                 return !0;
3506                         }
3507                         return 0;
3508                 }
3509                 if (!hdw->state_encoder_waitok) {
3510                         if (!timer_pending(&hdw->encoder_wait_timer)) {
3511                                 /* waitok flag wasn't set and timer isn't
3512                                    running.  Check flag once more to avoid
3513                                    a race then start the timer.  This is
3514                                    the point when we measure out a minimal
3515                                    quiet interval before doing something to
3516                                    the encoder. */
3517                                 if (!hdw->state_encoder_waitok) {
3518                                         hdw->encoder_wait_timer.expires =
3519                                                 jiffies + (HZ*50/1000);
3520                                         add_timer(&hdw->encoder_wait_timer);
3521                                 }
3522                         }
3523                         /* We can't continue until we know we have been
3524                            quiet for the interval measured by this
3525                            timer. */
3526                         return 0;
3527                 }
3528                 pvr2_encoder_configure(hdw);
3529                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
3530         }
3531         trace_stbit("state_encoder_config",hdw->state_encoder_config);
3532         return !0;
3533 }
3534
3535
3536 /* Evaluate whether or not state_encoder_run can change */
3537 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
3538 {
3539         if (hdw->state_encoder_run) {
3540                 if (hdw->state_encoder_ok) {
3541                         if (hdw->state_decoder_run &&
3542                             hdw->state_pathway_ok) return 0;
3543                         if (pvr2_encoder_stop(hdw) < 0) return !0;
3544                 }
3545                 hdw->state_encoder_run = 0;
3546         } else {
3547                 if (!hdw->state_encoder_ok) return 0;
3548                 if (!hdw->state_decoder_run) return 0;
3549                 if (!hdw->state_pathway_ok) return 0;
3550                 if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) return 0;
3551                 if (pvr2_encoder_start(hdw) < 0) return !0;
3552                 hdw->state_encoder_run = !0;
3553         }
3554         trace_stbit("state_encoder_run",hdw->state_encoder_run);
3555         return !0;
3556 }
3557
3558
3559 /* Timeout function for quiescent timer. */
3560 static void pvr2_hdw_quiescent_timeout(unsigned long data)
3561 {
3562         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3563         hdw->state_decoder_quiescent = !0;
3564         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3565         hdw->state_stale = !0;
3566         queue_work(hdw->workqueue,&hdw->workpoll);
3567 }
3568
3569
3570 /* Timeout function for encoder wait timer. */
3571 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
3572 {
3573         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3574         hdw->state_encoder_waitok = !0;
3575         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3576         hdw->state_stale = !0;
3577         queue_work(hdw->workqueue,&hdw->workpoll);
3578 }
3579
3580
3581 /* Evaluate whether or not state_decoder_run can change */
3582 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
3583 {
3584         if (hdw->state_decoder_run) {
3585                 if (hdw->state_encoder_ok) {
3586                         if (hdw->state_pipeline_req &&
3587                             !hdw->state_pipeline_pause &&
3588                             hdw->state_pathway_ok) return 0;
3589                 }
3590                 if (!hdw->flag_decoder_missed) {
3591                         pvr2_decoder_enable(hdw,0);
3592                 }
3593                 hdw->state_decoder_quiescent = 0;
3594                 hdw->state_decoder_run = 0;
3595                 /* paranoia - solve race if timer just completed */
3596                 del_timer_sync(&hdw->quiescent_timer);
3597         } else {
3598                 if (!hdw->state_decoder_quiescent) {
3599                         if (!timer_pending(&hdw->quiescent_timer)) {
3600                                 /* We don't do something about the
3601                                    quiescent timer until right here because
3602                                    we also want to catch cases where the
3603                                    decoder was already not running (like
3604                                    after initialization) as opposed to
3605                                    knowing that we had just stopped it.
3606                                    The second flag check is here to cover a
3607                                    race - the timer could have run and set
3608                                    this flag just after the previous check
3609                                    but before we did the pending check. */
3610                                 if (!hdw->state_decoder_quiescent) {
3611                                         hdw->quiescent_timer.expires =
3612                                                 jiffies + (HZ*50/1000);
3613                                         add_timer(&hdw->quiescent_timer);
3614                                 }
3615                         }
3616                         /* Don't allow decoder to start again until it has
3617                            been quiesced first.  This little detail should
3618                            hopefully further stabilize the encoder. */
3619                         return 0;
3620                 }
3621                 if (!hdw->state_pathway_ok ||
3622                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
3623                     !hdw->state_pipeline_req ||
3624                     hdw->state_pipeline_pause ||
3625                     !hdw->state_pipeline_config ||
3626                     !hdw->state_encoder_config ||
3627                     !hdw->state_encoder_ok) return 0;
3628                 del_timer_sync(&hdw->quiescent_timer);
3629                 if (hdw->flag_decoder_missed) return 0;
3630                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
3631                 hdw->state_decoder_quiescent = 0;
3632                 hdw->state_decoder_run = !0;
3633         }
3634         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3635         trace_stbit("state_decoder_run",hdw->state_decoder_run);
3636         return !0;
3637 }
3638
3639
3640 /* Evaluate whether or not state_usbstream_run can change */
3641 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
3642 {
3643         if (hdw->state_usbstream_run) {
3644                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
3645                         if (hdw->state_encoder_ok &&
3646                             hdw->state_encoder_run &&
3647                             hdw->state_pathway_ok) return 0;
3648                 } else {
3649                         if (hdw->state_pipeline_req &&
3650                             !hdw->state_pipeline_pause &&
3651                             hdw->state_pathway_ok) return 0;
3652                 }
3653                 pvr2_hdw_cmd_usbstream(hdw,0);
3654                 hdw->state_usbstream_run = 0;
3655         } else {
3656                 if (!hdw->state_pipeline_req ||
3657                     hdw->state_pipeline_pause ||
3658                     !hdw->state_pathway_ok) return 0;
3659                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
3660                         if (!hdw->state_encoder_ok ||
3661                             !hdw->state_encoder_run) return 0;
3662                 }
3663                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
3664                 hdw->state_usbstream_run = !0;
3665         }
3666         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
3667         return !0;
3668 }
3669
3670
3671 /* Attempt to configure pipeline, if needed */
3672 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
3673 {
3674         if (hdw->state_pipeline_config ||
3675             hdw->state_pipeline_pause) return 0;
3676         pvr2_hdw_commit_execute(hdw);
3677         return !0;
3678 }
3679
3680
3681 /* Update pipeline idle and pipeline pause tracking states based on other
3682    inputs.  This must be called whenever the other relevant inputs have
3683    changed. */
3684 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
3685 {
3686         unsigned int st;
3687         int updatedFl = 0;
3688         /* Update pipeline state */
3689         st = !(hdw->state_encoder_run ||
3690                hdw->state_decoder_run ||
3691                hdw->state_usbstream_run ||
3692                (!hdw->state_decoder_quiescent));
3693         if (!st != !hdw->state_pipeline_idle) {
3694                 hdw->state_pipeline_idle = st;
3695                 updatedFl = !0;
3696         }
3697         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
3698                 hdw->state_pipeline_pause = 0;
3699                 updatedFl = !0;
3700         }
3701         return updatedFl;
3702 }
3703
3704
3705 typedef int (*state_eval_func)(struct pvr2_hdw *);
3706
3707 /* Set of functions to be run to evaluate various states in the driver. */
3708 const static state_eval_func eval_funcs[] = {
3709         state_eval_pathway_ok,
3710         state_eval_pipeline_config,
3711         state_eval_encoder_ok,
3712         state_eval_encoder_config,
3713         state_eval_decoder_run,
3714         state_eval_encoder_run,
3715         state_eval_usbstream_run,
3716 };
3717
3718
3719 /* Process various states and return true if we did anything interesting. */
3720 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
3721 {
3722         unsigned int i;
3723         int state_updated = 0;
3724         int check_flag;
3725
3726         if (!hdw->state_stale) return 0;
3727         if ((hdw->fw1_state != FW1_STATE_OK) ||
3728             !hdw->flag_ok) {
3729                 hdw->state_stale = 0;
3730                 return !0;
3731         }
3732         /* This loop is the heart of the entire driver.  It keeps trying to
3733            evaluate various bits of driver state until nothing changes for
3734            one full iteration.  Each "bit of state" tracks some global
3735            aspect of the driver, e.g. whether decoder should run, if
3736            pipeline is configured, usb streaming is on, etc.  We separately
3737            evaluate each of those questions based on other driver state to
3738            arrive at the correct running configuration. */
3739         do {
3740                 check_flag = 0;
3741                 state_update_pipeline_state(hdw);
3742                 /* Iterate over each bit of state */
3743                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
3744                         if ((*eval_funcs[i])(hdw)) {
3745                                 check_flag = !0;
3746                                 state_updated = !0;
3747                                 state_update_pipeline_state(hdw);
3748                         }
3749                 }
3750         } while (check_flag && hdw->flag_ok);
3751         hdw->state_stale = 0;
3752         trace_stbit("state_stale",hdw->state_stale);
3753         return state_updated;
3754 }
3755
3756
3757 static const char *pvr2_pathway_state_name(int id)
3758 {
3759         switch (id) {
3760         case PVR2_PATHWAY_ANALOG: return "analog";
3761         case PVR2_PATHWAY_DIGITAL: return "digital";
3762         default: return "unknown";
3763         }
3764 }
3765
3766
3767 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
3768                                              char *buf,unsigned int acnt)
3769 {
3770         switch (which) {
3771         case 0:
3772                 return scnprintf(
3773                         buf,acnt,
3774                         "driver:%s%s%s%s%s <mode=%s>",
3775                         (hdw->flag_ok ? " <ok>" : " <fail>"),
3776                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
3777                         (hdw->flag_disconnected ? " <disconnected>" :
3778                          " <connected>"),
3779                         (hdw->flag_tripped ? " <tripped>" : ""),
3780                         (hdw->flag_decoder_missed ? " <no decoder>" : ""),
3781                         pvr2_pathway_state_name(hdw->pathway_state));
3782
3783         case 1:
3784                 return scnprintf(
3785                         buf,acnt,
3786                         "pipeline:%s%s%s%s",
3787                         (hdw->state_pipeline_idle ? " <idle>" : ""),
3788                         (hdw->state_pipeline_config ?
3789                          " <configok>" : " <stale>"),
3790                         (hdw->state_pipeline_req ? " <req>" : ""),
3791                         (hdw->state_pipeline_pause ? " <pause>" : ""));
3792         case 2:
3793                 return scnprintf(
3794                         buf,acnt,
3795                         "worker:%s%s%s%s%s%s%s",
3796                         (hdw->state_decoder_run ?
3797                          " <decode:run>" :
3798                          (hdw->state_decoder_quiescent ?
3799                           "" : " <decode:stop>")),
3800                         (hdw->state_decoder_quiescent ?
3801                          " <decode:quiescent>" : ""),
3802                         (hdw->state_encoder_ok ?
3803                          "" : " <encode:init>"),
3804                         (hdw->state_encoder_run ?
3805                          " <encode:run>" : " <encode:stop>"),
3806                         (hdw->state_encoder_config ?
3807                          " <encode:configok>" :
3808                          (hdw->state_encoder_waitok ?
3809                           "" : " <encode:wait>")),
3810                         (hdw->state_usbstream_run ?
3811                          " <usb:run>" : " <usb:stop>"),
3812                         (hdw->state_pathway_ok ?
3813                          " <pathway:ok>" : ""));
3814                 break;
3815         case 3:
3816                 return scnprintf(
3817                         buf,acnt,
3818                         "state: %s",
3819                         pvr2_get_state_name(hdw->master_state));
3820                 break;
3821         default: break;
3822         }
3823         return 0;
3824 }
3825
3826
3827 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
3828                                    char *buf,unsigned int acnt)
3829 {
3830         unsigned int bcnt,ccnt,idx;
3831         bcnt = 0;
3832         LOCK_TAKE(hdw->big_lock);
3833         for (idx = 0; ; idx++) {
3834                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
3835                 if (!ccnt) break;
3836                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
3837                 if (!acnt) break;
3838                 buf[0] = '\n'; ccnt = 1;
3839                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
3840         }
3841         LOCK_GIVE(hdw->big_lock);
3842         return bcnt;
3843 }
3844
3845
3846 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
3847 {
3848         char buf[128];
3849         unsigned int idx,ccnt;
3850
3851         for (idx = 0; ; idx++) {
3852                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
3853                 if (!ccnt) break;
3854                 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
3855         }
3856 }
3857
3858
3859 /* Evaluate and update the driver's current state, taking various actions
3860    as appropriate for the update. */
3861 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
3862 {
3863         unsigned int st;
3864         int state_updated = 0;
3865         int callback_flag = 0;
3866         int analog_mode;
3867
3868         pvr2_trace(PVR2_TRACE_STBITS,
3869                    "Drive state check START");
3870         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
3871                 pvr2_hdw_state_log_state(hdw);
3872         }
3873
3874         /* Process all state and get back over disposition */
3875         state_updated = pvr2_hdw_state_update(hdw);
3876
3877         analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
3878
3879         /* Update master state based upon all other states. */
3880         if (!hdw->flag_ok) {
3881                 st = PVR2_STATE_DEAD;
3882         } else if (hdw->fw1_state != FW1_STATE_OK) {
3883                 st = PVR2_STATE_COLD;
3884         } else if (analog_mode && !hdw->state_encoder_ok) {
3885                 st = PVR2_STATE_WARM;
3886         } else if (hdw->flag_tripped ||
3887                    (analog_mode && hdw->flag_decoder_missed)) {
3888                 st = PVR2_STATE_ERROR;
3889         } else if (hdw->state_usbstream_run &&
3890                    (!analog_mode ||
3891                     (hdw->state_encoder_run && hdw->state_decoder_run))) {
3892                 st = PVR2_STATE_RUN;
3893         } else {
3894                 st = PVR2_STATE_READY;
3895         }
3896         if (hdw->master_state != st) {
3897                 pvr2_trace(PVR2_TRACE_STATE,
3898                            "Device state change from %s to %s",
3899                            pvr2_get_state_name(hdw->master_state),
3900                            pvr2_get_state_name(st));
3901                 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
3902                 hdw->master_state = st;
3903                 state_updated = !0;
3904                 callback_flag = !0;
3905         }
3906         if (state_updated) {
3907                 /* Trigger anyone waiting on any state changes here. */
3908                 wake_up(&hdw->state_wait_data);
3909         }
3910
3911         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
3912                 pvr2_hdw_state_log_state(hdw);
3913         }
3914         pvr2_trace(PVR2_TRACE_STBITS,
3915                    "Drive state check DONE callback=%d",callback_flag);
3916
3917         return callback_flag;
3918 }
3919
3920
3921 /* Cause kernel thread to check / update driver state */
3922 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
3923 {
3924         if (hdw->state_stale) return;
3925         hdw->state_stale = !0;
3926         trace_stbit("state_stale",hdw->state_stale);
3927         queue_work(hdw->workqueue,&hdw->workpoll);
3928 }
3929
3930
3931 void pvr2_hdw_get_debug_info_unlocked(const struct pvr2_hdw *hdw,
3932                                       struct pvr2_hdw_debug_info *ptr)
3933 {
3934         ptr->big_lock_held = hdw->big_lock_held;
3935         ptr->ctl_lock_held = hdw->ctl_lock_held;
3936         ptr->flag_disconnected = hdw->flag_disconnected;
3937         ptr->flag_init_ok = hdw->flag_init_ok;
3938         ptr->flag_ok = hdw->flag_ok;
3939         ptr->fw1_state = hdw->fw1_state;
3940         ptr->flag_decoder_missed = hdw->flag_decoder_missed;
3941         ptr->flag_tripped = hdw->flag_tripped;
3942         ptr->state_encoder_ok = hdw->state_encoder_ok;
3943         ptr->state_encoder_run = hdw->state_encoder_run;
3944         ptr->state_decoder_run = hdw->state_decoder_run;
3945         ptr->state_usbstream_run = hdw->state_usbstream_run;
3946         ptr->state_decoder_quiescent = hdw->state_decoder_quiescent;
3947         ptr->state_pipeline_config = hdw->state_pipeline_config;
3948         ptr->state_pipeline_req = hdw->state_pipeline_req;
3949         ptr->state_pipeline_pause = hdw->state_pipeline_pause;
3950         ptr->state_pipeline_idle = hdw->state_pipeline_idle;
3951         ptr->cmd_debug_state = hdw->cmd_debug_state;
3952         ptr->cmd_code = hdw->cmd_debug_code;
3953         ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
3954         ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
3955         ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
3956         ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
3957         ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
3958         ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
3959         ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
3960 }
3961
3962
3963 void pvr2_hdw_get_debug_info_locked(struct pvr2_hdw *hdw,
3964                                     struct pvr2_hdw_debug_info *ptr)
3965 {
3966         LOCK_TAKE(hdw->ctl_lock); do {
3967                 pvr2_hdw_get_debug_info_unlocked(hdw,ptr);
3968         } while(0); LOCK_GIVE(hdw->ctl_lock);
3969 }
3970
3971
3972 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
3973 {
3974         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
3975 }
3976
3977
3978 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
3979 {
3980         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
3981 }
3982
3983
3984 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
3985 {
3986         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
3987 }
3988
3989
3990 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
3991 {
3992         u32 cval,nval;
3993         int ret;
3994         if (~msk) {
3995                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
3996                 if (ret) return ret;
3997                 nval = (cval & ~msk) | (val & msk);
3998                 pvr2_trace(PVR2_TRACE_GPIO,
3999                            "GPIO direction changing 0x%x:0x%x"
4000                            " from 0x%x to 0x%x",
4001                            msk,val,cval,nval);
4002         } else {
4003                 nval = val;
4004                 pvr2_trace(PVR2_TRACE_GPIO,
4005                            "GPIO direction changing to 0x%x",nval);
4006         }
4007         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
4008 }
4009
4010
4011 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
4012 {
4013         u32 cval,nval;
4014         int ret;
4015         if (~msk) {
4016                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
4017                 if (ret) return ret;
4018                 nval = (cval & ~msk) | (val & msk);
4019                 pvr2_trace(PVR2_TRACE_GPIO,
4020                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
4021                            msk,val,cval,nval);
4022         } else {
4023                 nval = val;
4024                 pvr2_trace(PVR2_TRACE_GPIO,
4025                            "GPIO output changing to 0x%x",nval);
4026         }
4027         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
4028 }
4029
4030
4031 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
4032 {
4033         return hdw->input_avail_mask;
4034 }
4035
4036
4037 /* Find I2C address of eeprom */
4038 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
4039 {
4040         int result;
4041         LOCK_TAKE(hdw->ctl_lock); do {
4042                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
4043                 result = pvr2_send_request(hdw,
4044                                            hdw->cmd_buffer,1,
4045                                            hdw->cmd_buffer,1);
4046                 if (result < 0) break;
4047                 result = hdw->cmd_buffer[0];
4048         } while(0); LOCK_GIVE(hdw->ctl_lock);
4049         return result;
4050 }
4051
4052
4053 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
4054                              u32 match_type, u32 match_chip, u64 reg_id,
4055                              int setFl,u64 *val_ptr)
4056 {
4057 #ifdef CONFIG_VIDEO_ADV_DEBUG
4058         struct pvr2_i2c_client *cp;
4059         struct v4l2_register req;
4060         int stat = 0;
4061         int okFl = 0;
4062
4063         if (!capable(CAP_SYS_ADMIN)) return -EPERM;
4064
4065         req.match_type = match_type;
4066         req.match_chip = match_chip;
4067         req.reg = reg_id;
4068         if (setFl) req.val = *val_ptr;
4069         mutex_lock(&hdw->i2c_list_lock); do {
4070                 list_for_each_entry(cp, &hdw->i2c_clients, list) {
4071                         if (!v4l2_chip_match_i2c_client(
4072                                     cp->client,
4073                                     req.match_type, req.match_chip)) {
4074                                 continue;
4075                         }
4076                         stat = pvr2_i2c_client_cmd(
4077                                 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
4078                                     VIDIOC_DBG_G_REGISTER),&req);
4079                         if (!setFl) *val_ptr = req.val;
4080                         okFl = !0;
4081                         break;
4082                 }
4083         } while (0); mutex_unlock(&hdw->i2c_list_lock);
4084         if (okFl) {
4085                 return stat;
4086         }
4087         return -EINVAL;
4088 #else
4089         return -ENOSYS;
4090 #endif
4091 }
4092
4093
4094 /*
4095   Stuff for Emacs to see, in order to encourage consistent editing style:
4096   *** Local Variables: ***
4097   *** mode: c ***
4098   *** fill-column: 75 ***
4099   *** tab-width: 8 ***
4100   *** c-basic-offset: 8 ***
4101   *** End: ***
4102   */