5 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/errno.h>
23 #include <linux/string.h>
24 #include <linux/slab.h>
25 #include <linux/firmware.h>
26 #include <linux/videodev2.h>
27 #include <media/v4l2-common.h>
29 #include "pvrusb2-std.h"
30 #include "pvrusb2-util.h"
31 #include "pvrusb2-hdw.h"
32 #include "pvrusb2-i2c-core.h"
33 #include "pvrusb2-tuner.h"
34 #include "pvrusb2-eeprom.h"
35 #include "pvrusb2-hdw-internal.h"
36 #include "pvrusb2-encoder.h"
37 #include "pvrusb2-debug.h"
38 #include "pvrusb2-fx2-cmd.h"
40 #define TV_MIN_FREQ 55250000L
41 #define TV_MAX_FREQ 850000000L
43 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
44 static DEFINE_MUTEX(pvr2_unit_mtx);
47 static int initusbreset = 1;
48 static int procreload;
49 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
50 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
51 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
52 static int init_pause_msec;
54 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
55 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
56 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
57 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
58 module_param(initusbreset, int, S_IRUGO|S_IWUSR);
59 MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
60 module_param(procreload, int, S_IRUGO|S_IWUSR);
61 MODULE_PARM_DESC(procreload,
62 "Attempt init failure recovery with firmware reload");
63 module_param_array(tuner, int, NULL, 0444);
64 MODULE_PARM_DESC(tuner,"specify installed tuner type");
65 module_param_array(video_std, int, NULL, 0444);
66 MODULE_PARM_DESC(video_std,"specify initial video standard");
67 module_param_array(tolerance, int, NULL, 0444);
68 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
70 #define PVR2_CTL_WRITE_ENDPOINT 0x01
71 #define PVR2_CTL_READ_ENDPOINT 0x81
73 #define PVR2_GPIO_IN 0x9008
74 #define PVR2_GPIO_OUT 0x900c
75 #define PVR2_GPIO_DIR 0x9020
77 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
79 #define PVR2_FIRMWARE_ENDPOINT 0x02
81 /* size of a firmware chunk */
82 #define FIRMWARE_CHUNK_SIZE 0x2000
84 /* Define the list of additional controls we'll dynamically construct based
85 on query of the cx2341x module. */
86 struct pvr2_mpeg_ids {
90 static const struct pvr2_mpeg_ids mpeg_ids[] = {
92 .strid = "audio_layer",
93 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
95 .strid = "audio_bitrate",
96 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
98 /* Already using audio_mode elsewhere :-( */
99 .strid = "mpeg_audio_mode",
100 .id = V4L2_CID_MPEG_AUDIO_MODE,
102 .strid = "mpeg_audio_mode_extension",
103 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
105 .strid = "audio_emphasis",
106 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
108 .strid = "audio_crc",
109 .id = V4L2_CID_MPEG_AUDIO_CRC,
111 .strid = "video_aspect",
112 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
114 .strid = "video_b_frames",
115 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
117 .strid = "video_gop_size",
118 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
120 .strid = "video_gop_closure",
121 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
123 .strid = "video_bitrate_mode",
124 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
126 .strid = "video_bitrate",
127 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
129 .strid = "video_bitrate_peak",
130 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
132 .strid = "video_temporal_decimation",
133 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
135 .strid = "stream_type",
136 .id = V4L2_CID_MPEG_STREAM_TYPE,
138 .strid = "video_spatial_filter_mode",
139 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
141 .strid = "video_spatial_filter",
142 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
144 .strid = "video_luma_spatial_filter_type",
145 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
147 .strid = "video_chroma_spatial_filter_type",
148 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
150 .strid = "video_temporal_filter_mode",
151 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
153 .strid = "video_temporal_filter",
154 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
156 .strid = "video_median_filter_type",
157 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
159 .strid = "video_luma_median_filter_top",
160 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
162 .strid = "video_luma_median_filter_bottom",
163 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
165 .strid = "video_chroma_median_filter_top",
166 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
168 .strid = "video_chroma_median_filter_bottom",
169 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
172 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
175 static const char *control_values_srate[] = {
176 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
177 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
178 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
183 static const char *control_values_input[] = {
184 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
185 [PVR2_CVAL_INPUT_DTV] = "dtv",
186 [PVR2_CVAL_INPUT_RADIO] = "radio",
187 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
188 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
192 static const char *control_values_audiomode[] = {
193 [V4L2_TUNER_MODE_MONO] = "Mono",
194 [V4L2_TUNER_MODE_STEREO] = "Stereo",
195 [V4L2_TUNER_MODE_LANG1] = "Lang1",
196 [V4L2_TUNER_MODE_LANG2] = "Lang2",
197 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
201 static const char *control_values_hsm[] = {
202 [PVR2_CVAL_HSM_FAIL] = "Fail",
203 [PVR2_CVAL_HSM_HIGH] = "High",
204 [PVR2_CVAL_HSM_FULL] = "Full",
208 static const char *pvr2_state_names[] = {
209 [PVR2_STATE_NONE] = "none",
210 [PVR2_STATE_DEAD] = "dead",
211 [PVR2_STATE_COLD] = "cold",
212 [PVR2_STATE_WARM] = "warm",
213 [PVR2_STATE_ERROR] = "error",
214 [PVR2_STATE_READY] = "ready",
215 [PVR2_STATE_RUN] = "run",
219 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
220 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
221 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
222 static void pvr2_hdw_worker_i2c(struct work_struct *work);
223 static void pvr2_hdw_worker_poll(struct work_struct *work);
224 static void pvr2_hdw_worker_init(struct work_struct *work);
225 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
226 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
227 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
228 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
229 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
230 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
231 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
232 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
233 static void pvr2_hdw_quiescent_timeout(unsigned long);
234 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
235 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
236 unsigned int timeout,int probe_fl,
237 void *write_data,unsigned int write_len,
238 void *read_data,unsigned int read_len);
241 static void trace_stbit(const char *name,int val)
243 pvr2_trace(PVR2_TRACE_STBITS,
244 "State bit %s <-- %s",
245 name,(val ? "true" : "false"));
248 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
250 struct pvr2_hdw *hdw = cptr->hdw;
251 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
252 *vp = hdw->freqTable[hdw->freqProgSlot-1];
259 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
261 struct pvr2_hdw *hdw = cptr->hdw;
262 unsigned int slotId = hdw->freqProgSlot;
263 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
264 hdw->freqTable[slotId-1] = v;
265 /* Handle side effects correctly - if we're tuned to this
266 slot, then forgot the slot id relation since the stored
267 frequency has been changed. */
268 if (hdw->freqSelector) {
269 if (hdw->freqSlotRadio == slotId) {
270 hdw->freqSlotRadio = 0;
273 if (hdw->freqSlotTelevision == slotId) {
274 hdw->freqSlotTelevision = 0;
281 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
283 *vp = cptr->hdw->freqProgSlot;
287 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
289 struct pvr2_hdw *hdw = cptr->hdw;
290 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
291 hdw->freqProgSlot = v;
296 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
298 struct pvr2_hdw *hdw = cptr->hdw;
299 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
303 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
306 struct pvr2_hdw *hdw = cptr->hdw;
307 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
309 freq = hdw->freqTable[slotId-1];
311 pvr2_hdw_set_cur_freq(hdw,freq);
313 if (hdw->freqSelector) {
314 hdw->freqSlotRadio = slotId;
316 hdw->freqSlotTelevision = slotId;
321 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
323 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
327 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
329 return cptr->hdw->freqDirty != 0;
332 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
334 cptr->hdw->freqDirty = 0;
337 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
339 pvr2_hdw_set_cur_freq(cptr->hdw,v);
343 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
345 /* Actual maximum depends on the video standard in effect. */
346 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
354 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
356 /* Actual minimum depends on device digitizer type. */
357 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
365 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
367 *vp = cptr->hdw->input_val;
371 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
373 return ((1 << v) & cptr->hdw->input_avail_mask) != 0;
376 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
378 struct pvr2_hdw *hdw = cptr->hdw;
380 if (hdw->input_val != v) {
382 hdw->input_dirty = !0;
385 /* Handle side effects - if we switch to a mode that needs the RF
386 tuner, then select the right frequency choice as well and mark
388 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
389 hdw->freqSelector = 0;
391 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
392 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
393 hdw->freqSelector = 1;
399 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
401 return cptr->hdw->input_dirty != 0;
404 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
406 cptr->hdw->input_dirty = 0;
410 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
413 struct pvr2_hdw *hdw = cptr->hdw;
414 if (hdw->tuner_signal_stale) {
415 pvr2_i2c_core_status_poll(hdw);
417 fv = hdw->tuner_signal_info.rangehigh;
419 /* Safety fallback */
423 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
432 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
435 struct pvr2_hdw *hdw = cptr->hdw;
436 if (hdw->tuner_signal_stale) {
437 pvr2_i2c_core_status_poll(hdw);
439 fv = hdw->tuner_signal_info.rangelow;
441 /* Safety fallback */
445 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
454 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
456 return cptr->hdw->enc_stale != 0;
459 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
461 cptr->hdw->enc_stale = 0;
462 cptr->hdw->enc_unsafe_stale = 0;
465 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
468 struct v4l2_ext_controls cs;
469 struct v4l2_ext_control c1;
470 memset(&cs,0,sizeof(cs));
471 memset(&c1,0,sizeof(c1));
474 c1.id = cptr->info->v4l_id;
475 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
482 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
485 struct pvr2_hdw *hdw = cptr->hdw;
486 struct v4l2_ext_controls cs;
487 struct v4l2_ext_control c1;
488 memset(&cs,0,sizeof(cs));
489 memset(&c1,0,sizeof(c1));
492 c1.id = cptr->info->v4l_id;
494 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
495 hdw->state_encoder_run, &cs,
498 /* Oops. cx2341x is telling us it's not safe to change
499 this control while we're capturing. Make a note of this
500 fact so that the pipeline will be stopped the next time
501 controls are committed. Then go on ahead and store this
503 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
506 if (!ret) hdw->enc_unsafe_stale = !0;
513 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
515 struct v4l2_queryctrl qctrl;
516 struct pvr2_ctl_info *info;
517 qctrl.id = cptr->info->v4l_id;
518 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
519 /* Strip out the const so we can adjust a function pointer. It's
520 OK to do this here because we know this is a dynamically created
521 control, so the underlying storage for the info pointer is (a)
522 private to us, and (b) not in read-only storage. Either we do
523 this or we significantly complicate the underlying control
525 info = (struct pvr2_ctl_info *)(cptr->info);
526 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
527 if (info->set_value) {
528 info->set_value = NULL;
531 if (!(info->set_value)) {
532 info->set_value = ctrl_cx2341x_set;
538 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
540 *vp = cptr->hdw->state_pipeline_req;
544 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
546 *vp = cptr->hdw->master_state;
550 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
552 int result = pvr2_hdw_is_hsm(cptr->hdw);
553 *vp = PVR2_CVAL_HSM_FULL;
554 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
555 if (result) *vp = PVR2_CVAL_HSM_HIGH;
559 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
561 *vp = cptr->hdw->std_mask_avail;
565 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
567 struct pvr2_hdw *hdw = cptr->hdw;
569 ns = hdw->std_mask_avail;
570 ns = (ns & ~m) | (v & m);
571 if (ns == hdw->std_mask_avail) return 0;
572 hdw->std_mask_avail = ns;
573 pvr2_hdw_internal_set_std_avail(hdw);
574 pvr2_hdw_internal_find_stdenum(hdw);
578 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
579 char *bufPtr,unsigned int bufSize,
582 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
586 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
587 const char *bufPtr,unsigned int bufSize,
592 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
593 if (ret < 0) return ret;
594 if (mskp) *mskp = id;
595 if (valp) *valp = id;
599 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
601 *vp = cptr->hdw->std_mask_cur;
605 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
607 struct pvr2_hdw *hdw = cptr->hdw;
609 ns = hdw->std_mask_cur;
610 ns = (ns & ~m) | (v & m);
611 if (ns == hdw->std_mask_cur) return 0;
612 hdw->std_mask_cur = ns;
614 pvr2_hdw_internal_find_stdenum(hdw);
618 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
620 return cptr->hdw->std_dirty != 0;
623 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
625 cptr->hdw->std_dirty = 0;
628 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
630 struct pvr2_hdw *hdw = cptr->hdw;
631 pvr2_i2c_core_status_poll(hdw);
632 *vp = hdw->tuner_signal_info.signal;
636 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
639 unsigned int subchan;
640 struct pvr2_hdw *hdw = cptr->hdw;
641 pvr2_i2c_core_status_poll(hdw);
642 subchan = hdw->tuner_signal_info.rxsubchans;
643 if (subchan & V4L2_TUNER_SUB_MONO) {
644 val |= (1 << V4L2_TUNER_MODE_MONO);
646 if (subchan & V4L2_TUNER_SUB_STEREO) {
647 val |= (1 << V4L2_TUNER_MODE_STEREO);
649 if (subchan & V4L2_TUNER_SUB_LANG1) {
650 val |= (1 << V4L2_TUNER_MODE_LANG1);
652 if (subchan & V4L2_TUNER_SUB_LANG2) {
653 val |= (1 << V4L2_TUNER_MODE_LANG2);
660 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
662 struct pvr2_hdw *hdw = cptr->hdw;
663 if (v < 0) return -EINVAL;
664 if (v > hdw->std_enum_cnt) return -EINVAL;
665 hdw->std_enum_cur = v;
668 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
669 hdw->std_mask_cur = hdw->std_defs[v].id;
675 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
677 *vp = cptr->hdw->std_enum_cur;
682 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
684 return cptr->hdw->std_dirty != 0;
688 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
690 cptr->hdw->std_dirty = 0;
694 #define DEFINT(vmin,vmax) \
695 .type = pvr2_ctl_int, \
696 .def.type_int.min_value = vmin, \
697 .def.type_int.max_value = vmax
699 #define DEFENUM(tab) \
700 .type = pvr2_ctl_enum, \
701 .def.type_enum.count = ARRAY_SIZE(tab), \
702 .def.type_enum.value_names = tab
705 .type = pvr2_ctl_bool
707 #define DEFMASK(msk,tab) \
708 .type = pvr2_ctl_bitmask, \
709 .def.type_bitmask.valid_bits = msk, \
710 .def.type_bitmask.bit_names = tab
712 #define DEFREF(vname) \
713 .set_value = ctrl_set_##vname, \
714 .get_value = ctrl_get_##vname, \
715 .is_dirty = ctrl_isdirty_##vname, \
716 .clear_dirty = ctrl_cleardirty_##vname
719 #define VCREATE_FUNCS(vname) \
720 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
721 {*vp = cptr->hdw->vname##_val; return 0;} \
722 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
723 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
724 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
725 {return cptr->hdw->vname##_dirty != 0;} \
726 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
727 {cptr->hdw->vname##_dirty = 0;}
729 VCREATE_FUNCS(brightness)
730 VCREATE_FUNCS(contrast)
731 VCREATE_FUNCS(saturation)
733 VCREATE_FUNCS(volume)
734 VCREATE_FUNCS(balance)
736 VCREATE_FUNCS(treble)
738 VCREATE_FUNCS(audiomode)
739 VCREATE_FUNCS(res_hor)
740 VCREATE_FUNCS(res_ver)
743 /* Table definition of all controls which can be manipulated */
744 static const struct pvr2_ctl_info control_defs[] = {
746 .v4l_id = V4L2_CID_BRIGHTNESS,
747 .desc = "Brightness",
748 .name = "brightness",
749 .default_value = 128,
753 .v4l_id = V4L2_CID_CONTRAST,
760 .v4l_id = V4L2_CID_SATURATION,
761 .desc = "Saturation",
762 .name = "saturation",
767 .v4l_id = V4L2_CID_HUE,
774 .v4l_id = V4L2_CID_AUDIO_VOLUME,
777 .default_value = 62000,
781 .v4l_id = V4L2_CID_AUDIO_BALANCE,
786 DEFINT(-32768,32767),
788 .v4l_id = V4L2_CID_AUDIO_BASS,
793 DEFINT(-32768,32767),
795 .v4l_id = V4L2_CID_AUDIO_TREBLE,
800 DEFINT(-32768,32767),
802 .v4l_id = V4L2_CID_AUDIO_MUTE,
809 .desc = "Video Source",
811 .internal_id = PVR2_CID_INPUT,
812 .default_value = PVR2_CVAL_INPUT_TV,
813 .check_value = ctrl_check_input,
815 DEFENUM(control_values_input),
817 .desc = "Audio Mode",
818 .name = "audio_mode",
819 .internal_id = PVR2_CID_AUDIOMODE,
820 .default_value = V4L2_TUNER_MODE_STEREO,
822 DEFENUM(control_values_audiomode),
824 .desc = "Horizontal capture resolution",
825 .name = "resolution_hor",
826 .internal_id = PVR2_CID_HRES,
827 .default_value = 720,
831 .desc = "Vertical capture resolution",
832 .name = "resolution_ver",
833 .internal_id = PVR2_CID_VRES,
834 .default_value = 480,
837 /* Hook in check for video standard and adjust maximum
838 depending on the standard. */
839 .get_max_value = ctrl_vres_max_get,
840 .get_min_value = ctrl_vres_min_get,
842 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
843 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
844 .desc = "Audio Sampling Frequency",
847 DEFENUM(control_values_srate),
849 .desc = "Tuner Frequency (Hz)",
851 .internal_id = PVR2_CID_FREQUENCY,
853 .set_value = ctrl_freq_set,
854 .get_value = ctrl_freq_get,
855 .is_dirty = ctrl_freq_is_dirty,
856 .clear_dirty = ctrl_freq_clear_dirty,
858 /* Hook in check for input value (tv/radio) and adjust
859 max/min values accordingly */
860 .get_max_value = ctrl_freq_max_get,
861 .get_min_value = ctrl_freq_min_get,
865 .set_value = ctrl_channel_set,
866 .get_value = ctrl_channel_get,
867 DEFINT(0,FREQTABLE_SIZE),
869 .desc = "Channel Program Frequency",
870 .name = "freq_table_value",
871 .set_value = ctrl_channelfreq_set,
872 .get_value = ctrl_channelfreq_get,
874 /* Hook in check for input value (tv/radio) and adjust
875 max/min values accordingly */
876 .get_max_value = ctrl_freq_max_get,
877 .get_min_value = ctrl_freq_min_get,
879 .desc = "Channel Program ID",
880 .name = "freq_table_channel",
881 .set_value = ctrl_channelprog_set,
882 .get_value = ctrl_channelprog_get,
883 DEFINT(0,FREQTABLE_SIZE),
885 .desc = "Streaming Enabled",
886 .name = "streaming_enabled",
887 .get_value = ctrl_streamingenabled_get,
892 .get_value = ctrl_hsm_get,
893 DEFENUM(control_values_hsm),
895 .desc = "Master State",
896 .name = "master_state",
897 .get_value = ctrl_masterstate_get,
898 DEFENUM(pvr2_state_names),
900 .desc = "Signal Present",
901 .name = "signal_present",
902 .get_value = ctrl_signal_get,
905 .desc = "Audio Modes Present",
906 .name = "audio_modes_present",
907 .get_value = ctrl_audio_modes_present_get,
908 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
909 v4l. Nothing outside of this module cares about this,
910 but I reuse it in order to also reuse the
911 control_values_audiomode string table. */
912 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
913 (1 << V4L2_TUNER_MODE_STEREO)|
914 (1 << V4L2_TUNER_MODE_LANG1)|
915 (1 << V4L2_TUNER_MODE_LANG2)),
916 control_values_audiomode),
918 .desc = "Video Standards Available Mask",
919 .name = "video_standard_mask_available",
920 .internal_id = PVR2_CID_STDAVAIL,
922 .get_value = ctrl_stdavail_get,
923 .set_value = ctrl_stdavail_set,
924 .val_to_sym = ctrl_std_val_to_sym,
925 .sym_to_val = ctrl_std_sym_to_val,
926 .type = pvr2_ctl_bitmask,
928 .desc = "Video Standards In Use Mask",
929 .name = "video_standard_mask_active",
930 .internal_id = PVR2_CID_STDCUR,
932 .get_value = ctrl_stdcur_get,
933 .set_value = ctrl_stdcur_set,
934 .is_dirty = ctrl_stdcur_is_dirty,
935 .clear_dirty = ctrl_stdcur_clear_dirty,
936 .val_to_sym = ctrl_std_val_to_sym,
937 .sym_to_val = ctrl_std_sym_to_val,
938 .type = pvr2_ctl_bitmask,
940 .desc = "Video Standard Name",
941 .name = "video_standard",
942 .internal_id = PVR2_CID_STDENUM,
944 .get_value = ctrl_stdenumcur_get,
945 .set_value = ctrl_stdenumcur_set,
946 .is_dirty = ctrl_stdenumcur_is_dirty,
947 .clear_dirty = ctrl_stdenumcur_clear_dirty,
948 .type = pvr2_ctl_enum,
952 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
955 const char *pvr2_config_get_name(enum pvr2_config cfg)
958 case pvr2_config_empty: return "empty";
959 case pvr2_config_mpeg: return "mpeg";
960 case pvr2_config_vbi: return "vbi";
961 case pvr2_config_pcm: return "pcm";
962 case pvr2_config_rawvideo: return "raw video";
968 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
974 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
976 return hdw->serial_number;
980 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
982 return hdw->bus_info;
986 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
988 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
991 /* Set the currently tuned frequency and account for all possible
992 driver-core side effects of this action. */
993 void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
995 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
996 if (hdw->freqSelector) {
997 /* Swing over to radio frequency selection */
998 hdw->freqSelector = 0;
1001 if (hdw->freqValRadio != val) {
1002 hdw->freqValRadio = val;
1003 hdw->freqSlotRadio = 0;
1004 hdw->freqDirty = !0;
1007 if (!(hdw->freqSelector)) {
1008 /* Swing over to television frequency selection */
1009 hdw->freqSelector = 1;
1010 hdw->freqDirty = !0;
1012 if (hdw->freqValTelevision != val) {
1013 hdw->freqValTelevision = val;
1014 hdw->freqSlotTelevision = 0;
1015 hdw->freqDirty = !0;
1020 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1022 return hdw->unit_number;
1026 /* Attempt to locate one of the given set of files. Messages are logged
1027 appropriate to what has been found. The return value will be 0 or
1028 greater on success (it will be the index of the file name found) and
1029 fw_entry will be filled in. Otherwise a negative error is returned on
1030 failure. If the return value is -ENOENT then no viable firmware file
1031 could be located. */
1032 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1033 const struct firmware **fw_entry,
1034 const char *fwtypename,
1035 unsigned int fwcount,
1036 const char *fwnames[])
1040 for (idx = 0; idx < fwcount; idx++) {
1041 ret = request_firmware(fw_entry,
1043 &hdw->usb_dev->dev);
1045 trace_firmware("Located %s firmware: %s;"
1051 if (ret == -ENOENT) continue;
1052 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1053 "request_firmware fatal error with code=%d",ret);
1056 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1058 " Device %s firmware"
1059 " seems to be missing.",
1061 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1062 "Did you install the pvrusb2 firmware files"
1063 " in their proper location?");
1065 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1066 "request_firmware unable to locate %s file %s",
1067 fwtypename,fwnames[0]);
1069 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1070 "request_firmware unable to locate"
1071 " one of the following %s files:",
1073 for (idx = 0; idx < fwcount; idx++) {
1074 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1075 "request_firmware: Failed to find %s",
1084 * pvr2_upload_firmware1().
1086 * Send the 8051 firmware to the device. After the upload, arrange for
1087 * device to re-enumerate.
1089 * NOTE : the pointer to the firmware data given by request_firmware()
1090 * is not suitable for an usb transaction.
1093 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1095 const struct firmware *fw_entry = NULL;
1101 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1102 hdw->fw1_state = FW1_STATE_OK;
1103 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1104 "Connected device type defines"
1105 " no firmware to upload; ignoring firmware");
1109 hdw->fw1_state = FW1_STATE_FAILED; // default result
1111 trace_firmware("pvr2_upload_firmware1");
1113 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1114 hdw->hdw_desc->fx2_firmware.cnt,
1115 hdw->hdw_desc->fx2_firmware.lst);
1117 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1121 usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1122 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1124 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1126 if (fw_entry->size != 0x2000){
1127 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1128 release_firmware(fw_entry);
1132 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1133 if (fw_ptr == NULL){
1134 release_firmware(fw_entry);
1138 /* We have to hold the CPU during firmware upload. */
1139 pvr2_hdw_cpureset_assert(hdw,1);
1141 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1145 for(address = 0; address < fw_entry->size; address += 0x800) {
1146 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1147 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1148 0, fw_ptr, 0x800, HZ);
1151 trace_firmware("Upload done, releasing device's CPU");
1153 /* Now release the CPU. It will disconnect and reconnect later. */
1154 pvr2_hdw_cpureset_assert(hdw,0);
1157 release_firmware(fw_entry);
1159 trace_firmware("Upload done (%d bytes sent)",ret);
1161 /* We should have written 8192 bytes */
1163 hdw->fw1_state = FW1_STATE_RELOAD;
1172 * pvr2_upload_firmware2()
1174 * This uploads encoder firmware on endpoint 2.
1178 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1180 const struct firmware *fw_entry = NULL;
1182 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1186 static const char *fw_files[] = {
1187 CX2341X_FIRM_ENC_FILENAME,
1190 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1194 trace_firmware("pvr2_upload_firmware2");
1196 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1197 ARRAY_SIZE(fw_files), fw_files);
1198 if (ret < 0) return ret;
1201 /* Since we're about to completely reinitialize the encoder,
1202 invalidate our cached copy of its configuration state. Next
1203 time we configure the encoder, then we'll fully configure it. */
1204 hdw->enc_cur_valid = 0;
1206 /* First prepare firmware loading */
1207 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1208 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1209 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1210 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1211 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1212 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1213 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1214 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1215 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1216 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1217 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1218 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1219 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1220 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1221 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1222 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1223 LOCK_TAKE(hdw->ctl_lock); do {
1224 hdw->cmd_buffer[0] = FX2CMD_FWPOST1;
1225 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
1226 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1227 hdw->cmd_buffer[1] = 0;
1228 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0);
1229 } while (0); LOCK_GIVE(hdw->ctl_lock);
1232 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1233 "firmware2 upload prep failed, ret=%d",ret);
1234 release_firmware(fw_entry);
1238 /* Now send firmware */
1240 fw_len = fw_entry->size;
1242 if (fw_len % sizeof(u32)) {
1243 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1244 "size of %s firmware"
1245 " must be a multiple of %zu bytes",
1246 fw_files[fwidx],sizeof(u32));
1247 release_firmware(fw_entry);
1251 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1252 if (fw_ptr == NULL){
1253 release_firmware(fw_entry);
1254 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1255 "failed to allocate memory for firmware2 upload");
1259 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1262 for (fw_done = 0; fw_done < fw_len;) {
1263 bcnt = fw_len - fw_done;
1264 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1265 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1266 /* Usbsnoop log shows that we must swap bytes... */
1267 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1268 ((u32 *)fw_ptr)[icnt] =
1269 ___swab32(((u32 *)fw_ptr)[icnt]);
1271 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1272 &actual_length, HZ);
1273 ret |= (actual_length != bcnt);
1278 trace_firmware("upload of %s : %i / %i ",
1279 fw_files[fwidx],fw_done,fw_len);
1282 release_firmware(fw_entry);
1285 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1286 "firmware2 upload transfer failure");
1292 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1293 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1294 LOCK_TAKE(hdw->ctl_lock); do {
1295 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1296 hdw->cmd_buffer[1] = 0;
1297 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0);
1298 } while (0); LOCK_GIVE(hdw->ctl_lock);
1301 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1302 "firmware2 upload post-proc failure");
1308 static const char *pvr2_get_state_name(unsigned int st)
1310 if (st < ARRAY_SIZE(pvr2_state_names)) {
1311 return pvr2_state_names[st];
1316 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1318 if (!hdw->decoder_ctrl) {
1319 if (!hdw->flag_decoder_missed) {
1320 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1321 "WARNING: No decoder present");
1322 hdw->flag_decoder_missed = !0;
1323 trace_stbit("flag_decoder_missed",
1324 hdw->flag_decoder_missed);
1328 hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt,enablefl);
1333 void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
1335 if (hdw->decoder_ctrl == ptr) return;
1336 hdw->decoder_ctrl = ptr;
1337 if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1338 hdw->flag_decoder_missed = 0;
1339 trace_stbit("flag_decoder_missed",
1340 hdw->flag_decoder_missed);
1341 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1342 "Decoder has appeared");
1343 pvr2_hdw_state_sched(hdw);
1348 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1350 return hdw->master_state;
1354 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1356 if (!hdw->flag_tripped) return 0;
1357 hdw->flag_tripped = 0;
1358 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1359 "Clearing driver error statuss");
1364 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1367 LOCK_TAKE(hdw->big_lock); do {
1368 fl = pvr2_hdw_untrip_unlocked(hdw);
1369 } while (0); LOCK_GIVE(hdw->big_lock);
1370 if (fl) pvr2_hdw_state_sched(hdw);
1375 const char *pvr2_hdw_get_state_name(unsigned int id)
1377 if (id >= ARRAY_SIZE(pvr2_state_names)) return NULL;
1378 return pvr2_state_names[id];
1382 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1384 return hdw->state_pipeline_req != 0;
1388 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1391 LOCK_TAKE(hdw->big_lock); do {
1392 pvr2_hdw_untrip_unlocked(hdw);
1393 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1394 hdw->state_pipeline_req = enable_flag != 0;
1395 pvr2_trace(PVR2_TRACE_START_STOP,
1396 "/*--TRACE_STREAM--*/ %s",
1397 enable_flag ? "enable" : "disable");
1399 pvr2_hdw_state_sched(hdw);
1400 } while (0); LOCK_GIVE(hdw->big_lock);
1401 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1403 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1404 if (st != PVR2_STATE_READY) return -EIO;
1405 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1412 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1415 LOCK_TAKE(hdw->big_lock);
1416 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1417 hdw->desired_stream_type = config;
1418 hdw->state_pipeline_config = 0;
1419 trace_stbit("state_pipeline_config",
1420 hdw->state_pipeline_config);
1421 pvr2_hdw_state_sched(hdw);
1423 LOCK_GIVE(hdw->big_lock);
1425 return pvr2_hdw_wait(hdw,0);
1429 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1431 int unit_number = hdw->unit_number;
1433 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1434 tp = tuner[unit_number];
1436 if (tp < 0) return -EINVAL;
1437 hdw->tuner_type = tp;
1438 hdw->tuner_updated = !0;
1443 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1445 int unit_number = hdw->unit_number;
1447 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1448 tp = video_std[unit_number];
1455 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1457 int unit_number = hdw->unit_number;
1459 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1460 tp = tolerance[unit_number];
1466 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1468 /* Try a harmless request to fetch the eeprom's address over
1469 endpoint 1. See what happens. Only the full FX2 image can
1470 respond to this. If this probe fails then likely the FX2
1471 firmware needs be loaded. */
1473 LOCK_TAKE(hdw->ctl_lock); do {
1474 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1475 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1478 if (result < 0) break;
1479 } while(0); LOCK_GIVE(hdw->ctl_lock);
1481 pvr2_trace(PVR2_TRACE_INIT,
1482 "Probe of device endpoint 1 result status %d",
1485 pvr2_trace(PVR2_TRACE_INIT,
1486 "Probe of device endpoint 1 succeeded");
1491 struct pvr2_std_hack {
1492 v4l2_std_id pat; /* Pattern to match */
1493 v4l2_std_id msk; /* Which bits we care about */
1494 v4l2_std_id std; /* What additional standards or default to set */
1497 /* This data structure labels specific combinations of standards from
1498 tveeprom that we'll try to recognize. If we recognize one, then assume
1499 a specified default standard to use. This is here because tveeprom only
1500 tells us about available standards not the intended default standard (if
1501 any) for the device in question. We guess the default based on what has
1502 been reported as available. Note that this is only for guessing a
1503 default - which can always be overridden explicitly - and if the user
1504 has otherwise named a default then that default will always be used in
1505 place of this table. */
1506 const static struct pvr2_std_hack std_eeprom_maps[] = {
1508 .pat = V4L2_STD_B|V4L2_STD_GH,
1509 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1513 .std = V4L2_STD_NTSC_M,
1516 .pat = V4L2_STD_PAL_I,
1517 .std = V4L2_STD_PAL_I,
1520 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1521 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1525 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1529 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1533 v4l2_std_id std1,std2,std3;
1535 std1 = get_default_standard(hdw);
1536 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1538 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1539 pvr2_trace(PVR2_TRACE_STD,
1540 "Supported video standard(s) reported available"
1541 " in hardware: %.*s",
1544 hdw->std_mask_avail = hdw->std_mask_eeprom;
1546 std2 = (std1|std3) & ~hdw->std_mask_avail;
1548 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1549 pvr2_trace(PVR2_TRACE_STD,
1550 "Expanding supported video standards"
1551 " to include: %.*s",
1553 hdw->std_mask_avail |= std2;
1556 pvr2_hdw_internal_set_std_avail(hdw);
1559 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1560 pvr2_trace(PVR2_TRACE_STD,
1561 "Initial video standard forced to %.*s",
1563 hdw->std_mask_cur = std1;
1564 hdw->std_dirty = !0;
1565 pvr2_hdw_internal_find_stdenum(hdw);
1569 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1570 pvr2_trace(PVR2_TRACE_STD,
1571 "Initial video standard"
1572 " (determined by device type): %.*s",bcnt,buf);
1573 hdw->std_mask_cur = std3;
1574 hdw->std_dirty = !0;
1575 pvr2_hdw_internal_find_stdenum(hdw);
1581 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1582 if (std_eeprom_maps[idx].msk ?
1583 ((std_eeprom_maps[idx].pat ^
1584 hdw->std_mask_eeprom) &
1585 std_eeprom_maps[idx].msk) :
1586 (std_eeprom_maps[idx].pat !=
1587 hdw->std_mask_eeprom)) continue;
1588 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1589 std_eeprom_maps[idx].std);
1590 pvr2_trace(PVR2_TRACE_STD,
1591 "Initial video standard guessed as %.*s",
1593 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1594 hdw->std_dirty = !0;
1595 pvr2_hdw_internal_find_stdenum(hdw);
1600 if (hdw->std_enum_cnt > 1) {
1601 // Autoselect the first listed standard
1602 hdw->std_enum_cur = 1;
1603 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1604 hdw->std_dirty = !0;
1605 pvr2_trace(PVR2_TRACE_STD,
1606 "Initial video standard auto-selected to %s",
1607 hdw->std_defs[hdw->std_enum_cur-1].name);
1611 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1612 "Unable to select a viable initial video standard");
1616 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1620 struct pvr2_ctrl *cptr;
1622 if (hdw->hdw_desc->fx2_firmware.cnt) {
1625 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1628 pvr2_trace(PVR2_TRACE_INIT,
1629 "USB endpoint config looks strange"
1630 "; possibly firmware needs to be"
1635 reloadFl = !pvr2_hdw_check_firmware(hdw);
1637 pvr2_trace(PVR2_TRACE_INIT,
1638 "Check for FX2 firmware failed"
1639 "; possibly firmware needs to be"
1644 if (pvr2_upload_firmware1(hdw) != 0) {
1645 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1646 "Failure uploading firmware1");
1651 hdw->fw1_state = FW1_STATE_OK;
1654 pvr2_hdw_device_reset(hdw);
1656 if (!pvr2_hdw_dev_ok(hdw)) return;
1658 for (idx = 0; idx < hdw->hdw_desc->client_modules.cnt; idx++) {
1659 request_module(hdw->hdw_desc->client_modules.lst[idx]);
1662 if (!hdw->hdw_desc->flag_no_powerup) {
1663 pvr2_hdw_cmd_powerup(hdw);
1664 if (!pvr2_hdw_dev_ok(hdw)) return;
1667 // This step MUST happen after the earlier powerup step.
1668 pvr2_i2c_core_init(hdw);
1669 if (!pvr2_hdw_dev_ok(hdw)) return;
1671 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1672 cptr = hdw->controls + idx;
1673 if (cptr->info->skip_init) continue;
1674 if (!cptr->info->set_value) continue;
1675 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1678 /* Set up special default values for the television and radio
1679 frequencies here. It's not really important what these defaults
1680 are, but I set them to something usable in the Chicago area just
1681 to make driver testing a little easier. */
1683 /* US Broadcast channel 7 (175.25 MHz) */
1684 hdw->freqValTelevision = 175250000L;
1685 /* 104.3 MHz, a usable FM station for my area */
1686 hdw->freqValRadio = 104300000L;
1688 // Do not use pvr2_reset_ctl_endpoints() here. It is not
1689 // thread-safe against the normal pvr2_send_request() mechanism.
1690 // (We should make it thread safe).
1692 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
1693 ret = pvr2_hdw_get_eeprom_addr(hdw);
1694 if (!pvr2_hdw_dev_ok(hdw)) return;
1696 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1697 "Unable to determine location of eeprom,"
1700 hdw->eeprom_addr = ret;
1701 pvr2_eeprom_analyze(hdw);
1702 if (!pvr2_hdw_dev_ok(hdw)) return;
1705 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
1706 hdw->tuner_updated = !0;
1707 hdw->std_mask_eeprom = V4L2_STD_ALL;
1710 pvr2_hdw_setup_std(hdw);
1712 if (!get_default_tuner_type(hdw)) {
1713 pvr2_trace(PVR2_TRACE_INIT,
1714 "pvr2_hdw_setup: Tuner type overridden to %d",
1718 pvr2_i2c_core_check_stale(hdw);
1719 hdw->tuner_updated = 0;
1721 if (!pvr2_hdw_dev_ok(hdw)) return;
1723 pvr2_hdw_commit_setup(hdw);
1725 hdw->vid_stream = pvr2_stream_create();
1726 if (!pvr2_hdw_dev_ok(hdw)) return;
1727 pvr2_trace(PVR2_TRACE_INIT,
1728 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1729 if (hdw->vid_stream) {
1730 idx = get_default_error_tolerance(hdw);
1732 pvr2_trace(PVR2_TRACE_INIT,
1733 "pvr2_hdw_setup: video stream %p"
1734 " setting tolerance %u",
1735 hdw->vid_stream,idx);
1737 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1738 PVR2_VID_ENDPOINT,idx);
1741 if (!pvr2_hdw_dev_ok(hdw)) return;
1743 hdw->flag_init_ok = !0;
1745 pvr2_hdw_state_sched(hdw);
1749 /* Set up the structure and attempt to put the device into a usable state.
1750 This can be a time-consuming operation, which is why it is not done
1751 internally as part of the create() step. */
1752 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
1754 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1756 pvr2_hdw_setup_low(hdw);
1757 pvr2_trace(PVR2_TRACE_INIT,
1758 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1759 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
1760 if (pvr2_hdw_dev_ok(hdw)) {
1761 if (hdw->flag_init_ok) {
1764 "Device initialization"
1765 " completed successfully.");
1768 if (hdw->fw1_state == FW1_STATE_RELOAD) {
1771 "Device microcontroller firmware"
1772 " (re)loaded; it should now reset"
1777 PVR2_TRACE_ERROR_LEGS,
1778 "Device initialization was not successful.");
1779 if (hdw->fw1_state == FW1_STATE_MISSING) {
1781 PVR2_TRACE_ERROR_LEGS,
1782 "Giving up since device"
1783 " microcontroller firmware"
1784 " appears to be missing.");
1790 PVR2_TRACE_ERROR_LEGS,
1791 "Attempting pvrusb2 recovery by reloading"
1792 " primary firmware.");
1794 PVR2_TRACE_ERROR_LEGS,
1795 "If this works, device should disconnect"
1796 " and reconnect in a sane state.");
1797 hdw->fw1_state = FW1_STATE_UNKNOWN;
1798 pvr2_upload_firmware1(hdw);
1801 PVR2_TRACE_ERROR_LEGS,
1802 "***WARNING*** pvrusb2 device hardware"
1803 " appears to be jammed"
1804 " and I can't clear it.");
1806 PVR2_TRACE_ERROR_LEGS,
1807 "You might need to power cycle"
1808 " the pvrusb2 device"
1809 " in order to recover.");
1812 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
1816 /* Create and return a structure for interacting with the underlying
1818 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1819 const struct usb_device_id *devid)
1821 unsigned int idx,cnt1,cnt2,m;
1822 struct pvr2_hdw *hdw;
1824 struct pvr2_ctrl *cptr;
1825 const struct pvr2_device_desc *hdw_desc;
1827 struct v4l2_queryctrl qctrl;
1828 struct pvr2_ctl_info *ciptr;
1830 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
1832 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
1833 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
1834 hdw,hdw_desc->description);
1835 if (!hdw) goto fail;
1837 init_timer(&hdw->quiescent_timer);
1838 hdw->quiescent_timer.data = (unsigned long)hdw;
1839 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
1841 init_timer(&hdw->encoder_wait_timer);
1842 hdw->encoder_wait_timer.data = (unsigned long)hdw;
1843 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
1845 hdw->master_state = PVR2_STATE_DEAD;
1847 init_waitqueue_head(&hdw->state_wait_data);
1849 hdw->tuner_signal_stale = !0;
1850 cx2341x_fill_defaults(&hdw->enc_ctl_state);
1852 /* Calculate which inputs are OK */
1854 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
1855 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
1856 m |= 1 << PVR2_CVAL_INPUT_DTV;
1858 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
1859 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
1860 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
1861 hdw->input_avail_mask = m;
1863 /* If not a hybrid device, pathway_state never changes. So
1864 initialize it here to what it should forever be. */
1865 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
1866 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
1867 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
1868 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
1871 hdw->control_cnt = CTRLDEF_COUNT;
1872 hdw->control_cnt += MPEGDEF_COUNT;
1873 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
1875 if (!hdw->controls) goto fail;
1876 hdw->hdw_desc = hdw_desc;
1877 for (idx = 0; idx < hdw->control_cnt; idx++) {
1878 cptr = hdw->controls + idx;
1881 for (idx = 0; idx < 32; idx++) {
1882 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1884 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1885 cptr = hdw->controls + idx;
1886 cptr->info = control_defs+idx;
1889 /* Ensure that default input choice is a valid one. */
1890 m = hdw->input_avail_mask;
1891 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
1892 if (!((1 << idx) & m)) continue;
1893 hdw->input_val = idx;
1897 /* Define and configure additional controls from cx2341x module. */
1898 hdw->mpeg_ctrl_info = kzalloc(
1899 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
1900 if (!hdw->mpeg_ctrl_info) goto fail;
1901 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
1902 cptr = hdw->controls + idx + CTRLDEF_COUNT;
1903 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
1904 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
1905 ciptr->name = mpeg_ids[idx].strid;
1906 ciptr->v4l_id = mpeg_ids[idx].id;
1907 ciptr->skip_init = !0;
1908 ciptr->get_value = ctrl_cx2341x_get;
1909 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
1910 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
1911 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
1912 qctrl.id = ciptr->v4l_id;
1913 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
1914 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
1915 ciptr->set_value = ctrl_cx2341x_set;
1917 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
1918 PVR2_CTLD_INFO_DESC_SIZE);
1919 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
1920 ciptr->default_value = qctrl.default_value;
1921 switch (qctrl.type) {
1923 case V4L2_CTRL_TYPE_INTEGER:
1924 ciptr->type = pvr2_ctl_int;
1925 ciptr->def.type_int.min_value = qctrl.minimum;
1926 ciptr->def.type_int.max_value = qctrl.maximum;
1928 case V4L2_CTRL_TYPE_BOOLEAN:
1929 ciptr->type = pvr2_ctl_bool;
1931 case V4L2_CTRL_TYPE_MENU:
1932 ciptr->type = pvr2_ctl_enum;
1933 ciptr->def.type_enum.value_names =
1934 cx2341x_ctrl_get_menu(ciptr->v4l_id);
1936 ciptr->def.type_enum.value_names[cnt1] != NULL;
1938 ciptr->def.type_enum.count = cnt1;
1944 // Initialize video standard enum dynamic control
1945 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
1947 memcpy(&hdw->std_info_enum,cptr->info,
1948 sizeof(hdw->std_info_enum));
1949 cptr->info = &hdw->std_info_enum;
1952 // Initialize control data regarding video standard masks
1953 valid_std_mask = pvr2_std_get_usable();
1954 for (idx = 0; idx < 32; idx++) {
1955 if (!(valid_std_mask & (1 << idx))) continue;
1956 cnt1 = pvr2_std_id_to_str(
1957 hdw->std_mask_names[idx],
1958 sizeof(hdw->std_mask_names[idx])-1,
1960 hdw->std_mask_names[idx][cnt1] = 0;
1962 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
1964 memcpy(&hdw->std_info_avail,cptr->info,
1965 sizeof(hdw->std_info_avail));
1966 cptr->info = &hdw->std_info_avail;
1967 hdw->std_info_avail.def.type_bitmask.bit_names =
1969 hdw->std_info_avail.def.type_bitmask.valid_bits =
1972 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
1974 memcpy(&hdw->std_info_cur,cptr->info,
1975 sizeof(hdw->std_info_cur));
1976 cptr->info = &hdw->std_info_cur;
1977 hdw->std_info_cur.def.type_bitmask.bit_names =
1979 hdw->std_info_avail.def.type_bitmask.valid_bits =
1983 hdw->eeprom_addr = -1;
1984 hdw->unit_number = -1;
1985 hdw->v4l_minor_number_video = -1;
1986 hdw->v4l_minor_number_vbi = -1;
1987 hdw->v4l_minor_number_radio = -1;
1988 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1989 if (!hdw->ctl_write_buffer) goto fail;
1990 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1991 if (!hdw->ctl_read_buffer) goto fail;
1992 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
1993 if (!hdw->ctl_write_urb) goto fail;
1994 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
1995 if (!hdw->ctl_read_urb) goto fail;
1997 mutex_lock(&pvr2_unit_mtx); do {
1998 for (idx = 0; idx < PVR_NUM; idx++) {
1999 if (unit_pointers[idx]) continue;
2000 hdw->unit_number = idx;
2001 unit_pointers[idx] = hdw;
2004 } while (0); mutex_unlock(&pvr2_unit_mtx);
2007 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2009 if (hdw->unit_number >= 0) {
2010 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2011 ('a' + hdw->unit_number));
2014 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2015 hdw->name[cnt1] = 0;
2017 hdw->workqueue = create_singlethread_workqueue(hdw->name);
2018 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2019 INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
2020 INIT_WORK(&hdw->workinit,pvr2_hdw_worker_init);
2022 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2023 hdw->unit_number,hdw->name);
2025 hdw->tuner_type = -1;
2028 hdw->usb_intf = intf;
2029 hdw->usb_dev = interface_to_usbdev(intf);
2031 scnprintf(hdw->bus_info,sizeof(hdw->bus_info),
2032 "usb %s address %d",
2033 hdw->usb_dev->dev.bus_id,
2034 hdw->usb_dev->devnum);
2036 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2037 usb_set_interface(hdw->usb_dev,ifnum,0);
2039 mutex_init(&hdw->ctl_lock_mutex);
2040 mutex_init(&hdw->big_lock_mutex);
2042 queue_work(hdw->workqueue,&hdw->workinit);
2046 del_timer_sync(&hdw->quiescent_timer);
2047 del_timer_sync(&hdw->encoder_wait_timer);
2048 if (hdw->workqueue) {
2049 flush_workqueue(hdw->workqueue);
2050 destroy_workqueue(hdw->workqueue);
2051 hdw->workqueue = NULL;
2053 usb_free_urb(hdw->ctl_read_urb);
2054 usb_free_urb(hdw->ctl_write_urb);
2055 kfree(hdw->ctl_read_buffer);
2056 kfree(hdw->ctl_write_buffer);
2057 kfree(hdw->controls);
2058 kfree(hdw->mpeg_ctrl_info);
2059 kfree(hdw->std_defs);
2060 kfree(hdw->std_enum_names);
2067 /* Remove _all_ associations between this driver and the underlying USB
2069 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2071 if (hdw->flag_disconnected) return;
2072 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2073 if (hdw->ctl_read_urb) {
2074 usb_kill_urb(hdw->ctl_read_urb);
2075 usb_free_urb(hdw->ctl_read_urb);
2076 hdw->ctl_read_urb = NULL;
2078 if (hdw->ctl_write_urb) {
2079 usb_kill_urb(hdw->ctl_write_urb);
2080 usb_free_urb(hdw->ctl_write_urb);
2081 hdw->ctl_write_urb = NULL;
2083 if (hdw->ctl_read_buffer) {
2084 kfree(hdw->ctl_read_buffer);
2085 hdw->ctl_read_buffer = NULL;
2087 if (hdw->ctl_write_buffer) {
2088 kfree(hdw->ctl_write_buffer);
2089 hdw->ctl_write_buffer = NULL;
2091 hdw->flag_disconnected = !0;
2092 hdw->usb_dev = NULL;
2093 hdw->usb_intf = NULL;
2094 pvr2_hdw_render_useless(hdw);
2098 /* Destroy hardware interaction structure */
2099 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2102 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2103 del_timer_sync(&hdw->quiescent_timer);
2104 del_timer_sync(&hdw->encoder_wait_timer);
2105 if (hdw->workqueue) {
2106 flush_workqueue(hdw->workqueue);
2107 destroy_workqueue(hdw->workqueue);
2108 hdw->workqueue = NULL;
2110 if (hdw->fw_buffer) {
2111 kfree(hdw->fw_buffer);
2112 hdw->fw_buffer = NULL;
2114 if (hdw->vid_stream) {
2115 pvr2_stream_destroy(hdw->vid_stream);
2116 hdw->vid_stream = NULL;
2118 if (hdw->decoder_ctrl) {
2119 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2121 pvr2_i2c_core_done(hdw);
2122 pvr2_hdw_remove_usb_stuff(hdw);
2123 mutex_lock(&pvr2_unit_mtx); do {
2124 if ((hdw->unit_number >= 0) &&
2125 (hdw->unit_number < PVR_NUM) &&
2126 (unit_pointers[hdw->unit_number] == hdw)) {
2127 unit_pointers[hdw->unit_number] = NULL;
2129 } while (0); mutex_unlock(&pvr2_unit_mtx);
2130 kfree(hdw->controls);
2131 kfree(hdw->mpeg_ctrl_info);
2132 kfree(hdw->std_defs);
2133 kfree(hdw->std_enum_names);
2138 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2140 return (hdw && hdw->flag_ok);
2144 /* Called when hardware has been unplugged */
2145 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2147 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2148 LOCK_TAKE(hdw->big_lock);
2149 LOCK_TAKE(hdw->ctl_lock);
2150 pvr2_hdw_remove_usb_stuff(hdw);
2151 LOCK_GIVE(hdw->ctl_lock);
2152 LOCK_GIVE(hdw->big_lock);
2156 // Attempt to autoselect an appropriate value for std_enum_cur given
2157 // whatever is currently in std_mask_cur
2158 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2161 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2162 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2163 hdw->std_enum_cur = idx;
2167 hdw->std_enum_cur = 0;
2171 // Calculate correct set of enumerated standards based on currently known
2172 // set of available standards bits.
2173 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2175 struct v4l2_standard *newstd;
2176 unsigned int std_cnt;
2179 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2181 if (hdw->std_defs) {
2182 kfree(hdw->std_defs);
2183 hdw->std_defs = NULL;
2185 hdw->std_enum_cnt = 0;
2186 if (hdw->std_enum_names) {
2187 kfree(hdw->std_enum_names);
2188 hdw->std_enum_names = NULL;
2193 PVR2_TRACE_ERROR_LEGS,
2194 "WARNING: Failed to identify any viable standards");
2196 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2197 hdw->std_enum_names[0] = "none";
2198 for (idx = 0; idx < std_cnt; idx++) {
2199 hdw->std_enum_names[idx+1] =
2202 // Set up the dynamic control for this standard
2203 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2204 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2205 hdw->std_defs = newstd;
2206 hdw->std_enum_cnt = std_cnt+1;
2207 hdw->std_enum_cur = 0;
2208 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2212 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2213 struct v4l2_standard *std,
2217 if (!idx) return ret;
2218 LOCK_TAKE(hdw->big_lock); do {
2219 if (idx >= hdw->std_enum_cnt) break;
2221 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2223 } while (0); LOCK_GIVE(hdw->big_lock);
2228 /* Get the number of defined controls */
2229 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2231 return hdw->control_cnt;
2235 /* Retrieve a control handle given its index (0..count-1) */
2236 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2239 if (idx >= hdw->control_cnt) return NULL;
2240 return hdw->controls + idx;
2244 /* Retrieve a control handle given its index (0..count-1) */
2245 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2246 unsigned int ctl_id)
2248 struct pvr2_ctrl *cptr;
2252 /* This could be made a lot more efficient, but for now... */
2253 for (idx = 0; idx < hdw->control_cnt; idx++) {
2254 cptr = hdw->controls + idx;
2255 i = cptr->info->internal_id;
2256 if (i && (i == ctl_id)) return cptr;
2262 /* Given a V4L ID, retrieve the control structure associated with it. */
2263 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2265 struct pvr2_ctrl *cptr;
2269 /* This could be made a lot more efficient, but for now... */
2270 for (idx = 0; idx < hdw->control_cnt; idx++) {
2271 cptr = hdw->controls + idx;
2272 i = cptr->info->v4l_id;
2273 if (i && (i == ctl_id)) return cptr;
2279 /* Given a V4L ID for its immediate predecessor, retrieve the control
2280 structure associated with it. */
2281 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2282 unsigned int ctl_id)
2284 struct pvr2_ctrl *cptr,*cp2;
2288 /* This could be made a lot more efficient, but for now... */
2290 for (idx = 0; idx < hdw->control_cnt; idx++) {
2291 cptr = hdw->controls + idx;
2292 i = cptr->info->v4l_id;
2294 if (i <= ctl_id) continue;
2295 if (cp2 && (cp2->info->v4l_id < i)) continue;
2303 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2306 case pvr2_ctl_int: return "integer";
2307 case pvr2_ctl_enum: return "enum";
2308 case pvr2_ctl_bool: return "boolean";
2309 case pvr2_ctl_bitmask: return "bitmask";
2315 /* Figure out if we need to commit control changes. If so, mark internal
2316 state flags to indicate this fact and return true. Otherwise do nothing
2317 else and return false. */
2318 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
2321 struct pvr2_ctrl *cptr;
2323 int commit_flag = 0;
2325 unsigned int bcnt,ccnt;
2327 for (idx = 0; idx < hdw->control_cnt; idx++) {
2328 cptr = hdw->controls + idx;
2329 if (!cptr->info->is_dirty) continue;
2330 if (!cptr->info->is_dirty(cptr)) continue;
2333 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
2334 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2337 cptr->info->get_value(cptr,&value);
2338 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2340 sizeof(buf)-bcnt,&ccnt);
2342 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2343 get_ctrl_typename(cptr->info->type));
2344 pvr2_trace(PVR2_TRACE_CTL,
2345 "/*--TRACE_COMMIT--*/ %.*s",
2350 /* Nothing has changed */
2354 hdw->state_pipeline_config = 0;
2355 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2356 pvr2_hdw_state_sched(hdw);
2362 /* Perform all operations needed to commit all control changes. This must
2363 be performed in synchronization with the pipeline state and is thus
2364 expected to be called as part of the driver's worker thread. Return
2365 true if commit successful, otherwise return false to indicate that
2366 commit isn't possible at this time. */
2367 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
2370 struct pvr2_ctrl *cptr;
2371 int disruptive_change;
2373 /* When video standard changes, reset the hres and vres values -
2374 but if the user has pending changes there, then let the changes
2376 if (hdw->std_dirty) {
2377 /* Rewrite the vertical resolution to be appropriate to the
2378 video standard that has been selected. */
2380 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2385 if (nvres != hdw->res_ver_val) {
2386 hdw->res_ver_val = nvres;
2387 hdw->res_ver_dirty = !0;
2391 if (hdw->input_dirty &&
2392 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
2393 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
2394 hdw->pathway_state)) {
2395 /* Change of mode being asked for... */
2396 hdw->state_pathway_ok = 0;
2398 if (!hdw->state_pathway_ok) {
2399 /* Can't commit anything until pathway is ok. */
2402 /* If any of the below has changed, then we can't do the update
2403 while the pipeline is running. Pipeline must be paused first
2404 and decoder -> encoder connection be made quiescent before we
2408 hdw->enc_unsafe_stale ||
2410 hdw->res_ver_dirty ||
2411 hdw->res_hor_dirty ||
2413 (hdw->active_stream_type != hdw->desired_stream_type));
2414 if (disruptive_change && !hdw->state_pipeline_idle) {
2415 /* Pipeline is not idle; we can't proceed. Arrange to
2416 cause pipeline to stop so that we can try this again
2418 hdw->state_pipeline_pause = !0;
2422 if (hdw->srate_dirty) {
2423 /* Write new sample rate into control structure since
2424 * the master copy is stale. We must track srate
2425 * separate from the mpeg control structure because
2426 * other logic also uses this value. */
2427 struct v4l2_ext_controls cs;
2428 struct v4l2_ext_control c1;
2429 memset(&cs,0,sizeof(cs));
2430 memset(&c1,0,sizeof(c1));
2433 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2434 c1.value = hdw->srate_val;
2435 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
2438 /* Scan i2c core at this point - before we clear all the dirty
2439 bits. Various parts of the i2c core will notice dirty bits as
2440 appropriate and arrange to broadcast or directly send updates to
2441 the client drivers in order to keep everything in sync */
2442 pvr2_i2c_core_check_stale(hdw);
2444 for (idx = 0; idx < hdw->control_cnt; idx++) {
2445 cptr = hdw->controls + idx;
2446 if (!cptr->info->clear_dirty) continue;
2447 cptr->info->clear_dirty(cptr);
2450 if (hdw->active_stream_type != hdw->desired_stream_type) {
2451 /* Handle any side effects of stream config here */
2452 hdw->active_stream_type = hdw->desired_stream_type;
2455 /* Now execute i2c core update */
2456 pvr2_i2c_core_sync(hdw);
2458 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
2459 hdw->state_encoder_run) {
2460 /* If encoder isn't running or it can't be touched, then
2461 this will get worked out later when we start the
2463 if (pvr2_encoder_adjust(hdw) < 0) return !0;
2466 hdw->state_pipeline_config = !0;
2467 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2472 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2475 LOCK_TAKE(hdw->big_lock);
2476 fl = pvr2_hdw_commit_setup(hdw);
2477 LOCK_GIVE(hdw->big_lock);
2479 return pvr2_hdw_wait(hdw,0);
2483 static void pvr2_hdw_worker_i2c(struct work_struct *work)
2485 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
2486 LOCK_TAKE(hdw->big_lock); do {
2487 pvr2_i2c_core_sync(hdw);
2488 } while (0); LOCK_GIVE(hdw->big_lock);
2492 static void pvr2_hdw_worker_poll(struct work_struct *work)
2495 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
2496 LOCK_TAKE(hdw->big_lock); do {
2497 fl = pvr2_hdw_state_eval(hdw);
2498 } while (0); LOCK_GIVE(hdw->big_lock);
2499 if (fl && hdw->state_func) {
2500 hdw->state_func(hdw->state_data);
2505 static void pvr2_hdw_worker_init(struct work_struct *work)
2507 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workinit);
2508 LOCK_TAKE(hdw->big_lock); do {
2509 pvr2_hdw_setup(hdw);
2510 } while (0); LOCK_GIVE(hdw->big_lock);
2514 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
2516 return wait_event_interruptible(
2517 hdw->state_wait_data,
2518 (hdw->state_stale == 0) &&
2519 (!state || (hdw->master_state != state)));
2523 void pvr2_hdw_set_state_callback(struct pvr2_hdw *hdw,
2524 void (*callback_func)(void *),
2525 void *callback_data)
2527 LOCK_TAKE(hdw->big_lock); do {
2528 hdw->state_data = callback_data;
2529 hdw->state_func = callback_func;
2530 } while (0); LOCK_GIVE(hdw->big_lock);
2534 /* Return name for this driver instance */
2535 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2541 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
2543 return hdw->hdw_desc->description;
2547 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
2549 return hdw->hdw_desc->shortname;
2553 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2556 LOCK_TAKE(hdw->ctl_lock); do {
2557 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
2558 result = pvr2_send_request(hdw,
2561 if (result < 0) break;
2562 result = (hdw->cmd_buffer[0] != 0);
2563 } while(0); LOCK_GIVE(hdw->ctl_lock);
2568 /* Execute poll of tuner status */
2569 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
2571 LOCK_TAKE(hdw->big_lock); do {
2572 pvr2_i2c_core_status_poll(hdw);
2573 } while (0); LOCK_GIVE(hdw->big_lock);
2577 /* Return information about the tuner */
2578 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
2580 LOCK_TAKE(hdw->big_lock); do {
2581 if (hdw->tuner_signal_stale) {
2582 pvr2_i2c_core_status_poll(hdw);
2584 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
2585 } while (0); LOCK_GIVE(hdw->big_lock);
2590 /* Get handle to video output stream */
2591 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2593 return hp->vid_stream;
2597 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2599 int nr = pvr2_hdw_get_unit_number(hdw);
2600 LOCK_TAKE(hdw->big_lock); do {
2601 hdw->log_requested = !0;
2602 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
2603 pvr2_i2c_core_check_stale(hdw);
2604 hdw->log_requested = 0;
2605 pvr2_i2c_core_sync(hdw);
2606 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
2607 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
2608 pvr2_hdw_state_log_state(hdw);
2609 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
2610 } while (0); LOCK_GIVE(hdw->big_lock);
2614 /* Grab EEPROM contents, needed for direct method. */
2615 #define EEPROM_SIZE 8192
2616 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
2617 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
2619 struct i2c_msg msg[2];
2628 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
2630 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2631 "Failed to allocate memory"
2632 " required to read eeprom");
2636 trace_eeprom("Value for eeprom addr from controller was 0x%x",
2638 addr = hdw->eeprom_addr;
2639 /* Seems that if the high bit is set, then the *real* eeprom
2640 address is shifted right now bit position (noticed this in
2641 newer PVR USB2 hardware) */
2642 if (addr & 0x80) addr >>= 1;
2644 /* FX2 documentation states that a 16bit-addressed eeprom is
2645 expected if the I2C address is an odd number (yeah, this is
2646 strange but it's what they do) */
2647 mode16 = (addr & 1);
2648 eepromSize = (mode16 ? EEPROM_SIZE : 256);
2649 trace_eeprom("Examining %d byte eeprom at location 0x%x"
2650 " using %d bit addressing",eepromSize,addr,
2655 msg[0].len = mode16 ? 2 : 1;
2658 msg[1].flags = I2C_M_RD;
2660 /* We have to do the actual eeprom data fetch ourselves, because
2661 (1) we're only fetching part of the eeprom, and (2) if we were
2662 getting the whole thing our I2C driver can't grab it in one
2663 pass - which is what tveeprom is otherwise going to attempt */
2664 memset(eeprom,0,EEPROM_SIZE);
2665 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
2667 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
2668 offs = tcnt + (eepromSize - EEPROM_SIZE);
2670 iadd[0] = offs >> 8;
2676 msg[1].buf = eeprom+tcnt;
2677 if ((ret = i2c_transfer(&hdw->i2c_adap,
2678 msg,ARRAY_SIZE(msg))) != 2) {
2679 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2680 "eeprom fetch set offs err=%d",ret);
2689 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
2696 LOCK_TAKE(hdw->big_lock); do {
2697 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
2700 pvr2_trace(PVR2_TRACE_FIRMWARE,
2701 "Cleaning up after CPU firmware fetch");
2702 kfree(hdw->fw_buffer);
2703 hdw->fw_buffer = NULL;
2705 if (hdw->fw_cpu_flag) {
2706 /* Now release the CPU. It will disconnect
2707 and reconnect later. */
2708 pvr2_hdw_cpureset_assert(hdw,0);
2713 hdw->fw_cpu_flag = (prom_flag == 0);
2714 if (hdw->fw_cpu_flag) {
2715 pvr2_trace(PVR2_TRACE_FIRMWARE,
2716 "Preparing to suck out CPU firmware");
2717 hdw->fw_size = 0x2000;
2718 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
2719 if (!hdw->fw_buffer) {
2724 /* We have to hold the CPU during firmware upload. */
2725 pvr2_hdw_cpureset_assert(hdw,1);
2727 /* download the firmware from address 0000-1fff in 2048
2728 (=0x800) bytes chunk. */
2730 pvr2_trace(PVR2_TRACE_FIRMWARE,
2731 "Grabbing CPU firmware");
2732 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2733 for(address = 0; address < hdw->fw_size;
2735 ret = usb_control_msg(hdw->usb_dev,pipe,
2738 hdw->fw_buffer+address,
2743 pvr2_trace(PVR2_TRACE_FIRMWARE,
2744 "Done grabbing CPU firmware");
2746 pvr2_trace(PVR2_TRACE_FIRMWARE,
2747 "Sucking down EEPROM contents");
2748 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
2749 if (!hdw->fw_buffer) {
2750 pvr2_trace(PVR2_TRACE_FIRMWARE,
2751 "EEPROM content suck failed.");
2754 hdw->fw_size = EEPROM_SIZE;
2755 pvr2_trace(PVR2_TRACE_FIRMWARE,
2756 "Done sucking down EEPROM contents");
2759 } while (0); LOCK_GIVE(hdw->big_lock);
2763 /* Return true if we're in a mode for retrieval CPU firmware */
2764 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2766 return hdw->fw_buffer != NULL;
2770 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2771 char *buf,unsigned int cnt)
2774 LOCK_TAKE(hdw->big_lock); do {
2778 if (!hdw->fw_buffer) {
2783 if (offs >= hdw->fw_size) {
2784 pvr2_trace(PVR2_TRACE_FIRMWARE,
2785 "Read firmware data offs=%d EOF",
2791 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2793 memcpy(buf,hdw->fw_buffer+offs,cnt);
2795 pvr2_trace(PVR2_TRACE_FIRMWARE,
2796 "Read firmware data offs=%d cnt=%d",
2799 } while (0); LOCK_GIVE(hdw->big_lock);
2805 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
2806 enum pvr2_v4l_type index)
2809 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
2810 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
2811 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
2817 /* Store a v4l minor device number */
2818 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
2819 enum pvr2_v4l_type index,int v)
2822 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
2823 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
2824 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
2830 static void pvr2_ctl_write_complete(struct urb *urb)
2832 struct pvr2_hdw *hdw = urb->context;
2833 hdw->ctl_write_pend_flag = 0;
2834 if (hdw->ctl_read_pend_flag) return;
2835 complete(&hdw->ctl_done);
2839 static void pvr2_ctl_read_complete(struct urb *urb)
2841 struct pvr2_hdw *hdw = urb->context;
2842 hdw->ctl_read_pend_flag = 0;
2843 if (hdw->ctl_write_pend_flag) return;
2844 complete(&hdw->ctl_done);
2848 static void pvr2_ctl_timeout(unsigned long data)
2850 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2851 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2852 hdw->ctl_timeout_flag = !0;
2853 if (hdw->ctl_write_pend_flag)
2854 usb_unlink_urb(hdw->ctl_write_urb);
2855 if (hdw->ctl_read_pend_flag)
2856 usb_unlink_urb(hdw->ctl_read_urb);
2861 /* Issue a command and get a response from the device. This extended
2862 version includes a probe flag (which if set means that device errors
2863 should not be logged or treated as fatal) and a timeout in jiffies.
2864 This can be used to non-lethally probe the health of endpoint 1. */
2865 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2866 unsigned int timeout,int probe_fl,
2867 void *write_data,unsigned int write_len,
2868 void *read_data,unsigned int read_len)
2872 struct timer_list timer;
2873 if (!hdw->ctl_lock_held) {
2874 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2875 "Attempted to execute control transfer"
2879 if (!hdw->flag_ok && !probe_fl) {
2880 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2881 "Attempted to execute control transfer"
2882 " when device not ok");
2885 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2887 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2888 "Attempted to execute control transfer"
2889 " when USB is disconnected");
2894 /* Ensure that we have sane parameters */
2895 if (!write_data) write_len = 0;
2896 if (!read_data) read_len = 0;
2897 if (write_len > PVR2_CTL_BUFFSIZE) {
2899 PVR2_TRACE_ERROR_LEGS,
2900 "Attempted to execute %d byte"
2901 " control-write transfer (limit=%d)",
2902 write_len,PVR2_CTL_BUFFSIZE);
2905 if (read_len > PVR2_CTL_BUFFSIZE) {
2907 PVR2_TRACE_ERROR_LEGS,
2908 "Attempted to execute %d byte"
2909 " control-read transfer (limit=%d)",
2910 write_len,PVR2_CTL_BUFFSIZE);
2913 if ((!write_len) && (!read_len)) {
2915 PVR2_TRACE_ERROR_LEGS,
2916 "Attempted to execute null control transfer?");
2921 hdw->cmd_debug_state = 1;
2923 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2925 hdw->cmd_debug_code = 0;
2927 hdw->cmd_debug_write_len = write_len;
2928 hdw->cmd_debug_read_len = read_len;
2930 /* Initialize common stuff */
2931 init_completion(&hdw->ctl_done);
2932 hdw->ctl_timeout_flag = 0;
2933 hdw->ctl_write_pend_flag = 0;
2934 hdw->ctl_read_pend_flag = 0;
2936 timer.expires = jiffies + timeout;
2937 timer.data = (unsigned long)hdw;
2938 timer.function = pvr2_ctl_timeout;
2941 hdw->cmd_debug_state = 2;
2942 /* Transfer write data to internal buffer */
2943 for (idx = 0; idx < write_len; idx++) {
2944 hdw->ctl_write_buffer[idx] =
2945 ((unsigned char *)write_data)[idx];
2947 /* Initiate a write request */
2948 usb_fill_bulk_urb(hdw->ctl_write_urb,
2950 usb_sndbulkpipe(hdw->usb_dev,
2951 PVR2_CTL_WRITE_ENDPOINT),
2952 hdw->ctl_write_buffer,
2954 pvr2_ctl_write_complete,
2956 hdw->ctl_write_urb->actual_length = 0;
2957 hdw->ctl_write_pend_flag = !0;
2958 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2960 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2961 "Failed to submit write-control"
2962 " URB status=%d",status);
2963 hdw->ctl_write_pend_flag = 0;
2969 hdw->cmd_debug_state = 3;
2970 memset(hdw->ctl_read_buffer,0x43,read_len);
2971 /* Initiate a read request */
2972 usb_fill_bulk_urb(hdw->ctl_read_urb,
2974 usb_rcvbulkpipe(hdw->usb_dev,
2975 PVR2_CTL_READ_ENDPOINT),
2976 hdw->ctl_read_buffer,
2978 pvr2_ctl_read_complete,
2980 hdw->ctl_read_urb->actual_length = 0;
2981 hdw->ctl_read_pend_flag = !0;
2982 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
2984 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2985 "Failed to submit read-control"
2986 " URB status=%d",status);
2987 hdw->ctl_read_pend_flag = 0;
2995 /* Now wait for all I/O to complete */
2996 hdw->cmd_debug_state = 4;
2997 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2998 wait_for_completion(&hdw->ctl_done);
3000 hdw->cmd_debug_state = 5;
3003 del_timer_sync(&timer);
3005 hdw->cmd_debug_state = 6;
3008 if (hdw->ctl_timeout_flag) {
3009 status = -ETIMEDOUT;
3011 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3012 "Timed out control-write");
3018 /* Validate results of write request */
3019 if ((hdw->ctl_write_urb->status != 0) &&
3020 (hdw->ctl_write_urb->status != -ENOENT) &&
3021 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3022 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3023 /* USB subsystem is reporting some kind of failure
3025 status = hdw->ctl_write_urb->status;
3027 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3028 "control-write URB failure,"
3034 if (hdw->ctl_write_urb->actual_length < write_len) {
3035 /* Failed to write enough data */
3038 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3039 "control-write URB short,"
3040 " expected=%d got=%d",
3042 hdw->ctl_write_urb->actual_length);
3048 /* Validate results of read request */
3049 if ((hdw->ctl_read_urb->status != 0) &&
3050 (hdw->ctl_read_urb->status != -ENOENT) &&
3051 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3052 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3053 /* USB subsystem is reporting some kind of failure
3055 status = hdw->ctl_read_urb->status;
3057 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3058 "control-read URB failure,"
3064 if (hdw->ctl_read_urb->actual_length < read_len) {
3065 /* Failed to read enough data */
3068 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3069 "control-read URB short,"
3070 " expected=%d got=%d",
3072 hdw->ctl_read_urb->actual_length);
3076 /* Transfer retrieved data out from internal buffer */
3077 for (idx = 0; idx < read_len; idx++) {
3078 ((unsigned char *)read_data)[idx] =
3079 hdw->ctl_read_buffer[idx];
3085 hdw->cmd_debug_state = 0;
3086 if ((status < 0) && (!probe_fl)) {
3087 pvr2_hdw_render_useless(hdw);
3093 int pvr2_send_request(struct pvr2_hdw *hdw,
3094 void *write_data,unsigned int write_len,
3095 void *read_data,unsigned int read_len)
3097 return pvr2_send_request_ex(hdw,HZ*4,0,
3098 write_data,write_len,
3099 read_data,read_len);
3102 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3106 LOCK_TAKE(hdw->ctl_lock);
3108 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
3109 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3110 hdw->cmd_buffer[5] = 0;
3111 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3112 hdw->cmd_buffer[7] = reg & 0xff;
3115 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3117 LOCK_GIVE(hdw->ctl_lock);
3123 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3127 LOCK_TAKE(hdw->ctl_lock);
3129 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
3130 hdw->cmd_buffer[1] = 0;
3131 hdw->cmd_buffer[2] = 0;
3132 hdw->cmd_buffer[3] = 0;
3133 hdw->cmd_buffer[4] = 0;
3134 hdw->cmd_buffer[5] = 0;
3135 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3136 hdw->cmd_buffer[7] = reg & 0xff;
3138 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3139 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3141 LOCK_GIVE(hdw->ctl_lock);
3147 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3149 if (!hdw->flag_ok) return;
3150 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3151 "Device being rendered inoperable");
3152 if (hdw->vid_stream) {
3153 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3156 trace_stbit("flag_ok",hdw->flag_ok);
3157 pvr2_hdw_state_sched(hdw);
3161 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3164 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3165 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3167 ret = usb_reset_device(hdw->usb_dev);
3168 usb_unlock_device(hdw->usb_dev);
3170 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3171 "Failed to lock USB device ret=%d",ret);
3173 if (init_pause_msec) {
3174 pvr2_trace(PVR2_TRACE_INFO,
3175 "Waiting %u msec for hardware to settle",
3177 msleep(init_pause_msec);
3183 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3189 if (!hdw->usb_dev) return;
3191 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3193 da[0] = val ? 0x01 : 0x00;
3195 /* Write the CPUCS register on the 8051. The lsb of the register
3196 is the reset bit; a 1 asserts reset while a 0 clears it. */
3197 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3198 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3200 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3201 "cpureset_assert(%d) error=%d",val,ret);
3202 pvr2_hdw_render_useless(hdw);
3207 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3210 LOCK_TAKE(hdw->ctl_lock); do {
3211 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
3212 hdw->cmd_buffer[0] = FX2CMD_DEEP_RESET;
3213 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
3214 } while (0); LOCK_GIVE(hdw->ctl_lock);
3219 static int pvr2_hdw_cmd_power_ctrl(struct pvr2_hdw *hdw, int onoff)
3222 LOCK_TAKE(hdw->ctl_lock); do {
3224 pvr2_trace(PVR2_TRACE_INIT, "Requesting powerup");
3225 hdw->cmd_buffer[0] = FX2CMD_POWER_ON;
3227 pvr2_trace(PVR2_TRACE_INIT, "Requesting powerdown");
3228 hdw->cmd_buffer[0] = FX2CMD_POWER_OFF;
3230 status = pvr2_send_request(hdw, hdw->cmd_buffer, 1, NULL, 0);
3231 } while (0); LOCK_GIVE(hdw->ctl_lock);
3235 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3237 return pvr2_hdw_cmd_power_ctrl(hdw, 1);
3240 int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
3242 return pvr2_hdw_cmd_power_ctrl(hdw, 0);
3246 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3248 if (!hdw->decoder_ctrl) {
3249 pvr2_trace(PVR2_TRACE_INIT,
3250 "Unable to reset decoder: nothing attached");
3254 if (!hdw->decoder_ctrl->force_reset) {
3255 pvr2_trace(PVR2_TRACE_INIT,
3256 "Unable to reset decoder: not implemented");
3260 pvr2_trace(PVR2_TRACE_INIT,
3261 "Requesting decoder reset");
3262 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3267 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
3271 LOCK_TAKE(hdw->ctl_lock); do {
3272 pvr2_trace(PVR2_TRACE_INIT,
3273 "Issuing fe demod wake command (%s)",
3274 (onoff ? "on" : "off"));
3276 hdw->cmd_buffer[0] = FX2CMD_HCW_DEMOD_RESETIN;
3277 hdw->cmd_buffer[1] = onoff;
3278 status = pvr2_send_request(hdw, hdw->cmd_buffer, 2, NULL, 0);
3279 } while (0); LOCK_GIVE(hdw->ctl_lock);
3285 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
3289 LOCK_TAKE(hdw->ctl_lock); do {
3290 pvr2_trace(PVR2_TRACE_INIT,
3291 "Issuing fe power command to CPLD (%s)",
3292 (onoff ? "on" : "off"));
3294 hdw->cmd_buffer[0] =
3295 (onoff ? FX2CMD_ONAIR_DTV_POWER_ON :
3296 FX2CMD_ONAIR_DTV_POWER_OFF);
3297 status = pvr2_send_request(hdw, hdw->cmd_buffer, 1, NULL, 0);
3298 } while (0); LOCK_GIVE(hdw->ctl_lock);
3304 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
3308 LOCK_TAKE(hdw->ctl_lock); do {
3309 pvr2_trace(PVR2_TRACE_INIT,
3310 "Issuing onair digital setup command (%s)",
3311 (onoff ? "on" : "off"));
3312 hdw->cmd_buffer[0] =
3313 (onoff ? FX2CMD_ONAIR_DTV_STREAMING_ON :
3314 FX2CMD_ONAIR_DTV_STREAMING_OFF);
3315 status = pvr2_send_request(hdw, hdw->cmd_buffer, 1, NULL, 0);
3316 } while (0); LOCK_GIVE(hdw->ctl_lock);
3321 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
3324 /* Compare digital/analog desired setting with current setting. If
3325 they don't match, fix it... */
3326 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
3327 if (cmode == hdw->pathway_state) {
3328 /* They match; nothing to do */
3332 switch (hdw->hdw_desc->digital_control_scheme) {
3333 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
3334 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
3335 if (cmode == PVR2_PATHWAY_ANALOG) {
3336 /* If moving to analog mode, also force the decoder
3337 to reset. If no decoder is attached, then it's
3338 ok to ignore this because if/when the decoder
3339 attaches, it will reset itself at that time. */
3340 pvr2_hdw_cmd_decoder_reset(hdw);
3343 case PVR2_DIGITAL_SCHEME_ONAIR:
3344 /* Supposedly we should always have the power on whether in
3345 digital or analog mode. But for now do what appears to
3347 if (digitalFl) pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,!0);
3348 pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,digitalFl);
3349 if (!digitalFl) pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,0);
3354 hdw->pathway_state = cmode;
3358 /* Stop / start video stream transport */
3359 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
3362 if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
3363 hdw->hdw_desc->digital_control_scheme ==
3364 PVR2_DIGITAL_SCHEME_HAUPPAUGE) {
3366 FX2CMD_HCW_DTV_STREAMING_ON :
3367 FX2CMD_HCW_DTV_STREAMING_OFF);
3370 FX2CMD_STREAMING_ON :
3371 FX2CMD_STREAMING_OFF);
3374 LOCK_TAKE(hdw->ctl_lock); do {
3375 hdw->cmd_buffer[0] = cc;
3376 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
3377 } while (0); LOCK_GIVE(hdw->ctl_lock);
3382 /* Evaluate whether or not state_pathway_ok can change */
3383 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
3385 if (hdw->state_pathway_ok) {
3386 /* Nothing to do if pathway is already ok */
3389 if (!hdw->state_pipeline_idle) {
3390 /* Not allowed to change anything if pipeline is not idle */
3393 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
3394 hdw->state_pathway_ok = !0;
3399 /* Evaluate whether or not state_encoder_ok can change */
3400 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
3402 if (hdw->state_encoder_ok) return 0;
3403 if (hdw->flag_tripped) return 0;
3404 if (hdw->state_encoder_run) return 0;
3405 if (hdw->state_encoder_config) return 0;
3406 if (hdw->state_decoder_run) return 0;
3407 if (hdw->state_usbstream_run) return 0;
3408 if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) return 0;
3409 if (pvr2_upload_firmware2(hdw) < 0) {
3410 hdw->flag_tripped = !0;
3411 trace_stbit("flag_tripped",hdw->flag_tripped);
3414 hdw->state_encoder_ok = !0;
3415 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
3420 /* Evaluate whether or not state_encoder_config can change */
3421 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
3423 if (hdw->state_encoder_config) {
3424 if (hdw->state_encoder_ok) {
3425 if (hdw->state_pipeline_req &&
3426 !hdw->state_pipeline_pause) return 0;
3428 hdw->state_encoder_config = 0;
3429 hdw->state_encoder_waitok = 0;
3430 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3431 /* paranoia - solve race if timer just completed */
3432 del_timer_sync(&hdw->encoder_wait_timer);
3434 if (!hdw->state_pathway_ok ||
3435 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
3436 !hdw->state_encoder_ok ||
3437 !hdw->state_pipeline_idle ||
3438 hdw->state_pipeline_pause ||
3439 !hdw->state_pipeline_req ||
3440 !hdw->state_pipeline_config) {
3441 /* We must reset the enforced wait interval if
3442 anything has happened that might have disturbed
3443 the encoder. This should be a rare case. */
3444 if (timer_pending(&hdw->encoder_wait_timer)) {
3445 del_timer_sync(&hdw->encoder_wait_timer);
3447 if (hdw->state_encoder_waitok) {
3448 /* Must clear the state - therefore we did
3449 something to a state bit and must also
3451 hdw->state_encoder_waitok = 0;
3452 trace_stbit("state_encoder_waitok",
3453 hdw->state_encoder_waitok);
3458 if (!hdw->state_encoder_waitok) {
3459 if (!timer_pending(&hdw->encoder_wait_timer)) {
3460 /* waitok flag wasn't set and timer isn't
3461 running. Check flag once more to avoid
3462 a race then start the timer. This is
3463 the point when we measure out a minimal
3464 quiet interval before doing something to
3466 if (!hdw->state_encoder_waitok) {
3467 hdw->encoder_wait_timer.expires =
3468 jiffies + (HZ*50/1000);
3469 add_timer(&hdw->encoder_wait_timer);
3472 /* We can't continue until we know we have been
3473 quiet for the interval measured by this
3477 pvr2_encoder_configure(hdw);
3478 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
3480 trace_stbit("state_encoder_config",hdw->state_encoder_config);
3485 /* Evaluate whether or not state_encoder_run can change */
3486 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
3488 if (hdw->state_encoder_run) {
3489 if (hdw->state_encoder_ok) {
3490 if (hdw->state_decoder_run &&
3491 hdw->state_pathway_ok) return 0;
3492 if (pvr2_encoder_stop(hdw) < 0) return !0;
3494 hdw->state_encoder_run = 0;
3496 if (!hdw->state_encoder_ok) return 0;
3497 if (!hdw->state_decoder_run) return 0;
3498 if (!hdw->state_pathway_ok) return 0;
3499 if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) return 0;
3500 if (pvr2_encoder_start(hdw) < 0) return !0;
3501 hdw->state_encoder_run = !0;
3503 trace_stbit("state_encoder_run",hdw->state_encoder_run);
3508 /* Timeout function for quiescent timer. */
3509 static void pvr2_hdw_quiescent_timeout(unsigned long data)
3511 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3512 hdw->state_decoder_quiescent = !0;
3513 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3514 hdw->state_stale = !0;
3515 queue_work(hdw->workqueue,&hdw->workpoll);
3519 /* Timeout function for encoder wait timer. */
3520 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
3522 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3523 hdw->state_encoder_waitok = !0;
3524 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3525 hdw->state_stale = !0;
3526 queue_work(hdw->workqueue,&hdw->workpoll);
3530 /* Evaluate whether or not state_decoder_run can change */
3531 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
3533 if (hdw->state_decoder_run) {
3534 if (hdw->state_encoder_ok) {
3535 if (hdw->state_pipeline_req &&
3536 !hdw->state_pipeline_pause &&
3537 hdw->state_pathway_ok) return 0;
3539 if (!hdw->flag_decoder_missed) {
3540 pvr2_decoder_enable(hdw,0);
3542 hdw->state_decoder_quiescent = 0;
3543 hdw->state_decoder_run = 0;
3544 /* paranoia - solve race if timer just completed */
3545 del_timer_sync(&hdw->quiescent_timer);
3547 if (!hdw->state_decoder_quiescent) {
3548 if (!timer_pending(&hdw->quiescent_timer)) {
3549 /* We don't do something about the
3550 quiescent timer until right here because
3551 we also want to catch cases where the
3552 decoder was already not running (like
3553 after initialization) as opposed to
3554 knowing that we had just stopped it.
3555 The second flag check is here to cover a
3556 race - the timer could have run and set
3557 this flag just after the previous check
3558 but before we did the pending check. */
3559 if (!hdw->state_decoder_quiescent) {
3560 hdw->quiescent_timer.expires =
3561 jiffies + (HZ*50/1000);
3562 add_timer(&hdw->quiescent_timer);
3565 /* Don't allow decoder to start again until it has
3566 been quiesced first. This little detail should
3567 hopefully further stabilize the encoder. */
3570 if (!hdw->state_pathway_ok ||
3571 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
3572 !hdw->state_pipeline_req ||
3573 hdw->state_pipeline_pause ||
3574 !hdw->state_pipeline_config ||
3575 !hdw->state_encoder_config ||
3576 !hdw->state_encoder_ok) return 0;
3577 del_timer_sync(&hdw->quiescent_timer);
3578 if (hdw->flag_decoder_missed) return 0;
3579 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
3580 hdw->state_decoder_quiescent = 0;
3581 hdw->state_decoder_run = !0;
3583 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3584 trace_stbit("state_decoder_run",hdw->state_decoder_run);
3589 /* Evaluate whether or not state_usbstream_run can change */
3590 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
3592 if (hdw->state_usbstream_run) {
3593 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
3594 if (hdw->state_encoder_ok &&
3595 hdw->state_encoder_run &&
3596 hdw->state_pathway_ok) return 0;
3598 if (hdw->state_pipeline_req &&
3599 !hdw->state_pipeline_pause &&
3600 hdw->state_pathway_ok) return 0;
3602 pvr2_hdw_cmd_usbstream(hdw,0);
3603 hdw->state_usbstream_run = 0;
3605 if (!hdw->state_pipeline_req ||
3606 hdw->state_pipeline_pause ||
3607 !hdw->state_pathway_ok) return 0;
3608 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
3609 if (!hdw->state_encoder_ok ||
3610 !hdw->state_encoder_run) return 0;
3612 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
3613 hdw->state_usbstream_run = !0;
3615 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
3620 /* Attempt to configure pipeline, if needed */
3621 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
3623 if (hdw->state_pipeline_config ||
3624 hdw->state_pipeline_pause) return 0;
3625 pvr2_hdw_commit_execute(hdw);
3630 /* Update pipeline idle and pipeline pause tracking states based on other
3631 inputs. This must be called whenever the other relevant inputs have
3633 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
3637 /* Update pipeline state */
3638 st = !(hdw->state_encoder_run ||
3639 hdw->state_decoder_run ||
3640 hdw->state_usbstream_run ||
3641 (!hdw->state_decoder_quiescent));
3642 if (!st != !hdw->state_pipeline_idle) {
3643 hdw->state_pipeline_idle = st;
3646 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
3647 hdw->state_pipeline_pause = 0;
3654 typedef int (*state_eval_func)(struct pvr2_hdw *);
3656 /* Set of functions to be run to evaluate various states in the driver. */
3657 const static state_eval_func eval_funcs[] = {
3658 state_eval_pathway_ok,
3659 state_eval_pipeline_config,
3660 state_eval_encoder_ok,
3661 state_eval_encoder_config,
3662 state_eval_decoder_run,
3663 state_eval_encoder_run,
3664 state_eval_usbstream_run,
3668 /* Process various states and return true if we did anything interesting. */
3669 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
3672 int state_updated = 0;
3675 if (!hdw->state_stale) return 0;
3676 if ((hdw->fw1_state != FW1_STATE_OK) ||
3678 hdw->state_stale = 0;
3681 /* This loop is the heart of the entire driver. It keeps trying to
3682 evaluate various bits of driver state until nothing changes for
3683 one full iteration. Each "bit of state" tracks some global
3684 aspect of the driver, e.g. whether decoder should run, if
3685 pipeline is configured, usb streaming is on, etc. We separately
3686 evaluate each of those questions based on other driver state to
3687 arrive at the correct running configuration. */
3690 state_update_pipeline_state(hdw);
3691 /* Iterate over each bit of state */
3692 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
3693 if ((*eval_funcs[i])(hdw)) {
3696 state_update_pipeline_state(hdw);
3699 } while (check_flag && hdw->flag_ok);
3700 hdw->state_stale = 0;
3701 trace_stbit("state_stale",hdw->state_stale);
3702 return state_updated;
3706 static const char *pvr2_pathway_state_name(int id)
3709 case PVR2_PATHWAY_ANALOG: return "analog";
3710 case PVR2_PATHWAY_DIGITAL: return "digital";
3711 default: return "unknown";
3716 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
3717 char *buf,unsigned int acnt)
3723 "driver:%s%s%s%s%s<mode=%s>",
3724 (hdw->flag_ok ? " <ok>" : " <fail>"),
3725 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
3726 (hdw->flag_disconnected ? " <disconnected>" :
3728 (hdw->flag_tripped ? " <tripped>" : ""),
3729 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
3730 pvr2_pathway_state_name(hdw->pathway_state));
3735 "pipeline:%s%s%s%s",
3736 (hdw->state_pipeline_idle ? " <idle>" : ""),
3737 (hdw->state_pipeline_config ?
3738 " <configok>" : " <stale>"),
3739 (hdw->state_pipeline_req ? " <req>" : ""),
3740 (hdw->state_pipeline_pause ? " <pause>" : ""));
3744 "worker:%s%s%s%s%s%s%s",
3745 (hdw->state_decoder_run ?
3747 (hdw->state_decoder_quiescent ?
3748 "" : " <decode:stop>")),
3749 (hdw->state_decoder_quiescent ?
3750 " <decode:quiescent>" : ""),
3751 (hdw->state_encoder_ok ?
3752 "" : " <encode:init>"),
3753 (hdw->state_encoder_run ?
3754 " <encode:run>" : " <encode:stop>"),
3755 (hdw->state_encoder_config ?
3756 " <encode:configok>" :
3757 (hdw->state_encoder_waitok ?
3758 "" : " <encode:wait>")),
3759 (hdw->state_usbstream_run ?
3760 " <usb:run>" : " <usb:stop>"),
3761 (hdw->state_pathway_ok ?
3762 "<pathway:ok>" : ""));
3768 pvr2_get_state_name(hdw->master_state));
3776 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
3777 char *buf,unsigned int acnt)
3779 unsigned int bcnt,ccnt,idx;
3781 LOCK_TAKE(hdw->big_lock);
3782 for (idx = 0; ; idx++) {
3783 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
3785 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
3787 buf[0] = '\n'; ccnt = 1;
3788 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
3790 LOCK_GIVE(hdw->big_lock);
3795 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
3798 unsigned int idx,ccnt;
3800 for (idx = 0; ; idx++) {
3801 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
3803 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
3808 /* Evaluate and update the driver's current state, taking various actions
3809 as appropriate for the update. */
3810 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
3813 int state_updated = 0;
3814 int callback_flag = 0;
3816 pvr2_trace(PVR2_TRACE_STBITS,
3817 "Drive state check START");
3818 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
3819 pvr2_hdw_state_log_state(hdw);
3822 /* Process all state and get back over disposition */
3823 state_updated = pvr2_hdw_state_update(hdw);
3825 /* Update master state based upon all other states. */
3826 if (!hdw->flag_ok) {
3827 st = PVR2_STATE_DEAD;
3828 } else if (hdw->fw1_state != FW1_STATE_OK) {
3829 st = PVR2_STATE_COLD;
3830 } else if (!hdw->state_encoder_ok) {
3831 st = PVR2_STATE_WARM;
3832 } else if (hdw->flag_tripped || hdw->flag_decoder_missed) {
3833 st = PVR2_STATE_ERROR;
3834 } else if (hdw->state_usbstream_run &&
3835 ((hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
3836 (hdw->state_encoder_run && hdw->state_decoder_run))) {
3837 st = PVR2_STATE_RUN;
3839 st = PVR2_STATE_READY;
3841 if (hdw->master_state != st) {
3842 pvr2_trace(PVR2_TRACE_STATE,
3843 "Device state change from %s to %s",
3844 pvr2_get_state_name(hdw->master_state),
3845 pvr2_get_state_name(st));
3846 hdw->master_state = st;
3850 if (state_updated) {
3851 /* Trigger anyone waiting on any state changes here. */
3852 wake_up(&hdw->state_wait_data);
3855 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
3856 pvr2_hdw_state_log_state(hdw);
3858 pvr2_trace(PVR2_TRACE_STBITS,
3859 "Drive state check DONE callback=%d",callback_flag);
3861 return callback_flag;
3865 /* Cause kernel thread to check / update driver state */
3866 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
3868 if (hdw->state_stale) return;
3869 hdw->state_stale = !0;
3870 trace_stbit("state_stale",hdw->state_stale);
3871 queue_work(hdw->workqueue,&hdw->workpoll);
3875 void pvr2_hdw_get_debug_info_unlocked(const struct pvr2_hdw *hdw,
3876 struct pvr2_hdw_debug_info *ptr)
3878 ptr->big_lock_held = hdw->big_lock_held;
3879 ptr->ctl_lock_held = hdw->ctl_lock_held;
3880 ptr->flag_disconnected = hdw->flag_disconnected;
3881 ptr->flag_init_ok = hdw->flag_init_ok;
3882 ptr->flag_ok = hdw->flag_ok;
3883 ptr->fw1_state = hdw->fw1_state;
3884 ptr->flag_decoder_missed = hdw->flag_decoder_missed;
3885 ptr->flag_tripped = hdw->flag_tripped;
3886 ptr->state_encoder_ok = hdw->state_encoder_ok;
3887 ptr->state_encoder_run = hdw->state_encoder_run;
3888 ptr->state_decoder_run = hdw->state_decoder_run;
3889 ptr->state_usbstream_run = hdw->state_usbstream_run;
3890 ptr->state_decoder_quiescent = hdw->state_decoder_quiescent;
3891 ptr->state_pipeline_config = hdw->state_pipeline_config;
3892 ptr->state_pipeline_req = hdw->state_pipeline_req;
3893 ptr->state_pipeline_pause = hdw->state_pipeline_pause;
3894 ptr->state_pipeline_idle = hdw->state_pipeline_idle;
3895 ptr->cmd_debug_state = hdw->cmd_debug_state;
3896 ptr->cmd_code = hdw->cmd_debug_code;
3897 ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
3898 ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
3899 ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
3900 ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
3901 ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
3902 ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
3903 ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
3907 void pvr2_hdw_get_debug_info_locked(struct pvr2_hdw *hdw,
3908 struct pvr2_hdw_debug_info *ptr)
3910 LOCK_TAKE(hdw->ctl_lock); do {
3911 pvr2_hdw_get_debug_info_unlocked(hdw,ptr);
3912 } while(0); LOCK_GIVE(hdw->ctl_lock);
3916 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
3918 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
3922 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
3924 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
3928 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
3930 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
3934 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
3939 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
3940 if (ret) return ret;
3941 nval = (cval & ~msk) | (val & msk);
3942 pvr2_trace(PVR2_TRACE_GPIO,
3943 "GPIO direction changing 0x%x:0x%x"
3944 " from 0x%x to 0x%x",
3948 pvr2_trace(PVR2_TRACE_GPIO,
3949 "GPIO direction changing to 0x%x",nval);
3951 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
3955 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
3960 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
3961 if (ret) return ret;
3962 nval = (cval & ~msk) | (val & msk);
3963 pvr2_trace(PVR2_TRACE_GPIO,
3964 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
3968 pvr2_trace(PVR2_TRACE_GPIO,
3969 "GPIO output changing to 0x%x",nval);
3971 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
3975 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
3977 return hdw->input_avail_mask;
3981 /* Find I2C address of eeprom */
3982 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
3985 LOCK_TAKE(hdw->ctl_lock); do {
3986 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
3987 result = pvr2_send_request(hdw,
3990 if (result < 0) break;
3991 result = hdw->cmd_buffer[0];
3992 } while(0); LOCK_GIVE(hdw->ctl_lock);
3997 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
3998 u32 match_type, u32 match_chip, u64 reg_id,
3999 int setFl,u64 *val_ptr)
4001 #ifdef CONFIG_VIDEO_ADV_DEBUG
4002 struct pvr2_i2c_client *cp;
4003 struct v4l2_register req;
4007 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
4009 req.match_type = match_type;
4010 req.match_chip = match_chip;
4012 if (setFl) req.val = *val_ptr;
4013 mutex_lock(&hdw->i2c_list_lock); do {
4014 list_for_each_entry(cp, &hdw->i2c_clients, list) {
4015 if (!v4l2_chip_match_i2c_client(
4017 req.match_type, req.match_chip)) {
4020 stat = pvr2_i2c_client_cmd(
4021 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
4022 VIDIOC_DBG_G_REGISTER),&req);
4023 if (!setFl) *val_ptr = req.val;
4027 } while (0); mutex_unlock(&hdw->i2c_list_lock);
4039 Stuff for Emacs to see, in order to encourage consistent editing style:
4040 *** Local Variables: ***
4042 *** fill-column: 75 ***
4043 *** tab-width: 8 ***
4044 *** c-basic-offset: 8 ***