err.no Git - linux-2.6/blob - drivers/media/video/cx23885/cx23885-core.c

   1 /*
   2  *  Driver for the Conexant CX23885 PCIe bridge
   3  *
   4  *  Copyright (c) 2006 Steven Toth <stoth@hauppauge.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/list.h>
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/kmod.h>
  27 #include <linux/kernel.h>
  28 #include <linux/slab.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/delay.h>
  31 #include <asm/div64.h>
  32
  33 #include "cx23885.h"
  34
  35 MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
  36 MODULE_AUTHOR("Steven Toth <stoth@hauppauge.com>");
  37 MODULE_LICENSE("GPL");
  38
  39 static unsigned int debug;
  40 module_param(debug,int,0644);
  41 MODULE_PARM_DESC(debug,"enable debug messages");
  42
  43 static unsigned int card[]  = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
  44 module_param_array(card,  int, NULL, 0444);
  45 MODULE_PARM_DESC(card,"card type");
  46
  47 #define dprintk(level, fmt, arg...)\
  48         do { if (debug >= level)\
  49                 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
  50         } while (0)
  51
  52 static unsigned int cx23885_devcount;
  53
  54 static DEFINE_MUTEX(devlist);
  55 LIST_HEAD(cx23885_devlist);
  56
  57 #define NO_SYNC_LINE (-1U)
  58
  59 /*
  60  * CX23885 Assumptions
  61  * 1 line = 16 bytes of CDT
  62  * cmds size = 80
  63  * cdt size = 16 * linesize
  64  * iqsize = 64
  65  * maxlines = 6
  66  *
  67  * Address Space:
  68  * 0x00000000 0x00008fff FIFO clusters
  69  * 0x00010000 0x000104af Channel Management Data Structures
  70  * 0x000104b0 0x000104ff Free
  71  * 0x00010500 0x000108bf 15 channels * iqsize
  72  * 0x000108c0 0x000108ff Free
  73  * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
  74  *                       15 channels * (iqsize + (maxlines * linesize))
  75  * 0x00010ea0 0x00010xxx Free
  76  */
  77
  78 static struct sram_channel cx23885_sram_channels[] = {
  79         [SRAM_CH01] = {
  80                 .name           = "VID A",
  81                 .cmds_start     = 0x10000,
  82                 .ctrl_start     = 0x105b0,
  83                 .cdt            = 0x107b0,
  84                 .fifo_start     = 0x40,
  85                 .fifo_size      = 0x2800,
  86                 .ptr1_reg       = DMA1_PTR1,
  87                 .ptr2_reg       = DMA1_PTR2,
  88                 .cnt1_reg       = DMA1_CNT1,
  89                 .cnt2_reg       = DMA1_CNT2,
  90                 .jumponly       = 1,
  91         },
  92         [SRAM_CH02] = {
  93                 .name           = "ch2",
  94                 .cmds_start     = 0x0,
  95                 .ctrl_start     = 0x0,
  96                 .cdt            = 0x0,
  97                 .fifo_start     = 0x0,
  98                 .fifo_size      = 0x0,
  99                 .ptr1_reg       = DMA2_PTR1,
 100                 .ptr2_reg       = DMA2_PTR2,
 101                 .cnt1_reg       = DMA2_CNT1,
 102                 .cnt2_reg       = DMA2_CNT2,
 103         },
 104         [SRAM_CH03] = {
 105                 .name           = "TS1 B",
 106                 .cmds_start     = 0x100A0,
 107                 .ctrl_start     = 0x10630,
 108                 .cdt            = 0x10870,
 109                 .fifo_start     = 0x5000,
 110                 .fifo_size      = 0x1000,
 111                 .ptr1_reg       = DMA3_PTR1,
 112                 .ptr2_reg       = DMA3_PTR2,
 113                 .cnt1_reg       = DMA3_CNT1,
 114                 .cnt2_reg       = DMA3_CNT2,
 115         },
 116         [SRAM_CH04] = {
 117                 .name           = "ch4",
 118                 .cmds_start     = 0x0,
 119                 .ctrl_start     = 0x0,
 120                 .cdt            = 0x0,
 121                 .fifo_start     = 0x0,
 122                 .fifo_size      = 0x0,
 123                 .ptr1_reg       = DMA4_PTR1,
 124                 .ptr2_reg       = DMA4_PTR2,
 125                 .cnt1_reg       = DMA4_CNT1,
 126                 .cnt2_reg       = DMA4_CNT2,
 127         },
 128         [SRAM_CH05] = {
 129                 .name           = "ch5",
 130                 .cmds_start     = 0x0,
 131                 .ctrl_start     = 0x0,
 132                 .cdt            = 0x0,
 133                 .fifo_start     = 0x0,
 134                 .fifo_size      = 0x0,
 135                 .ptr1_reg       = DMA5_PTR1,
 136                 .ptr2_reg       = DMA5_PTR2,
 137                 .cnt1_reg       = DMA5_CNT1,
 138                 .cnt2_reg       = DMA5_CNT2,
 139         },
 140         [SRAM_CH06] = {
 141                 .name           = "TS2 C",
 142                 .cmds_start     = 0x10140,
 143                 .ctrl_start     = 0x10680,
 144                 .cdt            = 0x108d0,
 145                 .fifo_start     = 0x6000,
 146                 .fifo_size      = 0x1000,
 147                 .ptr1_reg       = DMA5_PTR1,
 148                 .ptr2_reg       = DMA5_PTR2,
 149                 .cnt1_reg       = DMA5_CNT1,
 150                 .cnt2_reg       = DMA5_CNT2,
 151         },
 152         [SRAM_CH07] = {
 153                 .name           = "ch7",
 154                 .cmds_start     = 0x0,
 155                 .ctrl_start     = 0x0,
 156                 .cdt            = 0x0,
 157                 .fifo_start     = 0x0,
 158                 .fifo_size      = 0x0,
 159                 .ptr1_reg       = DMA6_PTR1,
 160                 .ptr2_reg       = DMA6_PTR2,
 161                 .cnt1_reg       = DMA6_CNT1,
 162                 .cnt2_reg       = DMA6_CNT2,
 163         },
 164         [SRAM_CH08] = {
 165                 .name           = "ch8",
 166                 .cmds_start     = 0x0,
 167                 .ctrl_start     = 0x0,
 168                 .cdt            = 0x0,
 169                 .fifo_start     = 0x0,
 170                 .fifo_size      = 0x0,
 171                 .ptr1_reg       = DMA7_PTR1,
 172                 .ptr2_reg       = DMA7_PTR2,
 173                 .cnt1_reg       = DMA7_CNT1,
 174                 .cnt2_reg       = DMA7_CNT2,
 175         },
 176         [SRAM_CH09] = {
 177                 .name           = "ch9",
 178                 .cmds_start     = 0x0,
 179                 .ctrl_start     = 0x0,
 180                 .cdt            = 0x0,
 181                 .fifo_start     = 0x0,
 182                 .fifo_size      = 0x0,
 183                 .ptr1_reg       = DMA8_PTR1,
 184                 .ptr2_reg       = DMA8_PTR2,
 185                 .cnt1_reg       = DMA8_CNT1,
 186                 .cnt2_reg       = DMA8_CNT2,
 187         },
 188 };
 189
 190 /* FIXME, these allocations will change when
 191  * analog arrives. The be reviewed.
 192  * CX23887 Assumptions
 193  * 1 line = 16 bytes of CDT
 194  * cmds size = 80
 195  * cdt size = 16 * linesize
 196  * iqsize = 64
 197  * maxlines = 6
 198  *
 199  * Address Space:
 200  * 0x00000000 0x00008fff FIFO clusters
 201  * 0x00010000 0x000104af Channel Management Data Structures
 202  * 0x000104b0 0x000104ff Free
 203  * 0x00010500 0x000108bf 15 channels * iqsize
 204  * 0x000108c0 0x000108ff Free
 205  * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
 206  *                       15 channels * (iqsize + (maxlines * linesize))
 207  * 0x00010ea0 0x00010xxx Free
 208  */
 209
 210 static struct sram_channel cx23887_sram_channels[] = {
 211         [SRAM_CH01] = {
 212                 .name           = "VID A",
 213                 .cmds_start     = 0x10000,
 214                 .ctrl_start     = 0x105b0,
 215                 .cdt            = 0x107b0,
 216                 .fifo_start     = 0x40,
 217                 .fifo_size      = 0x2800,
 218                 .ptr1_reg       = DMA1_PTR1,
 219                 .ptr2_reg       = DMA1_PTR2,
 220                 .cnt1_reg       = DMA1_CNT1,
 221                 .cnt2_reg       = DMA1_CNT2,
 222         },
 223         [SRAM_CH02] = {
 224                 .name           = "ch2",
 225                 .cmds_start     = 0x0,
 226                 .ctrl_start     = 0x0,
 227                 .cdt            = 0x0,
 228                 .fifo_start     = 0x0,
 229                 .fifo_size      = 0x0,
 230                 .ptr1_reg       = DMA2_PTR1,
 231                 .ptr2_reg       = DMA2_PTR2,
 232                 .cnt1_reg       = DMA2_CNT1,
 233                 .cnt2_reg       = DMA2_CNT2,
 234         },
 235         [SRAM_CH03] = {
 236                 .name           = "TS1 B",
 237                 .cmds_start     = 0x100A0,
 238                 .ctrl_start     = 0x10780,
 239                 .cdt            = 0x10400,
 240                 .fifo_start     = 0x5000,
 241                 .fifo_size      = 0x1000,
 242                 .ptr1_reg       = DMA3_PTR1,
 243                 .ptr2_reg       = DMA3_PTR2,
 244                 .cnt1_reg       = DMA3_CNT1,
 245                 .cnt2_reg       = DMA3_CNT2,
 246         },
 247         [SRAM_CH04] = {
 248                 .name           = "ch4",
 249                 .cmds_start     = 0x0,
 250                 .ctrl_start     = 0x0,
 251                 .cdt            = 0x0,
 252                 .fifo_start     = 0x0,
 253                 .fifo_size      = 0x0,
 254                 .ptr1_reg       = DMA4_PTR1,
 255                 .ptr2_reg       = DMA4_PTR2,
 256                 .cnt1_reg       = DMA4_CNT1,
 257                 .cnt2_reg       = DMA4_CNT2,
 258         },
 259         [SRAM_CH05] = {
 260                 .name           = "ch5",
 261                 .cmds_start     = 0x0,
 262                 .ctrl_start     = 0x0,
 263                 .cdt            = 0x0,
 264                 .fifo_start     = 0x0,
 265                 .fifo_size      = 0x0,
 266                 .ptr1_reg       = DMA5_PTR1,
 267                 .ptr2_reg       = DMA5_PTR2,
 268                 .cnt1_reg       = DMA5_CNT1,
 269                 .cnt2_reg       = DMA5_CNT2,
 270         },
 271         [SRAM_CH06] = {
 272                 .name           = "TS2 C",
 273                 .cmds_start     = 0x10140,
 274                 .ctrl_start     = 0x10680,
 275                 .cdt            = 0x108d0,
 276                 .fifo_start     = 0x6000,
 277                 .fifo_size      = 0x1000,
 278                 .ptr1_reg       = DMA5_PTR1,
 279                 .ptr2_reg       = DMA5_PTR2,
 280                 .cnt1_reg       = DMA5_CNT1,
 281                 .cnt2_reg       = DMA5_CNT2,
 282         },
 283         [SRAM_CH07] = {
 284                 .name           = "ch7",
 285                 .cmds_start     = 0x0,
 286                 .ctrl_start     = 0x0,
 287                 .cdt            = 0x0,
 288                 .fifo_start     = 0x0,
 289                 .fifo_size      = 0x0,
 290                 .ptr1_reg       = DMA6_PTR1,
 291                 .ptr2_reg       = DMA6_PTR2,
 292                 .cnt1_reg       = DMA6_CNT1,
 293                 .cnt2_reg       = DMA6_CNT2,
 294         },
 295         [SRAM_CH08] = {
 296                 .name           = "ch8",
 297                 .cmds_start     = 0x0,
 298                 .ctrl_start     = 0x0,
 299                 .cdt            = 0x0,
 300                 .fifo_start     = 0x0,
 301                 .fifo_size      = 0x0,
 302                 .ptr1_reg       = DMA7_PTR1,
 303                 .ptr2_reg       = DMA7_PTR2,
 304                 .cnt1_reg       = DMA7_CNT1,
 305                 .cnt2_reg       = DMA7_CNT2,
 306         },
 307         [SRAM_CH09] = {
 308                 .name           = "ch9",
 309                 .cmds_start     = 0x0,
 310                 .ctrl_start     = 0x0,
 311                 .cdt            = 0x0,
 312                 .fifo_start     = 0x0,
 313                 .fifo_size      = 0x0,
 314                 .ptr1_reg       = DMA8_PTR1,
 315                 .ptr2_reg       = DMA8_PTR2,
 316                 .cnt1_reg       = DMA8_CNT1,
 317                 .cnt2_reg       = DMA8_CNT2,
 318         },
 319 };
 320
 321 static int cx23885_risc_decode(u32 risc)
 322 {
 323         static char *instr[16] = {
 324                 [ RISC_SYNC    >> 28 ] = "sync",
 325                 [ RISC_WRITE   >> 28 ] = "write",
 326                 [ RISC_WRITEC  >> 28 ] = "writec",
 327                 [ RISC_READ    >> 28 ] = "read",
 328                 [ RISC_READC   >> 28 ] = "readc",
 329                 [ RISC_JUMP    >> 28 ] = "jump",
 330                 [ RISC_SKIP    >> 28 ] = "skip",
 331                 [ RISC_WRITERM >> 28 ] = "writerm",
 332                 [ RISC_WRITECM >> 28 ] = "writecm",
 333                 [ RISC_WRITECR >> 28 ] = "writecr",
 334         };
 335         static int incr[16] = {
 336                 [ RISC_WRITE   >> 28 ] = 3,
 337                 [ RISC_JUMP    >> 28 ] = 3,
 338                 [ RISC_SKIP    >> 28 ] = 1,
 339                 [ RISC_SYNC    >> 28 ] = 1,
 340                 [ RISC_WRITERM >> 28 ] = 3,
 341                 [ RISC_WRITECM >> 28 ] = 3,
 342                 [ RISC_WRITECR >> 28 ] = 4,
 343         };
 344         static char *bits[] = {
 345                 "12",   "13",   "14",   "resync",
 346                 "cnt0", "cnt1", "18",   "19",
 347                 "20",   "21",   "22",   "23",
 348                 "irq1", "irq2", "eol",  "sol",
 349         };
 350         int i;
 351
 352         printk("0x%08x [ %s", risc,
 353                instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
 354         for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
 355                 if (risc & (1 << (i + 12)))
 356                         printk(" %s", bits[i]);
 357         printk(" count=%d ]\n", risc & 0xfff);
 358         return incr[risc >> 28] ? incr[risc >> 28] : 1;
 359 }
 360
 361 void cx23885_wakeup(struct cx23885_tsport *port,
 362                            struct cx23885_dmaqueue *q, u32 count)
 363 {
 364         struct cx23885_dev *dev = port->dev;
 365         struct cx23885_buffer *buf;
 366         int bc;
 367
 368         for (bc = 0;; bc++) {
 369                 if (list_empty(&q->active))
 370                         break;
 371                 buf = list_entry(q->active.next,
 372                                  struct cx23885_buffer, vb.queue);
 373
 374                 /* count comes from the hw and is is 16bit wide --
 375                  * this trick handles wrap-arounds correctly for
 376                  * up to 32767 buffers in flight... */
 377                 if ((s16) (count - buf->count) < 0)
 378                         break;
 379
 380                 do_gettimeofday(&buf->vb.ts);
 381                 dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
 382                         count, buf->count);
 383                 buf->vb.state = VIDEOBUF_DONE;
 384                 list_del(&buf->vb.queue);
 385                 wake_up(&buf->vb.done);
 386         }
 387         if (list_empty(&q->active)) {
 388                 del_timer(&q->timeout);
 389         } else {
 390                 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
 391         }
 392         if (bc != 1)
 393                 printk("%s: %d buffers handled (should be 1)\n",
 394                        __FUNCTION__, bc);
 395 }
 396
 397 int cx23885_sram_channel_setup(struct cx23885_dev *dev,
 398                                       struct sram_channel *ch,
 399                                       unsigned int bpl, u32 risc)
 400 {
 401         unsigned int i, lines;
 402         u32 cdt;
 403
 404         if (ch->cmds_start == 0)
 405         {
 406                 dprintk(1, "%s() Erasing channel [%s]\n", __FUNCTION__,
 407                         ch->name);
 408                 cx_write(ch->ptr1_reg, 0);
 409                 cx_write(ch->ptr2_reg, 0);
 410                 cx_write(ch->cnt2_reg, 0);
 411                 cx_write(ch->cnt1_reg, 0);
 412                 return 0;
 413         } else {
 414                 dprintk(1, "%s() Configuring channel [%s]\n", __FUNCTION__,
 415                         ch->name);
 416         }
 417
 418         bpl   = (bpl + 7) & ~7; /* alignment */
 419         cdt   = ch->cdt;
 420         lines = ch->fifo_size / bpl;
 421         if (lines > 6)
 422                 lines = 6;
 423         BUG_ON(lines < 2);
 424
 425         cx_write(8 + 0, cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC) );
 426         cx_write(8 + 4, cpu_to_le32(8) );
 427         cx_write(8 + 8, cpu_to_le32(0) );
 428
 429         /* write CDT */
 430         for (i = 0; i < lines; i++) {
 431                 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __FUNCTION__, cdt + 16*i,
 432                         ch->fifo_start + bpl*i);
 433                 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
 434                 cx_write(cdt + 16*i +  4, 0);
 435                 cx_write(cdt + 16*i +  8, 0);
 436                 cx_write(cdt + 16*i + 12, 0);
 437         }
 438
 439         /* write CMDS */
 440         if (ch->jumponly)
 441                 cx_write(ch->cmds_start +  0, 8);
 442         else
 443                 cx_write(ch->cmds_start +  0, risc);
 444         cx_write(ch->cmds_start +  4, 0); /* 64 bits 63-32 */
 445         cx_write(ch->cmds_start +  8, cdt);
 446         cx_write(ch->cmds_start + 12, (lines*16) >> 3);
 447         cx_write(ch->cmds_start + 16, ch->ctrl_start);
 448         if (ch->jumponly)
 449                 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2) );
 450         else
 451                 cx_write(ch->cmds_start + 20, 64 >> 2);
 452         for (i = 24; i < 80; i += 4)
 453                 cx_write(ch->cmds_start + i, 0);
 454
 455         /* fill registers */
 456         cx_write(ch->ptr1_reg, ch->fifo_start);
 457         cx_write(ch->ptr2_reg, cdt);
 458         cx_write(ch->cnt2_reg, (lines*16) >> 3);
 459         cx_write(ch->cnt1_reg, (bpl >> 3) -1);
 460
 461         dprintk(2,"[bridge %d] sram setup %s: bpl=%d lines=%d\n",
 462                 dev->bridge,
 463                 ch->name,
 464                 bpl,
 465                 lines);
 466
 467         return 0;
 468 }
 469
 470 void cx23885_sram_channel_dump(struct cx23885_dev *dev,
 471                                       struct sram_channel *ch)
 472 {
 473         static char *name[] = {
 474                 "init risc lo",
 475                 "init risc hi",
 476                 "cdt base",
 477                 "cdt size",
 478                 "iq base",
 479                 "iq size",
 480                 "risc pc lo",
 481                 "risc pc hi",
 482                 "iq wr ptr",
 483                 "iq rd ptr",
 484                 "cdt current",
 485                 "pci target lo",
 486                 "pci target hi",
 487                 "line / byte",
 488         };
 489         u32 risc;
 490         unsigned int i, j, n;
 491
 492         printk("%s: %s - dma channel status dump\n",
 493                dev->name, ch->name);
 494         for (i = 0; i < ARRAY_SIZE(name); i++)
 495                 printk("%s:   cmds: %-15s: 0x%08x\n",
 496                        dev->name, name[i],
 497                        cx_read(ch->cmds_start + 4*i));
 498
 499         for (i = 0; i < 4; i++) {
 500                 risc = cx_read(ch->cmds_start + 4 * (i + 14));
 501                 printk("%s:   risc%d: ", dev->name, i);
 502                 cx23885_risc_decode(risc);
 503         }
 504         for (i = 0; i < (64 >> 2); i += n) {
 505                 risc = cx_read(ch->ctrl_start + 4 * i);
 506                 /* No consideration for bits 63-32 */
 507
 508                 printk("%s:   (0x%08x) iq %x: ", dev->name,
 509                        ch->ctrl_start + 4 * i, i);
 510                 n = cx23885_risc_decode(risc);
 511                 for (j = 1; j < n; j++) {
 512                         risc = cx_read(ch->ctrl_start + 4 * (i + j));
 513                         printk("%s:   iq %x: 0x%08x [ arg #%d ]\n",
 514                                dev->name, i+j, risc, j);
 515                 }
 516         }
 517
 518         printk("%s: fifo: 0x%08x -> 0x%x\n",
 519                dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
 520         printk("%s: ctrl: 0x%08x -> 0x%x\n",
 521                dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
 522         printk("%s:   ptr1_reg: 0x%08x\n",
 523                dev->name, cx_read(ch->ptr1_reg));
 524         printk("%s:   ptr2_reg: 0x%08x\n",
 525                dev->name, cx_read(ch->ptr2_reg));
 526         printk("%s:   cnt1_reg: 0x%08x\n",
 527                dev->name, cx_read(ch->cnt1_reg));
 528         printk("%s:   cnt2_reg: 0x%08x\n",
 529                dev->name, cx_read(ch->cnt2_reg));
 530 }
 531
 532 static void cx23885_risc_disasm(struct cx23885_tsport *port,
 533                                 struct btcx_riscmem *risc)
 534 {
 535         struct cx23885_dev *dev = port->dev;
 536         unsigned int i, j, n;
 537
 538         printk("%s: risc disasm: %p [dma=0x%08lx]\n",
 539                dev->name, risc->cpu, (unsigned long)risc->dma);
 540         for (i = 0; i < (risc->size >> 2); i += n) {
 541                 printk("%s:   %04d: ", dev->name, i);
 542                 n = cx23885_risc_decode(risc->cpu[i]);
 543                 for (j = 1; j < n; j++)
 544                         printk("%s:   %04d: 0x%08x [ arg #%d ]\n",
 545                                dev->name, i + j, risc->cpu[i + j], j);
 546                 if (risc->cpu[i] == RISC_JUMP)
 547                         break;
 548         }
 549 }
 550
 551 static void cx23885_shutdown(struct cx23885_dev *dev)
 552 {
 553         /* disable RISC controller */
 554         cx_write(DEV_CNTRL2, 0);
 555
 556         /* Disable all IR activity */
 557         cx_write(IR_CNTRL_REG, 0);
 558
 559         /* Disable Video A/B activity */
 560         cx_write(VID_A_DMA_CTL, 0);
 561         cx_write(VID_B_DMA_CTL, 0);
 562         cx_write(VID_C_DMA_CTL, 0);
 563
 564         /* Disable Audio activity */
 565         cx_write(AUD_INT_DMA_CTL, 0);
 566         cx_write(AUD_EXT_DMA_CTL, 0);
 567
 568         /* Disable Serial port */
 569         cx_write(UART_CTL, 0);
 570
 571         /* Disable Interrupts */
 572         cx_write(PCI_INT_MSK, 0);
 573         cx_write(VID_A_INT_MSK, 0);
 574         cx_write(VID_B_INT_MSK, 0);
 575         cx_write(VID_C_INT_MSK, 0);
 576         cx_write(AUDIO_INT_INT_MSK, 0);
 577         cx_write(AUDIO_EXT_INT_MSK, 0);
 578
 579 }
 580
 581 static void cx23885_reset(struct cx23885_dev *dev)
 582 {
 583         dprintk(1, "%s()\n", __FUNCTION__);
 584
 585         cx23885_shutdown(dev);
 586
 587         cx_write(PCI_INT_STAT, 0xffffffff);
 588         cx_write(VID_A_INT_STAT, 0xffffffff);
 589         cx_write(VID_B_INT_STAT, 0xffffffff);
 590         cx_write(VID_C_INT_STAT, 0xffffffff);
 591         cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
 592         cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
 593         cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
 594
 595         mdelay(100);
 596
 597         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01],
 598                 720*4, 0);
 599         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02], 128, 0);
 600         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH03],
 601                 188*4, 0);
 602         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH04], 128, 0);
 603         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH05], 128, 0);
 604         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH06],
 605                 188*4, 0);
 606         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH07], 128, 0);
 607         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH08], 128, 0);
 608         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH09], 128, 0);
 609
 610         cx23885_gpio_setup(dev);
 611 }
 612
 613
 614 static int cx23885_pci_quirks(struct cx23885_dev *dev)
 615 {
 616         dprintk(1, "%s()\n", __FUNCTION__);
 617
 618         /* The cx23885 bridge has a weird bug which causes NMI to be asserted
 619          * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
 620          * occur on the cx23887 bridge.
 621          */
 622         if(dev->bridge == CX23885_BRIDGE_885)
 623                 cx_clear(RDR_TLCTL0, 1 << 4);
 624
 625         return 0;
 626 }
 627
 628 static int get_resources(struct cx23885_dev *dev)
 629 {
 630         if (request_mem_region(pci_resource_start(dev->pci,0),
 631                                pci_resource_len(dev->pci,0),
 632                                dev->name))
 633                 return 0;
 634
 635         printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
 636                 dev->name, (unsigned long long)pci_resource_start(dev->pci,0));
 637
 638         return -EBUSY;
 639 }
 640
 641 static void cx23885_timeout(unsigned long data);
 642 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
 643                                 u32 reg, u32 mask, u32 value);
 644
 645 static int cx23885_init_tsport(struct cx23885_dev *dev, struct cx23885_tsport *port, int portno)
 646 {
 647         dprintk(1, "%s(portno=%d)\n", __FUNCTION__, portno);
 648
 649         /* Transport bus init dma queue  - Common settings */
 650         port->dma_ctl_val        = 0x11; /* Enable RISC controller and Fifo */
 651         port->ts_int_msk_val     = 0x1111; /* TS port bits for RISC */
 652
 653         spin_lock_init(&port->slock);
 654         port->dev = dev;
 655         port->nr = portno;
 656
 657         INIT_LIST_HEAD(&port->mpegq.active);
 658         INIT_LIST_HEAD(&port->mpegq.queued);
 659         port->mpegq.timeout.function = cx23885_timeout;
 660         port->mpegq.timeout.data = (unsigned long)port;
 661         init_timer(&port->mpegq.timeout);
 662
 663         switch(portno) {
 664         case 1:
 665                 port->reg_gpcnt          = VID_B_GPCNT;
 666                 port->reg_gpcnt_ctl      = VID_B_GPCNT_CTL;
 667                 port->reg_dma_ctl        = VID_B_DMA_CTL;
 668                 port->reg_lngth          = VID_B_LNGTH;
 669                 port->reg_hw_sop_ctrl    = VID_B_HW_SOP_CTL;
 670                 port->reg_gen_ctrl       = VID_B_GEN_CTL;
 671                 port->reg_bd_pkt_status  = VID_B_BD_PKT_STATUS;
 672                 port->reg_sop_status     = VID_B_SOP_STATUS;
 673                 port->reg_fifo_ovfl_stat = VID_B_FIFO_OVFL_STAT;
 674                 port->reg_vld_misc       = VID_B_VLD_MISC;
 675                 port->reg_ts_clk_en      = VID_B_TS_CLK_EN;
 676                 port->reg_src_sel        = VID_B_SRC_SEL;
 677                 port->reg_ts_int_msk     = VID_B_INT_MSK;
 678                 port->reg_ts_int_stat   = VID_B_INT_STAT;
 679                 port->sram_chno          = SRAM_CH03; /* VID_B */
 680                 port->pci_irqmask        = 0x02; /* VID_B bit1 */
 681                 break;
 682         case 2:
 683                 port->reg_gpcnt          = VID_C_GPCNT;
 684                 port->reg_gpcnt_ctl      = VID_C_GPCNT_CTL;
 685                 port->reg_dma_ctl        = VID_C_DMA_CTL;
 686                 port->reg_lngth          = VID_C_LNGTH;
 687                 port->reg_hw_sop_ctrl    = VID_C_HW_SOP_CTL;
 688                 port->reg_gen_ctrl       = VID_C_GEN_CTL;
 689                 port->reg_bd_pkt_status  = VID_C_BD_PKT_STATUS;
 690                 port->reg_sop_status     = VID_C_SOP_STATUS;
 691                 port->reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
 692                 port->reg_vld_misc       = VID_C_VLD_MISC;
 693                 port->reg_ts_clk_en      = VID_C_TS_CLK_EN;
 694                 port->reg_src_sel        = 0;
 695                 port->reg_ts_int_msk     = VID_C_INT_MSK;
 696                 port->reg_ts_int_stat    = VID_C_INT_STAT;
 697                 port->sram_chno          = SRAM_CH06; /* VID_C */
 698                 port->pci_irqmask        = 0x04; /* VID_C bit2 */
 699                 break;
 700         default:
 701                 BUG();
 702         }
 703
 704         cx23885_risc_stopper(dev->pci, &port->mpegq.stopper,
 705                      port->reg_dma_ctl, port->dma_ctl_val, 0x00);
 706
 707         return 0;
 708 }
 709
 710 static void cx23885_dev_checkrevision(struct cx23885_dev *dev)
 711 {
 712         switch (cx_read(RDR_CFG2) & 0xff) {
 713         case 0x00:
 714                 /* cx23885 */
 715                 dev->hwrevision = 0xa0;
 716                 break;
 717         case 0x01:
 718                 /* CX23885-12Z */
 719                 dev->hwrevision = 0xa1;
 720                 break;
 721         case 0x02:
 722                 /* CX23885-13Z */
 723                 dev->hwrevision = 0xb0;
 724                 break;
 725         case 0x03:
 726                 /* CX23888-22Z */
 727                 dev->hwrevision = 0xc0;
 728                 break;
 729         case 0x0e:
 730                 /* CX23887-15Z */
 731                 dev->hwrevision = 0xc0;
 732         case 0x0f:
 733                 /* CX23887-14Z */
 734                 dev->hwrevision = 0xb1;
 735                 break;
 736         default:
 737                 printk(KERN_ERR "%s() New hardware revision found 0x%x\n",
 738                         __FUNCTION__, dev->hwrevision);
 739         }
 740         if (dev->hwrevision)
 741                 printk(KERN_INFO "%s() Hardware revision = 0x%02x\n",
 742                         __FUNCTION__, dev->hwrevision);
 743         else
 744                 printk(KERN_ERR "%s() Hardware revision unknown 0x%x\n",
 745                         __FUNCTION__, dev->hwrevision);
 746 }
 747
 748 static int cx23885_dev_setup(struct cx23885_dev *dev)
 749 {
 750         int i;
 751
 752         mutex_init(&dev->lock);
 753
 754         atomic_inc(&dev->refcount);
 755
 756         dev->nr = cx23885_devcount++;
 757         sprintf(dev->name, "cx23885[%d]", dev->nr);
 758
 759         mutex_lock(&devlist);
 760         list_add_tail(&dev->devlist, &cx23885_devlist);
 761         mutex_unlock(&devlist);
 762
 763         /* Configure the internal memory */
 764         if(dev->pci->device == 0x8880) {
 765                 dev->bridge = CX23885_BRIDGE_887;
 766                 dev->sram_channels = cx23887_sram_channels;
 767                 /* Apply a sensible clock frequency for the PCIe bridge */
 768                 dev->clk_freq = 25000000;
 769         } else
 770         if(dev->pci->device == 0x8852) {
 771                 dev->bridge = CX23885_BRIDGE_885;
 772                 dev->sram_channels = cx23885_sram_channels;
 773                 /* Apply a sensible clock frequency for the PCIe bridge */
 774                 dev->clk_freq = 28000000;
 775         } else
 776                 BUG();
 777
 778         dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
 779                 __FUNCTION__, dev->bridge);
 780
 781         /* board config */
 782         dev->board = UNSET;
 783         if (card[dev->nr] < cx23885_bcount)
 784                 dev->board = card[dev->nr];
 785         for (i = 0; UNSET == dev->board  &&  i < cx23885_idcount; i++)
 786                 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
 787                     dev->pci->subsystem_device == cx23885_subids[i].subdevice)
 788                         dev->board = cx23885_subids[i].card;
 789         if (UNSET == dev->board) {
 790                 dev->board = CX23885_BOARD_UNKNOWN;
 791                 cx23885_card_list(dev);
 792         }
 793
 794         /* If the user specific a clk freq override, apply it */
 795         if (cx23885_boards[dev->board].clk_freq > 0)
 796                 dev->clk_freq = cx23885_boards[dev->board].clk_freq;
 797
 798         dev->pci_bus  = dev->pci->bus->number;
 799         dev->pci_slot = PCI_SLOT(dev->pci->devfn);
 800         dev->pci_irqmask = 0x001f00;
 801
 802         /* External Master 1 Bus */
 803         dev->i2c_bus[0].nr = 0;
 804         dev->i2c_bus[0].dev = dev;
 805         dev->i2c_bus[0].reg_stat  = I2C1_STAT;
 806         dev->i2c_bus[0].reg_ctrl  = I2C1_CTRL;
 807         dev->i2c_bus[0].reg_addr  = I2C1_ADDR;
 808         dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
 809         dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
 810         dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
 811
 812         /* External Master 2 Bus */
 813         dev->i2c_bus[1].nr = 1;
 814         dev->i2c_bus[1].dev = dev;
 815         dev->i2c_bus[1].reg_stat  = I2C2_STAT;
 816         dev->i2c_bus[1].reg_ctrl  = I2C2_CTRL;
 817         dev->i2c_bus[1].reg_addr  = I2C2_ADDR;
 818         dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
 819         dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
 820         dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
 821
 822         /* Internal Master 3 Bus */
 823         dev->i2c_bus[2].nr = 2;
 824         dev->i2c_bus[2].dev = dev;
 825         dev->i2c_bus[2].reg_stat  = I2C3_STAT;
 826         dev->i2c_bus[2].reg_ctrl  = I2C3_CTRL;
 827         dev->i2c_bus[2].reg_addr  = I2C3_ADDR;
 828         dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
 829         dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
 830         dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
 831
 832         if(cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
 833                 cx23885_init_tsport(dev, &dev->ts1, 1);
 834
 835         if(cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
 836                 cx23885_init_tsport(dev, &dev->ts2, 2);
 837
 838         if (get_resources(dev) < 0) {
 839                 printk(KERN_ERR "CORE %s No more PCIe resources for "
 840                        "subsystem: %04x:%04x\n",
 841                        dev->name, dev->pci->subsystem_vendor,
 842                        dev->pci->subsystem_device);
 843
 844                 cx23885_devcount--;
 845                 return -ENODEV;
 846         }
 847
 848         /* PCIe stuff */
 849         dev->lmmio = ioremap(pci_resource_start(dev->pci,0),
 850                              pci_resource_len(dev->pci,0));
 851
 852         dev->bmmio = (u8 __iomem *)dev->lmmio;
 853
 854         printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
 855                dev->name, dev->pci->subsystem_vendor,
 856                dev->pci->subsystem_device, cx23885_boards[dev->board].name,
 857                dev->board, card[dev->nr] == dev->board ?
 858                "insmod option" : "autodetected");
 859
 860         cx23885_pci_quirks(dev);
 861
 862         /* Assume some sensible defaults */
 863         dev->tuner_type = cx23885_boards[dev->board].tuner_type;
 864         dev->tuner_addr = cx23885_boards[dev->board].tuner_addr;
 865         dev->radio_type = cx23885_boards[dev->board].radio_type;
 866         dev->radio_addr = cx23885_boards[dev->board].radio_addr;
 867
 868         dprintk(1, "%s() tuner_type = 0x%x tuner_addr = 0x%x\n",
 869                 __FUNCTION__, dev->tuner_type, dev->tuner_addr);
 870         dprintk(1, "%s() radio_type = 0x%x radio_addr = 0x%x\n",
 871                 __FUNCTION__, dev->radio_type, dev->radio_addr);
 872
 873         /* init hardware */
 874         cx23885_reset(dev);
 875
 876         cx23885_i2c_register(&dev->i2c_bus[0]);
 877         cx23885_i2c_register(&dev->i2c_bus[1]);
 878         cx23885_i2c_register(&dev->i2c_bus[2]);
 879         cx23885_call_i2c_clients (&dev->i2c_bus[0], TUNER_SET_STANDBY, NULL);
 880         cx23885_card_setup(dev);
 881         cx23885_ir_init(dev);
 882
 883         if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO) {
 884                 if (cx23885_video_register(dev) < 0) {
 885                         printk(KERN_ERR "%s() Failed to register analog "
 886                                 "video adapters on VID_A\n", __FUNCTION__);
 887                 }
 888         }
 889
 890         if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
 891                 if (cx23885_dvb_register(&dev->ts1) < 0) {
 892                         printk(KERN_ERR "%s() Failed to register dvb adapters on VID_B\n",
 893                                __FUNCTION__);
 894                 }
 895         }
 896
 897         if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
 898                 if (cx23885_dvb_register(&dev->ts2) < 0) {
 899                         printk(KERN_ERR "%s() Failed to register dvb adapters on VID_C\n",
 900                                __FUNCTION__);
 901                 }
 902         }
 903
 904         cx23885_dev_checkrevision(dev);
 905
 906         return 0;
 907 }
 908
 909 static void cx23885_dev_unregister(struct cx23885_dev *dev)
 910 {
 911         release_mem_region(pci_resource_start(dev->pci,0),
 912                            pci_resource_len(dev->pci,0));
 913
 914         if (!atomic_dec_and_test(&dev->refcount))
 915                 return;
 916
 917         if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO)
 918                 cx23885_video_unregister(dev);
 919
 920         if(cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
 921                 cx23885_dvb_unregister(&dev->ts1);
 922
 923         if(cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
 924                 cx23885_dvb_unregister(&dev->ts2);
 925
 926         cx23885_i2c_unregister(&dev->i2c_bus[2]);
 927         cx23885_i2c_unregister(&dev->i2c_bus[1]);
 928         cx23885_i2c_unregister(&dev->i2c_bus[0]);
 929
 930         iounmap(dev->lmmio);
 931 }
 932
 933 static u32* cx23885_risc_field(u32 *rp, struct scatterlist *sglist,
 934                                unsigned int offset, u32 sync_line,
 935                                unsigned int bpl, unsigned int padding,
 936                                unsigned int lines)
 937 {
 938         struct scatterlist *sg;
 939         unsigned int line, todo;
 940
 941         /* sync instruction */
 942         if (sync_line != NO_SYNC_LINE)
 943                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
 944
 945         /* scan lines */
 946         sg = sglist;
 947         for (line = 0; line < lines; line++) {
 948                 while (offset && offset >= sg_dma_len(sg)) {
 949                         offset -= sg_dma_len(sg);
 950                         sg++;
 951                 }
 952                 if (bpl <= sg_dma_len(sg)-offset) {
 953                         /* fits into current chunk */
 954                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
 955                         *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
 956                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 957                         offset+=bpl;
 958                 } else {
 959                         /* scanline needs to be split */
 960                         todo = bpl;
 961                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|
 962                                             (sg_dma_len(sg)-offset));
 963                         *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
 964                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 965                         todo -= (sg_dma_len(sg)-offset);
 966                         offset = 0;
 967                         sg++;
 968                         while (todo > sg_dma_len(sg)) {
 969                                 *(rp++)=cpu_to_le32(RISC_WRITE|
 970                                                     sg_dma_len(sg));
 971                                 *(rp++)=cpu_to_le32(sg_dma_address(sg));
 972                                 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 973                                 todo -= sg_dma_len(sg);
 974                                 sg++;
 975                         }
 976                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
 977                         *(rp++)=cpu_to_le32(sg_dma_address(sg));
 978                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 979                         offset += todo;
 980                 }
 981                 offset += padding;
 982         }
 983
 984         return rp;
 985 }
 986
 987 int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
 988                         struct scatterlist *sglist, unsigned int top_offset,
 989                         unsigned int bottom_offset, unsigned int bpl,
 990                         unsigned int padding, unsigned int lines)
 991 {
 992         u32 instructions, fields;
 993         u32 *rp;
 994         int rc;
 995
 996         fields = 0;
 997         if (UNSET != top_offset)
 998                 fields++;
 999         if (UNSET != bottom_offset)
1000                 fields++;
1001
1002         /* estimate risc mem: worst case is one write per page border +
1003            one write per scan line + syncs + jump (all 2 dwords).  Padding
1004            can cause next bpl to start close to a page border.  First DMA
1005            region may be smaller than PAGE_SIZE */
1006         /* write and jump need and extra dword */
1007         instructions  = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
1008         instructions += 2;
1009         if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
1010                 return rc;
1011
1012         /* write risc instructions */
1013         rp = risc->cpu;
1014         if (UNSET != top_offset)
1015                 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
1016                                         bpl, padding, lines);
1017         if (UNSET != bottom_offset)
1018                 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
1019                                         bpl, padding, lines);
1020
1021         /* save pointer to jmp instruction address */
1022         risc->jmp = rp;
1023         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
1024         return 0;
1025 }
1026
1027 static int cx23885_risc_databuffer(struct pci_dev *pci,
1028                                    struct btcx_riscmem *risc,
1029                                    struct scatterlist *sglist,
1030                                    unsigned int bpl,
1031                                    unsigned int lines)
1032 {
1033         u32 instructions;
1034         u32 *rp;
1035         int rc;
1036
1037         /* estimate risc mem: worst case is one write per page border +
1038            one write per scan line + syncs + jump (all 2 dwords).  Here
1039            there is no padding and no sync.  First DMA region may be smaller
1040            than PAGE_SIZE */
1041         /* Jump and write need an extra dword */
1042         instructions  = 1 + (bpl * lines) / PAGE_SIZE + lines;
1043         instructions += 1;
1044
1045         if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
1046                 return rc;
1047
1048         /* write risc instructions */
1049         rp = risc->cpu;
1050         rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
1051
1052         /* save pointer to jmp instruction address */
1053         risc->jmp = rp;
1054         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
1055         return 0;
1056 }
1057
1058 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
1059                                 u32 reg, u32 mask, u32 value)
1060 {
1061         u32 *rp;
1062         int rc;
1063
1064         if ((rc = btcx_riscmem_alloc(pci, risc, 4*16)) < 0)
1065                 return rc;
1066
1067         /* write risc instructions */
1068         rp = risc->cpu;
1069         *(rp++) = cpu_to_le32(RISC_WRITECR  | RISC_IRQ2);
1070         *(rp++) = cpu_to_le32(reg);
1071         *(rp++) = cpu_to_le32(value);
1072         *(rp++) = cpu_to_le32(mask);
1073         *(rp++) = cpu_to_le32(RISC_JUMP);
1074         *(rp++) = cpu_to_le32(risc->dma);
1075         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1076         return 0;
1077 }
1078
1079 void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
1080 {
1081         struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
1082
1083         BUG_ON(in_interrupt());
1084         videobuf_waiton(&buf->vb, 0, 0);
1085         videobuf_dma_unmap(q, dma);
1086         videobuf_dma_free(dma);
1087         btcx_riscmem_free((struct pci_dev *)q->dev, &buf->risc);
1088         buf->vb.state = VIDEOBUF_NEEDS_INIT;
1089 }
1090
1091 static void cx23885_tsport_reg_dump(struct cx23885_tsport *port)
1092 {
1093         struct cx23885_dev *dev = port->dev;
1094
1095         dprintk(1, "%s() Register Dump\n", __FUNCTION__);
1096         dprintk(1, "%s() DEV_CNTRL2               0x%08X\n", __FUNCTION__,
1097                 cx_read(DEV_CNTRL2));
1098         dprintk(1, "%s() PCI_INT_MSK              0x%08X\n", __FUNCTION__,
1099                 cx_read(PCI_INT_MSK));
1100         dprintk(1, "%s() AUD_INT_INT_MSK          0x%08X\n", __FUNCTION__,
1101                 cx_read(AUDIO_INT_INT_MSK));
1102         dprintk(1, "%s() AUD_INT_DMA_CTL          0x%08X\n", __FUNCTION__,
1103                 cx_read(AUD_INT_DMA_CTL));
1104         dprintk(1, "%s() AUD_EXT_INT_MSK          0x%08X\n", __FUNCTION__,
1105                 cx_read(AUDIO_EXT_INT_MSK));
1106         dprintk(1, "%s() AUD_EXT_DMA_CTL          0x%08X\n", __FUNCTION__,
1107                 cx_read(AUD_EXT_DMA_CTL));
1108         dprintk(1, "%s() PAD_CTRL                 0x%08X\n", __FUNCTION__,
1109                 cx_read(PAD_CTRL));
1110         dprintk(1, "%s() ALT_PIN_OUT_SEL          0x%08X\n", __FUNCTION__,
1111                 cx_read(ALT_PIN_OUT_SEL));
1112         dprintk(1, "%s() GPIO2                    0x%08X\n", __FUNCTION__,
1113                 cx_read(GPIO2));
1114         dprintk(1, "%s() gpcnt(0x%08X)          0x%08X\n", __FUNCTION__,
1115                 port->reg_gpcnt, cx_read(port->reg_gpcnt));
1116         dprintk(1, "%s() gpcnt_ctl(0x%08X)      0x%08x\n", __FUNCTION__,
1117                 port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl));
1118         dprintk(1, "%s() dma_ctl(0x%08X)        0x%08x\n", __FUNCTION__,
1119                 port->reg_dma_ctl, cx_read(port->reg_dma_ctl));
1120         dprintk(1, "%s() src_sel(0x%08X)        0x%08x\n", __FUNCTION__,
1121                 port->reg_src_sel, cx_read(port->reg_src_sel));
1122         dprintk(1, "%s() lngth(0x%08X)          0x%08x\n", __FUNCTION__,
1123                 port->reg_lngth, cx_read(port->reg_lngth));
1124         dprintk(1, "%s() hw_sop_ctrl(0x%08X)    0x%08x\n", __FUNCTION__,
1125                 port->reg_hw_sop_ctrl, cx_read(port->reg_hw_sop_ctrl));
1126         dprintk(1, "%s() gen_ctrl(0x%08X)       0x%08x\n", __FUNCTION__,
1127                 port->reg_gen_ctrl, cx_read(port->reg_gen_ctrl));
1128         dprintk(1, "%s() bd_pkt_status(0x%08X)  0x%08x\n", __FUNCTION__,
1129                 port->reg_bd_pkt_status, cx_read(port->reg_bd_pkt_status));
1130         dprintk(1, "%s() sop_status(0x%08X)     0x%08x\n", __FUNCTION__,
1131                 port->reg_sop_status, cx_read(port->reg_sop_status));
1132         dprintk(1, "%s() fifo_ovfl_stat(0x%08X) 0x%08x\n", __FUNCTION__,
1133                 port->reg_fifo_ovfl_stat, cx_read(port->reg_fifo_ovfl_stat));
1134         dprintk(1, "%s() vld_misc(0x%08X)       0x%08x\n", __FUNCTION__,
1135                 port->reg_vld_misc, cx_read(port->reg_vld_misc));
1136         dprintk(1, "%s() ts_clk_en(0x%08X)      0x%08x\n", __FUNCTION__,
1137                 port->reg_ts_clk_en, cx_read(port->reg_ts_clk_en));
1138         dprintk(1, "%s() ts_int_msk(0x%08X)     0x%08x\n", __FUNCTION__,
1139                 port->reg_ts_int_msk, cx_read(port->reg_ts_int_msk));
1140 }
1141
1142 static int cx23885_start_dma(struct cx23885_tsport *port,
1143                              struct cx23885_dmaqueue *q,
1144                              struct cx23885_buffer   *buf)
1145 {
1146         struct cx23885_dev *dev = port->dev;
1147
1148         dprintk(1, "%s() w: %d, h: %d, f: %d\n", __FUNCTION__,
1149                 buf->vb.width, buf->vb.height, buf->vb.field);
1150
1151         /* setup fifo + format */
1152         cx23885_sram_channel_setup(dev,
1153                                    &dev->sram_channels[ port->sram_chno ],
1154                                    port->ts_packet_size, buf->risc.dma);
1155         if(debug > 5) {
1156                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ] );
1157                 cx23885_risc_disasm(port, &buf->risc);
1158         }
1159
1160         /* write TS length to chip */
1161         cx_write(port->reg_lngth, buf->vb.width);
1162
1163         if ( (!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) &&
1164                 (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB)) ) {
1165                 printk( "%s() Failed. Unsupported value in .portb/c (0x%08x)/(0x%08x)\n",
1166                         __FUNCTION__,
1167                         cx23885_boards[dev->board].portb,
1168                         cx23885_boards[dev->board].portc );
1169                 return -EINVAL;
1170         }
1171
1172         udelay(100);
1173
1174         /* If the port supports SRC SELECT, configure it */
1175         if(port->reg_src_sel)
1176                 cx_write(port->reg_src_sel, port->src_sel_val);
1177
1178         cx_write(port->reg_hw_sop_ctrl, 0x47 << 16 | 188 << 4);
1179         cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1180         cx_write(port->reg_vld_misc, 0x00);
1181         cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1182         udelay(100);
1183
1184         // NOTE: this is 2 (reserved) for portb, does it matter?
1185         /* reset counter to zero */
1186         cx_write(port->reg_gpcnt_ctl, 3);
1187         q->count = 1;
1188
1189         switch(dev->bridge) {
1190         case CX23885_BRIDGE_885:
1191         case CX23885_BRIDGE_887:
1192                 /* enable irqs */
1193                 dprintk(1, "%s() enabling TS int's and DMA\n", __FUNCTION__ );
1194                 cx_set(port->reg_ts_int_msk,  port->ts_int_msk_val);
1195                 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1196                 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
1197                 break;
1198         default:
1199                 BUG();
1200         }
1201
1202         cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1203
1204         if (debug > 4)
1205                 cx23885_tsport_reg_dump(port);
1206
1207         return 0;
1208 }
1209
1210 static int cx23885_stop_dma(struct cx23885_tsport *port)
1211 {
1212         struct cx23885_dev *dev = port->dev;
1213         dprintk(1, "%s()\n", __FUNCTION__);
1214
1215         /* Stop interrupts and DMA */
1216         cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1217         cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1218
1219         return 0;
1220 }
1221
1222 int cx23885_restart_queue(struct cx23885_tsport *port,
1223                                 struct cx23885_dmaqueue *q)
1224 {
1225         struct cx23885_dev *dev = port->dev;
1226         struct cx23885_buffer *buf;
1227
1228         dprintk(5, "%s()\n", __FUNCTION__);
1229         if (list_empty(&q->active))
1230         {
1231                 struct cx23885_buffer *prev;
1232                 prev = NULL;
1233
1234                 dprintk(5, "%s() queue is empty\n", __FUNCTION__);
1235
1236                 for (;;) {
1237                         if (list_empty(&q->queued))
1238                                 return 0;
1239                         buf = list_entry(q->queued.next, struct cx23885_buffer,
1240                                          vb.queue);
1241                         if (NULL == prev) {
1242                                 list_del(&buf->vb.queue);
1243                                 list_add_tail(&buf->vb.queue, &q->active);
1244                                 cx23885_start_dma(port, q, buf);
1245                                 buf->vb.state = VIDEOBUF_ACTIVE;
1246                                 buf->count    = q->count++;
1247                                 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1248                                 dprintk(5, "[%p/%d] restart_queue - first active\n",
1249                                         buf, buf->vb.i);
1250
1251                         } else if (prev->vb.width  == buf->vb.width  &&
1252                                    prev->vb.height == buf->vb.height &&
1253                                    prev->fmt       == buf->fmt) {
1254                                 list_del(&buf->vb.queue);
1255                                 list_add_tail(&buf->vb.queue, &q->active);
1256                                 buf->vb.state = VIDEOBUF_ACTIVE;
1257                                 buf->count    = q->count++;
1258                                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1259                                 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1260                                 dprintk(5,"[%p/%d] restart_queue - move to active\n",
1261                                         buf, buf->vb.i);
1262                         } else {
1263                                 return 0;
1264                         }
1265                         prev = buf;
1266                 }
1267                 return 0;
1268         }
1269
1270         buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
1271         dprintk(2, "restart_queue [%p/%d]: restart dma\n",
1272                 buf, buf->vb.i);
1273         cx23885_start_dma(port, q, buf);
1274         list_for_each_entry(buf, &q->active, vb.queue)
1275                 buf->count = q->count++;
1276         mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
1277         return 0;
1278 }
1279
1280 /* ------------------------------------------------------------------ */
1281
1282 int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1283                         struct cx23885_buffer *buf, enum v4l2_field field)
1284 {
1285         struct cx23885_dev *dev = port->dev;
1286         int size = port->ts_packet_size * port->ts_packet_count;
1287         int rc;
1288
1289         dprintk(1, "%s: %p\n", __FUNCTION__, buf);
1290         if (0 != buf->vb.baddr  &&  buf->vb.bsize < size)
1291                 return -EINVAL;
1292
1293         if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
1294                 buf->vb.width  = port->ts_packet_size;
1295                 buf->vb.height = port->ts_packet_count;
1296                 buf->vb.size   = size;
1297                 buf->vb.field  = field /*V4L2_FIELD_TOP*/;
1298
1299                 if (0 != (rc = videobuf_iolock(q, &buf->vb, NULL)))
1300                         goto fail;
1301                 cx23885_risc_databuffer(dev->pci, &buf->risc,
1302                                         videobuf_to_dma(&buf->vb)->sglist,
1303                                         buf->vb.width, buf->vb.height);
1304         }
1305         buf->vb.state = VIDEOBUF_PREPARED;
1306         return 0;
1307
1308  fail:
1309         cx23885_free_buffer(q, buf);
1310         return rc;
1311 }
1312
1313 void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1314 {
1315         struct cx23885_buffer    *prev;
1316         struct cx23885_dev *dev = port->dev;
1317         struct cx23885_dmaqueue  *cx88q = &port->mpegq;
1318
1319         /* add jump to stopper */
1320         buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
1321         buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
1322         buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1323
1324         if (list_empty(&cx88q->active)) {
1325                 dprintk( 1, "queue is empty - first active\n" );
1326                 list_add_tail(&buf->vb.queue, &cx88q->active);
1327                 cx23885_start_dma(port, cx88q, buf);
1328                 buf->vb.state = VIDEOBUF_ACTIVE;
1329                 buf->count    = cx88q->count++;
1330                 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
1331                 dprintk(1, "[%p/%d] %s - first active\n",
1332                         buf, buf->vb.i, __FUNCTION__);
1333         } else {
1334                 dprintk( 1, "queue is not empty - append to active\n" );
1335                 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1336                                   vb.queue);
1337                 list_add_tail(&buf->vb.queue, &cx88q->active);
1338                 buf->vb.state = VIDEOBUF_ACTIVE;
1339                 buf->count    = cx88q->count++;
1340                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1341                 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1342                 dprintk( 1, "[%p/%d] %s - append to active\n",
1343                          buf, buf->vb.i, __FUNCTION__);
1344         }
1345 }
1346
1347 /* ----------------------------------------------------------- */
1348
1349 static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
1350                               int restart)
1351 {
1352         struct cx23885_dev *dev = port->dev;
1353         struct cx23885_dmaqueue *q = &port->mpegq;
1354         struct cx23885_buffer *buf;
1355         unsigned long flags;
1356
1357         spin_lock_irqsave(&port->slock, flags);
1358         while (!list_empty(&q->active)) {
1359                 buf = list_entry(q->active.next, struct cx23885_buffer,
1360                                  vb.queue);
1361                 list_del(&buf->vb.queue);
1362                 buf->vb.state = VIDEOBUF_ERROR;
1363                 wake_up(&buf->vb.done);
1364                 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
1365                         buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
1366         }
1367         if (restart) {
1368                 dprintk(1, "restarting queue\n" );
1369                 cx23885_restart_queue(port, q);
1370         }
1371         spin_unlock_irqrestore(&port->slock, flags);
1372 }
1373
1374
1375 static void cx23885_timeout(unsigned long data)
1376 {
1377         struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1378         struct cx23885_dev *dev = port->dev;
1379
1380         dprintk(1, "%s()\n",__FUNCTION__);
1381
1382         if (debug > 5)
1383                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1384
1385         cx23885_stop_dma(port);
1386         do_cancel_buffers(port, "timeout", 1);
1387 }
1388
1389 static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status)
1390 {
1391         struct cx23885_dev *dev = port->dev;
1392         int handled = 0;
1393         u32 count;
1394
1395         if ( (status & VID_BC_MSK_OPC_ERR) ||
1396              (status & VID_BC_MSK_BAD_PKT) ||
1397              (status & VID_BC_MSK_SYNC) ||
1398              (status & VID_BC_MSK_OF))
1399         {
1400                 if (status & VID_BC_MSK_OPC_ERR)
1401                         dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n", VID_BC_MSK_OPC_ERR);
1402                 if (status & VID_BC_MSK_BAD_PKT)
1403                         dprintk(7, " (VID_BC_MSK_BAD_PKT 0x%08x)\n", VID_BC_MSK_BAD_PKT);
1404                 if (status & VID_BC_MSK_SYNC)
1405                         dprintk(7, " (VID_BC_MSK_SYNC    0x%08x)\n", VID_BC_MSK_SYNC);
1406                 if (status & VID_BC_MSK_OF)
1407                         dprintk(7, " (VID_BC_MSK_OF      0x%08x)\n", VID_BC_MSK_OF);
1408
1409                 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1410
1411                 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1412                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1413
1414         } else if (status & VID_BC_MSK_RISCI1) {
1415
1416                 dprintk(7, " (RISCI1            0x%08x)\n", VID_BC_MSK_RISCI1);
1417
1418                 spin_lock(&port->slock);
1419                 count = cx_read(port->reg_gpcnt);
1420                 cx23885_wakeup(port, &port->mpegq, count);
1421                 spin_unlock(&port->slock);
1422
1423         } else if (status & VID_BC_MSK_RISCI2) {
1424
1425                 dprintk(7, " (RISCI2            0x%08x)\n", VID_BC_MSK_RISCI2);
1426
1427                 spin_lock(&port->slock);
1428                 cx23885_restart_queue(port, &port->mpegq);
1429                 spin_unlock(&port->slock);
1430
1431         }
1432         if (status) {
1433                 cx_write(port->reg_ts_int_stat, status);
1434                 handled = 1;
1435         }
1436
1437         return handled;
1438 }
1439
1440 static irqreturn_t cx23885_irq(int irq, void *dev_id)
1441 {
1442         struct cx23885_dev *dev = dev_id;
1443         struct cx23885_tsport *ts1 = &dev->ts1;
1444         struct cx23885_tsport *ts2 = &dev->ts2;
1445         u32 pci_status, pci_mask;
1446         u32 vida_status, vida_mask;
1447         u32 ts1_status, ts1_mask;
1448         u32 ts2_status, ts2_mask;
1449         int vida_count = 0, ts1_count = 0, ts2_count = 0, handled = 0;
1450
1451         pci_status = cx_read(PCI_INT_STAT);
1452         pci_mask = cx_read(PCI_INT_MSK);
1453         vida_status = cx_read(VID_A_INT_STAT);
1454         vida_mask = cx_read(VID_A_INT_MSK);
1455         ts1_status = cx_read(VID_B_INT_STAT);
1456         ts1_mask = cx_read(VID_B_INT_MSK);
1457         ts2_status = cx_read(VID_C_INT_STAT);
1458         ts2_mask = cx_read(VID_C_INT_MSK);
1459
1460         if ( (pci_status == 0) && (ts2_status == 0) && (ts1_status == 0) )
1461                 goto out;
1462
1463         vida_count = cx_read(VID_A_GPCNT);
1464         ts1_count = cx_read(ts1->reg_gpcnt);
1465         ts2_count = cx_read(ts2->reg_gpcnt);
1466         dprintk(7, "pci_status: 0x%08x  pci_mask: 0x%08x\n",
1467                 pci_status, pci_mask);
1468         dprintk(7, "vida_status: 0x%08x vida_mask: 0x%08x count: 0x%x\n",
1469                 vida_status, vida_mask, vida_count);
1470         dprintk(7, "ts1_status: 0x%08x  ts1_mask: 0x%08x count: 0x%x\n",
1471                 ts1_status, ts1_mask, ts1_count);
1472         dprintk(7, "ts2_status: 0x%08x  ts2_mask: 0x%08x count: 0x%x\n",
1473                 ts2_status, ts2_mask, ts2_count);
1474
1475         if ( (pci_status & PCI_MSK_RISC_RD) ||
1476              (pci_status & PCI_MSK_RISC_WR) ||
1477              (pci_status & PCI_MSK_AL_RD) ||
1478              (pci_status & PCI_MSK_AL_WR) ||
1479              (pci_status & PCI_MSK_APB_DMA) ||
1480              (pci_status & PCI_MSK_VID_C) ||
1481              (pci_status & PCI_MSK_VID_B) ||
1482              (pci_status & PCI_MSK_VID_A) ||
1483              (pci_status & PCI_MSK_AUD_INT) ||
1484              (pci_status & PCI_MSK_AUD_EXT) )
1485         {
1486
1487                 if (pci_status & PCI_MSK_RISC_RD)
1488                         dprintk(7, " (PCI_MSK_RISC_RD   0x%08x)\n", PCI_MSK_RISC_RD);
1489                 if (pci_status & PCI_MSK_RISC_WR)
1490                         dprintk(7, " (PCI_MSK_RISC_WR   0x%08x)\n", PCI_MSK_RISC_WR);
1491                 if (pci_status & PCI_MSK_AL_RD)
1492                         dprintk(7, " (PCI_MSK_AL_RD     0x%08x)\n", PCI_MSK_AL_RD);
1493                 if (pci_status & PCI_MSK_AL_WR)
1494                         dprintk(7, " (PCI_MSK_AL_WR     0x%08x)\n", PCI_MSK_AL_WR);
1495                 if (pci_status & PCI_MSK_APB_DMA)
1496                         dprintk(7, " (PCI_MSK_APB_DMA   0x%08x)\n", PCI_MSK_APB_DMA);
1497                 if (pci_status & PCI_MSK_VID_C)
1498                         dprintk(7, " (PCI_MSK_VID_C     0x%08x)\n", PCI_MSK_VID_C);
1499                 if (pci_status & PCI_MSK_VID_B)
1500                         dprintk(7, " (PCI_MSK_VID_B     0x%08x)\n", PCI_MSK_VID_B);
1501                 if (pci_status & PCI_MSK_VID_A)
1502                         dprintk(7, " (PCI_MSK_VID_A     0x%08x)\n", PCI_MSK_VID_A);
1503                 if (pci_status & PCI_MSK_AUD_INT)
1504                         dprintk(7, " (PCI_MSK_AUD_INT   0x%08x)\n", PCI_MSK_AUD_INT);
1505                 if (pci_status & PCI_MSK_AUD_EXT)
1506                         dprintk(7, " (PCI_MSK_AUD_EXT   0x%08x)\n", PCI_MSK_AUD_EXT);
1507
1508         }
1509
1510         if (ts1_status) {
1511                 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
1512                         handled += cx23885_irq_ts(ts1, ts1_status);
1513         }
1514
1515         if (ts2_status) {
1516                 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
1517                         handled += cx23885_irq_ts(ts2, ts2_status);
1518         }
1519
1520         if (vida_status)
1521                 handled += cx23885_video_irq(dev, vida_status);
1522
1523         if (handled)
1524                 cx_write(PCI_INT_STAT, pci_status);
1525 out:
1526         return IRQ_RETVAL(handled);
1527 }
1528
1529 static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
1530                                      const struct pci_device_id *pci_id)
1531 {
1532         struct cx23885_dev *dev;
1533         int err;
1534
1535         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1536         if (NULL == dev)
1537                 return -ENOMEM;
1538
1539         /* pci init */
1540         dev->pci = pci_dev;
1541         if (pci_enable_device(pci_dev)) {
1542                 err = -EIO;
1543                 goto fail_free;
1544         }
1545
1546         if (cx23885_dev_setup(dev) < 0) {
1547                 err = -EINVAL;
1548                 goto fail_free;
1549         }
1550
1551         /* print pci info */
1552         pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1553         pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER,  &dev->pci_lat);
1554         printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1555                "latency: %d, mmio: 0x%llx\n", dev->name,
1556                pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1557                dev->pci_lat, (unsigned long long)pci_resource_start(pci_dev,0));
1558
1559         pci_set_master(pci_dev);
1560         if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1561                 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1562                 err = -EIO;
1563                 goto fail_irq;
1564         }
1565
1566         err = request_irq(pci_dev->irq, cx23885_irq,
1567                           IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
1568         if (err < 0) {
1569                 printk(KERN_ERR "%s: can't get IRQ %d\n",
1570                        dev->name, pci_dev->irq);
1571                 goto fail_irq;
1572         }
1573
1574         pci_set_drvdata(pci_dev, dev);
1575         return 0;
1576
1577 fail_irq:
1578         cx23885_dev_unregister(dev);
1579 fail_free:
1580         kfree(dev);
1581         return err;
1582 }
1583
1584 static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
1585 {
1586         struct cx23885_dev *dev = pci_get_drvdata(pci_dev);
1587
1588         cx23885_shutdown(dev);
1589
1590         pci_disable_device(pci_dev);
1591
1592         /* unregister stuff */
1593         free_irq(pci_dev->irq, dev);
1594         pci_set_drvdata(pci_dev, NULL);
1595
1596         mutex_lock(&devlist);
1597         list_del(&dev->devlist);
1598         mutex_unlock(&devlist);
1599
1600         cx23885_dev_unregister(dev);
1601         kfree(dev);
1602 }
1603
1604 static struct pci_device_id cx23885_pci_tbl[] = {
1605         {
1606                 /* CX23885 */
1607                 .vendor       = 0x14f1,
1608                 .device       = 0x8852,
1609                 .subvendor    = PCI_ANY_ID,
1610                 .subdevice    = PCI_ANY_ID,
1611         },{
1612                 /* CX23887 Rev 2 */
1613                 .vendor       = 0x14f1,
1614                 .device       = 0x8880,
1615                 .subvendor    = PCI_ANY_ID,
1616                 .subdevice    = PCI_ANY_ID,
1617         },{
1618                 /* --- end of list --- */
1619         }
1620 };
1621 MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
1622
1623 static struct pci_driver cx23885_pci_driver = {
1624         .name     = "cx23885",
1625         .id_table = cx23885_pci_tbl,
1626         .probe    = cx23885_initdev,
1627         .remove   = __devexit_p(cx23885_finidev),
1628         /* TODO */
1629         .suspend  = NULL,
1630         .resume   = NULL,
1631 };
1632
1633 static int cx23885_init(void)
1634 {
1635         printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
1636                (CX23885_VERSION_CODE >> 16) & 0xff,
1637                (CX23885_VERSION_CODE >>  8) & 0xff,
1638                CX23885_VERSION_CODE & 0xff);
1639 #ifdef SNAPSHOT
1640         printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
1641                SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
1642 #endif
1643         return pci_register_driver(&cx23885_pci_driver);
1644 }
1645
1646 static void cx23885_fini(void)
1647 {
1648         pci_unregister_driver(&cx23885_pci_driver);
1649 }
1650
1651 module_init(cx23885_init);
1652 module_exit(cx23885_fini);
1653
1654 /* ----------------------------------------------------------- */
1655 /*
1656  * Local variables:
1657  * c-basic-offset: 8
1658  * End:
1659  * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off
1660  */