err.no Git - linux-2.6/blob - drivers/media/video/cx23885/cx23885-core.c

   1 /*
   2  *  Driver for the Conexant CX23885 PCIe bridge
   3  *
   4  *  Copyright (c) 2006 Steven Toth <stoth@hauppauge.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/list.h>
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/kmod.h>
  27 #include <linux/kernel.h>
  28 #include <linux/slab.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/delay.h>
  31 #include <asm/div64.h>
  32
  33 #include "cx23885.h"
  34
  35 MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
  36 MODULE_AUTHOR("Steven Toth <stoth@hauppauge.com>");
  37 MODULE_LICENSE("GPL");
  38
  39 static unsigned int debug = 0;
  40 module_param(debug,int,0644);
  41 MODULE_PARM_DESC(debug,"enable debug messages");
  42
  43 static unsigned int card[]  = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
  44 module_param_array(card,  int, NULL, 0444);
  45 MODULE_PARM_DESC(card,"card type");
  46
  47 #define dprintk(level,fmt, arg...)      if (debug >= level) \
  48         printk(KERN_DEBUG "%s/0: " fmt, dev->name , ## arg)
  49
  50 static unsigned int cx23885_devcount;
  51
  52 static DEFINE_MUTEX(devlist);
  53 LIST_HEAD(cx23885_devlist);
  54
  55 #define NO_SYNC_LINE (-1U)
  56
  57 /*
  58  * CX23885 Assumptions
  59  * 1 line = 16 bytes of CDT
  60  * cmds size = 80
  61  * cdt size = 16 * linesize
  62  * iqsize = 64
  63  * maxlines = 6
  64  *
  65  * Address Space:
  66  * 0x00000000 0x00008fff FIFO clusters
  67  * 0x00010000 0x000104af Channel Management Data Structures
  68  * 0x000104b0 0x000104ff Free
  69  * 0x00010500 0x000108bf 15 channels * iqsize
  70  * 0x000108c0 0x000108ff Free
  71  * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
  72  *                       15 channels * (iqsize + (maxlines * linesize))
  73  * 0x00010ea0 0x00010xxx Free
  74  */
  75
  76 static struct sram_channel cx23885_sram_channels[] = {
  77         [SRAM_CH01] = {
  78                 .name           = "VID A",
  79                 .cmds_start     = 0x10000,
  80                 .ctrl_start     = 0x105b0,
  81                 .cdt            = 0x107b0,
  82                 .fifo_start     = 0x40,
  83                 .fifo_size      = 0x2800,
  84                 .ptr1_reg       = DMA1_PTR1,
  85                 .ptr2_reg       = DMA1_PTR2,
  86                 .cnt1_reg       = DMA1_CNT1,
  87                 .cnt2_reg       = DMA1_CNT2,
  88                 .jumponly       = 1,
  89         },
  90         [SRAM_CH02] = {
  91                 .name           = "ch2",
  92                 .cmds_start     = 0x0,
  93                 .ctrl_start     = 0x0,
  94                 .cdt            = 0x0,
  95                 .fifo_start     = 0x0,
  96                 .fifo_size      = 0x0,
  97                 .ptr1_reg       = DMA2_PTR1,
  98                 .ptr2_reg       = DMA2_PTR2,
  99                 .cnt1_reg       = DMA2_CNT1,
 100                 .cnt2_reg       = DMA2_CNT2,
 101         },
 102         [SRAM_CH03] = {
 103                 .name           = "TS1 B",
 104                 .cmds_start     = 0x100A0,
 105                 .ctrl_start     = 0x10630,
 106                 .cdt            = 0x10870,
 107                 .fifo_start     = 0x5000,
 108                 .fifo_size      = 0x1000,
 109                 .ptr1_reg       = DMA3_PTR1,
 110                 .ptr2_reg       = DMA3_PTR2,
 111                 .cnt1_reg       = DMA3_CNT1,
 112                 .cnt2_reg       = DMA3_CNT2,
 113         },
 114         [SRAM_CH04] = {
 115                 .name           = "ch4",
 116                 .cmds_start     = 0x0,
 117                 .ctrl_start     = 0x0,
 118                 .cdt            = 0x0,
 119                 .fifo_start     = 0x0,
 120                 .fifo_size      = 0x0,
 121                 .ptr1_reg       = DMA4_PTR1,
 122                 .ptr2_reg       = DMA4_PTR2,
 123                 .cnt1_reg       = DMA4_CNT1,
 124                 .cnt2_reg       = DMA4_CNT2,
 125         },
 126         [SRAM_CH05] = {
 127                 .name           = "ch5",
 128                 .cmds_start     = 0x0,
 129                 .ctrl_start     = 0x0,
 130                 .cdt            = 0x0,
 131                 .fifo_start     = 0x0,
 132                 .fifo_size      = 0x0,
 133                 .ptr1_reg       = DMA5_PTR1,
 134                 .ptr2_reg       = DMA5_PTR2,
 135                 .cnt1_reg       = DMA5_CNT1,
 136                 .cnt2_reg       = DMA5_CNT2,
 137         },
 138         [SRAM_CH06] = {
 139                 .name           = "TS2 C",
 140                 .cmds_start     = 0x10140,
 141                 .ctrl_start     = 0x10680,
 142                 .cdt            = 0x108d0,
 143                 .fifo_start     = 0x6000,
 144                 .fifo_size      = 0x1000,
 145                 .ptr1_reg       = DMA5_PTR1,
 146                 .ptr2_reg       = DMA5_PTR2,
 147                 .cnt1_reg       = DMA5_CNT1,
 148                 .cnt2_reg       = DMA5_CNT2,
 149         },
 150         [SRAM_CH07] = {
 151                 .name           = "ch7",
 152                 .cmds_start     = 0x0,
 153                 .ctrl_start     = 0x0,
 154                 .cdt            = 0x0,
 155                 .fifo_start     = 0x0,
 156                 .fifo_size      = 0x0,
 157                 .ptr1_reg       = DMA6_PTR1,
 158                 .ptr2_reg       = DMA6_PTR2,
 159                 .cnt1_reg       = DMA6_CNT1,
 160                 .cnt2_reg       = DMA6_CNT2,
 161         },
 162         [SRAM_CH08] = {
 163                 .name           = "ch8",
 164                 .cmds_start     = 0x0,
 165                 .ctrl_start     = 0x0,
 166                 .cdt            = 0x0,
 167                 .fifo_start     = 0x0,
 168                 .fifo_size      = 0x0,
 169                 .ptr1_reg       = DMA7_PTR1,
 170                 .ptr2_reg       = DMA7_PTR2,
 171                 .cnt1_reg       = DMA7_CNT1,
 172                 .cnt2_reg       = DMA7_CNT2,
 173         },
 174         [SRAM_CH09] = {
 175                 .name           = "ch9",
 176                 .cmds_start     = 0x0,
 177                 .ctrl_start     = 0x0,
 178                 .cdt            = 0x0,
 179                 .fifo_start     = 0x0,
 180                 .fifo_size      = 0x0,
 181                 .ptr1_reg       = DMA8_PTR1,
 182                 .ptr2_reg       = DMA8_PTR2,
 183                 .cnt1_reg       = DMA8_CNT1,
 184                 .cnt2_reg       = DMA8_CNT2,
 185         },
 186 };
 187
 188 /* FIXME, these allocations will change when
 189  * analog arrives. The be reviewed.
 190  * CX23887 Assumptions
 191  * 1 line = 16 bytes of CDT
 192  * cmds size = 80
 193  * cdt size = 16 * linesize
 194  * iqsize = 64
 195  * maxlines = 6
 196  *
 197  * Address Space:
 198  * 0x00000000 0x00008fff FIFO clusters
 199  * 0x00010000 0x000104af Channel Management Data Structures
 200  * 0x000104b0 0x000104ff Free
 201  * 0x00010500 0x000108bf 15 channels * iqsize
 202  * 0x000108c0 0x000108ff Free
 203  * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
 204  *                       15 channels * (iqsize + (maxlines * linesize))
 205  * 0x00010ea0 0x00010xxx Free
 206  */
 207
 208 static struct sram_channel cx23887_sram_channels[] = {
 209         [SRAM_CH01] = {
 210                 .name           = "VID A",
 211                 .cmds_start     = 0x10000,
 212                 .ctrl_start     = 0x105b0,
 213                 .cdt            = 0x107b0,
 214                 .fifo_start     = 0x40,
 215                 .fifo_size      = 0x2800,
 216                 .ptr1_reg       = DMA1_PTR1,
 217                 .ptr2_reg       = DMA1_PTR2,
 218                 .cnt1_reg       = DMA1_CNT1,
 219                 .cnt2_reg       = DMA1_CNT2,
 220         },
 221         [SRAM_CH02] = {
 222                 .name           = "ch2",
 223                 .cmds_start     = 0x0,
 224                 .ctrl_start     = 0x0,
 225                 .cdt            = 0x0,
 226                 .fifo_start     = 0x0,
 227                 .fifo_size      = 0x0,
 228                 .ptr1_reg       = DMA2_PTR1,
 229                 .ptr2_reg       = DMA2_PTR2,
 230                 .cnt1_reg       = DMA2_CNT1,
 231                 .cnt2_reg       = DMA2_CNT2,
 232         },
 233         [SRAM_CH03] = {
 234                 .name           = "TS1 B",
 235                 .cmds_start     = 0x100A0,
 236                 .ctrl_start     = 0x10780,
 237                 .cdt            = 0x10400,
 238                 .fifo_start     = 0x5000,
 239                 .fifo_size      = 0x1000,
 240                 .ptr1_reg       = DMA3_PTR1,
 241                 .ptr2_reg       = DMA3_PTR2,
 242                 .cnt1_reg       = DMA3_CNT1,
 243                 .cnt2_reg       = DMA3_CNT2,
 244         },
 245         [SRAM_CH04] = {
 246                 .name           = "ch4",
 247                 .cmds_start     = 0x0,
 248                 .ctrl_start     = 0x0,
 249                 .cdt            = 0x0,
 250                 .fifo_start     = 0x0,
 251                 .fifo_size      = 0x0,
 252                 .ptr1_reg       = DMA4_PTR1,
 253                 .ptr2_reg       = DMA4_PTR2,
 254                 .cnt1_reg       = DMA4_CNT1,
 255                 .cnt2_reg       = DMA4_CNT2,
 256         },
 257         [SRAM_CH05] = {
 258                 .name           = "ch5",
 259                 .cmds_start     = 0x0,
 260                 .ctrl_start     = 0x0,
 261                 .cdt            = 0x0,
 262                 .fifo_start     = 0x0,
 263                 .fifo_size      = 0x0,
 264                 .ptr1_reg       = DMA5_PTR1,
 265                 .ptr2_reg       = DMA5_PTR2,
 266                 .cnt1_reg       = DMA5_CNT1,
 267                 .cnt2_reg       = DMA5_CNT2,
 268         },
 269         [SRAM_CH06] = {
 270                 .name           = "TS2 C",
 271                 .cmds_start     = 0x10140,
 272                 .ctrl_start     = 0x10680,
 273                 .cdt            = 0x108d0,
 274                 .fifo_start     = 0x6000,
 275                 .fifo_size      = 0x1000,
 276                 .ptr1_reg       = DMA5_PTR1,
 277                 .ptr2_reg       = DMA5_PTR2,
 278                 .cnt1_reg       = DMA5_CNT1,
 279                 .cnt2_reg       = DMA5_CNT2,
 280         },
 281         [SRAM_CH07] = {
 282                 .name           = "ch7",
 283                 .cmds_start     = 0x0,
 284                 .ctrl_start     = 0x0,
 285                 .cdt            = 0x0,
 286                 .fifo_start     = 0x0,
 287                 .fifo_size      = 0x0,
 288                 .ptr1_reg       = DMA6_PTR1,
 289                 .ptr2_reg       = DMA6_PTR2,
 290                 .cnt1_reg       = DMA6_CNT1,
 291                 .cnt2_reg       = DMA6_CNT2,
 292         },
 293         [SRAM_CH08] = {
 294                 .name           = "ch8",
 295                 .cmds_start     = 0x0,
 296                 .ctrl_start     = 0x0,
 297                 .cdt            = 0x0,
 298                 .fifo_start     = 0x0,
 299                 .fifo_size      = 0x0,
 300                 .ptr1_reg       = DMA7_PTR1,
 301                 .ptr2_reg       = DMA7_PTR2,
 302                 .cnt1_reg       = DMA7_CNT1,
 303                 .cnt2_reg       = DMA7_CNT2,
 304         },
 305         [SRAM_CH09] = {
 306                 .name           = "ch9",
 307                 .cmds_start     = 0x0,
 308                 .ctrl_start     = 0x0,
 309                 .cdt            = 0x0,
 310                 .fifo_start     = 0x0,
 311                 .fifo_size      = 0x0,
 312                 .ptr1_reg       = DMA8_PTR1,
 313                 .ptr2_reg       = DMA8_PTR2,
 314                 .cnt1_reg       = DMA8_CNT1,
 315                 .cnt2_reg       = DMA8_CNT2,
 316         },
 317 };
 318
 319 static int cx23885_risc_decode(u32 risc)
 320 {
 321         static char *instr[16] = {
 322                 [ RISC_SYNC    >> 28 ] = "sync",
 323                 [ RISC_WRITE   >> 28 ] = "write",
 324                 [ RISC_WRITEC  >> 28 ] = "writec",
 325                 [ RISC_READ    >> 28 ] = "read",
 326                 [ RISC_READC   >> 28 ] = "readc",
 327                 [ RISC_JUMP    >> 28 ] = "jump",
 328                 [ RISC_SKIP    >> 28 ] = "skip",
 329                 [ RISC_WRITERM >> 28 ] = "writerm",
 330                 [ RISC_WRITECM >> 28 ] = "writecm",
 331                 [ RISC_WRITECR >> 28 ] = "writecr",
 332         };
 333         static int incr[16] = {
 334                 [ RISC_WRITE   >> 28 ] = 3,
 335                 [ RISC_JUMP    >> 28 ] = 3,
 336                 [ RISC_SKIP    >> 28 ] = 1,
 337                 [ RISC_SYNC    >> 28 ] = 1,
 338                 [ RISC_WRITERM >> 28 ] = 3,
 339                 [ RISC_WRITECM >> 28 ] = 3,
 340                 [ RISC_WRITECR >> 28 ] = 4,
 341         };
 342         static char *bits[] = {
 343                 "12",   "13",   "14",   "resync",
 344                 "cnt0", "cnt1", "18",   "19",
 345                 "20",   "21",   "22",   "23",
 346                 "irq1", "irq2", "eol",  "sol",
 347         };
 348         int i;
 349
 350         printk("0x%08x [ %s", risc,
 351                instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
 352         for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
 353                 if (risc & (1 << (i + 12)))
 354                         printk(" %s", bits[i]);
 355         printk(" count=%d ]\n", risc & 0xfff);
 356         return incr[risc >> 28] ? incr[risc >> 28] : 1;
 357 }
 358
 359 void cx23885_wakeup(struct cx23885_tsport *port,
 360                            struct cx23885_dmaqueue *q, u32 count)
 361 {
 362         struct cx23885_dev *dev = port->dev;
 363         struct cx23885_buffer *buf;
 364         int bc;
 365
 366         for (bc = 0;; bc++) {
 367                 if (list_empty(&q->active))
 368                         break;
 369                 buf = list_entry(q->active.next,
 370                                  struct cx23885_buffer, vb.queue);
 371
 372                 /* count comes from the hw and is is 16bit wide --
 373                  * this trick handles wrap-arounds correctly for
 374                  * up to 32767 buffers in flight... */
 375                 if ((s16) (count - buf->count) < 0)
 376                         break;
 377
 378                 do_gettimeofday(&buf->vb.ts);
 379                 dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
 380                         count, buf->count);
 381                 buf->vb.state = VIDEOBUF_DONE;
 382                 list_del(&buf->vb.queue);
 383                 wake_up(&buf->vb.done);
 384         }
 385         if (list_empty(&q->active)) {
 386                 del_timer(&q->timeout);
 387         } else {
 388                 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
 389         }
 390         if (bc != 1)
 391                 printk("%s: %d buffers handled (should be 1)\n",
 392                        __FUNCTION__, bc);
 393 }
 394
 395 int cx23885_sram_channel_setup(struct cx23885_dev *dev,
 396                                       struct sram_channel *ch,
 397                                       unsigned int bpl, u32 risc)
 398 {
 399         unsigned int i, lines;
 400         u32 cdt;
 401
 402         if (ch->cmds_start == 0)
 403         {
 404                 dprintk(1, "%s() Erasing channel [%s]\n", __FUNCTION__,
 405                         ch->name);
 406                 cx_write(ch->ptr1_reg, 0);
 407                 cx_write(ch->ptr2_reg, 0);
 408                 cx_write(ch->cnt2_reg, 0);
 409                 cx_write(ch->cnt1_reg, 0);
 410                 return 0;
 411         } else {
 412                 dprintk(1, "%s() Configuring channel [%s]\n", __FUNCTION__,
 413                         ch->name);
 414         }
 415
 416         bpl   = (bpl + 7) & ~7; /* alignment */
 417         cdt   = ch->cdt;
 418         lines = ch->fifo_size / bpl;
 419         if (lines > 6)
 420                 lines = 6;
 421         BUG_ON(lines < 2);
 422
 423         cx_write(8 + 0, cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC) );
 424         cx_write(8 + 4, cpu_to_le32(8) );
 425         cx_write(8 + 8, cpu_to_le32(0) );
 426
 427         /* write CDT */
 428         for (i = 0; i < lines; i++) {
 429                 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __FUNCTION__, cdt + 16*i,
 430                         ch->fifo_start + bpl*i);
 431                 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
 432                 cx_write(cdt + 16*i +  4, 0);
 433                 cx_write(cdt + 16*i +  8, 0);
 434                 cx_write(cdt + 16*i + 12, 0);
 435         }
 436
 437         /* write CMDS */
 438         if (ch->jumponly)
 439                 cx_write(ch->cmds_start +  0, 8);
 440         else
 441                 cx_write(ch->cmds_start +  0, risc);
 442         cx_write(ch->cmds_start +  4, 0); /* 64 bits 63-32 */
 443         cx_write(ch->cmds_start +  8, cdt);
 444         cx_write(ch->cmds_start + 12, (lines*16) >> 3);
 445         cx_write(ch->cmds_start + 16, ch->ctrl_start);
 446         if (ch->jumponly)
 447                 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2) );
 448         else
 449                 cx_write(ch->cmds_start + 20, 64 >> 2);
 450         for (i = 24; i < 80; i += 4)
 451                 cx_write(ch->cmds_start + i, 0);
 452
 453         /* fill registers */
 454         cx_write(ch->ptr1_reg, ch->fifo_start);
 455         cx_write(ch->ptr2_reg, cdt);
 456         cx_write(ch->cnt2_reg, (lines*16) >> 3);
 457         cx_write(ch->cnt1_reg, (bpl >> 3) -1);
 458
 459         dprintk(2,"[bridge %d] sram setup %s: bpl=%d lines=%d\n",
 460                 dev->bridge,
 461                 ch->name,
 462                 bpl,
 463                 lines);
 464
 465         return 0;
 466 }
 467
 468 void cx23885_sram_channel_dump(struct cx23885_dev *dev,
 469                                       struct sram_channel *ch)
 470 {
 471         static char *name[] = {
 472                 "init risc lo",
 473                 "init risc hi",
 474                 "cdt base",
 475                 "cdt size",
 476                 "iq base",
 477                 "iq size",
 478                 "risc pc lo",
 479                 "risc pc hi",
 480                 "iq wr ptr",
 481                 "iq rd ptr",
 482                 "cdt current",
 483                 "pci target lo",
 484                 "pci target hi",
 485                 "line / byte",
 486         };
 487         u32 risc;
 488         unsigned int i, j, n;
 489
 490         printk("%s: %s - dma channel status dump\n",
 491                dev->name, ch->name);
 492         for (i = 0; i < ARRAY_SIZE(name); i++)
 493                 printk("%s:   cmds: %-15s: 0x%08x\n",
 494                        dev->name, name[i],
 495                        cx_read(ch->cmds_start + 4*i));
 496
 497         for (i = 0; i < 4; i++) {
 498                 risc = cx_read(ch->cmds_start + 4 * (i + 14));
 499                 printk("%s:   risc%d: ", dev->name, i);
 500                 cx23885_risc_decode(risc);
 501         }
 502         for (i = 0; i < (64 >> 2); i += n) {
 503                 risc = cx_read(ch->ctrl_start + 4 * i);
 504                 /* No consideration for bits 63-32 */
 505
 506                 printk("%s:   (0x%08x) iq %x: ", dev->name,
 507                        ch->ctrl_start + 4 * i, i);
 508                 n = cx23885_risc_decode(risc);
 509                 for (j = 1; j < n; j++) {
 510                         risc = cx_read(ch->ctrl_start + 4 * (i + j));
 511                         printk("%s:   iq %x: 0x%08x [ arg #%d ]\n",
 512                                dev->name, i+j, risc, j);
 513                 }
 514         }
 515
 516         printk("%s: fifo: 0x%08x -> 0x%x\n",
 517                dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
 518         printk("%s: ctrl: 0x%08x -> 0x%x\n",
 519                dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
 520         printk("%s:   ptr1_reg: 0x%08x\n",
 521                dev->name, cx_read(ch->ptr1_reg));
 522         printk("%s:   ptr2_reg: 0x%08x\n",
 523                dev->name, cx_read(ch->ptr2_reg));
 524         printk("%s:   cnt1_reg: 0x%08x\n",
 525                dev->name, cx_read(ch->cnt1_reg));
 526         printk("%s:   cnt2_reg: 0x%08x\n",
 527                dev->name, cx_read(ch->cnt2_reg));
 528 }
 529
 530 static void cx23885_risc_disasm(struct cx23885_tsport *port,
 531                                 struct btcx_riscmem *risc)
 532 {
 533         struct cx23885_dev *dev = port->dev;
 534         unsigned int i, j, n;
 535
 536         printk("%s: risc disasm: %p [dma=0x%08lx]\n",
 537                dev->name, risc->cpu, (unsigned long)risc->dma);
 538         for (i = 0; i < (risc->size >> 2); i += n) {
 539                 printk("%s:   %04d: ", dev->name, i);
 540                 n = cx23885_risc_decode(risc->cpu[i]);
 541                 for (j = 1; j < n; j++)
 542                         printk("%s:   %04d: 0x%08x [ arg #%d ]\n",
 543                                dev->name, i + j, risc->cpu[i + j], j);
 544                 if (risc->cpu[i] == RISC_JUMP)
 545                         break;
 546         }
 547 }
 548
 549 static void cx23885_shutdown(struct cx23885_dev *dev)
 550 {
 551         /* disable RISC controller */
 552         cx_write(DEV_CNTRL2, 0);
 553
 554         /* Disable all IR activity */
 555         cx_write(IR_CNTRL_REG, 0);
 556
 557         /* Disable Video A/B activity */
 558         cx_write(VID_A_DMA_CTL, 0);
 559         cx_write(VID_B_DMA_CTL, 0);
 560         cx_write(VID_C_DMA_CTL, 0);
 561
 562         /* Disable Audio activity */
 563         cx_write(AUD_INT_DMA_CTL, 0);
 564         cx_write(AUD_EXT_DMA_CTL, 0);
 565
 566         /* Disable Serial port */
 567         cx_write(UART_CTL, 0);
 568
 569         /* Disable Interrupts */
 570         cx_write(PCI_INT_MSK, 0);
 571         cx_write(VID_A_INT_MSK, 0);
 572         cx_write(VID_B_INT_MSK, 0);
 573         cx_write(VID_C_INT_MSK, 0);
 574         cx_write(AUDIO_INT_INT_MSK, 0);
 575         cx_write(AUDIO_EXT_INT_MSK, 0);
 576
 577 }
 578
 579 static void cx23885_reset(struct cx23885_dev *dev)
 580 {
 581         dprintk(1, "%s()\n", __FUNCTION__);
 582
 583         cx23885_shutdown(dev);
 584
 585         cx_write(PCI_INT_STAT, 0xffffffff);
 586         cx_write(VID_A_INT_STAT, 0xffffffff);
 587         cx_write(VID_B_INT_STAT, 0xffffffff);
 588         cx_write(VID_C_INT_STAT, 0xffffffff);
 589         cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
 590         cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
 591         cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
 592
 593         mdelay(100);
 594
 595         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01],
 596                 720*4, 0);
 597         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02], 128, 0);
 598         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH03],
 599                 188*4, 0);
 600         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH04], 128, 0);
 601         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH05], 128, 0);
 602         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH06],
 603                 188*4, 0);
 604         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH07], 128, 0);
 605         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH08], 128, 0);
 606         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH09], 128, 0);
 607
 608         cx23885_gpio_setup(dev);
 609 }
 610
 611
 612 static int cx23885_pci_quirks(struct cx23885_dev *dev)
 613 {
 614         dprintk(1, "%s()\n", __FUNCTION__);
 615
 616         /* The cx23885 bridge has a weird bug which causes NMI to be asserted
 617          * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
 618          * occur on the cx23887 bridge.
 619          */
 620         if(dev->bridge == CX23885_BRIDGE_885)
 621                 cx_clear(RDR_TLCTL0, 1 << 4);
 622
 623         return 0;
 624 }
 625
 626 static int get_resources(struct cx23885_dev *dev)
 627 {
 628         if (request_mem_region(pci_resource_start(dev->pci,0),
 629                                pci_resource_len(dev->pci,0),
 630                                dev->name))
 631                 return 0;
 632
 633         printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
 634                 dev->name, (unsigned long long)pci_resource_start(dev->pci,0));
 635
 636         return -EBUSY;
 637 }
 638
 639 static void cx23885_timeout(unsigned long data);
 640 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
 641                                 u32 reg, u32 mask, u32 value);
 642
 643 static int cx23885_init_tsport(struct cx23885_dev *dev, struct cx23885_tsport *port, int portno)
 644 {
 645         dprintk(1, "%s(portno=%d)\n", __FUNCTION__, portno);
 646
 647         /* Transport bus init dma queue  - Common settings */
 648         port->dma_ctl_val        = 0x11; /* Enable RISC controller and Fifo */
 649         port->ts_int_msk_val     = 0x1111; /* TS port bits for RISC */
 650
 651         spin_lock_init(&port->slock);
 652         port->dev = dev;
 653         port->nr = portno;
 654
 655         INIT_LIST_HEAD(&port->mpegq.active);
 656         INIT_LIST_HEAD(&port->mpegq.queued);
 657         port->mpegq.timeout.function = cx23885_timeout;
 658         port->mpegq.timeout.data = (unsigned long)port;
 659         init_timer(&port->mpegq.timeout);
 660
 661         switch(portno) {
 662         case 1:
 663                 port->reg_gpcnt          = VID_B_GPCNT;
 664                 port->reg_gpcnt_ctl      = VID_B_GPCNT_CTL;
 665                 port->reg_dma_ctl        = VID_B_DMA_CTL;
 666                 port->reg_lngth          = VID_B_LNGTH;
 667                 port->reg_hw_sop_ctrl    = VID_B_HW_SOP_CTL;
 668                 port->reg_gen_ctrl       = VID_B_GEN_CTL;
 669                 port->reg_bd_pkt_status  = VID_B_BD_PKT_STATUS;
 670                 port->reg_sop_status     = VID_B_SOP_STATUS;
 671                 port->reg_fifo_ovfl_stat = VID_B_FIFO_OVFL_STAT;
 672                 port->reg_vld_misc       = VID_B_VLD_MISC;
 673                 port->reg_ts_clk_en      = VID_B_TS_CLK_EN;
 674                 port->reg_src_sel        = VID_B_SRC_SEL;
 675                 port->reg_ts_int_msk     = VID_B_INT_MSK;
 676                 port->reg_ts_int_stat   = VID_B_INT_STAT;
 677                 port->sram_chno          = SRAM_CH03; /* VID_B */
 678                 port->pci_irqmask        = 0x02; /* VID_B bit1 */
 679                 break;
 680         case 2:
 681                 port->reg_gpcnt          = VID_C_GPCNT;
 682                 port->reg_gpcnt_ctl      = VID_C_GPCNT_CTL;
 683                 port->reg_dma_ctl        = VID_C_DMA_CTL;
 684                 port->reg_lngth          = VID_C_LNGTH;
 685                 port->reg_hw_sop_ctrl    = VID_C_HW_SOP_CTL;
 686                 port->reg_gen_ctrl       = VID_C_GEN_CTL;
 687                 port->reg_bd_pkt_status  = VID_C_BD_PKT_STATUS;
 688                 port->reg_sop_status     = VID_C_SOP_STATUS;
 689                 port->reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
 690                 port->reg_vld_misc       = VID_C_VLD_MISC;
 691                 port->reg_ts_clk_en      = VID_C_TS_CLK_EN;
 692                 port->reg_src_sel        = 0;
 693                 port->reg_ts_int_msk     = VID_C_INT_MSK;
 694                 port->reg_ts_int_stat    = VID_C_INT_STAT;
 695                 port->sram_chno          = SRAM_CH06; /* VID_C */
 696                 port->pci_irqmask        = 0x04; /* VID_C bit2 */
 697                 break;
 698         default:
 699                 BUG();
 700         }
 701
 702         cx23885_risc_stopper(dev->pci, &port->mpegq.stopper,
 703                      port->reg_dma_ctl, port->dma_ctl_val, 0x00);
 704
 705         return 0;
 706 }
 707
 708 static void cx23885_dev_checkrevision(struct cx23885_dev *dev)
 709 {
 710         switch (cx_read(RDR_CFG2) & 0xff) {
 711         case 0x00:
 712                 /* cx23885 */
 713                 dev->hwrevision = 0xa0;
 714                 break;
 715         case 0x01:
 716                 /* CX23885-12Z */
 717                 dev->hwrevision = 0xa1;
 718                 break;
 719         case 0x02:
 720                 /* CX23885-13Z */
 721                 dev->hwrevision = 0xb0;
 722                 break;
 723         case 0x03:
 724                 /* CX23888-22Z */
 725                 dev->hwrevision = 0xc0;
 726                 break;
 727         case 0x0e:
 728                 /* CX23887-15Z */
 729                 dev->hwrevision = 0xc0;
 730         case 0x0f:
 731                 /* CX23887-14Z */
 732                 dev->hwrevision = 0xb1;
 733                 break;
 734         default:
 735                 printk(KERN_ERR "%s() New hardware revision found 0x%x\n",
 736                         __FUNCTION__, dev->hwrevision);
 737         }
 738         if (dev->hwrevision)
 739                 printk(KERN_INFO "%s() Hardware revision = 0x%02x\n",
 740                         __FUNCTION__, dev->hwrevision);
 741         else
 742                 printk(KERN_ERR "%s() Hardware revision unknown 0x%x\n",
 743                         __FUNCTION__, dev->hwrevision);
 744 }
 745
 746 static int cx23885_dev_setup(struct cx23885_dev *dev)
 747 {
 748         int i;
 749
 750         mutex_init(&dev->lock);
 751
 752         atomic_inc(&dev->refcount);
 753
 754         dev->nr = cx23885_devcount++;
 755         sprintf(dev->name, "cx23885[%d]", dev->nr);
 756
 757         mutex_lock(&devlist);
 758         list_add_tail(&dev->devlist, &cx23885_devlist);
 759         mutex_unlock(&devlist);
 760
 761         /* Configure the internal memory */
 762         if(dev->pci->device == 0x8880) {
 763                 dev->bridge = CX23885_BRIDGE_887;
 764                 dev->sram_channels = cx23887_sram_channels;
 765                 /* Apply a sensible clock frequency for the PCIe bridge */
 766                 dev->clk_freq = 25000000;
 767         } else
 768         if(dev->pci->device == 0x8852) {
 769                 dev->bridge = CX23885_BRIDGE_885;
 770                 dev->sram_channels = cx23885_sram_channels;
 771                 /* Apply a sensible clock frequency for the PCIe bridge */
 772                 dev->clk_freq = 28000000;
 773         } else
 774                 BUG();
 775
 776         dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
 777                 __FUNCTION__, dev->bridge);
 778
 779         /* board config */
 780         dev->board = UNSET;
 781         if (card[dev->nr] < cx23885_bcount)
 782                 dev->board = card[dev->nr];
 783         for (i = 0; UNSET == dev->board  &&  i < cx23885_idcount; i++)
 784                 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
 785                     dev->pci->subsystem_device == cx23885_subids[i].subdevice)
 786                         dev->board = cx23885_subids[i].card;
 787         if (UNSET == dev->board) {
 788                 dev->board = CX23885_BOARD_UNKNOWN;
 789                 cx23885_card_list(dev);
 790         }
 791
 792         /* If the user specific a clk freq override, apply it */
 793         if (cx23885_boards[dev->board].clk_freq > 0)
 794                 dev->clk_freq = cx23885_boards[dev->board].clk_freq;
 795
 796         dev->pci_bus  = dev->pci->bus->number;
 797         dev->pci_slot = PCI_SLOT(dev->pci->devfn);
 798         dev->pci_irqmask = 0x001f00;
 799
 800         /* External Master 1 Bus */
 801         dev->i2c_bus[0].nr = 0;
 802         dev->i2c_bus[0].dev = dev;
 803         dev->i2c_bus[0].reg_stat  = I2C1_STAT;
 804         dev->i2c_bus[0].reg_ctrl  = I2C1_CTRL;
 805         dev->i2c_bus[0].reg_addr  = I2C1_ADDR;
 806         dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
 807         dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
 808         dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
 809
 810         /* External Master 2 Bus */
 811         dev->i2c_bus[1].nr = 1;
 812         dev->i2c_bus[1].dev = dev;
 813         dev->i2c_bus[1].reg_stat  = I2C2_STAT;
 814         dev->i2c_bus[1].reg_ctrl  = I2C2_CTRL;
 815         dev->i2c_bus[1].reg_addr  = I2C2_ADDR;
 816         dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
 817         dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
 818         dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
 819
 820         /* Internal Master 3 Bus */
 821         dev->i2c_bus[2].nr = 2;
 822         dev->i2c_bus[2].dev = dev;
 823         dev->i2c_bus[2].reg_stat  = I2C3_STAT;
 824         dev->i2c_bus[2].reg_ctrl  = I2C3_CTRL;
 825         dev->i2c_bus[2].reg_addr  = I2C3_ADDR;
 826         dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
 827         dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
 828         dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
 829
 830         if(cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
 831                 cx23885_init_tsport(dev, &dev->ts1, 1);
 832
 833         if(cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
 834                 cx23885_init_tsport(dev, &dev->ts2, 2);
 835
 836         if (get_resources(dev) < 0) {
 837                 printk(KERN_ERR "CORE %s No more PCIe resources for "
 838                        "subsystem: %04x:%04x\n",
 839                        dev->name, dev->pci->subsystem_vendor,
 840                        dev->pci->subsystem_device);
 841
 842                 cx23885_devcount--;
 843                 return -ENODEV;
 844         }
 845
 846         /* PCIe stuff */
 847         dev->lmmio = ioremap(pci_resource_start(dev->pci,0),
 848                              pci_resource_len(dev->pci,0));
 849
 850         dev->bmmio = (u8 __iomem *)dev->lmmio;
 851
 852         printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
 853                dev->name, dev->pci->subsystem_vendor,
 854                dev->pci->subsystem_device, cx23885_boards[dev->board].name,
 855                dev->board, card[dev->nr] == dev->board ?
 856                "insmod option" : "autodetected");
 857
 858         cx23885_pci_quirks(dev);
 859
 860         /* Assume some sensible defaults */
 861         dev->tuner_type = cx23885_boards[dev->board].tuner_type;
 862         dev->tuner_addr = cx23885_boards[dev->board].tuner_addr;
 863         dev->radio_type = cx23885_boards[dev->board].radio_type;
 864         dev->radio_addr = cx23885_boards[dev->board].radio_addr;
 865
 866         dprintk(1, "%s() tuner_type = 0x%x tuner_addr = 0x%x\n",
 867                 __FUNCTION__, dev->tuner_type, dev->tuner_addr);
 868         dprintk(1, "%s() radio_type = 0x%x radio_addr = 0x%x\n",
 869                 __FUNCTION__, dev->radio_type, dev->radio_addr);
 870
 871         /* init hardware */
 872         cx23885_reset(dev);
 873
 874         cx23885_i2c_register(&dev->i2c_bus[0]);
 875         cx23885_i2c_register(&dev->i2c_bus[1]);
 876         cx23885_i2c_register(&dev->i2c_bus[2]);
 877         cx23885_call_i2c_clients (&dev->i2c_bus[0], TUNER_SET_STANDBY, NULL);
 878         cx23885_card_setup(dev);
 879         cx23885_ir_init(dev);
 880
 881         if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO) {
 882                 if (cx23885_video_register(dev) < 0) {
 883                         printk(KERN_ERR "%s() Failed to register analog "
 884                                 "video adapters on VID_A\n", __FUNCTION__);
 885                 }
 886         }
 887
 888         if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
 889                 if (cx23885_dvb_register(&dev->ts1) < 0) {
 890                         printk(KERN_ERR "%s() Failed to register dvb adapters on VID_B\n",
 891                                __FUNCTION__);
 892                 }
 893         }
 894
 895         if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
 896                 if (cx23885_dvb_register(&dev->ts2) < 0) {
 897                         printk(KERN_ERR "%s() Failed to register dvb adapters on VID_C\n",
 898                                __FUNCTION__);
 899                 }
 900         }
 901
 902         cx23885_dev_checkrevision(dev);
 903
 904         return 0;
 905 }
 906
 907 static void cx23885_dev_unregister(struct cx23885_dev *dev)
 908 {
 909         release_mem_region(pci_resource_start(dev->pci,0),
 910                            pci_resource_len(dev->pci,0));
 911
 912         if (!atomic_dec_and_test(&dev->refcount))
 913                 return;
 914
 915         if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO)
 916                 cx23885_video_unregister(dev);
 917
 918         if(cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
 919                 cx23885_dvb_unregister(&dev->ts1);
 920
 921         if(cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
 922                 cx23885_dvb_unregister(&dev->ts2);
 923
 924         cx23885_i2c_unregister(&dev->i2c_bus[2]);
 925         cx23885_i2c_unregister(&dev->i2c_bus[1]);
 926         cx23885_i2c_unregister(&dev->i2c_bus[0]);
 927
 928         iounmap(dev->lmmio);
 929 }
 930
 931 static u32* cx23885_risc_field(u32 *rp, struct scatterlist *sglist,
 932                                unsigned int offset, u32 sync_line,
 933                                unsigned int bpl, unsigned int padding,
 934                                unsigned int lines)
 935 {
 936         struct scatterlist *sg;
 937         unsigned int line, todo;
 938
 939         /* sync instruction */
 940         if (sync_line != NO_SYNC_LINE)
 941                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
 942
 943         /* scan lines */
 944         sg = sglist;
 945         for (line = 0; line < lines; line++) {
 946                 while (offset && offset >= sg_dma_len(sg)) {
 947                         offset -= sg_dma_len(sg);
 948                         sg++;
 949                 }
 950                 if (bpl <= sg_dma_len(sg)-offset) {
 951                         /* fits into current chunk */
 952                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
 953                         *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
 954                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 955                         offset+=bpl;
 956                 } else {
 957                         /* scanline needs to be split */
 958                         todo = bpl;
 959                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|
 960                                             (sg_dma_len(sg)-offset));
 961                         *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
 962                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 963                         todo -= (sg_dma_len(sg)-offset);
 964                         offset = 0;
 965                         sg++;
 966                         while (todo > sg_dma_len(sg)) {
 967                                 *(rp++)=cpu_to_le32(RISC_WRITE|
 968                                                     sg_dma_len(sg));
 969                                 *(rp++)=cpu_to_le32(sg_dma_address(sg));
 970                                 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 971                                 todo -= sg_dma_len(sg);
 972                                 sg++;
 973                         }
 974                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
 975                         *(rp++)=cpu_to_le32(sg_dma_address(sg));
 976                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 977                         offset += todo;
 978                 }
 979                 offset += padding;
 980         }
 981
 982         return rp;
 983 }
 984
 985 int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
 986                         struct scatterlist *sglist, unsigned int top_offset,
 987                         unsigned int bottom_offset, unsigned int bpl,
 988                         unsigned int padding, unsigned int lines)
 989 {
 990         u32 instructions, fields;
 991         u32 *rp;
 992         int rc;
 993
 994         fields = 0;
 995         if (UNSET != top_offset)
 996                 fields++;
 997         if (UNSET != bottom_offset)
 998                 fields++;
 999
1000         /* estimate risc mem: worst case is one write per page border +
1001            one write per scan line + syncs + jump (all 2 dwords).  Padding
1002            can cause next bpl to start close to a page border.  First DMA
1003            region may be smaller than PAGE_SIZE */
1004         /* write and jump need and extra dword */
1005         instructions  = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
1006         instructions += 2;
1007         if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
1008                 return rc;
1009
1010         /* write risc instructions */
1011         rp = risc->cpu;
1012         if (UNSET != top_offset)
1013                 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
1014                                         bpl, padding, lines);
1015         if (UNSET != bottom_offset)
1016                 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
1017                                         bpl, padding, lines);
1018
1019         /* save pointer to jmp instruction address */
1020         risc->jmp = rp;
1021         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
1022         return 0;
1023 }
1024
1025 static int cx23885_risc_databuffer(struct pci_dev *pci,
1026                                    struct btcx_riscmem *risc,
1027                                    struct scatterlist *sglist,
1028                                    unsigned int bpl,
1029                                    unsigned int lines)
1030 {
1031         u32 instructions;
1032         u32 *rp;
1033         int rc;
1034
1035         /* estimate risc mem: worst case is one write per page border +
1036            one write per scan line + syncs + jump (all 2 dwords).  Here
1037            there is no padding and no sync.  First DMA region may be smaller
1038            than PAGE_SIZE */
1039         /* Jump and write need an extra dword */
1040         instructions  = 1 + (bpl * lines) / PAGE_SIZE + lines;
1041         instructions += 1;
1042
1043         if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
1044                 return rc;
1045
1046         /* write risc instructions */
1047         rp = risc->cpu;
1048         rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
1049
1050         /* save pointer to jmp instruction address */
1051         risc->jmp = rp;
1052         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
1053         return 0;
1054 }
1055
1056 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
1057                                 u32 reg, u32 mask, u32 value)
1058 {
1059         u32 *rp;
1060         int rc;
1061
1062         if ((rc = btcx_riscmem_alloc(pci, risc, 4*16)) < 0)
1063                 return rc;
1064
1065         /* write risc instructions */
1066         rp = risc->cpu;
1067         *(rp++) = cpu_to_le32(RISC_WRITECR  | RISC_IRQ2);
1068         *(rp++) = cpu_to_le32(reg);
1069         *(rp++) = cpu_to_le32(value);
1070         *(rp++) = cpu_to_le32(mask);
1071         *(rp++) = cpu_to_le32(RISC_JUMP);
1072         *(rp++) = cpu_to_le32(risc->dma);
1073         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1074         return 0;
1075 }
1076
1077 void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
1078 {
1079         struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
1080
1081         BUG_ON(in_interrupt());
1082         videobuf_waiton(&buf->vb, 0, 0);
1083         videobuf_dma_unmap(q, dma);
1084         videobuf_dma_free(dma);
1085         btcx_riscmem_free((struct pci_dev *)q->dev, &buf->risc);
1086         buf->vb.state = VIDEOBUF_NEEDS_INIT;
1087 }
1088
1089 static void cx23885_tsport_reg_dump(struct cx23885_tsport *port)
1090 {
1091         struct cx23885_dev *dev = port->dev;
1092
1093         dprintk(1, "%s() Register Dump\n", __FUNCTION__);
1094         dprintk(1, "%s() DEV_CNTRL2               0x%08X\n", __FUNCTION__,
1095                 cx_read(DEV_CNTRL2));
1096         dprintk(1, "%s() PCI_INT_MSK              0x%08X\n", __FUNCTION__,
1097                 cx_read(PCI_INT_MSK));
1098         dprintk(1, "%s() AUD_INT_INT_MSK          0x%08X\n", __FUNCTION__,
1099                 cx_read(AUDIO_INT_INT_MSK));
1100         dprintk(1, "%s() AUD_INT_DMA_CTL          0x%08X\n", __FUNCTION__,
1101                 cx_read(AUD_INT_DMA_CTL));
1102         dprintk(1, "%s() AUD_EXT_INT_MSK          0x%08X\n", __FUNCTION__,
1103                 cx_read(AUDIO_EXT_INT_MSK));
1104         dprintk(1, "%s() AUD_EXT_DMA_CTL          0x%08X\n", __FUNCTION__,
1105                 cx_read(AUD_EXT_DMA_CTL));
1106         dprintk(1, "%s() PAD_CTRL                 0x%08X\n", __FUNCTION__,
1107                 cx_read(PAD_CTRL));
1108         dprintk(1, "%s() ALT_PIN_OUT_SEL          0x%08X\n", __FUNCTION__,
1109                 cx_read(ALT_PIN_OUT_SEL));
1110         dprintk(1, "%s() GPIO2                    0x%08X\n", __FUNCTION__,
1111                 cx_read(GPIO2));
1112         dprintk(1, "%s() gpcnt(0x%08X)          0x%08X\n", __FUNCTION__,
1113                 port->reg_gpcnt, cx_read(port->reg_gpcnt));
1114         dprintk(1, "%s() gpcnt_ctl(0x%08X)      0x%08x\n", __FUNCTION__,
1115                 port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl));
1116         dprintk(1, "%s() dma_ctl(0x%08X)        0x%08x\n", __FUNCTION__,
1117                 port->reg_dma_ctl, cx_read(port->reg_dma_ctl));
1118         dprintk(1, "%s() src_sel(0x%08X)        0x%08x\n", __FUNCTION__,
1119                 port->reg_src_sel, cx_read(port->reg_src_sel));
1120         dprintk(1, "%s() lngth(0x%08X)          0x%08x\n", __FUNCTION__,
1121                 port->reg_lngth, cx_read(port->reg_lngth));
1122         dprintk(1, "%s() hw_sop_ctrl(0x%08X)    0x%08x\n", __FUNCTION__,
1123                 port->reg_hw_sop_ctrl, cx_read(port->reg_hw_sop_ctrl));
1124         dprintk(1, "%s() gen_ctrl(0x%08X)       0x%08x\n", __FUNCTION__,
1125                 port->reg_gen_ctrl, cx_read(port->reg_gen_ctrl));
1126         dprintk(1, "%s() bd_pkt_status(0x%08X)  0x%08x\n", __FUNCTION__,
1127                 port->reg_bd_pkt_status, cx_read(port->reg_bd_pkt_status));
1128         dprintk(1, "%s() sop_status(0x%08X)     0x%08x\n", __FUNCTION__,
1129                 port->reg_sop_status, cx_read(port->reg_sop_status));
1130         dprintk(1, "%s() fifo_ovfl_stat(0x%08X) 0x%08x\n", __FUNCTION__,
1131                 port->reg_fifo_ovfl_stat, cx_read(port->reg_fifo_ovfl_stat));
1132         dprintk(1, "%s() vld_misc(0x%08X)       0x%08x\n", __FUNCTION__,
1133                 port->reg_vld_misc, cx_read(port->reg_vld_misc));
1134         dprintk(1, "%s() ts_clk_en(0x%08X)      0x%08x\n", __FUNCTION__,
1135                 port->reg_ts_clk_en, cx_read(port->reg_ts_clk_en));
1136         dprintk(1, "%s() ts_int_msk(0x%08X)     0x%08x\n", __FUNCTION__,
1137                 port->reg_ts_int_msk, cx_read(port->reg_ts_int_msk));
1138 }
1139
1140 static int cx23885_start_dma(struct cx23885_tsport *port,
1141                              struct cx23885_dmaqueue *q,
1142                              struct cx23885_buffer   *buf)
1143 {
1144         struct cx23885_dev *dev = port->dev;
1145
1146         dprintk(1, "%s() w: %d, h: %d, f: %d\n", __FUNCTION__,
1147                 buf->vb.width, buf->vb.height, buf->vb.field);
1148
1149         /* setup fifo + format */
1150         cx23885_sram_channel_setup(dev,
1151                                    &dev->sram_channels[ port->sram_chno ],
1152                                    port->ts_packet_size, buf->risc.dma);
1153         if(debug > 5) {
1154                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ] );
1155                 cx23885_risc_disasm(port, &buf->risc);
1156         }
1157
1158         /* write TS length to chip */
1159         cx_write(port->reg_lngth, buf->vb.width);
1160
1161         if ( (!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) &&
1162                 (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB)) ) {
1163                 printk( "%s() Failed. Unsupported value in .portb/c (0x%08x)/(0x%08x)\n",
1164                         __FUNCTION__,
1165                         cx23885_boards[dev->board].portb,
1166                         cx23885_boards[dev->board].portc );
1167                 return -EINVAL;
1168         }
1169
1170         udelay(100);
1171
1172         /* If the port supports SRC SELECT, configure it */
1173         if(port->reg_src_sel)
1174                 cx_write(port->reg_src_sel, port->src_sel_val);
1175
1176         cx_write(port->reg_hw_sop_ctrl, 0x47 << 16 | 188 << 4);
1177         cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1178         cx_write(port->reg_vld_misc, 0x00);
1179         cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1180         udelay(100);
1181
1182         // NOTE: this is 2 (reserved) for portb, does it matter?
1183         /* reset counter to zero */
1184         cx_write(port->reg_gpcnt_ctl, 3);
1185         q->count = 1;
1186
1187         switch(dev->bridge) {
1188         case CX23885_BRIDGE_885:
1189         case CX23885_BRIDGE_887:
1190                 /* enable irqs */
1191                 dprintk(1, "%s() enabling TS int's and DMA\n", __FUNCTION__ );
1192                 cx_set(port->reg_ts_int_msk,  port->ts_int_msk_val);
1193                 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1194                 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
1195                 break;
1196         default:
1197                 BUG();
1198         }
1199
1200         cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1201
1202         if (debug > 4)
1203                 cx23885_tsport_reg_dump(port);
1204
1205         return 0;
1206 }
1207
1208 static int cx23885_stop_dma(struct cx23885_tsport *port)
1209 {
1210         struct cx23885_dev *dev = port->dev;
1211         dprintk(1, "%s()\n", __FUNCTION__);
1212
1213         /* Stop interrupts and DMA */
1214         cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1215         cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1216
1217         return 0;
1218 }
1219
1220 int cx23885_restart_queue(struct cx23885_tsport *port,
1221                                 struct cx23885_dmaqueue *q)
1222 {
1223         struct cx23885_dev *dev = port->dev;
1224         struct cx23885_buffer *buf;
1225
1226         dprintk(5, "%s()\n", __FUNCTION__);
1227         if (list_empty(&q->active))
1228         {
1229                 struct cx23885_buffer *prev;
1230                 prev = NULL;
1231
1232                 dprintk(5, "%s() queue is empty\n", __FUNCTION__);
1233
1234                 for (;;) {
1235                         if (list_empty(&q->queued))
1236                                 return 0;
1237                         buf = list_entry(q->queued.next, struct cx23885_buffer,
1238                                          vb.queue);
1239                         if (NULL == prev) {
1240                                 list_del(&buf->vb.queue);
1241                                 list_add_tail(&buf->vb.queue, &q->active);
1242                                 cx23885_start_dma(port, q, buf);
1243                                 buf->vb.state = VIDEOBUF_ACTIVE;
1244                                 buf->count    = q->count++;
1245                                 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1246                                 dprintk(5, "[%p/%d] restart_queue - first active\n",
1247                                         buf, buf->vb.i);
1248
1249                         } else if (prev->vb.width  == buf->vb.width  &&
1250                                    prev->vb.height == buf->vb.height &&
1251                                    prev->fmt       == buf->fmt) {
1252                                 list_del(&buf->vb.queue);
1253                                 list_add_tail(&buf->vb.queue, &q->active);
1254                                 buf->vb.state = VIDEOBUF_ACTIVE;
1255                                 buf->count    = q->count++;
1256                                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1257                                 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1258                                 dprintk(5,"[%p/%d] restart_queue - move to active\n",
1259                                         buf, buf->vb.i);
1260                         } else {
1261                                 return 0;
1262                         }
1263                         prev = buf;
1264                 }
1265                 return 0;
1266         }
1267
1268         buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
1269         dprintk(2, "restart_queue [%p/%d]: restart dma\n",
1270                 buf, buf->vb.i);
1271         cx23885_start_dma(port, q, buf);
1272         list_for_each_entry(buf, &q->active, vb.queue)
1273                 buf->count = q->count++;
1274         mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
1275         return 0;
1276 }
1277
1278 /* ------------------------------------------------------------------ */
1279
1280 int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1281                         struct cx23885_buffer *buf, enum v4l2_field field)
1282 {
1283         struct cx23885_dev *dev = port->dev;
1284         int size = port->ts_packet_size * port->ts_packet_count;
1285         int rc;
1286
1287         dprintk(1, "%s: %p\n", __FUNCTION__, buf);
1288         if (0 != buf->vb.baddr  &&  buf->vb.bsize < size)
1289                 return -EINVAL;
1290
1291         if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
1292                 buf->vb.width  = port->ts_packet_size;
1293                 buf->vb.height = port->ts_packet_count;
1294                 buf->vb.size   = size;
1295                 buf->vb.field  = field /*V4L2_FIELD_TOP*/;
1296
1297                 if (0 != (rc = videobuf_iolock(q, &buf->vb, NULL)))
1298                         goto fail;
1299                 cx23885_risc_databuffer(dev->pci, &buf->risc,
1300                                         videobuf_to_dma(&buf->vb)->sglist,
1301                                         buf->vb.width, buf->vb.height);
1302         }
1303         buf->vb.state = VIDEOBUF_PREPARED;
1304         return 0;
1305
1306  fail:
1307         cx23885_free_buffer(q, buf);
1308         return rc;
1309 }
1310
1311 void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1312 {
1313         struct cx23885_buffer    *prev;
1314         struct cx23885_dev *dev = port->dev;
1315         struct cx23885_dmaqueue  *cx88q = &port->mpegq;
1316
1317         /* add jump to stopper */
1318         buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
1319         buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
1320         buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1321
1322         if (list_empty(&cx88q->active)) {
1323                 dprintk( 1, "queue is empty - first active\n" );
1324                 list_add_tail(&buf->vb.queue, &cx88q->active);
1325                 cx23885_start_dma(port, cx88q, buf);
1326                 buf->vb.state = VIDEOBUF_ACTIVE;
1327                 buf->count    = cx88q->count++;
1328                 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
1329                 dprintk(1, "[%p/%d] %s - first active\n",
1330                         buf, buf->vb.i, __FUNCTION__);
1331         } else {
1332                 dprintk( 1, "queue is not empty - append to active\n" );
1333                 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1334                                   vb.queue);
1335                 list_add_tail(&buf->vb.queue, &cx88q->active);
1336                 buf->vb.state = VIDEOBUF_ACTIVE;
1337                 buf->count    = cx88q->count++;
1338                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1339                 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1340                 dprintk( 1, "[%p/%d] %s - append to active\n",
1341                          buf, buf->vb.i, __FUNCTION__);
1342         }
1343 }
1344
1345 /* ----------------------------------------------------------- */
1346
1347 static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
1348                               int restart)
1349 {
1350         struct cx23885_dev *dev = port->dev;
1351         struct cx23885_dmaqueue *q = &port->mpegq;
1352         struct cx23885_buffer *buf;
1353         unsigned long flags;
1354
1355         spin_lock_irqsave(&port->slock, flags);
1356         while (!list_empty(&q->active)) {
1357                 buf = list_entry(q->active.next, struct cx23885_buffer,
1358                                  vb.queue);
1359                 list_del(&buf->vb.queue);
1360                 buf->vb.state = VIDEOBUF_ERROR;
1361                 wake_up(&buf->vb.done);
1362                 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
1363                         buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
1364         }
1365         if (restart) {
1366                 dprintk(1, "restarting queue\n" );
1367                 cx23885_restart_queue(port, q);
1368         }
1369         spin_unlock_irqrestore(&port->slock, flags);
1370 }
1371
1372
1373 static void cx23885_timeout(unsigned long data)
1374 {
1375         struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1376         struct cx23885_dev *dev = port->dev;
1377
1378         dprintk(1, "%s()\n",__FUNCTION__);
1379
1380         if (debug > 5)
1381                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1382
1383         cx23885_stop_dma(port);
1384         do_cancel_buffers(port, "timeout", 1);
1385 }
1386
1387 static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status)
1388 {
1389         struct cx23885_dev *dev = port->dev;
1390         int handled = 0;
1391         u32 count;
1392
1393         if ( (status & VID_BC_MSK_OPC_ERR) ||
1394              (status & VID_BC_MSK_BAD_PKT) ||
1395              (status & VID_BC_MSK_SYNC) ||
1396              (status & VID_BC_MSK_OF))
1397         {
1398                 if (status & VID_BC_MSK_OPC_ERR)
1399                         dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n", VID_BC_MSK_OPC_ERR);
1400                 if (status & VID_BC_MSK_BAD_PKT)
1401                         dprintk(7, " (VID_BC_MSK_BAD_PKT 0x%08x)\n", VID_BC_MSK_BAD_PKT);
1402                 if (status & VID_BC_MSK_SYNC)
1403                         dprintk(7, " (VID_BC_MSK_SYNC    0x%08x)\n", VID_BC_MSK_SYNC);
1404                 if (status & VID_BC_MSK_OF)
1405                         dprintk(7, " (VID_BC_MSK_OF      0x%08x)\n", VID_BC_MSK_OF);
1406
1407                 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1408
1409                 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1410                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1411
1412         } else if (status & VID_BC_MSK_RISCI1) {
1413
1414                 dprintk(7, " (RISCI1            0x%08x)\n", VID_BC_MSK_RISCI1);
1415
1416                 spin_lock(&port->slock);
1417                 count = cx_read(port->reg_gpcnt);
1418                 cx23885_wakeup(port, &port->mpegq, count);
1419                 spin_unlock(&port->slock);
1420
1421         } else if (status & VID_BC_MSK_RISCI2) {
1422
1423                 dprintk(7, " (RISCI2            0x%08x)\n", VID_BC_MSK_RISCI2);
1424
1425                 spin_lock(&port->slock);
1426                 cx23885_restart_queue(port, &port->mpegq);
1427                 spin_unlock(&port->slock);
1428
1429         }
1430         if (status) {
1431                 cx_write(port->reg_ts_int_stat, status);
1432                 handled = 1;
1433         }
1434
1435         return handled;
1436 }
1437
1438 static irqreturn_t cx23885_irq(int irq, void *dev_id)
1439 {
1440         struct cx23885_dev *dev = dev_id;
1441         struct cx23885_tsport *ts1 = &dev->ts1;
1442         struct cx23885_tsport *ts2 = &dev->ts2;
1443         u32 pci_status, pci_mask;
1444         u32 vida_status, vida_mask;
1445         u32 ts1_status, ts1_mask;
1446         u32 ts2_status, ts2_mask;
1447         int vida_count = 0, ts1_count = 0, ts2_count = 0, handled = 0;
1448
1449         pci_status = cx_read(PCI_INT_STAT);
1450         pci_mask = cx_read(PCI_INT_MSK);
1451         vida_status = cx_read(VID_A_INT_STAT);
1452         vida_mask = cx_read(VID_A_INT_MSK);
1453         ts1_status = cx_read(VID_B_INT_STAT);
1454         ts1_mask = cx_read(VID_B_INT_MSK);
1455         ts2_status = cx_read(VID_C_INT_STAT);
1456         ts2_mask = cx_read(VID_C_INT_MSK);
1457
1458         if ( (pci_status == 0) && (ts2_status == 0) && (ts1_status == 0) )
1459                 goto out;
1460
1461         vida_count = cx_read(VID_A_GPCNT);
1462         ts1_count = cx_read(ts1->reg_gpcnt);
1463         ts2_count = cx_read(ts2->reg_gpcnt);
1464         dprintk(7, "pci_status: 0x%08x  pci_mask: 0x%08x\n",
1465                 pci_status, pci_mask);
1466         dprintk(7, "vida_status: 0x%08x vida_mask: 0x%08x count: 0x%x\n",
1467                 vida_status, vida_mask, vida_count);
1468         dprintk(7, "ts1_status: 0x%08x  ts1_mask: 0x%08x count: 0x%x\n",
1469                 ts1_status, ts1_mask, ts1_count);
1470         dprintk(7, "ts2_status: 0x%08x  ts2_mask: 0x%08x count: 0x%x\n",
1471                 ts2_status, ts2_mask, ts2_count);
1472
1473         if ( (pci_status & PCI_MSK_RISC_RD) ||
1474              (pci_status & PCI_MSK_RISC_WR) ||
1475              (pci_status & PCI_MSK_AL_RD) ||
1476              (pci_status & PCI_MSK_AL_WR) ||
1477              (pci_status & PCI_MSK_APB_DMA) ||
1478              (pci_status & PCI_MSK_VID_C) ||
1479              (pci_status & PCI_MSK_VID_B) ||
1480              (pci_status & PCI_MSK_VID_A) ||
1481              (pci_status & PCI_MSK_AUD_INT) ||
1482              (pci_status & PCI_MSK_AUD_EXT) )
1483         {
1484
1485                 if (pci_status & PCI_MSK_RISC_RD)
1486                         dprintk(7, " (PCI_MSK_RISC_RD   0x%08x)\n", PCI_MSK_RISC_RD);
1487                 if (pci_status & PCI_MSK_RISC_WR)
1488                         dprintk(7, " (PCI_MSK_RISC_WR   0x%08x)\n", PCI_MSK_RISC_WR);
1489                 if (pci_status & PCI_MSK_AL_RD)
1490                         dprintk(7, " (PCI_MSK_AL_RD     0x%08x)\n", PCI_MSK_AL_RD);
1491                 if (pci_status & PCI_MSK_AL_WR)
1492                         dprintk(7, " (PCI_MSK_AL_WR     0x%08x)\n", PCI_MSK_AL_WR);
1493                 if (pci_status & PCI_MSK_APB_DMA)
1494                         dprintk(7, " (PCI_MSK_APB_DMA   0x%08x)\n", PCI_MSK_APB_DMA);
1495                 if (pci_status & PCI_MSK_VID_C)
1496                         dprintk(7, " (PCI_MSK_VID_C     0x%08x)\n", PCI_MSK_VID_C);
1497                 if (pci_status & PCI_MSK_VID_B)
1498                         dprintk(7, " (PCI_MSK_VID_B     0x%08x)\n", PCI_MSK_VID_B);
1499                 if (pci_status & PCI_MSK_VID_A)
1500                         dprintk(7, " (PCI_MSK_VID_A     0x%08x)\n", PCI_MSK_VID_A);
1501                 if (pci_status & PCI_MSK_AUD_INT)
1502                         dprintk(7, " (PCI_MSK_AUD_INT   0x%08x)\n", PCI_MSK_AUD_INT);
1503                 if (pci_status & PCI_MSK_AUD_EXT)
1504                         dprintk(7, " (PCI_MSK_AUD_EXT   0x%08x)\n", PCI_MSK_AUD_EXT);
1505
1506         }
1507
1508         if (ts1_status) {
1509                 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
1510                         handled += cx23885_irq_ts(ts1, ts1_status);
1511         }
1512
1513         if (ts2_status) {
1514                 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
1515                         handled += cx23885_irq_ts(ts2, ts2_status);
1516         }
1517
1518         if (vida_status)
1519                 handled += cx23885_video_irq(dev, vida_status);
1520
1521         if (handled)
1522                 cx_write(PCI_INT_STAT, pci_status);
1523 out:
1524         return IRQ_RETVAL(handled);
1525 }
1526
1527 static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
1528                                      const struct pci_device_id *pci_id)
1529 {
1530         struct cx23885_dev *dev;
1531         int err;
1532
1533         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1534         if (NULL == dev)
1535                 return -ENOMEM;
1536
1537         /* pci init */
1538         dev->pci = pci_dev;
1539         if (pci_enable_device(pci_dev)) {
1540                 err = -EIO;
1541                 goto fail_free;
1542         }
1543
1544         if (cx23885_dev_setup(dev) < 0) {
1545                 err = -EINVAL;
1546                 goto fail_free;
1547         }
1548
1549         /* print pci info */
1550         pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1551         pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER,  &dev->pci_lat);
1552         printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1553                "latency: %d, mmio: 0x%llx\n", dev->name,
1554                pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1555                dev->pci_lat, (unsigned long long)pci_resource_start(pci_dev,0));
1556
1557         pci_set_master(pci_dev);
1558         if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1559                 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1560                 err = -EIO;
1561                 goto fail_irq;
1562         }
1563
1564         err = request_irq(pci_dev->irq, cx23885_irq,
1565                           IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
1566         if (err < 0) {
1567                 printk(KERN_ERR "%s: can't get IRQ %d\n",
1568                        dev->name, pci_dev->irq);
1569                 goto fail_irq;
1570         }
1571
1572         pci_set_drvdata(pci_dev, dev);
1573         return 0;
1574
1575 fail_irq:
1576         cx23885_dev_unregister(dev);
1577 fail_free:
1578         kfree(dev);
1579         return err;
1580 }
1581
1582 static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
1583 {
1584         struct cx23885_dev *dev = pci_get_drvdata(pci_dev);
1585
1586         cx23885_shutdown(dev);
1587
1588         pci_disable_device(pci_dev);
1589
1590         /* unregister stuff */
1591         free_irq(pci_dev->irq, dev);
1592         pci_set_drvdata(pci_dev, NULL);
1593
1594         mutex_lock(&devlist);
1595         list_del(&dev->devlist);
1596         mutex_unlock(&devlist);
1597
1598         cx23885_dev_unregister(dev);
1599         kfree(dev);
1600 }
1601
1602 static struct pci_device_id cx23885_pci_tbl[] = {
1603         {
1604                 /* CX23885 */
1605                 .vendor       = 0x14f1,
1606                 .device       = 0x8852,
1607                 .subvendor    = PCI_ANY_ID,
1608                 .subdevice    = PCI_ANY_ID,
1609         },{
1610                 /* CX23887 Rev 2 */
1611                 .vendor       = 0x14f1,
1612                 .device       = 0x8880,
1613                 .subvendor    = PCI_ANY_ID,
1614                 .subdevice    = PCI_ANY_ID,
1615         },{
1616                 /* --- end of list --- */
1617         }
1618 };
1619 MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
1620
1621 static struct pci_driver cx23885_pci_driver = {
1622         .name     = "cx23885",
1623         .id_table = cx23885_pci_tbl,
1624         .probe    = cx23885_initdev,
1625         .remove   = __devexit_p(cx23885_finidev),
1626         /* TODO */
1627         .suspend  = NULL,
1628         .resume   = NULL,
1629 };
1630
1631 static int cx23885_init(void)
1632 {
1633         printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
1634                (CX23885_VERSION_CODE >> 16) & 0xff,
1635                (CX23885_VERSION_CODE >>  8) & 0xff,
1636                CX23885_VERSION_CODE & 0xff);
1637 #ifdef SNAPSHOT
1638         printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
1639                SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
1640 #endif
1641         return pci_register_driver(&cx23885_pci_driver);
1642 }
1643
1644 static void cx23885_fini(void)
1645 {
1646         pci_unregister_driver(&cx23885_pci_driver);
1647 }
1648
1649 module_init(cx23885_init);
1650 module_exit(cx23885_fini);
1651
1652 /* ----------------------------------------------------------- */
1653 /*
1654  * Local variables:
1655  * c-basic-offset: 8
1656  * End:
1657  * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off
1658  */