err.no Git - linux-2.6/blob - drivers/media/video/cx23885/cx23885-core.c

   1 /*
   2  *  Driver for the Conexant CX23885 PCIe bridge
   3  *
   4  *  Copyright (c) 2006 Steven Toth <stoth@hauppauge.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/list.h>
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/kmod.h>
  27 #include <linux/kernel.h>
  28 #include <linux/slab.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/delay.h>
  31 #include <asm/div64.h>
  32
  33 #include "cx23885.h"
  34
  35 MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
  36 MODULE_AUTHOR("Steven Toth <stoth@hauppauge.com>");
  37 MODULE_LICENSE("GPL");
  38
  39 static unsigned int debug = 0;
  40 module_param(debug,int,0644);
  41 MODULE_PARM_DESC(debug,"enable debug messages");
  42
  43 static unsigned int card[]  = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
  44 module_param_array(card,  int, NULL, 0444);
  45 MODULE_PARM_DESC(card,"card type");
  46
  47 #define dprintk(level,fmt, arg...)      if (debug >= level) \
  48         printk(KERN_DEBUG "%s/0: " fmt, dev->name , ## arg)
  49
  50 static unsigned int cx23885_devcount;
  51
  52 static DEFINE_MUTEX(devlist);
  53 static LIST_HEAD(cx23885_devlist);
  54
  55 #define NO_SYNC_LINE (-1U)
  56
  57 /*
  58  * CX23885 Assumptions
  59  * 1 line = 16 bytes of CDT
  60  * cmds size = 80
  61  * cdt size = 16 * linesize
  62  * iqsize = 64
  63  * maxlines = 6
  64  *
  65  * Address Space:
  66  * 0x00000000 0x00008fff FIFO clusters
  67  * 0x00010000 0x000104af Channel Management Data Structures
  68  * 0x000104b0 0x000104ff Free
  69  * 0x00010500 0x000108bf 15 channels * iqsize
  70  * 0x000108c0 0x000108ff Free
  71  * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
  72  *                       15 channels * (iqsize + (maxlines * linesize))
  73  * 0x00010ea0 0x00010xxx Free
  74  */
  75
  76 struct sram_channel cx23885_sram_channels[] = {
  77         [SRAM_CH01] = {
  78                 .name           = "test ch1",
  79                 .cmds_start     = 0x10000,
  80                 .ctrl_start     = 0x10500,
  81                 .cdt            = 0x10900,
  82                 .fifo_start     = 0x3000,
  83                 .fifo_size      = 0x1000,
  84                 .ptr1_reg       = DMA1_PTR1,
  85                 .ptr2_reg       = DMA1_PTR2,
  86                 .cnt1_reg       = DMA1_CNT1,
  87                 .cnt2_reg       = DMA1_CNT2,
  88                 .jumponly       = 1,
  89         },
  90         [SRAM_CH02] = {
  91                 .name           = "ch2",
  92                 .cmds_start     = 0x0,
  93                 .ctrl_start     = 0x0,
  94                 .cdt            = 0x0,
  95                 .fifo_start     = 0x0,
  96                 .fifo_size      = 0x0,
  97                 .ptr1_reg       = DMA2_PTR1,
  98                 .ptr2_reg       = DMA2_PTR2,
  99                 .cnt1_reg       = DMA2_CNT1,
 100                 .cnt2_reg       = DMA2_CNT2,
 101         },
 102         [SRAM_CH03] = {
 103                 .name           = "ch3",
 104                 .cmds_start     = 0x0,
 105                 .ctrl_start     = 0x0,
 106                 .cdt            = 0x0,
 107                 .fifo_start     = 0x0,
 108                 .fifo_size      = 0x0,
 109                 .ptr1_reg       = DMA3_PTR1,
 110                 .ptr2_reg       = DMA3_PTR2,
 111                 .cnt1_reg       = DMA3_CNT1,
 112                 .cnt2_reg       = DMA3_CNT2,
 113         },
 114         [SRAM_CH04] = {
 115                 .name           = "ch4",
 116                 .cmds_start     = 0x0,
 117                 .ctrl_start     = 0x0,
 118                 .cdt            = 0x0,
 119                 .fifo_start     = 0x0,
 120                 .fifo_size      = 0x0,
 121                 .ptr1_reg       = DMA4_PTR1,
 122                 .ptr2_reg       = DMA4_PTR2,
 123                 .cnt1_reg       = DMA4_CNT1,
 124                 .cnt2_reg       = DMA4_CNT2,
 125         },
 126         [SRAM_CH05] = {
 127                 .name           = "ch5",
 128                 .cmds_start     = 0x0,
 129                 .ctrl_start     = 0x0,
 130                 .cdt            = 0x0,
 131                 .fifo_start     = 0x0,
 132                 .fifo_size      = 0x0,
 133                 .ptr1_reg       = DMA5_PTR1,
 134                 .ptr2_reg       = DMA5_PTR2,
 135                 .cnt1_reg       = DMA5_CNT1,
 136                 .cnt2_reg       = DMA5_CNT2,
 137         },
 138         [SRAM_CH06] = {
 139                 .name           = "TS2 C",
 140                 .cmds_start     = 0x10140,
 141                 .ctrl_start     = 0x10680,
 142                 .cdt            = 0x10480,
 143                 .fifo_start     = 0x6000,
 144                 .fifo_size      = 0x1000,
 145                 .ptr1_reg       = DMA5_PTR1,
 146                 .ptr2_reg       = DMA5_PTR2,
 147                 .cnt1_reg       = DMA5_CNT1,
 148                 .cnt2_reg       = DMA5_CNT2,
 149         },
 150         [SRAM_CH07] = {
 151                 .name           = "ch7",
 152                 .cmds_start     = 0x0,
 153                 .ctrl_start     = 0x0,
 154                 .cdt            = 0x0,
 155                 .fifo_start     = 0x0,
 156                 .fifo_size      = 0x0,
 157                 .ptr1_reg       = DMA6_PTR1,
 158                 .ptr2_reg       = DMA6_PTR2,
 159                 .cnt1_reg       = DMA6_CNT1,
 160                 .cnt2_reg       = DMA6_CNT2,
 161         },
 162         [SRAM_CH08] = {
 163                 .name           = "ch8",
 164                 .cmds_start     = 0x0,
 165                 .ctrl_start     = 0x0,
 166                 .cdt            = 0x0,
 167                 .fifo_start     = 0x0,
 168                 .fifo_size      = 0x0,
 169                 .ptr1_reg       = DMA7_PTR1,
 170                 .ptr2_reg       = DMA7_PTR2,
 171                 .cnt1_reg       = DMA7_CNT1,
 172                 .cnt2_reg       = DMA7_CNT2,
 173         },
 174         [SRAM_CH09] = {
 175                 .name           = "ch9",
 176                 .cmds_start     = 0x0,
 177                 .ctrl_start     = 0x0,
 178                 .cdt            = 0x0,
 179                 .fifo_start     = 0x0,
 180                 .fifo_size      = 0x0,
 181                 .ptr1_reg       = DMA8_PTR1,
 182                 .ptr2_reg       = DMA8_PTR2,
 183                 .cnt1_reg       = DMA8_CNT1,
 184                 .cnt2_reg       = DMA8_CNT2,
 185         },
 186 };
 187
 188 /* FIXME, these allocations will change when
 189  * analog arrives. The be reviewed.
 190  * CX23887 Assumptions
 191  * 1 line = 16 bytes of CDT
 192  * cmds size = 80
 193  * cdt size = 16 * linesize
 194  * iqsize = 64
 195  * maxlines = 6
 196  *
 197  * Address Space:
 198  * 0x00000000 0x00008fff FIFO clusters
 199  * 0x00010000 0x000104af Channel Management Data Structures
 200  * 0x000104b0 0x000104ff Free
 201  * 0x00010500 0x000108bf 15 channels * iqsize
 202  * 0x000108c0 0x000108ff Free
 203  * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
 204  *                       15 channels * (iqsize + (maxlines * linesize))
 205  * 0x00010ea0 0x00010xxx Free
 206  */
 207
 208 struct sram_channel cx23887_sram_channels[] = {
 209         [SRAM_CH01] = {
 210                 .name           = "test ch1",
 211                 .cmds_start     = 0x0,
 212                 .ctrl_start     = 0x0,
 213                 .cdt            = 0x0,
 214                 .fifo_start     = 0x0,
 215                 .fifo_size      = 0x0,
 216                 .ptr1_reg       = DMA1_PTR1,
 217                 .ptr2_reg       = DMA1_PTR2,
 218                 .cnt1_reg       = DMA1_CNT1,
 219                 .cnt2_reg       = DMA1_CNT2,
 220         },
 221         [SRAM_CH02] = {
 222                 .name           = "ch2",
 223                 .cmds_start     = 0x0,
 224                 .ctrl_start     = 0x0,
 225                 .cdt            = 0x0,
 226                 .fifo_start     = 0x0,
 227                 .fifo_size      = 0x0,
 228                 .ptr1_reg       = DMA2_PTR1,
 229                 .ptr2_reg       = DMA2_PTR2,
 230                 .cnt1_reg       = DMA2_CNT1,
 231                 .cnt2_reg       = DMA2_CNT2,
 232         },
 233         [SRAM_CH03] = {
 234                 .name           = "ch3",
 235                 .cmds_start     = 0x0,
 236                 .ctrl_start     = 0x0,
 237                 .cdt            = 0x0,
 238                 .fifo_start     = 0x0,
 239                 .fifo_size      = 0x0,
 240                 .ptr1_reg       = DMA3_PTR1,
 241                 .ptr2_reg       = DMA3_PTR2,
 242                 .cnt1_reg       = DMA3_CNT1,
 243                 .cnt2_reg       = DMA3_CNT2,
 244         },
 245         [SRAM_CH04] = {
 246                 .name           = "ch4",
 247                 .cmds_start     = 0x0,
 248                 .ctrl_start     = 0x0,
 249                 .cdt            = 0x0,
 250                 .fifo_start     = 0x0,
 251                 .fifo_size      = 0x0,
 252                 .ptr1_reg       = DMA4_PTR1,
 253                 .ptr2_reg       = DMA4_PTR2,
 254                 .cnt1_reg       = DMA4_CNT1,
 255                 .cnt2_reg       = DMA4_CNT2,
 256         },
 257         [SRAM_CH05] = {
 258                 .name           = "ch5",
 259                 .cmds_start     = 0x0,
 260                 .ctrl_start     = 0x0,
 261                 .cdt            = 0x0,
 262                 .fifo_start     = 0x0,
 263                 .fifo_size      = 0x0,
 264                 .ptr1_reg       = DMA5_PTR1,
 265                 .ptr2_reg       = DMA5_PTR2,
 266                 .cnt1_reg       = DMA5_CNT1,
 267                 .cnt2_reg       = DMA5_CNT2,
 268         },
 269         [SRAM_CH06] = {
 270                 .name           = "TS2 C",
 271                 .cmds_start     = 0x10140,
 272                 .ctrl_start     = 0x10680,
 273                 .cdt            = 0x108d0,
 274                 .fifo_start     = 0x6000,
 275                 .fifo_size      = 0x1000,
 276                 .ptr1_reg       = DMA5_PTR1,
 277                 .ptr2_reg       = DMA5_PTR2,
 278                 .cnt1_reg       = DMA5_CNT1,
 279                 .cnt2_reg       = DMA5_CNT2,
 280         },
 281         [SRAM_CH07] = {
 282                 .name           = "ch7",
 283                 .cmds_start     = 0x0,
 284                 .ctrl_start     = 0x0,
 285                 .cdt            = 0x0,
 286                 .fifo_start     = 0x0,
 287                 .fifo_size      = 0x0,
 288                 .ptr1_reg       = DMA6_PTR1,
 289                 .ptr2_reg       = DMA6_PTR2,
 290                 .cnt1_reg       = DMA6_CNT1,
 291                 .cnt2_reg       = DMA6_CNT2,
 292         },
 293         [SRAM_CH08] = {
 294                 .name           = "ch8",
 295                 .cmds_start     = 0x0,
 296                 .ctrl_start     = 0x0,
 297                 .cdt            = 0x0,
 298                 .fifo_start     = 0x0,
 299                 .fifo_size      = 0x0,
 300                 .ptr1_reg       = DMA7_PTR1,
 301                 .ptr2_reg       = DMA7_PTR2,
 302                 .cnt1_reg       = DMA7_CNT1,
 303                 .cnt2_reg       = DMA7_CNT2,
 304         },
 305         [SRAM_CH09] = {
 306                 .name           = "ch9",
 307                 .cmds_start     = 0x0,
 308                 .ctrl_start     = 0x0,
 309                 .cdt            = 0x0,
 310                 .fifo_start     = 0x0,
 311                 .fifo_size      = 0x0,
 312                 .ptr1_reg       = DMA8_PTR1,
 313                 .ptr2_reg       = DMA8_PTR2,
 314                 .cnt1_reg       = DMA8_CNT1,
 315                 .cnt2_reg       = DMA8_CNT2,
 316         },
 317 };
 318
 319 static int cx23885_risc_decode(u32 risc)
 320 {
 321         static char *instr[16] = {
 322                 [ RISC_SYNC    >> 28 ] = "sync",
 323                 [ RISC_WRITE   >> 28 ] = "write",
 324                 [ RISC_WRITEC  >> 28 ] = "writec",
 325                 [ RISC_READ    >> 28 ] = "read",
 326                 [ RISC_READC   >> 28 ] = "readc",
 327                 [ RISC_JUMP    >> 28 ] = "jump",
 328                 [ RISC_SKIP    >> 28 ] = "skip",
 329                 [ RISC_WRITERM >> 28 ] = "writerm",
 330                 [ RISC_WRITECM >> 28 ] = "writecm",
 331                 [ RISC_WRITECR >> 28 ] = "writecr",
 332         };
 333         static int incr[16] = {
 334                 [ RISC_WRITE   >> 28 ] = 3, // 2
 335                 [ RISC_JUMP    >> 28 ] = 3, // 2
 336                 [ RISC_SKIP    >> 28 ] = 1,
 337                 [ RISC_SYNC    >> 28 ] = 1,
 338                 [ RISC_WRITERM >> 28 ] = 3,
 339                 [ RISC_WRITECM >> 28 ] = 3,
 340                 [ RISC_WRITECR >> 28 ] = 4,
 341         };
 342         static char *bits[] = {
 343                 "12",   "13",   "14",   "resync",
 344                 "cnt0", "cnt1", "18",   "19",
 345                 "20",   "21",   "22",   "23",
 346                 "irq1", "irq2", "eol",  "sol",
 347         };
 348         int i;
 349
 350         printk("0x%08x [ %s", risc,
 351                instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
 352         for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
 353                 if (risc & (1 << (i + 12)))
 354                         printk(" %s", bits[i]);
 355         printk(" count=%d ]\n", risc & 0xfff);
 356         return incr[risc >> 28] ? incr[risc >> 28] : 1;
 357 }
 358
 359 void cx23885_wakeup(struct cx23885_tsport *port,
 360                     struct cx23885_dmaqueue *q, u32 count)
 361 {
 362         struct cx23885_dev *dev = port->dev;
 363         struct cx23885_buffer *buf;
 364         int bc;
 365
 366         for (bc = 0;; bc++) {
 367                 if (list_empty(&q->active))
 368                         break;
 369                 buf = list_entry(q->active.next,
 370                                  struct cx23885_buffer, vb.queue);
 371                 /* count comes from the hw and is is 16bit wide --
 372                  * this trick handles wrap-arounds correctly for
 373                  * up to 32767 buffers in flight... */
 374                 if ((s16) (count - buf->count) < 0)
 375                         break;
 376                 do_gettimeofday(&buf->vb.ts);
 377                 dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
 378                         count, buf->count);
 379                 buf->vb.state = STATE_DONE;
 380                 list_del(&buf->vb.queue);
 381                 wake_up(&buf->vb.done);
 382         }
 383         if (list_empty(&q->active)) {
 384                 del_timer(&q->timeout);
 385         } else {
 386                 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
 387         }
 388         if (bc != 1)
 389                 printk("%s: %d buffers handled (should be 1)\n",
 390                        __FUNCTION__, bc);
 391 }
 392 void cx23885_sram_channel_dump(struct cx23885_dev *dev,
 393                                struct sram_channel *ch);
 394
 395 int cx23885_sram_channel_setup(struct cx23885_dev *dev,
 396                                struct sram_channel *ch,
 397                                unsigned int bpl, u32 risc)
 398 {
 399         unsigned int i, lines;
 400         u32 cdt;
 401
 402         if (ch->cmds_start == 0)
 403         {
 404                 dprintk(1, "%s() Erasing channel [%s]\n", __FUNCTION__,
 405                         ch->name);
 406                 cx_write(ch->ptr1_reg, 0);
 407                 cx_write(ch->ptr2_reg, 0);
 408                 cx_write(ch->cnt2_reg, 0);
 409                 cx_write(ch->cnt1_reg, 0);
 410                 return 0;
 411         } else {
 412                 dprintk(1, "%s() Configuring channel [%s]\n", __FUNCTION__,
 413                         ch->name);
 414         }
 415
 416         bpl   = (bpl + 7) & ~7; /* alignment */
 417         cdt   = ch->cdt;
 418         lines = ch->fifo_size / bpl;
 419         if (lines > 6)
 420                 lines = 6;
 421         BUG_ON(lines < 2);
 422
 423         cx_write(8 + 0, cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC) );
 424         cx_write(8 + 4, cpu_to_le32(8) );
 425         cx_write(8 + 8, cpu_to_le32(0) );
 426
 427         /* write CDT */
 428         for (i = 0; i < lines; i++) {
 429                 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __FUNCTION__, cdt + 16*i,
 430                         ch->fifo_start + bpl*i);
 431                 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
 432                 cx_write(cdt + 16*i +  4, 0);
 433                 cx_write(cdt + 16*i +  8, 0);
 434                 cx_write(cdt + 16*i + 12, 0);
 435         }
 436
 437         /* write CMDS */
 438         if (ch->jumponly)
 439                 cx_write(ch->cmds_start +  0, 8);
 440         else
 441                 cx_write(ch->cmds_start +  0, risc);
 442         cx_write(ch->cmds_start +  4, 0); /* 64 bits 63-32 */
 443         cx_write(ch->cmds_start +  8, cdt);
 444         cx_write(ch->cmds_start + 12, (lines*16) >> 3);
 445         cx_write(ch->cmds_start + 16, ch->ctrl_start);
 446         if (ch->jumponly)
 447                 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2) );
 448         else
 449                 cx_write(ch->cmds_start + 20, 64 >> 2);
 450         for (i = 24; i < 80; i += 4)
 451                 cx_write(ch->cmds_start + i, 0);
 452
 453         /* fill registers */
 454         cx_write(ch->ptr1_reg, ch->fifo_start);
 455         cx_write(ch->ptr2_reg, cdt);
 456         cx_write(ch->cnt2_reg, (lines*16) >> 3);
 457         cx_write(ch->cnt1_reg, (bpl >> 3) -1);
 458
 459         dprintk(2,"[bridge %d] sram setup %s: bpl=%d lines=%d\n",
 460                 dev->bridge,
 461                 ch->name,
 462                 bpl,
 463                 lines);
 464
 465         return 0;
 466 }
 467
 468 void cx23885_sram_channel_dump(struct cx23885_dev *dev,
 469                                struct sram_channel *ch)
 470 {
 471         static char *name[] = {
 472                 "init risc lo",
 473                 "init risc hi",
 474                 "cdt base",
 475                 "cdt size",
 476                 "iq base",
 477                 "iq size",
 478                 "risc pc lo",
 479                 "risc pc hi",
 480                 "iq wr ptr",
 481                 "iq rd ptr",
 482                 "cdt current",
 483                 "pci target lo",
 484                 "pci target hi",
 485                 "line / byte",
 486         };
 487         u32 risc;
 488         unsigned int i, j, n;
 489
 490         printk("%s: %s - dma channel status dump\n",
 491                dev->name, ch->name);
 492         for (i = 0; i < ARRAY_SIZE(name); i++)
 493                 printk("%s:   cmds: %-15s: 0x%08x\n",
 494                        dev->name, name[i],
 495                        cx_read(ch->cmds_start + 4*i));
 496
 497         for (i = 0; i < 4; i++) {
 498                 risc = cx_read(ch->cmds_start + 4 * (i + 14));
 499                 printk("%s:   risc%d: ", dev->name, i);
 500                 cx23885_risc_decode(risc);
 501         }
 502         for (i = 0; i < (64 >> 2); i += n) {
 503                 risc = cx_read(ch->ctrl_start + 4 * i);
 504                 /* No consideration for bits 63-32 */
 505
 506                 printk("%s:   (0x%08x) iq %x: ", dev->name,
 507                        ch->ctrl_start + 4 * i, i);
 508                 n = cx23885_risc_decode(risc);
 509                 for (j = 1; j < n; j++) {
 510                         risc = cx_read(ch->ctrl_start + 4 * (i + j));
 511                         printk("%s:   iq %x: 0x%08x [ arg #%d ]\n",
 512                                dev->name, i+j, risc, j);
 513                 }
 514         }
 515
 516         printk("%s: fifo: 0x%08x -> 0x%x\n",
 517                dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
 518         printk("%s: ctrl: 0x%08x -> 0x%x\n",
 519                dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
 520         printk("%s:   ptr1_reg: 0x%08x\n",
 521                dev->name, cx_read(ch->ptr1_reg));
 522         printk("%s:   ptr2_reg: 0x%08x\n",
 523                dev->name, cx_read(ch->ptr2_reg));
 524         printk("%s:   cnt1_reg: 0x%08x\n",
 525                dev->name, cx_read(ch->cnt1_reg));
 526         printk("%s:   cnt2_reg: 0x%08x\n",
 527                dev->name, cx_read(ch->cnt2_reg));
 528 }
 529
 530 void cx23885_risc_disasm(struct cx23885_tsport *port,
 531                          struct btcx_riscmem *risc)
 532 {
 533         struct cx23885_dev *dev = port->dev;
 534         unsigned int i, j, n;
 535
 536         printk("%s: risc disasm: %p [dma=0x%08lx]\n",
 537                dev->name, risc->cpu, (unsigned long)risc->dma);
 538         for (i = 0; i < (risc->size >> 2); i += n) {
 539                 printk("%s:   %04d: ", dev->name, i);
 540                 n = cx23885_risc_decode(risc->cpu[i]);
 541                 for (j = 1; j < n; j++)
 542                         printk("%s:   %04d: 0x%08x [ arg #%d ]\n",
 543                                dev->name, i + j, risc->cpu[i + j], j);
 544                 if (risc->cpu[i] == RISC_JUMP)
 545                         break;
 546         }
 547 }
 548
 549 void cx23885_shutdown(struct cx23885_dev *dev)
 550 {
 551         /* disable RISC controller */
 552         cx_write(DEV_CNTRL2, 0);
 553
 554         /* Disable all IR activity */
 555         cx_write(IR_CNTRL_REG, 0);
 556
 557         /* Disable Video A/B activity */
 558         cx_write(VID_A_DMA_CTL, 0);
 559         cx_write(VID_B_DMA_CTL, 0);
 560         cx_write(VID_C_DMA_CTL, 0);
 561
 562         /* Disable Audio activity */
 563         cx_write(AUD_INT_DMA_CTL, 0);
 564         cx_write(AUD_EXT_DMA_CTL, 0);
 565
 566         /* Disable Serial port */
 567         cx_write(UART_CTL, 0);
 568
 569         /* Disable Interrupts */
 570         cx_write(PCI_INT_MSK, 0);
 571         cx_write(VID_A_INT_MSK, 0);
 572         cx_write(VID_B_INT_MSK, 0);
 573         cx_write(VID_C_INT_MSK, 0);
 574         cx_write(AUDIO_INT_INT_MSK, 0);
 575         cx_write(AUDIO_EXT_INT_MSK, 0);
 576
 577 }
 578
 579 void cx23885_reset(struct cx23885_dev *dev)
 580 {
 581         dprintk(1, "%s()\n", __FUNCTION__);
 582
 583         cx23885_shutdown(dev);
 584
 585         cx_write(PCI_INT_STAT, 0xffffffff);
 586         cx_write(VID_A_INT_STAT, 0xffffffff);
 587         cx_write(VID_B_INT_STAT, 0xffffffff);
 588         cx_write(VID_C_INT_STAT, 0xffffffff);
 589         cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
 590         cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
 591         cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
 592
 593         mdelay(100);
 594
 595         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH01 ], 188*4, 0);
 596         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH02 ], 128, 0);
 597         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH03 ], 128, 0);
 598         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH04 ], 128, 0);
 599         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH05 ], 128, 0);
 600         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH06 ], 188*4, 0);
 601         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH07 ], 128, 0);
 602         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH08 ], 128, 0);
 603         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH09 ], 128, 0);
 604
 605         switch(dev->board) {
 606         case CX23885_BOARD_HAUPPAUGE_HVR1800:
 607                 /* GPIO-0 656_CLK */
 608                 /* GPIO-1 656_D0 */
 609                 /* GPIO-2 8295A Reset */
 610                 /* GPIO-3-10 cx23417 data0-7 */
 611                 /* GPIO-11-14 cx23417 addr0-3 */
 612                 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
 613                 /* GPIO-19 IR_RX */
 614                 dprintk( 1, "%s() Configuring HVR1800 GPIO's\n", __FUNCTION__);
 615                 // FIXME: Analog requires the tuner is brought out of reset
 616                 break;
 617         }
 618 }
 619
 620
 621 static int cx23885_pci_quirks(struct cx23885_dev *dev)
 622 {
 623         dprintk(1, "%s()\n", __FUNCTION__);
 624
 625         if(dev->bridge == CX23885_BRIDGE_885)
 626                 cx_clear(RDR_TLCTL0, 1 << 4);
 627
 628         return 0;
 629 }
 630
 631 static int get_resources(struct cx23885_dev *dev)
 632 {
 633         if (request_mem_region(pci_resource_start(dev->pci,0),
 634                                pci_resource_len(dev->pci,0),
 635                                dev->name))
 636                 return 0;
 637
 638         printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
 639                 dev->name, (unsigned long long)pci_resource_start(dev->pci,0));
 640
 641         return -EBUSY;
 642 }
 643
 644 static void cx23885_timeout(unsigned long data);
 645 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
 646                          u32 reg, u32 mask, u32 value);
 647
 648 static int cx23885_ir_init(struct cx23885_dev *dev)
 649 {
 650         dprintk(1, "%s()\n", __FUNCTION__);
 651
 652         switch (dev->board) {
 653         case CX23885_BOARD_HAUPPAUGE_HVR1800:
 654                 dprintk(1, "%s() FIXME - Implement IR support\n", __FUNCTION__);
 655                 break;
 656         }
 657
 658         return 0;
 659 }
 660
 661 static int cx23885_dev_setup(struct cx23885_dev *dev)
 662 {
 663         int i;
 664
 665         mutex_init(&dev->lock);
 666
 667         atomic_inc(&dev->refcount);
 668
 669         dev->nr = cx23885_devcount++;
 670         dev->pci_bus  = dev->pci->bus->number;
 671         dev->pci_slot = PCI_SLOT(dev->pci->devfn);
 672         dev->pci_irqmask = 0x001f00;
 673
 674         /* External Master 1 Bus */
 675         dev->i2c_bus[0].nr = 0;
 676         dev->i2c_bus[0].dev = dev;
 677         dev->i2c_bus[0].reg_stat  = I2C1_STAT;
 678         dev->i2c_bus[0].reg_ctrl  = I2C1_CTRL;
 679         dev->i2c_bus[0].reg_addr  = I2C1_ADDR;
 680         dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
 681         dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
 682         dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
 683
 684         /* External Master 2 Bus */
 685         dev->i2c_bus[1].nr = 1;
 686         dev->i2c_bus[1].dev = dev;
 687         dev->i2c_bus[1].reg_stat  = I2C2_STAT;
 688         dev->i2c_bus[1].reg_ctrl  = I2C2_CTRL;
 689         dev->i2c_bus[1].reg_addr  = I2C2_ADDR;
 690         dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
 691         dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
 692         dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
 693
 694         /* Internal Master 3 Bus */
 695         dev->i2c_bus[2].nr = 2;
 696         dev->i2c_bus[2].dev = dev;
 697         dev->i2c_bus[2].reg_stat  = I2C3_STAT;
 698         dev->i2c_bus[2].reg_ctrl  = I2C3_CTRL;
 699         dev->i2c_bus[2].reg_addr  = I2C3_ADDR;
 700         dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
 701         dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
 702         dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
 703
 704         /* Transport bus init dma queue */
 705         spin_lock_init(&dev->ts2.slock);
 706         dev->ts2.dev = dev;
 707         dev->ts2.nr = 2;
 708         dev->ts2.sram_chno = SRAM_CH06;
 709         INIT_LIST_HEAD(&dev->ts2.mpegq.active);
 710         INIT_LIST_HEAD(&dev->ts2.mpegq.queued);
 711         dev->ts2.mpegq.timeout.function = cx23885_timeout;
 712         dev->ts2.mpegq.timeout.data     = (unsigned long)&dev->ts2;
 713         init_timer(&dev->ts2.mpegq.timeout);
 714
 715         dev->ts2.reg_gpcnt = VID_C_GPCNT;
 716         dev->ts2.reg_gpcnt_ctl = VID_C_GPCNT_CTL;
 717         dev->ts2.reg_dma_ctl = VID_C_DMA_CTL;
 718         dev->ts2.reg_lngth = VID_C_LNGTH;
 719         dev->ts2.reg_hw_sop_ctrl = VID_C_HW_SOP_CTL;
 720         dev->ts2.reg_gen_ctrl = VID_C_GEN_CTL;
 721         dev->ts2.reg_bd_pkt_status = VID_C_BD_PKT_STATUS;
 722         dev->ts2.reg_sop_status = VID_C_SOP_STATUS;
 723         dev->ts2.reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
 724         dev->ts2.reg_vld_misc = VID_C_VLD_MISC;
 725         dev->ts2.reg_ts_clk_en = VID_C_TS_CLK_EN;
 726         dev->ts2.reg_ts_int_msk = VID_C_INT_MSK;
 727
 728         // FIXME: Make this board specific
 729         dev->ts2.pci_irqmask = 0x04; /* TS Port 2 bit */
 730         dev->ts2.dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */
 731         dev->ts2.ts_int_msk_val = 0x1111; /* TS port bits for RISC */
 732         dev->ts2.gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
 733         dev->ts2.ts_clk_en_val = 0x1; /* Enable TS_CLK */
 734
 735         cx23885_risc_stopper(dev->pci, &dev->ts2.mpegq.stopper,
 736                              dev->ts2.reg_dma_ctl, dev->ts2.dma_ctl_val, 0x00);
 737
 738         sprintf(dev->name, "cx23885[%d]", dev->nr);
 739
 740         if (get_resources(dev) < 0) {
 741                 printk(KERN_ERR "CORE %s No more PCIe resources for "
 742                        "subsystem: %04x:%04x\n",
 743                        dev->name, dev->pci->subsystem_vendor,
 744                        dev->pci->subsystem_device);
 745
 746                 cx23885_devcount--;
 747                 goto fail_free;
 748         }
 749
 750         mutex_lock(&devlist);
 751         list_add_tail(&dev->devlist, &cx23885_devlist);
 752         mutex_unlock(&devlist);
 753
 754         /* PCIe stuff */
 755         dev->lmmio = ioremap(pci_resource_start(dev->pci,0),
 756                              pci_resource_len(dev->pci,0));
 757
 758         dev->bmmio = (u8 __iomem *)dev->lmmio;
 759
 760         /* board config */
 761         dev->board = UNSET;
 762         if (card[dev->nr] < cx23885_bcount)
 763                 dev->board = card[dev->nr];
 764         for (i = 0; UNSET == dev->board  &&  i < cx23885_idcount; i++)
 765                 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
 766                     dev->pci->subsystem_device == cx23885_subids[i].subdevice)
 767                         dev->board = cx23885_subids[i].card;
 768         if (UNSET == dev->board) {
 769                 dev->board = CX23885_BOARD_UNKNOWN;
 770                 cx23885_card_list(dev);
 771         }
 772         printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
 773                dev->name, dev->pci->subsystem_vendor,
 774                dev->pci->subsystem_device, cx23885_boards[dev->board].name,
 775                dev->board, card[dev->nr] == dev->board ?
 776                "insmod option" : "autodetected");
 777
 778         /* Configure the internal memory */
 779         if(dev->pci->device == 0x8880) {
 780                 dev->bridge = CX23885_BRIDGE_887;
 781                 dev->sram_channels = cx23887_sram_channels;
 782         } else
 783         if(dev->pci->device == 0x8852) {
 784                 dev->bridge = CX23885_BRIDGE_885;
 785                 dev->sram_channels = cx23885_sram_channels;
 786         }
 787         dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
 788                 __FUNCTION__, dev->bridge);
 789
 790         cx23885_pci_quirks(dev);
 791
 792         /* init hardware */
 793         cx23885_reset(dev);
 794
 795         cx23885_i2c_register(&dev->i2c_bus[0]);
 796         cx23885_i2c_register(&dev->i2c_bus[1]);
 797         cx23885_i2c_register(&dev->i2c_bus[2]);
 798         cx23885_call_i2c_clients (&dev->i2c_bus[0], TUNER_SET_STANDBY, NULL);
 799
 800         cx23885_card_setup(dev);
 801         cx23885_ir_init(dev);
 802
 803         if (cx23885_dvb_register(&dev->ts2) < 0) {
 804                 printk(KERN_ERR "%s() Failed to register dvb adapters\n",
 805                        __FUNCTION__);
 806         }
 807
 808         return 0;
 809
 810 fail_free:
 811         kfree(dev);
 812         return -ENODEV;
 813 }
 814
 815 void cx23885_dev_unregister(struct cx23885_dev *dev)
 816 {
 817         release_mem_region(pci_resource_start(dev->pci,0),
 818                            pci_resource_len(dev->pci,0));
 819
 820         if (!atomic_dec_and_test(&dev->refcount))
 821                 return;
 822
 823         cx23885_dvb_unregister(&dev->ts2);
 824         cx23885_i2c_unregister(&dev->i2c_bus[2]);
 825         cx23885_i2c_unregister(&dev->i2c_bus[1]);
 826         cx23885_i2c_unregister(&dev->i2c_bus[0]);
 827
 828         iounmap(dev->lmmio);
 829 }
 830
 831 static u32* cx23885_risc_field(u32 *rp, struct scatterlist *sglist,
 832                                unsigned int offset, u32 sync_line,
 833                                unsigned int bpl, unsigned int padding,
 834                                unsigned int lines)
 835 {
 836         struct scatterlist *sg;
 837         unsigned int line, todo;
 838
 839         /* sync instruction */
 840         if (sync_line != NO_SYNC_LINE)
 841                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
 842
 843         /* scan lines */
 844         sg = sglist;
 845         for (line = 0; line < lines; line++) {
 846                 while (offset && offset >= sg_dma_len(sg)) {
 847                         offset -= sg_dma_len(sg);
 848                         sg++;
 849                 }
 850                 if (bpl <= sg_dma_len(sg)-offset) {
 851                         /* fits into current chunk */
 852                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
 853                         *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
 854                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 855                         offset+=bpl;
 856                 } else {
 857                         /* scanline needs to be split */
 858                         todo = bpl;
 859                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|
 860                                             (sg_dma_len(sg)-offset));
 861                         *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
 862                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 863                         todo -= (sg_dma_len(sg)-offset);
 864                         offset = 0;
 865                         sg++;
 866                         while (todo > sg_dma_len(sg)) {
 867                                 *(rp++)=cpu_to_le32(RISC_WRITE|
 868                                                     sg_dma_len(sg));
 869                                 *(rp++)=cpu_to_le32(sg_dma_address(sg));
 870                                 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 871                                 todo -= sg_dma_len(sg);
 872                                 sg++;
 873                         }
 874                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
 875                         *(rp++)=cpu_to_le32(sg_dma_address(sg));
 876                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 877                         offset += todo;
 878                 }
 879                 offset += padding;
 880         }
 881
 882         return rp;
 883 }
 884
 885 int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
 886                         struct scatterlist *sglist, unsigned int top_offset,
 887                         unsigned int bottom_offset, unsigned int bpl,
 888                         unsigned int padding, unsigned int lines)
 889 {
 890         u32 instructions, fields;
 891         u32 *rp;
 892         int rc;
 893
 894         fields = 0;
 895         if (UNSET != top_offset)
 896                 fields++;
 897         if (UNSET != bottom_offset)
 898                 fields++;
 899
 900         /* estimate risc mem: worst case is one write per page border +
 901            one write per scan line + syncs + jump (all 2 dwords).  Padding
 902            can cause next bpl to start close to a page border.  First DMA
 903            region may be smaller than PAGE_SIZE */
 904         /* write and jump need and extra dword */
 905         instructions  = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
 906         instructions += 2;
 907         //if ((rc = btcx_riscmem_alloc(pci,risc,instructions*8)) < 0)
 908         if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
 909                 return rc;
 910
 911         /* write risc instructions */
 912         rp = risc->cpu;
 913         if (UNSET != top_offset)
 914                 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
 915                                         bpl, padding, lines);
 916         if (UNSET != bottom_offset)
 917                 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
 918                                         bpl, padding, lines);
 919
 920         /* save pointer to jmp instruction address */
 921         risc->jmp = rp;
 922         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
 923         return 0;
 924 }
 925
 926 int cx23885_risc_databuffer(struct pci_dev *pci, struct btcx_riscmem *risc,
 927                             struct scatterlist *sglist, unsigned int bpl,
 928                             unsigned int lines)
 929 {
 930         u32 instructions;
 931         u32 *rp;
 932         int rc;
 933
 934         /* estimate risc mem: worst case is one write per page border +
 935            one write per scan line + syncs + jump (all 2 dwords).  Here
 936            there is no padding and no sync.  First DMA region may be smaller
 937            than PAGE_SIZE */
 938         /* Jump and write need an extra dword */
 939         instructions  = 1 + (bpl * lines) / PAGE_SIZE + lines;
 940         instructions += 1;
 941
 942         //if ((rc = btcx_riscmem_alloc(pci,risc,instructions*8)) < 0)
 943         if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
 944                 return rc;
 945
 946         /* write risc instructions */
 947         rp = risc->cpu;
 948         rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
 949
 950         /* save pointer to jmp instruction address */
 951         risc->jmp = rp;
 952         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
 953         return 0;
 954 }
 955
 956 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
 957                          u32 reg, u32 mask, u32 value)
 958 {
 959         u32 *rp;
 960         int rc;
 961
 962         if ((rc = btcx_riscmem_alloc(pci, risc, 4*16)) < 0)
 963                 return rc;
 964
 965         /* write risc instructions */
 966         rp = risc->cpu;
 967         //*(rp++) = cpu_to_le32(RISC_WRITECR  | RISC_IRQ2 | RISC_IMM);
 968         *(rp++) = cpu_to_le32(RISC_WRITECR  | RISC_IRQ2);
 969         *(rp++) = cpu_to_le32(reg);
 970         *(rp++) = cpu_to_le32(value);
 971         *(rp++) = cpu_to_le32(mask);
 972         *(rp++) = cpu_to_le32(RISC_JUMP);
 973         *(rp++) = cpu_to_le32(risc->dma);
 974         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
 975         return 0;
 976 }
 977
 978 void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
 979 {
 980         BUG_ON(in_interrupt());
 981         videobuf_waiton(&buf->vb, 0, 0);
 982         videobuf_dma_unmap(q, &buf->vb.dma);
 983         videobuf_dma_free(&buf->vb.dma);
 984         btcx_riscmem_free((struct pci_dev *)q->dev, &buf->risc);
 985         buf->vb.state = STATE_NEEDS_INIT;
 986 }
 987
 988 static int cx23885_start_dma(struct cx23885_tsport *port,
 989                              struct cx23885_dmaqueue *q,
 990                              struct cx23885_buffer   *buf)
 991 {
 992         struct cx23885_dev *dev = port->dev;
 993
 994         dprintk(1, "%s() w: %d, h: %d, f: %d\n", __FUNCTION__,
 995                 buf->vb.width, buf->vb.height, buf->vb.field);
 996
 997         /* setup fifo + format */
 998         cx23885_sram_channel_setup(dev,
 999                                    &dev->sram_channels[ port->sram_chno ],
1000                                    port->ts_packet_size, buf->risc.dma);
1001         if(debug > 5) {
1002                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ] );
1003                 cx23885_risc_disasm(port, &buf->risc);
1004         }
1005
1006         /* write TS length to chip */
1007         cx_write(port->reg_lngth, buf->vb.width);
1008
1009         if (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB)) {
1010                 printk( "%s() Failed. Unsupported value in .portc (0x%08x)\n",
1011                         __FUNCTION__, cx23885_boards[dev->board].portc );
1012                 return -EINVAL;
1013         }
1014
1015         // FIXME: review the need for these two lines
1016         dprintk( 1, "%s() doing .dvb\n", __FUNCTION__);
1017         udelay(100);
1018
1019         cx_write(port->reg_hw_sop_ctrl, 0x47 << 16 | 188 << 4);
1020         cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1021
1022         // FIXME: review the need for this
1023         cx_write(GPIO2, 0x00);
1024
1025         switch (dev->board) {
1026         case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1027         case CX23885_BOARD_HAUPPAUGE_HVR1800:
1028                 cx_write(port->reg_vld_misc, 0x00);
1029                 dprintk(1, "%s() Configuring HVR1800/lp/1500 board\n",
1030                         __FUNCTION__);
1031                 break;
1032         default:
1033                 // FIXME
1034                 printk(KERN_ERR "%s() error, default case", __FUNCTION__ );
1035         }
1036
1037         cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1038         udelay(100);
1039
1040         /* reset counter to zero */
1041         cx_write(port->reg_gpcnt_ctl, 3);
1042         q->count = 1;
1043
1044         switch(dev->bridge) {
1045         case CX23885_BRIDGE_885:
1046         case CX23885_BRIDGE_887:
1047                 /* enable irqs */
1048                 dprintk(1, "%s() enabling TS int's and DMA\n", __FUNCTION__ );
1049                 cx_set(port->reg_ts_int_msk,  port->ts_int_msk_val);
1050                 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1051                 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
1052                 break;
1053         default:
1054                 // FIXME: generate a sensible switch-default message
1055                 printk(KERN_ERR "%s() error, default case", __FUNCTION__ );
1056         }
1057
1058         dprintk(1, "%s() Register Dump\n", __FUNCTION__);
1059         dprintk(1, "%s() set port ts_int_msk, now %x\n", __FUNCTION__, cx_read(port->reg_ts_int_msk) );
1060         dprintk(1, "%s() DEV_CNTRL2      0x%08x\n", __FUNCTION__, cx_read(DEV_CNTRL2) );
1061         dprintk(1, "%s() PCI_INT_MSK     0x%08x\n", __FUNCTION__, cx_read(PCI_INT_MSK) );
1062         dprintk(1, "%s() VID_A_INT_MSK   0x%08x\n", __FUNCTION__, cx_read(VID_A_INT_MSK) );
1063         dprintk(1, "%s() VID_B_INT_MSK   0x%08x\n", __FUNCTION__, cx_read(VID_B_INT_MSK) );
1064         dprintk(1, "%s() VID_C_INT_MSK   0x%08x\n", __FUNCTION__, cx_read(VID_C_INT_MSK) );
1065         dprintk(1, "%s() VID_A_DMA_CTL   0x%08x\n", __FUNCTION__, cx_read(VID_A_DMA_CTL) );
1066         dprintk(1, "%s() VID_B_DMA_CTL   0x%08x\n", __FUNCTION__, cx_read(VID_B_DMA_CTL) );
1067         dprintk(1, "%s() VID_C_DMA_CTL   0x%08x\n", __FUNCTION__, cx_read(VID_C_DMA_CTL) );
1068         dprintk(1, "%s() AUD_INT_INT_MSK 0x%08x\n", __FUNCTION__, cx_read(AUDIO_INT_INT_MSK) );
1069         dprintk(1, "%s() AUD_INT_DMA_CTL 0x%08x\n", __FUNCTION__, cx_read(AUD_INT_DMA_CTL) );
1070         dprintk(1, "%s() AUD_EXT_INT_MSK 0x%08x\n", __FUNCTION__, cx_read(AUDIO_EXT_INT_MSK) );
1071         dprintk(1, "%s() AUD_EXT_DMA_CTL 0x%08x\n", __FUNCTION__, cx_read(AUD_EXT_DMA_CTL) );
1072
1073         cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1074
1075         dprintk(1, "%s() set dev_cntrl2, now %x\n", __FUNCTION__, cx_read(DEV_CNTRL2) );
1076         dprintk(1, "%s() VID_C_DMA_CTL   , now %x\n", __FUNCTION__, cx_read(port->reg_dma_ctl) );
1077         dprintk(1, "%s() VID_C_DMA_CTL   , now %x\n", __FUNCTION__, cx_read(VID_C_DMA_CTL) );
1078         dprintk(1, "%s() PAD_CTRL %x\n", __FUNCTION__, cx_read(PAD_CTRL) );
1079         dprintk(1, "%s() GPIO2 %x\n", __FUNCTION__, cx_read(GPIO2) );
1080         dprintk(1, "%s() VID_C_LN_LNGTH  , now %x\n", __FUNCTION__, cx_read(port->reg_lngth) );
1081         dprintk(1, "%s() VID_C_HW_SOP_CTL, now %x\n", __FUNCTION__, cx_read(port->reg_hw_sop_ctrl) );
1082         dprintk(1, "%s() VID_C_GEN_CTL   , now %x\n", __FUNCTION__, cx_read(port->reg_gen_ctrl) );
1083         dprintk(1, "%s() VID_C_SOP_STATUS, now %x\n", __FUNCTION__, cx_read(VID_C_SOP_STATUS) );
1084         dprintk(1, "%s() VID_C_TS_CLK_EN , now %x\n", __FUNCTION__, cx_read(VID_C_TS_CLK_EN) );
1085         dprintk(1, "%s() VID_C_FIFO_OVLST, now %x\n", __FUNCTION__, cx_read(VID_C_FIFO_OVFL_STAT) );
1086         dprintk(1, "%s() VID_C_INT_MSTAT , now 0x%08x\n", __FUNCTION__, cx_read(VID_C_INT_MSTAT) );
1087         return 0;
1088 }
1089
1090 static int cx23885_stop_dma(struct cx23885_tsport *port)
1091 {
1092         struct cx23885_dev *dev = port->dev;
1093         dprintk(1, "%s()\n", __FUNCTION__);
1094
1095         /* Stop interrupts and DMA */
1096         cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1097         cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1098
1099         return 0;
1100 }
1101
1102 static int cx23885_restart_queue(struct cx23885_tsport *port,
1103                                 struct cx23885_dmaqueue *q)
1104 {
1105         struct cx23885_dev *dev = port->dev;
1106         struct cx23885_buffer *buf;
1107         struct list_head *item;
1108
1109         dprintk(5, "%s()\n", __FUNCTION__);
1110         if (list_empty(&q->active))
1111         {
1112                 struct cx23885_buffer *prev;
1113                 prev = NULL;
1114
1115                 dprintk(5, "%s() queue is empty\n", __FUNCTION__);
1116
1117                 for (;;) {
1118                         if (list_empty(&q->queued))
1119                                 return 0;
1120                         buf = list_entry(q->queued.next, struct cx23885_buffer,
1121                                          vb.queue);
1122                         if (NULL == prev) {
1123                                 list_del(&buf->vb.queue);
1124                                 list_add_tail(&buf->vb.queue, &q->active);
1125                                 cx23885_start_dma(port, q, buf);
1126                                 buf->vb.state = STATE_ACTIVE;
1127                                 buf->count    = q->count++;
1128                                 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1129                                 dprintk(5, "[%p/%d] restart_queue - first active\n",
1130                                         buf, buf->vb.i);
1131
1132                         } else if (prev->vb.width  == buf->vb.width  &&
1133                                    prev->vb.height == buf->vb.height &&
1134                                    prev->fmt       == buf->fmt) {
1135                                 list_del(&buf->vb.queue);
1136                                 list_add_tail(&buf->vb.queue, &q->active);
1137                                 buf->vb.state = STATE_ACTIVE;
1138                                 buf->count    = q->count++;
1139                                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1140                                 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1141                                 dprintk(5,"[%p/%d] restart_queue - move to active\n",
1142                                         buf, buf->vb.i);
1143                         } else {
1144                                 return 0;
1145                         }
1146                         prev = buf;
1147                 }
1148                 return 0;
1149         }
1150
1151         buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
1152         dprintk(2, "restart_queue [%p/%d]: restart dma\n",
1153                 buf, buf->vb.i);
1154         cx23885_start_dma(port, q, buf);
1155         list_for_each(item, &q->active) {
1156                 buf = list_entry(item, struct cx23885_buffer, vb.queue);
1157                 buf->count = q->count++;
1158         }
1159         mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
1160         return 0;
1161 }
1162
1163 /* ------------------------------------------------------------------ */
1164
1165 int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1166                         struct cx23885_buffer *buf, enum v4l2_field field)
1167 {
1168         struct cx23885_dev *dev = port->dev;
1169         int size = port->ts_packet_size * port->ts_packet_count;
1170         int rc;
1171
1172         dprintk(1, "%s: %p\n", __FUNCTION__, buf);
1173         if (0 != buf->vb.baddr  &&  buf->vb.bsize < size)
1174                 return -EINVAL;
1175
1176         if (STATE_NEEDS_INIT == buf->vb.state) {
1177                 buf->vb.width  = port->ts_packet_size;
1178                 buf->vb.height = port->ts_packet_count;
1179                 buf->vb.size   = size;
1180                 buf->vb.field  = field /*V4L2_FIELD_TOP*/;
1181
1182                 if (0 != (rc = videobuf_iolock(q, &buf->vb, NULL)))
1183                         goto fail;
1184                 cx23885_risc_databuffer(dev->pci, &buf->risc,
1185                                      buf->vb.dma.sglist,
1186                                      buf->vb.width, buf->vb.height);
1187         }
1188         buf->vb.state = STATE_PREPARED;
1189         return 0;
1190
1191  fail:
1192         cx23885_free_buffer(q, buf);
1193         return rc;
1194 }
1195
1196 void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1197 {
1198         struct cx23885_buffer    *prev;
1199         struct cx23885_dev *dev = port->dev;
1200         struct cx23885_dmaqueue  *cx88q = &port->mpegq;
1201
1202         /* add jump to stopper */
1203         buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
1204         buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
1205         buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1206
1207         if (list_empty(&cx88q->active)) {
1208                 dprintk( 1, "queue is empty - first active\n" );
1209                 list_add_tail(&buf->vb.queue, &cx88q->active);
1210                 cx23885_start_dma(port, cx88q, buf);
1211                 buf->vb.state = STATE_ACTIVE;
1212                 buf->count    = cx88q->count++;
1213                 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
1214                 dprintk(1, "[%p/%d] %s - first active\n",
1215                         buf, buf->vb.i, __FUNCTION__);
1216
1217         } else {
1218                 dprintk( 1, "queue is not empty - append to active\n" );
1219                 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1220                                   vb.queue);
1221                 list_add_tail(&buf->vb.queue, &cx88q->active);
1222                 buf->vb.state = STATE_ACTIVE;
1223                 buf->count    = cx88q->count++;
1224                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1225                 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1226                 dprintk( 1, "[%p/%d] %s - append to active\n",
1227                          buf, buf->vb.i, __FUNCTION__);
1228         }
1229 }
1230
1231 /* ----------------------------------------------------------- */
1232
1233 static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
1234                               int restart)
1235 {
1236         struct cx23885_dev *dev = port->dev;
1237         struct cx23885_dmaqueue *q = &port->mpegq;
1238         struct cx23885_buffer *buf;
1239         unsigned long flags;
1240
1241         spin_lock_irqsave(&port->slock, flags);
1242         while (!list_empty(&q->active)) {
1243                 buf = list_entry(q->active.next, struct cx23885_buffer,
1244                                  vb.queue);
1245                 list_del(&buf->vb.queue);
1246                 buf->vb.state = STATE_ERROR;
1247                 wake_up(&buf->vb.done);
1248                 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
1249                         buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
1250         }
1251         if (restart) {
1252                 dprintk(1, "restarting queue\n" );
1253                 cx23885_restart_queue(port, q);
1254         }
1255         spin_unlock_irqrestore(&port->slock, flags);
1256 }
1257
1258 void cx23885_cancel_buffers(struct cx23885_tsport *port)
1259 {
1260         struct cx23885_dev *dev = port->dev;
1261         struct cx23885_dmaqueue *q = &port->mpegq;
1262
1263         dprintk(1, "%s()\n", __FUNCTION__);
1264         del_timer_sync(&q->timeout);
1265         cx23885_stop_dma(port);
1266         do_cancel_buffers(port, "cancel", 0);
1267 }
1268
1269 static void cx23885_timeout(unsigned long data)
1270 {
1271         struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1272         struct cx23885_dev *dev = port->dev;
1273
1274         dprintk(1, "%s()\n",__FUNCTION__);
1275
1276         if (debug > 5)
1277                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1278
1279         cx23885_stop_dma(port);
1280         do_cancel_buffers(port, "timeout", 1);
1281 }
1282
1283 #define PCI_MSK_APB_DMA   (1 << 12)
1284 #define PCI_MSK_AL_WR     (1 << 11)
1285 #define PCI_MSK_AL_RD     (1 << 10)
1286 #define PCI_MSK_RISC_WR   (1 <<  9)
1287 #define PCI_MSK_RISC_RD   (1 <<  8)
1288
1289 #define PCI_MSK_AUD_EXT   (1 <<  4)
1290 #define PCI_MSK_AUD_INT   (1 <<  3)
1291 #define PCI_MSK_VID_C     (1 <<  2)
1292 #define PCI_MSK_VID_B     (1 <<  1)
1293 #define PCI_MSK_VID_A      1
1294
1295 #define VID_C_MSK_BAD_PKT (1 << 20)
1296 #define VID_C_MSK_OPC_ERR (1 << 16)
1297 #define VID_C_MSK_SYNC    (1 << 12)
1298 #define VID_C_MSK_OF      (1 <<  8)
1299 #define VID_C_MSK_RISCI2  (1 <<  4)
1300 #define VID_C_MSK_RISCI1   1
1301
1302 static irqreturn_t cx23885_irq(int irq, void *dev_id)
1303 {
1304         struct cx23885_dev *dev = dev_id;
1305         struct cx23885_tsport *port = &dev->ts2;
1306         u32 pci_status, pci_mask;
1307         u32 ts2_status, ts2_mask;
1308         int count = 0, handled = 0;
1309
1310         pci_status = cx_read(PCI_INT_STAT);
1311         pci_mask = cx_read(PCI_INT_MSK);
1312
1313         ts2_status = cx_read(VID_C_INT_STAT);
1314         ts2_mask = cx_read(VID_C_INT_MSK);
1315
1316         if ( (pci_status == 0) && (ts2_status == 0) )
1317                 goto out;
1318
1319         count = cx_read(port->reg_gpcnt);
1320         dprintk(7, "pci_status: 0x%08x  pci_mask: 0x%08x\n", pci_status, pci_mask );
1321         dprintk(7, "ts2_status: 0x%08x  ts2_mask: 0x%08x count: 0x%x\n", ts2_status, ts2_mask, count );
1322
1323         if ( (pci_status & PCI_MSK_RISC_RD) ||
1324              (pci_status & PCI_MSK_RISC_WR) ||
1325              (pci_status & PCI_MSK_AL_RD) ||
1326              (pci_status & PCI_MSK_AL_WR) ||
1327              (pci_status & PCI_MSK_APB_DMA) ||
1328              (pci_status & PCI_MSK_VID_C) ||
1329              (pci_status & PCI_MSK_VID_B) ||
1330              (pci_status & PCI_MSK_VID_A) ||
1331              (pci_status & PCI_MSK_AUD_INT) ||
1332              (pci_status & PCI_MSK_AUD_EXT) )
1333         {
1334
1335                 if (pci_status & PCI_MSK_RISC_RD)
1336                         dprintk(7, " (PCI_MSK_RISC_RD   0x%08x)\n", PCI_MSK_RISC_RD);
1337                 if (pci_status & PCI_MSK_RISC_WR)
1338                         dprintk(7, " (PCI_MSK_RISC_WR   0x%08x)\n", PCI_MSK_RISC_WR);
1339                 if (pci_status & PCI_MSK_AL_RD)
1340                         dprintk(7, " (PCI_MSK_AL_RD     0x%08x)\n", PCI_MSK_AL_RD);
1341                 if (pci_status & PCI_MSK_AL_WR)
1342                         dprintk(7, " (PCI_MSK_AL_WR     0x%08x)\n", PCI_MSK_AL_WR);
1343                 if (pci_status & PCI_MSK_APB_DMA)
1344                         dprintk(7, " (PCI_MSK_APB_DMA   0x%08x)\n", PCI_MSK_APB_DMA);
1345                 if (pci_status & PCI_MSK_VID_C)
1346                         dprintk(7, " (PCI_MSK_VID_C     0x%08x)\n", PCI_MSK_VID_C);
1347                 if (pci_status & PCI_MSK_VID_B)
1348                         dprintk(7, " (PCI_MSK_VID_B     0x%08x)\n", PCI_MSK_VID_B);
1349                 if (pci_status & PCI_MSK_VID_A)
1350                         dprintk(7, " (PCI_MSK_VID_A     0x%08x)\n", PCI_MSK_VID_A);
1351                 if (pci_status & PCI_MSK_AUD_INT)
1352                         dprintk(7, " (PCI_MSK_AUD_INT   0x%08x)\n", PCI_MSK_AUD_INT);
1353                 if (pci_status & PCI_MSK_AUD_EXT)
1354                         dprintk(7, " (PCI_MSK_AUD_EXT   0x%08x)\n", PCI_MSK_AUD_EXT);
1355
1356         }
1357
1358         if ( (ts2_status & VID_C_MSK_OPC_ERR) ||
1359              (ts2_status & VID_C_MSK_BAD_PKT) ||
1360              (ts2_status & VID_C_MSK_SYNC) ||
1361              (ts2_status & VID_C_MSK_OF))
1362         {
1363                 if (ts2_status & VID_C_MSK_OPC_ERR)
1364                         dprintk(7, " (VID_C_MSK_OPC_ERR 0x%08x)\n", VID_C_MSK_OPC_ERR);
1365                 if (ts2_status & VID_C_MSK_BAD_PKT)
1366                         dprintk(7, " (VID_C_MSK_BAD_PKT 0x%08x)\n", VID_C_MSK_BAD_PKT);
1367                 if (ts2_status & VID_C_MSK_SYNC)
1368                         dprintk(7, " (VID_C_MSK_SYNC    0x%08x)\n", VID_C_MSK_SYNC);
1369                 if (ts2_status & VID_C_MSK_OF)
1370                         dprintk(7, " (VID_C_MSK_OF      0x%08x)\n", VID_C_MSK_OF);
1371
1372                 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1373
1374                 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1375                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1376
1377         } else if (ts2_status & VID_C_MSK_RISCI1) {
1378
1379                 dprintk(7, " (RISCI1            0x%08x)\n", VID_C_MSK_RISCI1);
1380
1381                 spin_lock(&port->slock);
1382                 count = cx_read(port->reg_gpcnt);
1383                 cx23885_wakeup(port, &port->mpegq, count);
1384                 spin_unlock(&port->slock);
1385
1386         } else if (ts2_status & VID_C_MSK_RISCI2) {
1387
1388                 dprintk(7, " (RISCI2            0x%08x)\n", VID_C_MSK_RISCI2);
1389
1390                 spin_lock(&port->slock);
1391                 cx23885_restart_queue(port, &port->mpegq);
1392                 spin_unlock(&port->slock);
1393
1394         }
1395
1396         cx_write(VID_C_INT_STAT, ts2_status);
1397         cx_write(PCI_INT_STAT, pci_status);
1398         handled = 1;
1399 out:
1400         return IRQ_RETVAL(handled);
1401 }
1402
1403 static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
1404                                      const struct pci_device_id *pci_id)
1405 {
1406         struct cx23885_dev *dev;
1407         int err;
1408
1409         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1410         if (NULL == dev)
1411                 return -ENOMEM;
1412
1413         /* pci init */
1414         dev->pci = pci_dev;
1415         if (pci_enable_device(pci_dev)) {
1416                 err = -EIO;
1417                 goto fail_free;
1418         }
1419
1420         if (cx23885_dev_setup(dev) < 0) {
1421                 err = -EINVAL;
1422                 goto fail_free;
1423         }
1424
1425         /* print pci info */
1426         pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1427         pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER,  &dev->pci_lat);
1428         printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1429                "latency: %d, mmio: 0x%llx\n", dev->name,
1430                pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1431                dev->pci_lat, (unsigned long long)pci_resource_start(pci_dev,0));
1432
1433         pci_set_master(pci_dev);
1434         if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1435                 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1436                 err = -EIO;
1437                 goto fail_irq;
1438         }
1439
1440         err = request_irq(pci_dev->irq, cx23885_irq,
1441                           IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
1442         if (err < 0) {
1443                 printk(KERN_ERR "%s: can't get IRQ %d\n",
1444                        dev->name, pci_dev->irq);
1445                 goto fail_irq;
1446         }
1447
1448         pci_set_drvdata(pci_dev, dev);
1449         return 0;
1450
1451 fail_irq:
1452         cx23885_dev_unregister(dev);
1453 fail_free:
1454         kfree(dev);
1455         return err;
1456 }
1457
1458 static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
1459 {
1460         struct cx23885_dev *dev = pci_get_drvdata(pci_dev);
1461
1462         cx23885_shutdown(dev);
1463
1464         pci_disable_device(pci_dev);
1465
1466         /* unregister stuff */
1467         free_irq(pci_dev->irq, dev);
1468         pci_set_drvdata(pci_dev, NULL);
1469
1470         mutex_lock(&devlist);
1471         list_del(&dev->devlist);
1472         mutex_unlock(&devlist);
1473
1474         cx23885_dev_unregister(dev);
1475         kfree(dev);
1476 }
1477
1478 static struct pci_device_id cx23885_pci_tbl[] = {
1479         {
1480                 /* CX23885 */
1481                 .vendor       = 0x14f1,
1482                 .device       = 0x8852,
1483                 .subvendor    = PCI_ANY_ID,
1484                 .subdevice    = PCI_ANY_ID,
1485         },{
1486                 /* CX23887 Rev 2 */
1487                 .vendor       = 0x14f1,
1488                 .device       = 0x8880,
1489                 .subvendor    = PCI_ANY_ID,
1490                 .subdevice    = PCI_ANY_ID,
1491         },{
1492                 /* --- end of list --- */
1493         }
1494 };
1495 MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
1496
1497 static struct pci_driver cx23885_pci_driver = {
1498         .name     = "cx23885",
1499         .id_table = cx23885_pci_tbl,
1500         .probe    = cx23885_initdev,
1501         .remove   = __devexit_p(cx23885_finidev),
1502         /* TODO */
1503         .suspend  = NULL,
1504         .resume   = NULL,
1505 };
1506
1507 static int cx23885_init(void)
1508 {
1509         printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
1510                (CX23885_VERSION_CODE >> 16) & 0xff,
1511                (CX23885_VERSION_CODE >>  8) & 0xff,
1512                CX23885_VERSION_CODE & 0xff);
1513 #ifdef SNAPSHOT
1514         printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
1515                SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
1516 #endif
1517         return pci_register_driver(&cx23885_pci_driver);
1518 }
1519
1520 static void cx23885_fini(void)
1521 {
1522         pci_unregister_driver(&cx23885_pci_driver);
1523 }
1524
1525 module_init(cx23885_init);
1526 module_exit(cx23885_fini);
1527
1528 /* ----------------------------------------------------------- */
1529 /*
1530  * Local variables:
1531  * c-basic-offset: 8
1532  * End:
1533  * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off
1534  */