err.no Git - linux-2.6/blob - drivers/media/video/cx23885/cx23885-core.c

   1 /*
   2  *  Driver for the Conexant CX23885 PCIe bridge
   3  *
   4  *  Copyright (c) 2006 Steven Toth <stoth@hauppauge.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/list.h>
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/kmod.h>
  27 #include <linux/kernel.h>
  28 #include <linux/slab.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/delay.h>
  31 #include <asm/div64.h>
  32
  33 #include "cx23885.h"
  34
  35 MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
  36 MODULE_AUTHOR("Steven Toth <stoth@hauppauge.com>");
  37 MODULE_LICENSE("GPL");
  38
  39 static unsigned int debug = 0;
  40 module_param(debug,int,0644);
  41 MODULE_PARM_DESC(debug,"enable debug messages");
  42
  43 static unsigned int card[]  = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
  44 module_param_array(card,  int, NULL, 0444);
  45 MODULE_PARM_DESC(card,"card type");
  46
  47 #define dprintk(level,fmt, arg...)      if (debug >= level) \
  48         printk(KERN_DEBUG "%s/0: " fmt, dev->name , ## arg)
  49
  50 static unsigned int cx23885_devcount;
  51
  52 static DEFINE_MUTEX(devlist);
  53 static LIST_HEAD(cx23885_devlist);
  54
  55 #define NO_SYNC_LINE (-1U)
  56
  57 /*
  58  * CX23885 Assumptions
  59  * 1 line = 16 bytes of CDT
  60  * cmds size = 80
  61  * cdt size = 16 * linesize
  62  * iqsize = 64
  63  * maxlines = 6
  64  *
  65  * Address Space:
  66  * 0x00000000 0x00008fff FIFO clusters
  67  * 0x00010000 0x000104af Channel Management Data Structures
  68  * 0x000104b0 0x000104ff Free
  69  * 0x00010500 0x000108bf 15 channels * iqsize
  70  * 0x000108c0 0x000108ff Free
  71  * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
  72  *                       15 channels * (iqsize + (maxlines * linesize))
  73  * 0x00010ea0 0x00010xxx Free
  74  */
  75
  76 static struct sram_channel cx23885_sram_channels[] = {
  77         [SRAM_CH01] = {
  78                 .name           = "VID A",
  79                 .cmds_start     = 0x10000,
  80                 .ctrl_start     = 0x105b0,
  81                 .cdt            = 0x107b0,
  82                 .fifo_start     = 0x40,
  83                 .fifo_size      = 0x2800,
  84                 .ptr1_reg       = DMA1_PTR1,
  85                 .ptr2_reg       = DMA1_PTR2,
  86                 .cnt1_reg       = DMA1_CNT1,
  87                 .cnt2_reg       = DMA1_CNT2,
  88                 .jumponly       = 1,
  89         },
  90         [SRAM_CH02] = {
  91                 .name           = "ch2",
  92                 .cmds_start     = 0x0,
  93                 .ctrl_start     = 0x0,
  94                 .cdt            = 0x0,
  95                 .fifo_start     = 0x0,
  96                 .fifo_size      = 0x0,
  97                 .ptr1_reg       = DMA2_PTR1,
  98                 .ptr2_reg       = DMA2_PTR2,
  99                 .cnt1_reg       = DMA2_CNT1,
 100                 .cnt2_reg       = DMA2_CNT2,
 101         },
 102         [SRAM_CH03] = {
 103                 .name           = "TS1 B",
 104                 .cmds_start     = 0x100A0,
 105                 .ctrl_start     = 0x10630,
 106                 .cdt            = 0x10870,
 107                 .fifo_start     = 0x5000,
 108                 .fifo_size      = 0x1000,
 109                 .ptr1_reg       = DMA3_PTR1,
 110                 .ptr2_reg       = DMA3_PTR2,
 111                 .cnt1_reg       = DMA3_CNT1,
 112                 .cnt2_reg       = DMA3_CNT2,
 113         },
 114         [SRAM_CH04] = {
 115                 .name           = "ch4",
 116                 .cmds_start     = 0x0,
 117                 .ctrl_start     = 0x0,
 118                 .cdt            = 0x0,
 119                 .fifo_start     = 0x0,
 120                 .fifo_size      = 0x0,
 121                 .ptr1_reg       = DMA4_PTR1,
 122                 .ptr2_reg       = DMA4_PTR2,
 123                 .cnt1_reg       = DMA4_CNT1,
 124                 .cnt2_reg       = DMA4_CNT2,
 125         },
 126         [SRAM_CH05] = {
 127                 .name           = "ch5",
 128                 .cmds_start     = 0x0,
 129                 .ctrl_start     = 0x0,
 130                 .cdt            = 0x0,
 131                 .fifo_start     = 0x0,
 132                 .fifo_size      = 0x0,
 133                 .ptr1_reg       = DMA5_PTR1,
 134                 .ptr2_reg       = DMA5_PTR2,
 135                 .cnt1_reg       = DMA5_CNT1,
 136                 .cnt2_reg       = DMA5_CNT2,
 137         },
 138         [SRAM_CH06] = {
 139                 .name           = "TS2 C",
 140                 .cmds_start     = 0x10140,
 141                 .ctrl_start     = 0x10680,
 142                 .cdt            = 0x108d0,
 143                 .fifo_start     = 0x6000,
 144                 .fifo_size      = 0x1000,
 145                 .ptr1_reg       = DMA5_PTR1,
 146                 .ptr2_reg       = DMA5_PTR2,
 147                 .cnt1_reg       = DMA5_CNT1,
 148                 .cnt2_reg       = DMA5_CNT2,
 149         },
 150         [SRAM_CH07] = {
 151                 .name           = "ch7",
 152                 .cmds_start     = 0x0,
 153                 .ctrl_start     = 0x0,
 154                 .cdt            = 0x0,
 155                 .fifo_start     = 0x0,
 156                 .fifo_size      = 0x0,
 157                 .ptr1_reg       = DMA6_PTR1,
 158                 .ptr2_reg       = DMA6_PTR2,
 159                 .cnt1_reg       = DMA6_CNT1,
 160                 .cnt2_reg       = DMA6_CNT2,
 161         },
 162         [SRAM_CH08] = {
 163                 .name           = "ch8",
 164                 .cmds_start     = 0x0,
 165                 .ctrl_start     = 0x0,
 166                 .cdt            = 0x0,
 167                 .fifo_start     = 0x0,
 168                 .fifo_size      = 0x0,
 169                 .ptr1_reg       = DMA7_PTR1,
 170                 .ptr2_reg       = DMA7_PTR2,
 171                 .cnt1_reg       = DMA7_CNT1,
 172                 .cnt2_reg       = DMA7_CNT2,
 173         },
 174         [SRAM_CH09] = {
 175                 .name           = "ch9",
 176                 .cmds_start     = 0x0,
 177                 .ctrl_start     = 0x0,
 178                 .cdt            = 0x0,
 179                 .fifo_start     = 0x0,
 180                 .fifo_size      = 0x0,
 181                 .ptr1_reg       = DMA8_PTR1,
 182                 .ptr2_reg       = DMA8_PTR2,
 183                 .cnt1_reg       = DMA8_CNT1,
 184                 .cnt2_reg       = DMA8_CNT2,
 185         },
 186 };
 187
 188 /* FIXME, these allocations will change when
 189  * analog arrives. The be reviewed.
 190  * CX23887 Assumptions
 191  * 1 line = 16 bytes of CDT
 192  * cmds size = 80
 193  * cdt size = 16 * linesize
 194  * iqsize = 64
 195  * maxlines = 6
 196  *
 197  * Address Space:
 198  * 0x00000000 0x00008fff FIFO clusters
 199  * 0x00010000 0x000104af Channel Management Data Structures
 200  * 0x000104b0 0x000104ff Free
 201  * 0x00010500 0x000108bf 15 channels * iqsize
 202  * 0x000108c0 0x000108ff Free
 203  * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
 204  *                       15 channels * (iqsize + (maxlines * linesize))
 205  * 0x00010ea0 0x00010xxx Free
 206  */
 207
 208 static struct sram_channel cx23887_sram_channels[] = {
 209         [SRAM_CH01] = {
 210                 .name           = "VID A",
 211                 .cmds_start     = 0x10000,
 212                 .ctrl_start     = 0x105b0,
 213                 .cdt            = 0x107b0,
 214                 .fifo_start     = 0x40,
 215                 .fifo_size      = 0x2800,
 216                 .ptr1_reg       = DMA1_PTR1,
 217                 .ptr2_reg       = DMA1_PTR2,
 218                 .cnt1_reg       = DMA1_CNT1,
 219                 .cnt2_reg       = DMA1_CNT2,
 220         },
 221         [SRAM_CH02] = {
 222                 .name           = "ch2",
 223                 .cmds_start     = 0x0,
 224                 .ctrl_start     = 0x0,
 225                 .cdt            = 0x0,
 226                 .fifo_start     = 0x0,
 227                 .fifo_size      = 0x0,
 228                 .ptr1_reg       = DMA2_PTR1,
 229                 .ptr2_reg       = DMA2_PTR2,
 230                 .cnt1_reg       = DMA2_CNT1,
 231                 .cnt2_reg       = DMA2_CNT2,
 232         },
 233         [SRAM_CH03] = {
 234                 .name           = "TS1 B",
 235                 .cmds_start     = 0x100A0,
 236                 .ctrl_start     = 0x10780,
 237                 .cdt            = 0x10400,
 238                 .fifo_start     = 0x5000,
 239                 .fifo_size      = 0x1000,
 240                 .ptr1_reg       = DMA3_PTR1,
 241                 .ptr2_reg       = DMA3_PTR2,
 242                 .cnt1_reg       = DMA3_CNT1,
 243                 .cnt2_reg       = DMA3_CNT2,
 244         },
 245         [SRAM_CH04] = {
 246                 .name           = "ch4",
 247                 .cmds_start     = 0x0,
 248                 .ctrl_start     = 0x0,
 249                 .cdt            = 0x0,
 250                 .fifo_start     = 0x0,
 251                 .fifo_size      = 0x0,
 252                 .ptr1_reg       = DMA4_PTR1,
 253                 .ptr2_reg       = DMA4_PTR2,
 254                 .cnt1_reg       = DMA4_CNT1,
 255                 .cnt2_reg       = DMA4_CNT2,
 256         },
 257         [SRAM_CH05] = {
 258                 .name           = "ch5",
 259                 .cmds_start     = 0x0,
 260                 .ctrl_start     = 0x0,
 261                 .cdt            = 0x0,
 262                 .fifo_start     = 0x0,
 263                 .fifo_size      = 0x0,
 264                 .ptr1_reg       = DMA5_PTR1,
 265                 .ptr2_reg       = DMA5_PTR2,
 266                 .cnt1_reg       = DMA5_CNT1,
 267                 .cnt2_reg       = DMA5_CNT2,
 268         },
 269         [SRAM_CH06] = {
 270                 .name           = "TS2 C",
 271                 .cmds_start     = 0x10140,
 272                 .ctrl_start     = 0x10680,
 273                 .cdt            = 0x108d0,
 274                 .fifo_start     = 0x6000,
 275                 .fifo_size      = 0x1000,
 276                 .ptr1_reg       = DMA5_PTR1,
 277                 .ptr2_reg       = DMA5_PTR2,
 278                 .cnt1_reg       = DMA5_CNT1,
 279                 .cnt2_reg       = DMA5_CNT2,
 280         },
 281         [SRAM_CH07] = {
 282                 .name           = "ch7",
 283                 .cmds_start     = 0x0,
 284                 .ctrl_start     = 0x0,
 285                 .cdt            = 0x0,
 286                 .fifo_start     = 0x0,
 287                 .fifo_size      = 0x0,
 288                 .ptr1_reg       = DMA6_PTR1,
 289                 .ptr2_reg       = DMA6_PTR2,
 290                 .cnt1_reg       = DMA6_CNT1,
 291                 .cnt2_reg       = DMA6_CNT2,
 292         },
 293         [SRAM_CH08] = {
 294                 .name           = "ch8",
 295                 .cmds_start     = 0x0,
 296                 .ctrl_start     = 0x0,
 297                 .cdt            = 0x0,
 298                 .fifo_start     = 0x0,
 299                 .fifo_size      = 0x0,
 300                 .ptr1_reg       = DMA7_PTR1,
 301                 .ptr2_reg       = DMA7_PTR2,
 302                 .cnt1_reg       = DMA7_CNT1,
 303                 .cnt2_reg       = DMA7_CNT2,
 304         },
 305         [SRAM_CH09] = {
 306                 .name           = "ch9",
 307                 .cmds_start     = 0x0,
 308                 .ctrl_start     = 0x0,
 309                 .cdt            = 0x0,
 310                 .fifo_start     = 0x0,
 311                 .fifo_size      = 0x0,
 312                 .ptr1_reg       = DMA8_PTR1,
 313                 .ptr2_reg       = DMA8_PTR2,
 314                 .cnt1_reg       = DMA8_CNT1,
 315                 .cnt2_reg       = DMA8_CNT2,
 316         },
 317 };
 318
 319 static int cx23885_risc_decode(u32 risc)
 320 {
 321         static char *instr[16] = {
 322                 [ RISC_SYNC    >> 28 ] = "sync",
 323                 [ RISC_WRITE   >> 28 ] = "write",
 324                 [ RISC_WRITEC  >> 28 ] = "writec",
 325                 [ RISC_READ    >> 28 ] = "read",
 326                 [ RISC_READC   >> 28 ] = "readc",
 327                 [ RISC_JUMP    >> 28 ] = "jump",
 328                 [ RISC_SKIP    >> 28 ] = "skip",
 329                 [ RISC_WRITERM >> 28 ] = "writerm",
 330                 [ RISC_WRITECM >> 28 ] = "writecm",
 331                 [ RISC_WRITECR >> 28 ] = "writecr",
 332         };
 333         static int incr[16] = {
 334                 [ RISC_WRITE   >> 28 ] = 3,
 335                 [ RISC_JUMP    >> 28 ] = 3,
 336                 [ RISC_SKIP    >> 28 ] = 1,
 337                 [ RISC_SYNC    >> 28 ] = 1,
 338                 [ RISC_WRITERM >> 28 ] = 3,
 339                 [ RISC_WRITECM >> 28 ] = 3,
 340                 [ RISC_WRITECR >> 28 ] = 4,
 341         };
 342         static char *bits[] = {
 343                 "12",   "13",   "14",   "resync",
 344                 "cnt0", "cnt1", "18",   "19",
 345                 "20",   "21",   "22",   "23",
 346                 "irq1", "irq2", "eol",  "sol",
 347         };
 348         int i;
 349
 350         printk("0x%08x [ %s", risc,
 351                instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
 352         for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
 353                 if (risc & (1 << (i + 12)))
 354                         printk(" %s", bits[i]);
 355         printk(" count=%d ]\n", risc & 0xfff);
 356         return incr[risc >> 28] ? incr[risc >> 28] : 1;
 357 }
 358
 359 static void cx23885_wakeup(struct cx23885_tsport *port,
 360                            struct cx23885_dmaqueue *q, u32 count)
 361 {
 362         struct cx23885_dev *dev = port->dev;
 363         struct cx23885_buffer *buf;
 364         int bc;
 365
 366         for (bc = 0;; bc++) {
 367                 if (list_empty(&q->active))
 368                         break;
 369                 buf = list_entry(q->active.next,
 370                                  struct cx23885_buffer, vb.queue);
 371
 372                 /* count comes from the hw and is is 16bit wide --
 373                  * this trick handles wrap-arounds correctly for
 374                  * up to 32767 buffers in flight... */
 375                 if ((s16) (count - buf->count) < 0)
 376                         break;
 377
 378                 do_gettimeofday(&buf->vb.ts);
 379                 dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
 380                         count, buf->count);
 381                 buf->vb.state = VIDEOBUF_DONE;
 382                 list_del(&buf->vb.queue);
 383                 wake_up(&buf->vb.done);
 384         }
 385         if (list_empty(&q->active)) {
 386                 del_timer(&q->timeout);
 387         } else {
 388                 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
 389         }
 390         if (bc != 1)
 391                 printk("%s: %d buffers handled (should be 1)\n",
 392                        __FUNCTION__, bc);
 393 }
 394
 395 static int cx23885_sram_channel_setup(struct cx23885_dev *dev,
 396                                       struct sram_channel *ch,
 397                                       unsigned int bpl, u32 risc)
 398 {
 399         unsigned int i, lines;
 400         u32 cdt;
 401
 402         if (ch->cmds_start == 0)
 403         {
 404                 dprintk(1, "%s() Erasing channel [%s]\n", __FUNCTION__,
 405                         ch->name);
 406                 cx_write(ch->ptr1_reg, 0);
 407                 cx_write(ch->ptr2_reg, 0);
 408                 cx_write(ch->cnt2_reg, 0);
 409                 cx_write(ch->cnt1_reg, 0);
 410                 return 0;
 411         } else {
 412                 dprintk(1, "%s() Configuring channel [%s]\n", __FUNCTION__,
 413                         ch->name);
 414         }
 415
 416         bpl   = (bpl + 7) & ~7; /* alignment */
 417         cdt   = ch->cdt;
 418         lines = ch->fifo_size / bpl;
 419         if (lines > 6)
 420                 lines = 6;
 421         BUG_ON(lines < 2);
 422
 423         cx_write(8 + 0, cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC) );
 424         cx_write(8 + 4, cpu_to_le32(8) );
 425         cx_write(8 + 8, cpu_to_le32(0) );
 426
 427         /* write CDT */
 428         for (i = 0; i < lines; i++) {
 429                 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __FUNCTION__, cdt + 16*i,
 430                         ch->fifo_start + bpl*i);
 431                 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
 432                 cx_write(cdt + 16*i +  4, 0);
 433                 cx_write(cdt + 16*i +  8, 0);
 434                 cx_write(cdt + 16*i + 12, 0);
 435         }
 436
 437         /* write CMDS */
 438         if (ch->jumponly)
 439                 cx_write(ch->cmds_start +  0, 8);
 440         else
 441                 cx_write(ch->cmds_start +  0, risc);
 442         cx_write(ch->cmds_start +  4, 0); /* 64 bits 63-32 */
 443         cx_write(ch->cmds_start +  8, cdt);
 444         cx_write(ch->cmds_start + 12, (lines*16) >> 3);
 445         cx_write(ch->cmds_start + 16, ch->ctrl_start);
 446         if (ch->jumponly)
 447                 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2) );
 448         else
 449                 cx_write(ch->cmds_start + 20, 64 >> 2);
 450         for (i = 24; i < 80; i += 4)
 451                 cx_write(ch->cmds_start + i, 0);
 452
 453         /* fill registers */
 454         cx_write(ch->ptr1_reg, ch->fifo_start);
 455         cx_write(ch->ptr2_reg, cdt);
 456         cx_write(ch->cnt2_reg, (lines*16) >> 3);
 457         cx_write(ch->cnt1_reg, (bpl >> 3) -1);
 458
 459         dprintk(2,"[bridge %d] sram setup %s: bpl=%d lines=%d\n",
 460                 dev->bridge,
 461                 ch->name,
 462                 bpl,
 463                 lines);
 464
 465         return 0;
 466 }
 467
 468 static void cx23885_sram_channel_dump(struct cx23885_dev *dev,
 469                                       struct sram_channel *ch)
 470 {
 471         static char *name[] = {
 472                 "init risc lo",
 473                 "init risc hi",
 474                 "cdt base",
 475                 "cdt size",
 476                 "iq base",
 477                 "iq size",
 478                 "risc pc lo",
 479                 "risc pc hi",
 480                 "iq wr ptr",
 481                 "iq rd ptr",
 482                 "cdt current",
 483                 "pci target lo",
 484                 "pci target hi",
 485                 "line / byte",
 486         };
 487         u32 risc;
 488         unsigned int i, j, n;
 489
 490         printk("%s: %s - dma channel status dump\n",
 491                dev->name, ch->name);
 492         for (i = 0; i < ARRAY_SIZE(name); i++)
 493                 printk("%s:   cmds: %-15s: 0x%08x\n",
 494                        dev->name, name[i],
 495                        cx_read(ch->cmds_start + 4*i));
 496
 497         for (i = 0; i < 4; i++) {
 498                 risc = cx_read(ch->cmds_start + 4 * (i + 14));
 499                 printk("%s:   risc%d: ", dev->name, i);
 500                 cx23885_risc_decode(risc);
 501         }
 502         for (i = 0; i < (64 >> 2); i += n) {
 503                 risc = cx_read(ch->ctrl_start + 4 * i);
 504                 /* No consideration for bits 63-32 */
 505
 506                 printk("%s:   (0x%08x) iq %x: ", dev->name,
 507                        ch->ctrl_start + 4 * i, i);
 508                 n = cx23885_risc_decode(risc);
 509                 for (j = 1; j < n; j++) {
 510                         risc = cx_read(ch->ctrl_start + 4 * (i + j));
 511                         printk("%s:   iq %x: 0x%08x [ arg #%d ]\n",
 512                                dev->name, i+j, risc, j);
 513                 }
 514         }
 515
 516         printk("%s: fifo: 0x%08x -> 0x%x\n",
 517                dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
 518         printk("%s: ctrl: 0x%08x -> 0x%x\n",
 519                dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
 520         printk("%s:   ptr1_reg: 0x%08x\n",
 521                dev->name, cx_read(ch->ptr1_reg));
 522         printk("%s:   ptr2_reg: 0x%08x\n",
 523                dev->name, cx_read(ch->ptr2_reg));
 524         printk("%s:   cnt1_reg: 0x%08x\n",
 525                dev->name, cx_read(ch->cnt1_reg));
 526         printk("%s:   cnt2_reg: 0x%08x\n",
 527                dev->name, cx_read(ch->cnt2_reg));
 528 }
 529
 530 static void cx23885_risc_disasm(struct cx23885_tsport *port,
 531                                 struct btcx_riscmem *risc)
 532 {
 533         struct cx23885_dev *dev = port->dev;
 534         unsigned int i, j, n;
 535
 536         printk("%s: risc disasm: %p [dma=0x%08lx]\n",
 537                dev->name, risc->cpu, (unsigned long)risc->dma);
 538         for (i = 0; i < (risc->size >> 2); i += n) {
 539                 printk("%s:   %04d: ", dev->name, i);
 540                 n = cx23885_risc_decode(risc->cpu[i]);
 541                 for (j = 1; j < n; j++)
 542                         printk("%s:   %04d: 0x%08x [ arg #%d ]\n",
 543                                dev->name, i + j, risc->cpu[i + j], j);
 544                 if (risc->cpu[i] == RISC_JUMP)
 545                         break;
 546         }
 547 }
 548
 549 static void cx23885_shutdown(struct cx23885_dev *dev)
 550 {
 551         /* disable RISC controller */
 552         cx_write(DEV_CNTRL2, 0);
 553
 554         /* Disable all IR activity */
 555         cx_write(IR_CNTRL_REG, 0);
 556
 557         /* Disable Video A/B activity */
 558         cx_write(VID_A_DMA_CTL, 0);
 559         cx_write(VID_B_DMA_CTL, 0);
 560         cx_write(VID_C_DMA_CTL, 0);
 561
 562         /* Disable Audio activity */
 563         cx_write(AUD_INT_DMA_CTL, 0);
 564         cx_write(AUD_EXT_DMA_CTL, 0);
 565
 566         /* Disable Serial port */
 567         cx_write(UART_CTL, 0);
 568
 569         /* Disable Interrupts */
 570         cx_write(PCI_INT_MSK, 0);
 571         cx_write(VID_A_INT_MSK, 0);
 572         cx_write(VID_B_INT_MSK, 0);
 573         cx_write(VID_C_INT_MSK, 0);
 574         cx_write(AUDIO_INT_INT_MSK, 0);
 575         cx_write(AUDIO_EXT_INT_MSK, 0);
 576
 577 }
 578
 579 static void cx23885_reset(struct cx23885_dev *dev)
 580 {
 581         dprintk(1, "%s()\n", __FUNCTION__);
 582
 583         cx23885_shutdown(dev);
 584
 585         cx_write(PCI_INT_STAT, 0xffffffff);
 586         cx_write(VID_A_INT_STAT, 0xffffffff);
 587         cx_write(VID_B_INT_STAT, 0xffffffff);
 588         cx_write(VID_C_INT_STAT, 0xffffffff);
 589         cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
 590         cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
 591         cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
 592
 593         mdelay(100);
 594
 595         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH01 ], 188*4, 0);
 596         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH02 ], 128, 0);
 597         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH03 ], 188*4, 0);
 598         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH04 ], 128, 0);
 599         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH05 ], 128, 0);
 600         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH06 ], 188*4, 0);
 601         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH07 ], 128, 0);
 602         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH08 ], 128, 0);
 603         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH09 ], 128, 0);
 604
 605         cx23885_gpio_setup(dev);
 606 }
 607
 608
 609 static int cx23885_pci_quirks(struct cx23885_dev *dev)
 610 {
 611         dprintk(1, "%s()\n", __FUNCTION__);
 612
 613         /* The cx23885 bridge has a weird bug which causes NMI to be asserted
 614          * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
 615          * occur on the cx23887 bridge.
 616          */
 617         if(dev->bridge == CX23885_BRIDGE_885)
 618                 cx_clear(RDR_TLCTL0, 1 << 4);
 619
 620         return 0;
 621 }
 622
 623 static int get_resources(struct cx23885_dev *dev)
 624 {
 625         if (request_mem_region(pci_resource_start(dev->pci,0),
 626                                pci_resource_len(dev->pci,0),
 627                                dev->name))
 628                 return 0;
 629
 630         printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
 631                 dev->name, (unsigned long long)pci_resource_start(dev->pci,0));
 632
 633         return -EBUSY;
 634 }
 635
 636 static void cx23885_timeout(unsigned long data);
 637 static int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
 638                                 u32 reg, u32 mask, u32 value);
 639
 640 static int cx23885_init_tsport(struct cx23885_dev *dev, struct cx23885_tsport *port, int portno)
 641 {
 642         dprintk(1, "%s(portno=%d)\n", __FUNCTION__, portno);
 643
 644         /* Transport bus init dma queue  - Common settings */
 645         port->dma_ctl_val        = 0x11; /* Enable RISC controller and Fifo */
 646         port->ts_int_msk_val     = 0x1111; /* TS port bits for RISC */
 647
 648         spin_lock_init(&port->slock);
 649         port->dev = dev;
 650         port->nr = portno;
 651
 652         INIT_LIST_HEAD(&port->mpegq.active);
 653         INIT_LIST_HEAD(&port->mpegq.queued);
 654         port->mpegq.timeout.function = cx23885_timeout;
 655         port->mpegq.timeout.data = (unsigned long)port;
 656         init_timer(&port->mpegq.timeout);
 657
 658         switch(portno) {
 659         case 1:
 660                 port->reg_gpcnt          = VID_B_GPCNT;
 661                 port->reg_gpcnt_ctl      = VID_B_GPCNT_CTL;
 662                 port->reg_dma_ctl        = VID_B_DMA_CTL;
 663                 port->reg_lngth          = VID_B_LNGTH;
 664                 port->reg_hw_sop_ctrl    = VID_B_HW_SOP_CTL;
 665                 port->reg_gen_ctrl       = VID_B_GEN_CTL;
 666                 port->reg_bd_pkt_status  = VID_B_BD_PKT_STATUS;
 667                 port->reg_sop_status     = VID_B_SOP_STATUS;
 668                 port->reg_fifo_ovfl_stat = VID_B_FIFO_OVFL_STAT;
 669                 port->reg_vld_misc       = VID_B_VLD_MISC;
 670                 port->reg_ts_clk_en      = VID_B_TS_CLK_EN;
 671                 port->reg_src_sel        = VID_B_SRC_SEL;
 672                 port->reg_ts_int_msk     = VID_B_INT_MSK;
 673                 port->reg_ts_int_stat   = VID_B_INT_STAT;
 674                 port->sram_chno          = SRAM_CH03; /* VID_B */
 675                 port->pci_irqmask        = 0x02; /* VID_B bit1 */
 676                 break;
 677         case 2:
 678                 port->reg_gpcnt          = VID_C_GPCNT;
 679                 port->reg_gpcnt_ctl      = VID_C_GPCNT_CTL;
 680                 port->reg_dma_ctl        = VID_C_DMA_CTL;
 681                 port->reg_lngth          = VID_C_LNGTH;
 682                 port->reg_hw_sop_ctrl    = VID_C_HW_SOP_CTL;
 683                 port->reg_gen_ctrl       = VID_C_GEN_CTL;
 684                 port->reg_bd_pkt_status  = VID_C_BD_PKT_STATUS;
 685                 port->reg_sop_status     = VID_C_SOP_STATUS;
 686                 port->reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
 687                 port->reg_vld_misc       = VID_C_VLD_MISC;
 688                 port->reg_ts_clk_en      = VID_C_TS_CLK_EN;
 689                 port->reg_src_sel        = 0;
 690                 port->reg_ts_int_msk     = VID_C_INT_MSK;
 691                 port->reg_ts_int_stat    = VID_C_INT_STAT;
 692                 port->sram_chno          = SRAM_CH06; /* VID_C */
 693                 port->pci_irqmask        = 0x04; /* VID_C bit2 */
 694                 break;
 695         default:
 696                 BUG();
 697         }
 698
 699         cx23885_risc_stopper(dev->pci, &port->mpegq.stopper,
 700                      port->reg_dma_ctl, port->dma_ctl_val, 0x00);
 701
 702         return 0;
 703 }
 704
 705 static void cx23885_dev_checkrevision(struct cx23885_dev *dev)
 706 {
 707         switch (cx_read(RDR_CFG2) & 0xff) {
 708         case 0x00:
 709                 /* cx23885 */
 710                 dev->hwrevision = 0xa0;
 711                 break;
 712         case 0x01:
 713                 /* CX23885-12Z */
 714                 dev->hwrevision = 0xa1;
 715                 break;
 716         case 0x02:
 717                 /* CX23885-13Z */
 718                 dev->hwrevision = 0xb0;
 719                 break;
 720         case 0x03:
 721                 /* CX23888-22Z */
 722                 dev->hwrevision = 0xc0;
 723                 break;
 724         case 0x0e:
 725                 /* CX23887-15Z */
 726                 dev->hwrevision = 0xc0;
 727         case 0x0f:
 728                 /* CX23887-14Z */
 729                 dev->hwrevision = 0xb1;
 730                 break;
 731         default:
 732                 printk(KERN_ERR "%s() New hardware revision found 0x%x\n",
 733                         __FUNCTION__, dev->hwrevision);
 734         }
 735         if (dev->hwrevision)
 736                 printk(KERN_INFO "%s() Hardware revision = 0x%02x\n",
 737                         __FUNCTION__, dev->hwrevision);
 738         else
 739                 printk(KERN_ERR "%s() Hardware revision unknown 0x%x\n",
 740                         __FUNCTION__, dev->hwrevision);
 741 }
 742
 743 static int cx23885_dev_setup(struct cx23885_dev *dev)
 744 {
 745         int i;
 746
 747         mutex_init(&dev->lock);
 748
 749         atomic_inc(&dev->refcount);
 750
 751         dev->nr = cx23885_devcount++;
 752         sprintf(dev->name, "cx23885[%d]", dev->nr);
 753
 754         mutex_lock(&devlist);
 755         list_add_tail(&dev->devlist, &cx23885_devlist);
 756         mutex_unlock(&devlist);
 757
 758         /* Configure the internal memory */
 759         if(dev->pci->device == 0x8880) {
 760                 dev->bridge = CX23885_BRIDGE_887;
 761                 dev->sram_channels = cx23887_sram_channels;
 762                 /* Apply a sensible clock frequency for the PCIe bridge */
 763                 dev->clk_freq = 25000000;
 764         } else
 765         if(dev->pci->device == 0x8852) {
 766                 dev->bridge = CX23885_BRIDGE_885;
 767                 dev->sram_channels = cx23885_sram_channels;
 768                 /* Apply a sensible clock frequency for the PCIe bridge */
 769                 dev->clk_freq = 28000000;
 770         } else
 771                 BUG();
 772
 773         dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
 774                 __FUNCTION__, dev->bridge);
 775
 776         /* board config */
 777         dev->board = UNSET;
 778         if (card[dev->nr] < cx23885_bcount)
 779                 dev->board = card[dev->nr];
 780         for (i = 0; UNSET == dev->board  &&  i < cx23885_idcount; i++)
 781                 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
 782                     dev->pci->subsystem_device == cx23885_subids[i].subdevice)
 783                         dev->board = cx23885_subids[i].card;
 784         if (UNSET == dev->board) {
 785                 dev->board = CX23885_BOARD_UNKNOWN;
 786                 cx23885_card_list(dev);
 787         }
 788
 789         /* If the user specific a clk freq override, apply it */
 790         if (cx23885_boards[dev->board].clk_freq > 0)
 791                 dev->clk_freq = cx23885_boards[dev->board].clk_freq;
 792
 793         dev->pci_bus  = dev->pci->bus->number;
 794         dev->pci_slot = PCI_SLOT(dev->pci->devfn);
 795         dev->pci_irqmask = 0x001f00;
 796
 797         /* External Master 1 Bus */
 798         dev->i2c_bus[0].nr = 0;
 799         dev->i2c_bus[0].dev = dev;
 800         dev->i2c_bus[0].reg_stat  = I2C1_STAT;
 801         dev->i2c_bus[0].reg_ctrl  = I2C1_CTRL;
 802         dev->i2c_bus[0].reg_addr  = I2C1_ADDR;
 803         dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
 804         dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
 805         dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
 806
 807         /* External Master 2 Bus */
 808         dev->i2c_bus[1].nr = 1;
 809         dev->i2c_bus[1].dev = dev;
 810         dev->i2c_bus[1].reg_stat  = I2C2_STAT;
 811         dev->i2c_bus[1].reg_ctrl  = I2C2_CTRL;
 812         dev->i2c_bus[1].reg_addr  = I2C2_ADDR;
 813         dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
 814         dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
 815         dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
 816
 817         /* Internal Master 3 Bus */
 818         dev->i2c_bus[2].nr = 2;
 819         dev->i2c_bus[2].dev = dev;
 820         dev->i2c_bus[2].reg_stat  = I2C3_STAT;
 821         dev->i2c_bus[2].reg_ctrl  = I2C3_CTRL;
 822         dev->i2c_bus[2].reg_addr  = I2C3_ADDR;
 823         dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
 824         dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
 825         dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
 826
 827         if(cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
 828                 cx23885_init_tsport(dev, &dev->ts1, 1);
 829
 830         if(cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
 831                 cx23885_init_tsport(dev, &dev->ts2, 2);
 832
 833         if (get_resources(dev) < 0) {
 834                 printk(KERN_ERR "CORE %s No more PCIe resources for "
 835                        "subsystem: %04x:%04x\n",
 836                        dev->name, dev->pci->subsystem_vendor,
 837                        dev->pci->subsystem_device);
 838
 839                 cx23885_devcount--;
 840                 return -ENODEV;
 841         }
 842
 843         /* PCIe stuff */
 844         dev->lmmio = ioremap(pci_resource_start(dev->pci,0),
 845                              pci_resource_len(dev->pci,0));
 846
 847         dev->bmmio = (u8 __iomem *)dev->lmmio;
 848
 849         printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
 850                dev->name, dev->pci->subsystem_vendor,
 851                dev->pci->subsystem_device, cx23885_boards[dev->board].name,
 852                dev->board, card[dev->nr] == dev->board ?
 853                "insmod option" : "autodetected");
 854
 855         cx23885_pci_quirks(dev);
 856
 857         /* init hardware */
 858         cx23885_reset(dev);
 859
 860         cx23885_i2c_register(&dev->i2c_bus[0]);
 861         cx23885_i2c_register(&dev->i2c_bus[1]);
 862         cx23885_i2c_register(&dev->i2c_bus[2]);
 863         cx23885_call_i2c_clients (&dev->i2c_bus[0], TUNER_SET_STANDBY, NULL);
 864         cx23885_card_setup(dev);
 865         cx23885_ir_init(dev);
 866
 867         if(cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
 868                 if (cx23885_dvb_register(&dev->ts1) < 0) {
 869                         printk(KERN_ERR "%s() Failed to register dvb adapters on VID_B\n",
 870                                __FUNCTION__);
 871                 }
 872         }
 873
 874         if(cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
 875                 if (cx23885_dvb_register(&dev->ts2) < 0) {
 876                         printk(KERN_ERR "%s() Failed to register dvb adapters on VID_C\n",
 877                                __FUNCTION__);
 878                 }
 879         }
 880
 881         cx23885_dev_checkrevision(dev);
 882
 883         return 0;
 884 }
 885
 886 static void cx23885_dev_unregister(struct cx23885_dev *dev)
 887 {
 888         release_mem_region(pci_resource_start(dev->pci,0),
 889                            pci_resource_len(dev->pci,0));
 890
 891         if (!atomic_dec_and_test(&dev->refcount))
 892                 return;
 893
 894         if(cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
 895                 cx23885_dvb_unregister(&dev->ts1);
 896
 897         if(cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
 898                 cx23885_dvb_unregister(&dev->ts2);
 899
 900         cx23885_i2c_unregister(&dev->i2c_bus[2]);
 901         cx23885_i2c_unregister(&dev->i2c_bus[1]);
 902         cx23885_i2c_unregister(&dev->i2c_bus[0]);
 903
 904         iounmap(dev->lmmio);
 905 }
 906
 907 static u32* cx23885_risc_field(u32 *rp, struct scatterlist *sglist,
 908                                unsigned int offset, u32 sync_line,
 909                                unsigned int bpl, unsigned int padding,
 910                                unsigned int lines)
 911 {
 912         struct scatterlist *sg;
 913         unsigned int line, todo;
 914
 915         /* sync instruction */
 916         if (sync_line != NO_SYNC_LINE)
 917                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
 918
 919         /* scan lines */
 920         sg = sglist;
 921         for (line = 0; line < lines; line++) {
 922                 while (offset && offset >= sg_dma_len(sg)) {
 923                         offset -= sg_dma_len(sg);
 924                         sg++;
 925                 }
 926                 if (bpl <= sg_dma_len(sg)-offset) {
 927                         /* fits into current chunk */
 928                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
 929                         *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
 930                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 931                         offset+=bpl;
 932                 } else {
 933                         /* scanline needs to be split */
 934                         todo = bpl;
 935                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|
 936                                             (sg_dma_len(sg)-offset));
 937                         *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
 938                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 939                         todo -= (sg_dma_len(sg)-offset);
 940                         offset = 0;
 941                         sg++;
 942                         while (todo > sg_dma_len(sg)) {
 943                                 *(rp++)=cpu_to_le32(RISC_WRITE|
 944                                                     sg_dma_len(sg));
 945                                 *(rp++)=cpu_to_le32(sg_dma_address(sg));
 946                                 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 947                                 todo -= sg_dma_len(sg);
 948                                 sg++;
 949                         }
 950                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
 951                         *(rp++)=cpu_to_le32(sg_dma_address(sg));
 952                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 953                         offset += todo;
 954                 }
 955                 offset += padding;
 956         }
 957
 958         return rp;
 959 }
 960
 961
 962 static int cx23885_risc_databuffer(struct pci_dev *pci,
 963                                    struct btcx_riscmem *risc,
 964                                    struct scatterlist *sglist,
 965                                    unsigned int bpl,
 966                                    unsigned int lines)
 967 {
 968         u32 instructions;
 969         u32 *rp;
 970         int rc;
 971
 972         /* estimate risc mem: worst case is one write per page border +
 973            one write per scan line + syncs + jump (all 2 dwords).  Here
 974            there is no padding and no sync.  First DMA region may be smaller
 975            than PAGE_SIZE */
 976         /* Jump and write need an extra dword */
 977         instructions  = 1 + (bpl * lines) / PAGE_SIZE + lines;
 978         instructions += 1;
 979
 980         if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
 981                 return rc;
 982
 983         /* write risc instructions */
 984         rp = risc->cpu;
 985         rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
 986
 987         /* save pointer to jmp instruction address */
 988         risc->jmp = rp;
 989         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
 990         return 0;
 991 }
 992
 993 static int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
 994                                 u32 reg, u32 mask, u32 value)
 995 {
 996         u32 *rp;
 997         int rc;
 998
 999         if ((rc = btcx_riscmem_alloc(pci, risc, 4*16)) < 0)
1000                 return rc;
1001
1002         /* write risc instructions */
1003         rp = risc->cpu;
1004         *(rp++) = cpu_to_le32(RISC_WRITECR  | RISC_IRQ2);
1005         *(rp++) = cpu_to_le32(reg);
1006         *(rp++) = cpu_to_le32(value);
1007         *(rp++) = cpu_to_le32(mask);
1008         *(rp++) = cpu_to_le32(RISC_JUMP);
1009         *(rp++) = cpu_to_le32(risc->dma);
1010         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1011         return 0;
1012 }
1013
1014 void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
1015 {
1016         struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
1017
1018         BUG_ON(in_interrupt());
1019         videobuf_waiton(&buf->vb, 0, 0);
1020         videobuf_dma_unmap(q, dma);
1021         videobuf_dma_free(dma);
1022         btcx_riscmem_free((struct pci_dev *)q->dev, &buf->risc);
1023         buf->vb.state = VIDEOBUF_NEEDS_INIT;
1024 }
1025
1026 static int cx23885_start_dma(struct cx23885_tsport *port,
1027                              struct cx23885_dmaqueue *q,
1028                              struct cx23885_buffer   *buf)
1029 {
1030         struct cx23885_dev *dev = port->dev;
1031
1032         dprintk(1, "%s() w: %d, h: %d, f: %d\n", __FUNCTION__,
1033                 buf->vb.width, buf->vb.height, buf->vb.field);
1034
1035         /* setup fifo + format */
1036         cx23885_sram_channel_setup(dev,
1037                                    &dev->sram_channels[ port->sram_chno ],
1038                                    port->ts_packet_size, buf->risc.dma);
1039         if(debug > 5) {
1040                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ] );
1041                 cx23885_risc_disasm(port, &buf->risc);
1042         }
1043
1044         /* write TS length to chip */
1045         cx_write(port->reg_lngth, buf->vb.width);
1046
1047         if ( (!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) &&
1048                 (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB)) ) {
1049                 printk( "%s() Failed. Unsupported value in .portb/c (0x%08x)/(0x%08x)\n",
1050                         __FUNCTION__,
1051                         cx23885_boards[dev->board].portb,
1052                         cx23885_boards[dev->board].portc );
1053                 return -EINVAL;
1054         }
1055
1056         udelay(100);
1057
1058         /* If the port supports SRC SELECT, configure it */
1059         if(port->reg_src_sel)
1060                 cx_write(port->reg_src_sel, port->src_sel_val);
1061
1062         cx_write(port->reg_hw_sop_ctrl, 0x47 << 16 | 188 << 4);
1063         cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1064         cx_write(port->reg_vld_misc, 0x00);
1065         cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1066         udelay(100);
1067
1068         // NOTE: this is 2 (reserved) for portb, does it matter?
1069         /* reset counter to zero */
1070         cx_write(port->reg_gpcnt_ctl, 3);
1071         q->count = 1;
1072
1073         switch(dev->bridge) {
1074         case CX23885_BRIDGE_885:
1075         case CX23885_BRIDGE_887:
1076                 /* enable irqs */
1077                 dprintk(1, "%s() enabling TS int's and DMA\n", __FUNCTION__ );
1078                 cx_set(port->reg_ts_int_msk,  port->ts_int_msk_val);
1079                 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1080                 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
1081                 break;
1082         default:
1083                 BUG();
1084         }
1085
1086         cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1087
1088         return 0;
1089 }
1090
1091 static int cx23885_stop_dma(struct cx23885_tsport *port)
1092 {
1093         struct cx23885_dev *dev = port->dev;
1094         dprintk(1, "%s()\n", __FUNCTION__);
1095
1096         /* Stop interrupts and DMA */
1097         cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1098         cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1099
1100         return 0;
1101 }
1102
1103 static int cx23885_restart_queue(struct cx23885_tsport *port,
1104                                 struct cx23885_dmaqueue *q)
1105 {
1106         struct cx23885_dev *dev = port->dev;
1107         struct cx23885_buffer *buf;
1108
1109         dprintk(5, "%s()\n", __FUNCTION__);
1110         if (list_empty(&q->active))
1111         {
1112                 struct cx23885_buffer *prev;
1113                 prev = NULL;
1114
1115                 dprintk(5, "%s() queue is empty\n", __FUNCTION__);
1116
1117                 for (;;) {
1118                         if (list_empty(&q->queued))
1119                                 return 0;
1120                         buf = list_entry(q->queued.next, struct cx23885_buffer,
1121                                          vb.queue);
1122                         if (NULL == prev) {
1123                                 list_del(&buf->vb.queue);
1124                                 list_add_tail(&buf->vb.queue, &q->active);
1125                                 cx23885_start_dma(port, q, buf);
1126                                 buf->vb.state = VIDEOBUF_ACTIVE;
1127                                 buf->count    = q->count++;
1128                                 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1129                                 dprintk(5, "[%p/%d] restart_queue - first active\n",
1130                                         buf, buf->vb.i);
1131
1132                         } else if (prev->vb.width  == buf->vb.width  &&
1133                                    prev->vb.height == buf->vb.height &&
1134                                    prev->fmt       == buf->fmt) {
1135                                 list_del(&buf->vb.queue);
1136                                 list_add_tail(&buf->vb.queue, &q->active);
1137                                 buf->vb.state = VIDEOBUF_ACTIVE;
1138                                 buf->count    = q->count++;
1139                                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1140                                 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1141                                 dprintk(5,"[%p/%d] restart_queue - move to active\n",
1142                                         buf, buf->vb.i);
1143                         } else {
1144                                 return 0;
1145                         }
1146                         prev = buf;
1147                 }
1148                 return 0;
1149         }
1150
1151         buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
1152         dprintk(2, "restart_queue [%p/%d]: restart dma\n",
1153                 buf, buf->vb.i);
1154         cx23885_start_dma(port, q, buf);
1155         list_for_each_entry(buf, &q->active, vb.queue)
1156                 buf->count = q->count++;
1157         mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
1158         return 0;
1159 }
1160
1161 /* ------------------------------------------------------------------ */
1162
1163 int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1164                         struct cx23885_buffer *buf, enum v4l2_field field)
1165 {
1166         struct cx23885_dev *dev = port->dev;
1167         int size = port->ts_packet_size * port->ts_packet_count;
1168         int rc;
1169
1170         dprintk(1, "%s: %p\n", __FUNCTION__, buf);
1171         if (0 != buf->vb.baddr  &&  buf->vb.bsize < size)
1172                 return -EINVAL;
1173
1174         if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
1175                 buf->vb.width  = port->ts_packet_size;
1176                 buf->vb.height = port->ts_packet_count;
1177                 buf->vb.size   = size;
1178                 buf->vb.field  = field /*V4L2_FIELD_TOP*/;
1179
1180                 if (0 != (rc = videobuf_iolock(q, &buf->vb, NULL)))
1181                         goto fail;
1182                 cx23885_risc_databuffer(dev->pci, &buf->risc,
1183                                         videobuf_to_dma(&buf->vb)->sglist,
1184                                         buf->vb.width, buf->vb.height);
1185         }
1186         buf->vb.state = VIDEOBUF_PREPARED;
1187         return 0;
1188
1189  fail:
1190         cx23885_free_buffer(q, buf);
1191         return rc;
1192 }
1193
1194 void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1195 {
1196         struct cx23885_buffer    *prev;
1197         struct cx23885_dev *dev = port->dev;
1198         struct cx23885_dmaqueue  *cx88q = &port->mpegq;
1199
1200         /* add jump to stopper */
1201         buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
1202         buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
1203         buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1204
1205         if (list_empty(&cx88q->active)) {
1206                 dprintk( 1, "queue is empty - first active\n" );
1207                 list_add_tail(&buf->vb.queue, &cx88q->active);
1208                 cx23885_start_dma(port, cx88q, buf);
1209                 buf->vb.state = VIDEOBUF_ACTIVE;
1210                 buf->count    = cx88q->count++;
1211                 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
1212                 dprintk(1, "[%p/%d] %s - first active\n",
1213                         buf, buf->vb.i, __FUNCTION__);
1214         } else {
1215                 dprintk( 1, "queue is not empty - append to active\n" );
1216                 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1217                                   vb.queue);
1218                 list_add_tail(&buf->vb.queue, &cx88q->active);
1219                 buf->vb.state = VIDEOBUF_ACTIVE;
1220                 buf->count    = cx88q->count++;
1221                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1222                 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1223                 dprintk( 1, "[%p/%d] %s - append to active\n",
1224                          buf, buf->vb.i, __FUNCTION__);
1225         }
1226 }
1227
1228 /* ----------------------------------------------------------- */
1229
1230 static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
1231                               int restart)
1232 {
1233         struct cx23885_dev *dev = port->dev;
1234         struct cx23885_dmaqueue *q = &port->mpegq;
1235         struct cx23885_buffer *buf;
1236         unsigned long flags;
1237
1238         spin_lock_irqsave(&port->slock, flags);
1239         while (!list_empty(&q->active)) {
1240                 buf = list_entry(q->active.next, struct cx23885_buffer,
1241                                  vb.queue);
1242                 list_del(&buf->vb.queue);
1243                 buf->vb.state = VIDEOBUF_ERROR;
1244                 wake_up(&buf->vb.done);
1245                 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
1246                         buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
1247         }
1248         if (restart) {
1249                 dprintk(1, "restarting queue\n" );
1250                 cx23885_restart_queue(port, q);
1251         }
1252         spin_unlock_irqrestore(&port->slock, flags);
1253 }
1254
1255
1256 static void cx23885_timeout(unsigned long data)
1257 {
1258         struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1259         struct cx23885_dev *dev = port->dev;
1260
1261         dprintk(1, "%s()\n",__FUNCTION__);
1262
1263         if (debug > 5)
1264                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1265
1266         cx23885_stop_dma(port);
1267         do_cancel_buffers(port, "timeout", 1);
1268 }
1269
1270 static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status)
1271 {
1272         struct cx23885_dev *dev = port->dev;
1273         int handled = 0;
1274         u32 count;
1275
1276         if ( (status & VID_BC_MSK_OPC_ERR) ||
1277              (status & VID_BC_MSK_BAD_PKT) ||
1278              (status & VID_BC_MSK_SYNC) ||
1279              (status & VID_BC_MSK_OF))
1280         {
1281                 if (status & VID_BC_MSK_OPC_ERR)
1282                         dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n", VID_BC_MSK_OPC_ERR);
1283                 if (status & VID_BC_MSK_BAD_PKT)
1284                         dprintk(7, " (VID_BC_MSK_BAD_PKT 0x%08x)\n", VID_BC_MSK_BAD_PKT);
1285                 if (status & VID_BC_MSK_SYNC)
1286                         dprintk(7, " (VID_BC_MSK_SYNC    0x%08x)\n", VID_BC_MSK_SYNC);
1287                 if (status & VID_BC_MSK_OF)
1288                         dprintk(7, " (VID_BC_MSK_OF      0x%08x)\n", VID_BC_MSK_OF);
1289
1290                 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1291
1292                 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1293                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1294
1295         } else if (status & VID_BC_MSK_RISCI1) {
1296
1297                 dprintk(7, " (RISCI1            0x%08x)\n", VID_BC_MSK_RISCI1);
1298
1299                 spin_lock(&port->slock);
1300                 count = cx_read(port->reg_gpcnt);
1301                 cx23885_wakeup(port, &port->mpegq, count);
1302                 spin_unlock(&port->slock);
1303
1304         } else if (status & VID_BC_MSK_RISCI2) {
1305
1306                 dprintk(7, " (RISCI2            0x%08x)\n", VID_BC_MSK_RISCI2);
1307
1308                 spin_lock(&port->slock);
1309                 cx23885_restart_queue(port, &port->mpegq);
1310                 spin_unlock(&port->slock);
1311
1312         }
1313         if (status) {
1314                 cx_write(port->reg_ts_int_stat, status);
1315                 handled = 1;
1316         }
1317
1318         return handled;
1319 }
1320
1321 static irqreturn_t cx23885_irq(int irq, void *dev_id)
1322 {
1323         struct cx23885_dev *dev = dev_id;
1324         struct cx23885_tsport *ts1 = &dev->ts1;
1325         struct cx23885_tsport *ts2 = &dev->ts2;
1326         u32 pci_status, pci_mask;
1327         u32 ts1_status, ts1_mask;
1328         u32 ts2_status, ts2_mask;
1329         int ts1_count = 0, ts2_count = 0, handled = 0;
1330
1331         pci_status = cx_read(PCI_INT_STAT);
1332         pci_mask = cx_read(PCI_INT_MSK);
1333         ts1_status = cx_read(VID_B_INT_STAT);
1334         ts1_mask = cx_read(VID_B_INT_MSK);
1335         ts2_status = cx_read(VID_C_INT_STAT);
1336         ts2_mask = cx_read(VID_C_INT_MSK);
1337
1338         if ( (pci_status == 0) && (ts2_status == 0) && (ts1_status == 0) )
1339                 goto out;
1340
1341         ts1_count = cx_read(ts1->reg_gpcnt);
1342         ts2_count = cx_read(ts2->reg_gpcnt);
1343         dprintk(7, "pci_status: 0x%08x  pci_mask: 0x%08x\n", pci_status, pci_mask );
1344         dprintk(7, "ts1_status: 0x%08x  ts1_mask: 0x%08x count: 0x%x\n", ts1_status, ts1_mask, ts1_count );
1345         dprintk(7, "ts2_status: 0x%08x  ts2_mask: 0x%08x count: 0x%x\n", ts2_status, ts2_mask, ts2_count );
1346
1347         if ( (pci_status & PCI_MSK_RISC_RD) ||
1348              (pci_status & PCI_MSK_RISC_WR) ||
1349              (pci_status & PCI_MSK_AL_RD) ||
1350              (pci_status & PCI_MSK_AL_WR) ||
1351              (pci_status & PCI_MSK_APB_DMA) ||
1352              (pci_status & PCI_MSK_VID_C) ||
1353              (pci_status & PCI_MSK_VID_B) ||
1354              (pci_status & PCI_MSK_VID_A) ||
1355              (pci_status & PCI_MSK_AUD_INT) ||
1356              (pci_status & PCI_MSK_AUD_EXT) )
1357         {
1358
1359                 if (pci_status & PCI_MSK_RISC_RD)
1360                         dprintk(7, " (PCI_MSK_RISC_RD   0x%08x)\n", PCI_MSK_RISC_RD);
1361                 if (pci_status & PCI_MSK_RISC_WR)
1362                         dprintk(7, " (PCI_MSK_RISC_WR   0x%08x)\n", PCI_MSK_RISC_WR);
1363                 if (pci_status & PCI_MSK_AL_RD)
1364                         dprintk(7, " (PCI_MSK_AL_RD     0x%08x)\n", PCI_MSK_AL_RD);
1365                 if (pci_status & PCI_MSK_AL_WR)
1366                         dprintk(7, " (PCI_MSK_AL_WR     0x%08x)\n", PCI_MSK_AL_WR);
1367                 if (pci_status & PCI_MSK_APB_DMA)
1368                         dprintk(7, " (PCI_MSK_APB_DMA   0x%08x)\n", PCI_MSK_APB_DMA);
1369                 if (pci_status & PCI_MSK_VID_C)
1370                         dprintk(7, " (PCI_MSK_VID_C     0x%08x)\n", PCI_MSK_VID_C);
1371                 if (pci_status & PCI_MSK_VID_B)
1372                         dprintk(7, " (PCI_MSK_VID_B     0x%08x)\n", PCI_MSK_VID_B);
1373                 if (pci_status & PCI_MSK_VID_A)
1374                         dprintk(7, " (PCI_MSK_VID_A     0x%08x)\n", PCI_MSK_VID_A);
1375                 if (pci_status & PCI_MSK_AUD_INT)
1376                         dprintk(7, " (PCI_MSK_AUD_INT   0x%08x)\n", PCI_MSK_AUD_INT);
1377                 if (pci_status & PCI_MSK_AUD_EXT)
1378                         dprintk(7, " (PCI_MSK_AUD_EXT   0x%08x)\n", PCI_MSK_AUD_EXT);
1379
1380         }
1381
1382         if (ts1_status)
1383                 handled += cx23885_irq_ts(ts1, ts1_status);
1384
1385         if (ts2_status)
1386                 handled += cx23885_irq_ts(ts2, ts2_status);
1387
1388         if (handled)
1389                 cx_write(PCI_INT_STAT, pci_status);
1390 out:
1391         return IRQ_RETVAL(handled);
1392 }
1393
1394 static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
1395                                      const struct pci_device_id *pci_id)
1396 {
1397         struct cx23885_dev *dev;
1398         int err;
1399
1400         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1401         if (NULL == dev)
1402                 return -ENOMEM;
1403
1404         /* pci init */
1405         dev->pci = pci_dev;
1406         if (pci_enable_device(pci_dev)) {
1407                 err = -EIO;
1408                 goto fail_free;
1409         }
1410
1411         if (cx23885_dev_setup(dev) < 0) {
1412                 err = -EINVAL;
1413                 goto fail_free;
1414         }
1415
1416         /* print pci info */
1417         pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1418         pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER,  &dev->pci_lat);
1419         printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1420                "latency: %d, mmio: 0x%llx\n", dev->name,
1421                pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1422                dev->pci_lat, (unsigned long long)pci_resource_start(pci_dev,0));
1423
1424         pci_set_master(pci_dev);
1425         if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1426                 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1427                 err = -EIO;
1428                 goto fail_irq;
1429         }
1430
1431         err = request_irq(pci_dev->irq, cx23885_irq,
1432                           IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
1433         if (err < 0) {
1434                 printk(KERN_ERR "%s: can't get IRQ %d\n",
1435                        dev->name, pci_dev->irq);
1436                 goto fail_irq;
1437         }
1438
1439         pci_set_drvdata(pci_dev, dev);
1440         return 0;
1441
1442 fail_irq:
1443         cx23885_dev_unregister(dev);
1444 fail_free:
1445         kfree(dev);
1446         return err;
1447 }
1448
1449 static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
1450 {
1451         struct cx23885_dev *dev = pci_get_drvdata(pci_dev);
1452
1453         cx23885_shutdown(dev);
1454
1455         pci_disable_device(pci_dev);
1456
1457         /* unregister stuff */
1458         free_irq(pci_dev->irq, dev);
1459         pci_set_drvdata(pci_dev, NULL);
1460
1461         mutex_lock(&devlist);
1462         list_del(&dev->devlist);
1463         mutex_unlock(&devlist);
1464
1465         cx23885_dev_unregister(dev);
1466         kfree(dev);
1467 }
1468
1469 static struct pci_device_id cx23885_pci_tbl[] = {
1470         {
1471                 /* CX23885 */
1472                 .vendor       = 0x14f1,
1473                 .device       = 0x8852,
1474                 .subvendor    = PCI_ANY_ID,
1475                 .subdevice    = PCI_ANY_ID,
1476         },{
1477                 /* CX23887 Rev 2 */
1478                 .vendor       = 0x14f1,
1479                 .device       = 0x8880,
1480                 .subvendor    = PCI_ANY_ID,
1481                 .subdevice    = PCI_ANY_ID,
1482         },{
1483                 /* --- end of list --- */
1484         }
1485 };
1486 MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
1487
1488 static struct pci_driver cx23885_pci_driver = {
1489         .name     = "cx23885",
1490         .id_table = cx23885_pci_tbl,
1491         .probe    = cx23885_initdev,
1492         .remove   = __devexit_p(cx23885_finidev),
1493         /* TODO */
1494         .suspend  = NULL,
1495         .resume   = NULL,
1496 };
1497
1498 static int cx23885_init(void)
1499 {
1500         printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
1501                (CX23885_VERSION_CODE >> 16) & 0xff,
1502                (CX23885_VERSION_CODE >>  8) & 0xff,
1503                CX23885_VERSION_CODE & 0xff);
1504 #ifdef SNAPSHOT
1505         printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
1506                SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
1507 #endif
1508         return pci_register_driver(&cx23885_pci_driver);
1509 }
1510
1511 static void cx23885_fini(void)
1512 {
1513         pci_unregister_driver(&cx23885_pci_driver);
1514 }
1515
1516 module_init(cx23885_init);
1517 module_exit(cx23885_fini);
1518
1519 /* ----------------------------------------------------------- */
1520 /*
1521  * Local variables:
1522  * c-basic-offset: 8
1523  * End:
1524  * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off
1525  */