err.no Git - linux-2.6/blob - drivers/media/dvb/frontends/tda18271-fe.c

   1 /*
   2     tda18271-fe.c - driver for the Philips / NXP TDA18271 silicon tuner
   3
   4     Copyright (C) 2007 Michael Krufky (mkrufky@linuxtv.org)
   5
   6     This program is free software; you can redistribute it and/or modify
   7     it under the terms of the GNU General Public License as published by
   8     the Free Software Foundation; either version 2 of the License, or
   9     (at your option) any later version.
  10
  11     This program is distributed in the hope that it will be useful,
  12     but WITHOUT ANY WARRANTY; without even the implied warranty of
  13     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14     GNU General Public License for more details.
  15
  16     You should have received a copy of the GNU General Public License
  17     along with this program; if not, write to the Free Software
  18     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19 */
  20
  21 #include <linux/delay.h>
  22 #include <linux/videodev2.h>
  23 #include "tuner-driver.h"
  24
  25 #include "tda18271.h"
  26 #include "tda18271-priv.h"
  27
  28 static int tda18271_debug;
  29 module_param_named(debug, tda18271_debug, int, 0644);
  30 MODULE_PARM_DESC(debug, "set debug level (info=1, map=2, reg=4 (or-able))");
  31
  32 #define dprintk(level, fmt, arg...) do {\
  33         if (tda18271_debug & level) \
  34                 printk(KERN_DEBUG "%s: " fmt, __FUNCTION__, ##arg); } while (0)
  35
  36 #define DBG_INFO 1
  37 #define DBG_MAP  2
  38 #define DBG_REG  4
  39
  40 #define dbg_info(fmt, arg...) dprintk(DBG_INFO, fmt, ##arg)
  41 #define dbg_map(fmt, arg...)   dprintk(DBG_MAP, fmt, ##arg)
  42 #define dbg_reg(fmt, arg...)   dprintk(DBG_REG, fmt, ##arg)
  43
  44 /*---------------------------------------------------------------------*/
  45
  46 #define TDA18271_ANALOG  0
  47 #define TDA18271_DIGITAL 1
  48
  49 struct tda18271_priv {
  50         u8 i2c_addr;
  51         struct i2c_adapter *i2c_adap;
  52         unsigned char tda18271_regs[TDA18271_NUM_REGS];
  53         int mode;
  54
  55         u32 frequency;
  56         u32 bandwidth;
  57 };
  58
  59 static int tda18271_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
  60 {
  61         struct tda18271_priv *priv = fe->tuner_priv;
  62         struct analog_tuner_ops *ops = fe->ops.analog_demod_ops;
  63         int ret = 0;
  64
  65         switch (priv->mode) {
  66         case TDA18271_ANALOG:
  67                 if (ops && ops->i2c_gate_ctrl)
  68                         ret = ops->i2c_gate_ctrl(fe, enable);
  69                 break;
  70         case TDA18271_DIGITAL:
  71                 if (fe->ops.i2c_gate_ctrl)
  72                         ret = fe->ops.i2c_gate_ctrl(fe, enable);
  73                 break;
  74         }
  75
  76         return ret;
  77 };
  78
  79 /*---------------------------------------------------------------------*/
  80
  81 static void tda18271_dump_regs(struct dvb_frontend *fe)
  82 {
  83         struct tda18271_priv *priv = fe->tuner_priv;
  84         unsigned char *regs = priv->tda18271_regs;
  85
  86         dbg_reg("=== TDA18271 REG DUMP ===\n");
  87         dbg_reg("ID_BYTE            = 0x%x\n", 0xff & regs[R_ID]);
  88         dbg_reg("THERMO_BYTE        = 0x%x\n", 0xff & regs[R_TM]);
  89         dbg_reg("POWER_LEVEL_BYTE   = 0x%x\n", 0xff & regs[R_PL]);
  90         dbg_reg("EASY_PROG_BYTE_1   = 0x%x\n", 0xff & regs[R_EP1]);
  91         dbg_reg("EASY_PROG_BYTE_2   = 0x%x\n", 0xff & regs[R_EP2]);
  92         dbg_reg("EASY_PROG_BYTE_3   = 0x%x\n", 0xff & regs[R_EP3]);
  93         dbg_reg("EASY_PROG_BYTE_4   = 0x%x\n", 0xff & regs[R_EP4]);
  94         dbg_reg("EASY_PROG_BYTE_5   = 0x%x\n", 0xff & regs[R_EP5]);
  95         dbg_reg("CAL_POST_DIV_BYTE  = 0x%x\n", 0xff & regs[R_CPD]);
  96         dbg_reg("CAL_DIV_BYTE_1     = 0x%x\n", 0xff & regs[R_CD1]);
  97         dbg_reg("CAL_DIV_BYTE_2     = 0x%x\n", 0xff & regs[R_CD2]);
  98         dbg_reg("CAL_DIV_BYTE_3     = 0x%x\n", 0xff & regs[R_CD3]);
  99         dbg_reg("MAIN_POST_DIV_BYTE = 0x%x\n", 0xff & regs[R_MPD]);
 100         dbg_reg("MAIN_DIV_BYTE_1    = 0x%x\n", 0xff & regs[R_MD1]);
 101         dbg_reg("MAIN_DIV_BYTE_2    = 0x%x\n", 0xff & regs[R_MD2]);
 102         dbg_reg("MAIN_DIV_BYTE_3    = 0x%x\n", 0xff & regs[R_MD3]);
 103 }
 104
 105 static void tda18271_read_regs(struct dvb_frontend *fe)
 106 {
 107         struct tda18271_priv *priv = fe->tuner_priv;
 108         unsigned char *regs = priv->tda18271_regs;
 109         unsigned char buf = 0x00;
 110         int ret;
 111         struct i2c_msg msg[] = {
 112                 { .addr = priv->i2c_addr, .flags = 0,
 113                   .buf = &buf, .len = 1 },
 114                 { .addr = priv->i2c_addr, .flags = I2C_M_RD,
 115                   .buf = regs, .len = 16 }
 116         };
 117
 118         tda18271_i2c_gate_ctrl(fe, 1);
 119
 120         /* read all registers */
 121         ret = i2c_transfer(priv->i2c_adap, msg, 2);
 122
 123         tda18271_i2c_gate_ctrl(fe, 0);
 124
 125         if (ret != 2)
 126                 printk("ERROR: %s: i2c_transfer returned: %d\n",
 127                        __FUNCTION__, ret);
 128
 129         if (tda18271_debug & DBG_REG)
 130                 tda18271_dump_regs(fe);
 131 }
 132
 133 static void tda18271_write_regs(struct dvb_frontend *fe, int idx, int len)
 134 {
 135         struct tda18271_priv *priv = fe->tuner_priv;
 136         unsigned char *regs = priv->tda18271_regs;
 137         unsigned char buf[TDA18271_NUM_REGS+1];
 138         struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0,
 139                                .buf = buf, .len = len+1 };
 140         int i, ret;
 141
 142         BUG_ON((len == 0) || (idx+len > sizeof(buf)));
 143
 144         buf[0] = idx;
 145         for (i = 1; i <= len; i++) {
 146                 buf[i] = regs[idx-1+i];
 147         }
 148
 149         tda18271_i2c_gate_ctrl(fe, 1);
 150
 151         /* write registers */
 152         ret = i2c_transfer(priv->i2c_adap, &msg, 1);
 153
 154         tda18271_i2c_gate_ctrl(fe, 0);
 155
 156         if (ret != 1)
 157                 printk(KERN_WARNING "ERROR: %s: i2c_transfer returned: %d\n",
 158                        __FUNCTION__, ret);
 159 }
 160
 161 /*---------------------------------------------------------------------*/
 162
 163 static int tda18271_init_regs(struct dvb_frontend *fe)
 164 {
 165         struct tda18271_priv *priv = fe->tuner_priv;
 166         unsigned char *regs = priv->tda18271_regs;
 167
 168         printk(KERN_INFO "tda18271: initializing registers\n");
 169
 170         /* initialize registers */
 171         regs[R_ID]   = 0x83;
 172         regs[R_TM]   = 0x08;
 173         regs[R_PL]   = 0x80;
 174         regs[R_EP1]  = 0xc6;
 175         regs[R_EP2]  = 0xdf;
 176         regs[R_EP3]  = 0x16;
 177         regs[R_EP4]  = 0x60;
 178         regs[R_EP5]  = 0x80;
 179         regs[R_CPD]  = 0x80;
 180         regs[R_CD1]  = 0x00;
 181         regs[R_CD2]  = 0x00;
 182         regs[R_CD3]  = 0x00;
 183         regs[R_MPD]  = 0x00;
 184         regs[R_MD1]  = 0x00;
 185         regs[R_MD2]  = 0x00;
 186         regs[R_MD3]  = 0x00;
 187         regs[R_EB1]  = 0xff;
 188         regs[R_EB2]  = 0x01;
 189         regs[R_EB3]  = 0x84;
 190         regs[R_EB4]  = 0x41;
 191         regs[R_EB5]  = 0x01;
 192         regs[R_EB6]  = 0x84;
 193         regs[R_EB7]  = 0x40;
 194         regs[R_EB8]  = 0x07;
 195         regs[R_EB9]  = 0x00;
 196         regs[R_EB10] = 0x00;
 197         regs[R_EB11] = 0x96;
 198         regs[R_EB12] = 0x0f;
 199         regs[R_EB13] = 0xc1;
 200         regs[R_EB14] = 0x00;
 201         regs[R_EB15] = 0x8f;
 202         regs[R_EB16] = 0x00;
 203         regs[R_EB17] = 0x00;
 204         regs[R_EB18] = 0x00;
 205         regs[R_EB19] = 0x00;
 206         regs[R_EB20] = 0x20;
 207         regs[R_EB21] = 0x33;
 208         regs[R_EB22] = 0x48;
 209         regs[R_EB23] = 0xb0;
 210
 211         tda18271_write_regs(fe, 0x00, TDA18271_NUM_REGS);
 212         /* setup AGC1 & AGC2 */
 213         regs[R_EB17] = 0x00;
 214         tda18271_write_regs(fe, R_EB17, 1);
 215         regs[R_EB17] = 0x03;
 216         tda18271_write_regs(fe, R_EB17, 1);
 217         regs[R_EB17] = 0x43;
 218         tda18271_write_regs(fe, R_EB17, 1);
 219         regs[R_EB17] = 0x4c;
 220         tda18271_write_regs(fe, R_EB17, 1);
 221
 222         regs[R_EB20] = 0xa0;
 223         tda18271_write_regs(fe, R_EB20, 1);
 224         regs[R_EB20] = 0xa7;
 225         tda18271_write_regs(fe, R_EB20, 1);
 226         regs[R_EB20] = 0xe7;
 227         tda18271_write_regs(fe, R_EB20, 1);
 228         regs[R_EB20] = 0xec;
 229         tda18271_write_regs(fe, R_EB20, 1);
 230
 231         /* image rejection calibration */
 232
 233         /* low-band */
 234         regs[R_EP3] = 0x1f;
 235         regs[R_EP4] = 0x66;
 236         regs[R_EP5] = 0x81;
 237         regs[R_CPD] = 0xcc;
 238         regs[R_CD1] = 0x6c;
 239         regs[R_CD2] = 0x00;
 240         regs[R_CD3] = 0x00;
 241         regs[R_MPD] = 0xcd;
 242         regs[R_MD1] = 0x77;
 243         regs[R_MD2] = 0x08;
 244         regs[R_MD3] = 0x00;
 245
 246         tda18271_write_regs(fe, R_EP3, 11);
 247         msleep(5); /* pll locking */
 248
 249         regs[R_EP1] = 0xc6;
 250         tda18271_write_regs(fe, R_EP1, 1);
 251         msleep(5); /* wanted low measurement */
 252
 253         regs[R_EP3] = 0x1f;
 254         regs[R_EP4] = 0x66;
 255         regs[R_EP5] = 0x85;
 256         regs[R_CPD] = 0xcb;
 257         regs[R_CD1] = 0x66;
 258         regs[R_CD2] = 0x70;
 259         regs[R_CD3] = 0x00;
 260
 261         tda18271_write_regs(fe, R_EP3, 7);
 262         msleep(5); /* pll locking */
 263
 264         regs[R_EP2] = 0xdf;
 265         tda18271_write_regs(fe, R_EP2, 1);
 266         msleep(30); /* image low optimization completion */
 267
 268         /* mid-band */
 269         regs[R_EP3] = 0x1f;
 270         regs[R_EP4] = 0x66;
 271         regs[R_EP5] = 0x82;
 272         regs[R_CPD] = 0xa8;
 273         regs[R_CD1] = 0x66;
 274         regs[R_CD2] = 0x00;
 275         regs[R_CD3] = 0x00;
 276         regs[R_MPD] = 0xa9;
 277         regs[R_MD1] = 0x73;
 278         regs[R_MD2] = 0x1a;
 279         regs[R_MD3] = 0x00;
 280
 281         tda18271_write_regs(fe, R_EP3, 11);
 282         msleep(5); /* pll locking */
 283
 284         regs[R_EP1] = 0xc6;
 285         tda18271_write_regs(fe, R_EP1, 1);
 286         msleep(5); /* wanted mid measurement */
 287
 288         regs[R_EP3] = 0x1f;
 289         regs[R_EP4] = 0x66;
 290         regs[R_EP5] = 0x86;
 291         regs[R_CPD] = 0xa8;
 292         regs[R_CD1] = 0x66;
 293         regs[R_CD2] = 0xa0;
 294         regs[R_CD3] = 0x00;
 295
 296         tda18271_write_regs(fe, R_EP3, 7);
 297         msleep(5); /* pll locking */
 298
 299         regs[R_EP2] = 0xdf;
 300         tda18271_write_regs(fe, R_EP2, 1);
 301         msleep(30); /* image mid optimization completion */
 302
 303         /* high-band */
 304         regs[R_EP3] = 0x1f;
 305         regs[R_EP4] = 0x66;
 306         regs[R_EP5] = 0x83;
 307         regs[R_CPD] = 0x98;
 308         regs[R_CD1] = 0x65;
 309         regs[R_CD2] = 0x00;
 310         regs[R_CD3] = 0x00;
 311         regs[R_MPD] = 0x99;
 312         regs[R_MD1] = 0x71;
 313         regs[R_MD2] = 0xcd;
 314         regs[R_MD3] = 0x00;
 315
 316         tda18271_write_regs(fe, R_EP3, 11);
 317         msleep(5); /* pll locking */
 318
 319         regs[R_EP1] = 0xc6;
 320         tda18271_write_regs(fe, R_EP1, 1);
 321         msleep(5); /* wanted high measurement */
 322
 323         regs[R_EP3] = 0x1f;
 324         regs[R_EP4] = 0x66;
 325         regs[R_EP5] = 0x87;
 326         regs[R_CPD] = 0x98;
 327         regs[R_CD1] = 0x65;
 328         regs[R_CD2] = 0x50;
 329         regs[R_CD3] = 0x00;
 330
 331         tda18271_write_regs(fe, R_EP3, 7);
 332         msleep(5); /* pll locking */
 333
 334         regs[R_EP2] = 0xdf;
 335
 336         tda18271_write_regs(fe, R_EP2, 1);
 337         msleep(30); /* image high optimization completion */
 338
 339         regs[R_EP4] = 0x64;
 340         tda18271_write_regs(fe, R_EP4, 1);
 341
 342         regs[R_EP1] = 0xc6;
 343         tda18271_write_regs(fe, R_EP1, 1);
 344
 345         return 0;
 346 }
 347
 348 static int tda18271_init(struct dvb_frontend *fe)
 349 {
 350         struct tda18271_priv *priv = fe->tuner_priv;
 351         unsigned char *regs = priv->tda18271_regs;
 352
 353         tda18271_read_regs(fe);
 354
 355         /* test IR_CAL_OK to see if we need init */
 356         if ((regs[R_EP1] & 0x08) == 0)
 357                 tda18271_init_regs(fe);
 358
 359         return 0;
 360 }
 361
 362 static int tda18271_tune(struct dvb_frontend *fe,
 363                          u32 ifc, u32 freq, u32 bw, u8 std)
 364 {
 365         struct tda18271_priv *priv = fe->tuner_priv;
 366         unsigned char *regs = priv->tda18271_regs;
 367         u32 div, N = 0;
 368         int i;
 369
 370         tda18271_init(fe);
 371
 372         dbg_info("freq = %d, ifc = %d\n", freq, ifc);
 373
 374         /* RF tracking filter calibration */
 375
 376         /* calculate BP_Filter */
 377         i = 0;
 378         while ((tda18271_bp_filter[i].rfmax * 1000) < freq) {
 379                 if (tda18271_bp_filter[i + 1].rfmax == 0)
 380                         break;
 381                 i++;
 382         }
 383         dbg_map("bp filter = 0x%x, i = %d\n", tda18271_bp_filter[i].val, i);
 384
 385         regs[R_EP1]  &= ~0x07; /* clear bp filter bits */
 386         regs[R_EP1]  |= tda18271_bp_filter[i].val;
 387         tda18271_write_regs(fe, R_EP1, 1);
 388
 389         regs[R_EB4]  &= 0x07;
 390         regs[R_EB4]  |= 0x60;
 391         tda18271_write_regs(fe, R_EB4, 1);
 392
 393         regs[R_EB7]   = 0x60;
 394         tda18271_write_regs(fe, R_EB7, 1);
 395
 396         regs[R_EB14]  = 0x00;
 397         tda18271_write_regs(fe, R_EB14, 1);
 398
 399         regs[R_EB20]  = 0xcc;
 400         tda18271_write_regs(fe, R_EB20, 1);
 401
 402         /* set CAL mode to RF tracking filter calibration */
 403         regs[R_EB4]  |= 0x03;
 404
 405         /* calculate CAL PLL */
 406
 407         switch (priv->mode) {
 408         case TDA18271_ANALOG:
 409                 N = freq - 1250000;
 410                 break;
 411         case TDA18271_DIGITAL:
 412                 N = freq + bw / 2;
 413                 break;
 414         }
 415
 416         i = 0;
 417         while ((tda18271_cal_pll[i].lomax * 1000) < N) {
 418                 if (tda18271_cal_pll[i + 1].lomax == 0)
 419                         break;
 420                 i++;
 421         }
 422         dbg_map("cal pll, pd = 0x%x, d = 0x%x, i = %d\n",
 423                 tda18271_cal_pll[i].pd, tda18271_cal_pll[i].d, i);
 424
 425         regs[R_CPD]   = tda18271_cal_pll[i].pd;
 426
 427         div =  ((tda18271_cal_pll[i].d * (N / 1000)) << 7) / 125;
 428         regs[R_CD1]   = 0xff & (div >> 16);
 429         regs[R_CD2]   = 0xff & (div >> 8);
 430         regs[R_CD3]   = 0xff & div;
 431
 432         /* calculate MAIN PLL */
 433
 434         switch (priv->mode) {
 435         case TDA18271_ANALOG:
 436                 N = freq - 250000;
 437                 break;
 438         case TDA18271_DIGITAL:
 439                 N = freq + bw / 2 + 1000000;
 440                 break;
 441         }
 442
 443         i = 0;
 444         while ((tda18271_main_pll[i].lomax * 1000) < N) {
 445                 if (tda18271_main_pll[i + 1].lomax == 0)
 446                         break;
 447                 i++;
 448         }
 449         dbg_map("main pll, pd = 0x%x, d = 0x%x, i = %d\n",
 450                 tda18271_main_pll[i].pd, tda18271_main_pll[i].d, i);
 451
 452         regs[R_MPD]   = (0x7f & tda18271_main_pll[i].pd);
 453
 454         switch (priv->mode) {
 455         case TDA18271_ANALOG:
 456                 regs[R_MPD]  &= ~0x08;
 457                 break;
 458         case TDA18271_DIGITAL:
 459                 regs[R_MPD]  |=  0x08;
 460                 break;
 461         }
 462
 463         div =  ((tda18271_main_pll[i].d * (N / 1000)) << 7) / 125;
 464         regs[R_MD1]   = 0xff & (div >> 16);
 465         regs[R_MD2]   = 0xff & (div >> 8);
 466         regs[R_MD3]   = 0xff & div;
 467
 468         tda18271_write_regs(fe, R_EP3, 11);
 469         msleep(5); /* RF tracking filter calibration initialization */
 470
 471         /* search for K,M,CO for RF Calibration */
 472         i = 0;
 473         while ((tda18271_km[i].rfmax * 1000) < freq) {
 474                 if (tda18271_km[i + 1].rfmax == 0)
 475                         break;
 476                 i++;
 477         }
 478         dbg_map("km = 0x%x, i = %d\n", tda18271_km[i].val, i);
 479
 480         regs[R_EB13] &= 0x83;
 481         regs[R_EB13] |= tda18271_km[i].val;
 482         tda18271_write_regs(fe, R_EB13, 1);
 483
 484         /* search for RF_BAND */
 485         i = 0;
 486         while ((tda18271_rf_band[i].rfmax * 1000) < freq) {
 487                 if (tda18271_rf_band[i + 1].rfmax == 0)
 488                         break;
 489                 i++;
 490         }
 491         dbg_map("rf band = 0x%x, i = %d\n", tda18271_rf_band[i].val, i);
 492
 493         regs[R_EP2]  &= ~0xe0; /* clear rf band bits */
 494         regs[R_EP2]  |= (tda18271_rf_band[i].val << 5);
 495
 496         /* search for Gain_Taper */
 497         i = 0;
 498         while ((tda18271_gain_taper[i].rfmax * 1000) < freq) {
 499                 if (tda18271_gain_taper[i + 1].rfmax == 0)
 500                         break;
 501                 i++;
 502         }
 503         dbg_map("gain taper = 0x%x, i = %d\n",
 504                 tda18271_gain_taper[i].val, i);
 505
 506         regs[R_EP2]  &= ~0x1f; /* clear gain taper bits */
 507         regs[R_EP2]  |= tda18271_gain_taper[i].val;
 508
 509         tda18271_write_regs(fe, R_EP2, 1);
 510         tda18271_write_regs(fe, R_EP1, 1);
 511         tda18271_write_regs(fe, R_EP2, 1);
 512         tda18271_write_regs(fe, R_EP1, 1);
 513
 514         regs[R_EB4]  &= 0x07;
 515         regs[R_EB4]  |= 0x40;
 516         tda18271_write_regs(fe, R_EB4, 1);
 517
 518         regs[R_EB7]   = 0x40;
 519         tda18271_write_regs(fe, R_EB7, 1);
 520         msleep(10);
 521
 522         regs[R_EB20]  = 0xec;
 523         tda18271_write_regs(fe, R_EB20, 1);
 524         msleep(60); /* RF tracking filter calibration completion */
 525
 526         regs[R_EP4]  &= ~0x03; /* set cal mode to normal */
 527         tda18271_write_regs(fe, R_EP4, 1);
 528
 529         tda18271_write_regs(fe, R_EP1, 1);
 530
 531         /* RF tracking filer correction for VHF_Low band */
 532         i = 0;
 533         while ((tda18271_rf_cal[i].rfmax * 1000) < freq) {
 534                 if (tda18271_rf_cal[i].rfmax == 0)
 535                         break;
 536                 i++;
 537         }
 538         dbg_map("rf cal = 0x%x, i = %d\n", tda18271_rf_cal[i].val, i);
 539
 540         /* VHF_Low band only */
 541         if (tda18271_rf_cal[i].rfmax != 0) {
 542                 regs[R_EB14]   = tda18271_rf_cal[i].val;
 543                 tda18271_write_regs(fe, R_EB14, 1);
 544         }
 545
 546         /* Channel Configuration */
 547
 548         switch (priv->mode) {
 549         case TDA18271_ANALOG:
 550                 regs[R_EB22]  = 0x2c;
 551                 break;
 552         case TDA18271_DIGITAL:
 553                 regs[R_EB22]  = 0x37;
 554                 break;
 555         }
 556         tda18271_write_regs(fe, R_EB22, 1);
 557
 558         regs[R_EP1]  |= 0x40; /* set dis power level on */
 559
 560         /* set standard */
 561         regs[R_EP3]  &= ~0x1f; /* clear std bits */
 562
 563         /* see table 22 */
 564         regs[R_EP3]  |= std;
 565
 566         regs[R_EP4]  &= ~0x03; /* set cal mode to normal */
 567
 568         regs[R_EP4]  &= ~0x1c; /* clear if level bits */
 569         switch (priv->mode) {
 570         case TDA18271_ANALOG:
 571                 regs[R_MPD]  &= ~0x80; /* IF notch = 0 */
 572                 break;
 573         case TDA18271_DIGITAL:
 574                 regs[R_EP4]  |= 0x04;
 575                 regs[R_MPD]  |= 0x80;
 576                 break;
 577         }
 578
 579         regs[R_EP4]  &= ~0x80; /* turn this bit on only for fm */
 580
 581         /* image rejection validity EP5[2:0] */
 582         i = 0;
 583         while ((tda18271_ir_measure[i].rfmax * 1000) < freq) {
 584                 if (tda18271_ir_measure[i].rfmax == 0)
 585                         break;
 586                 i++;
 587         }
 588         dbg_map("ir measure, i = %d\n", i);
 589         regs[R_EP5] &= ~0x07;
 590         regs[R_EP5] |= tda18271_ir_measure[i].val;
 591
 592         /* calculate MAIN PLL */
 593         N = freq + ifc;
 594
 595         i = 0;
 596         while ((tda18271_main_pll[i].lomax * 1000) < N) {
 597                 if (tda18271_main_pll[i + 1].lomax == 0)
 598                         break;
 599                 i++;
 600         }
 601         dbg_map("main pll, pd = 0x%x, d = 0x%x, i = %d\n",
 602                 tda18271_main_pll[i].pd, tda18271_main_pll[i].d, i);
 603
 604         regs[R_MPD]   = (0x7f & tda18271_main_pll[i].pd);
 605         switch (priv->mode) {
 606         case TDA18271_ANALOG:
 607                 regs[R_MPD]  &= ~0x08;
 608                 break;
 609         case TDA18271_DIGITAL:
 610                 regs[R_MPD]  |= 0x08;
 611                 break;
 612         }
 613
 614         div =  ((tda18271_main_pll[i].d * (N / 1000)) << 7) / 125;
 615         regs[R_MD1]   = 0xff & (div >> 16);
 616         regs[R_MD2]   = 0xff & (div >> 8);
 617         regs[R_MD3]   = 0xff & div;
 618
 619         tda18271_write_regs(fe, R_TM, 15);
 620         msleep(5);
 621
 622         return 0;
 623 }
 624
 625 /* ------------------------------------------------------------------ */
 626
 627 static int tda18271_set_params(struct dvb_frontend *fe,
 628                                struct dvb_frontend_parameters *params)
 629 {
 630         struct tda18271_priv *priv = fe->tuner_priv;
 631         u8 std;
 632         u32 bw, sgIF = 0;
 633
 634         u32 freq = params->frequency;
 635
 636         priv->mode = TDA18271_DIGITAL;
 637
 638         /* see table 22 */
 639         if (fe->ops.info.type == FE_ATSC) {
 640                 switch (params->u.vsb.modulation) {
 641                 case VSB_8:
 642                 case VSB_16:
 643                         std = 0x1b; /* device-specific (spec says 0x1c) */
 644                         sgIF = 5380000;
 645                         break;
 646                 case QAM_64:
 647                 case QAM_256:
 648                         std = 0x18; /* device-specific (spec says 0x1d) */
 649                         sgIF = 4000000;
 650                         break;
 651                 default:
 652                         printk(KERN_WARNING "%s: modulation not set!\n",
 653                                __FUNCTION__);
 654                         return -EINVAL;
 655                 }
 656                 freq += 1750000; /* Adjust to center (+1.75MHZ) */
 657                 bw = 6000000;
 658         } else if (fe->ops.info.type == FE_OFDM) {
 659                 switch (params->u.ofdm.bandwidth) {
 660                 case BANDWIDTH_6_MHZ:
 661                         std = 0x1b; /* device-specific (spec says 0x1c) */
 662                         bw = 6000000;
 663                         sgIF = 3300000;
 664                         break;
 665                 case BANDWIDTH_7_MHZ:
 666                         std = 0x19; /* device-specific (spec says 0x1d) */
 667                         bw = 7000000;
 668                         sgIF = 3800000;
 669                         break;
 670                 case BANDWIDTH_8_MHZ:
 671                         std = 0x1a; /* device-specific (spec says 0x1e) */
 672                         bw = 8000000;
 673                         sgIF = 4300000;
 674                         break;
 675                 default:
 676                         printk(KERN_WARNING "%s: bandwidth not set!\n",
 677                                __FUNCTION__);
 678                         return -EINVAL;
 679                 }
 680         } else {
 681                 printk(KERN_WARNING "%s: modulation type not supported!\n",
 682                        __FUNCTION__);
 683                 return -EINVAL;
 684         }
 685
 686         return tda18271_tune(fe, sgIF, freq, bw, std);
 687 }
 688
 689 static int tda18271_set_analog_params(struct dvb_frontend *fe,
 690                                       struct analog_parameters *params)
 691 {
 692         struct tda18271_priv *priv = fe->tuner_priv;
 693         u8 std;
 694         unsigned int sgIF;
 695         char *mode;
 696
 697         priv->mode = TDA18271_ANALOG;
 698
 699         /* see table 22 */
 700         if (params->std & V4L2_STD_MN) {
 701                 std = 0x0d;
 702                 sgIF =  92;
 703                 mode = "MN";
 704         } else if (params->std & V4L2_STD_B) {
 705                 std = 0x0e;
 706                 sgIF =  108;
 707                 mode = "B";
 708         } else if (params->std & V4L2_STD_GH) {
 709                 std = 0x0f;
 710                 sgIF =  124;
 711                 mode = "GH";
 712         } else if (params->std & V4L2_STD_PAL_I) {
 713                 std = 0x0f;
 714                 sgIF =  124;
 715                 mode = "I";
 716         } else if (params->std & V4L2_STD_DK) {
 717                 std = 0x0f;
 718                 sgIF =  124;
 719                 mode = "DK";
 720         } else if (params->std & V4L2_STD_SECAM_L) {
 721                 std = 0x0f;
 722                 sgIF =  124;
 723                 mode = "L";
 724         } else if (params->std & V4L2_STD_SECAM_LC) {
 725                 std = 0x0f;
 726                 sgIF =  20;
 727                 mode = "LC";
 728         } else {
 729                 std = 0x0f;
 730                 sgIF =  124;
 731                 mode = "xx";
 732         }
 733
 734         if (params->mode == V4L2_TUNER_RADIO)
 735                 sgIF =  88; /* if frequency is 5.5 MHz */
 736
 737         dbg_info("setting tda18271 to system %s\n", mode);
 738
 739         return tda18271_tune(fe, sgIF * 62500, params->frequency * 62500,
 740                              0, std);
 741 }
 742
 743 static int tda18271_release(struct dvb_frontend *fe)
 744 {
 745         kfree(fe->tuner_priv);
 746         fe->tuner_priv = NULL;
 747         return 0;
 748 }
 749
 750 static int tda18271_get_frequency(struct dvb_frontend *fe, u32 *frequency)
 751 {
 752         struct tda18271_priv *priv = fe->tuner_priv;
 753         *frequency = priv->frequency;
 754         return 0;
 755 }
 756
 757 static int tda18271_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
 758 {
 759         struct tda18271_priv *priv = fe->tuner_priv;
 760         *bandwidth = priv->bandwidth;
 761         return 0;
 762 }
 763
 764 static struct dvb_tuner_ops tda18271_tuner_ops = {
 765         .info = {
 766                 .name = "NXP TDA18271HD",
 767                 .frequency_min  =  45000000,
 768                 .frequency_max  = 864000000,
 769                 .frequency_step =     62500
 770         },
 771         .init              = tda18271_init,
 772         .set_params        = tda18271_set_params,
 773         .set_analog_params = tda18271_set_analog_params,
 774         .release           = tda18271_release,
 775         .get_frequency     = tda18271_get_frequency,
 776         .get_bandwidth     = tda18271_get_bandwidth,
 777 };
 778
 779 struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe, u8 addr,
 780                                      struct i2c_adapter *i2c)
 781 {
 782         struct tda18271_priv *priv = NULL;
 783
 784         dbg_info("@ %d-%04x\n", i2c_adapter_id(i2c), addr);
 785         priv = kzalloc(sizeof(struct tda18271_priv), GFP_KERNEL);
 786         if (priv == NULL)
 787                 return NULL;
 788
 789         priv->i2c_addr = addr;
 790         priv->i2c_adap = i2c;
 791
 792         memcpy(&fe->ops.tuner_ops, &tda18271_tuner_ops,
 793                sizeof(struct dvb_tuner_ops));
 794
 795         fe->tuner_priv = priv;
 796
 797         tda18271_init_regs(fe);
 798
 799         return fe;
 800 }
 801 EXPORT_SYMBOL_GPL(tda18271_attach);
 802 MODULE_DESCRIPTION("NXP TDA18271HD analog / digital tuner driver");
 803 MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
 804 MODULE_LICENSE("GPL");
 805
 806 /*
 807  * Overrides for Emacs so that we follow Linus's tabbing style.
 808  * ---------------------------------------------------------------------------
 809  * Local variables:
 810  * c-basic-offset: 8
 811  * End:
 812  */