err.no Git - linux-2.6/blob - drivers/media/dvb/frontends/tda18271-fe.c

   1 /*
   2     tda18271-fe.c - driver for the Philips / NXP TDA18271 silicon tuner
   3
   4     Copyright (C) 2007 Michael Krufky (mkrufky@linuxtv.org)
   5
   6     This program is free software; you can redistribute it and/or modify
   7     it under the terms of the GNU General Public License as published by
   8     the Free Software Foundation; either version 2 of the License, or
   9     (at your option) any later version.
  10
  11     This program is distributed in the hope that it will be useful,
  12     but WITHOUT ANY WARRANTY; without even the implied warranty of
  13     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14     GNU General Public License for more details.
  15
  16     You should have received a copy of the GNU General Public License
  17     along with this program; if not, write to the Free Software
  18     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19 */
  20
  21 #include <linux/delay.h>
  22 #include <linux/videodev2.h>
  23
  24 #include "tda18271.h"
  25 #include "tda18271-priv.h"
  26
  27 int tda18271_debug;
  28 module_param_named(debug, tda18271_debug, int, 0644);
  29 MODULE_PARM_DESC(debug, "set debug level (info=1, map=2, reg=4 (or-able))");
  30
  31 /*---------------------------------------------------------------------*/
  32
  33 enum tda18271_mode {
  34         TDA18271_ANALOG,
  35         TDA18271_DIGITAL,
  36 };
  37
  38 struct tda18271_priv {
  39         u8 i2c_addr;
  40         struct i2c_adapter *i2c_adap;
  41         unsigned char tda18271_regs[TDA18271_NUM_REGS];
  42
  43         enum tda18271_mode mode;
  44         enum tda18271_i2c_gate gate;
  45
  46         u32 frequency;
  47         u32 bandwidth;
  48 };
  49
  50 static int tda18271_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
  51 {
  52         struct tda18271_priv *priv = fe->tuner_priv;
  53         enum tda18271_i2c_gate gate;
  54         int ret = 0;
  55
  56         switch (priv->gate) {
  57         case TDA18271_GATE_DIGITAL:
  58         case TDA18271_GATE_ANALOG:
  59                 gate = priv->gate;
  60                 break;
  61         case TDA18271_GATE_AUTO:
  62         default:
  63                 switch (priv->mode) {
  64                 case TDA18271_DIGITAL:
  65                         gate = TDA18271_GATE_DIGITAL;
  66                         break;
  67                 case TDA18271_ANALOG:
  68                 default:
  69                         gate = TDA18271_GATE_ANALOG;
  70                         break;
  71                 }
  72         }
  73
  74         switch (gate) {
  75         case TDA18271_GATE_ANALOG:
  76                 if (fe->ops.analog_ops.i2c_gate_ctrl)
  77                         ret = fe->ops.analog_ops.i2c_gate_ctrl(fe, enable);
  78                 break;
  79         case TDA18271_GATE_DIGITAL:
  80                 if (fe->ops.i2c_gate_ctrl)
  81                         ret = fe->ops.i2c_gate_ctrl(fe, enable);
  82                 break;
  83         default:
  84                 ret = -EINVAL;
  85                 break;
  86         }
  87
  88         return ret;
  89 };
  90
  91 /*---------------------------------------------------------------------*/
  92
  93 static void tda18271_dump_regs(struct dvb_frontend *fe)
  94 {
  95         struct tda18271_priv *priv = fe->tuner_priv;
  96         unsigned char *regs = priv->tda18271_regs;
  97
  98         dbg_reg("=== TDA18271 REG DUMP ===\n");
  99         dbg_reg("ID_BYTE            = 0x%02x\n", 0xff & regs[R_ID]);
 100         dbg_reg("THERMO_BYTE        = 0x%02x\n", 0xff & regs[R_TM]);
 101         dbg_reg("POWER_LEVEL_BYTE   = 0x%02x\n", 0xff & regs[R_PL]);
 102         dbg_reg("EASY_PROG_BYTE_1   = 0x%02x\n", 0xff & regs[R_EP1]);
 103         dbg_reg("EASY_PROG_BYTE_2   = 0x%02x\n", 0xff & regs[R_EP2]);
 104         dbg_reg("EASY_PROG_BYTE_3   = 0x%02x\n", 0xff & regs[R_EP3]);
 105         dbg_reg("EASY_PROG_BYTE_4   = 0x%02x\n", 0xff & regs[R_EP4]);
 106         dbg_reg("EASY_PROG_BYTE_5   = 0x%02x\n", 0xff & regs[R_EP5]);
 107         dbg_reg("CAL_POST_DIV_BYTE  = 0x%02x\n", 0xff & regs[R_CPD]);
 108         dbg_reg("CAL_DIV_BYTE_1     = 0x%02x\n", 0xff & regs[R_CD1]);
 109         dbg_reg("CAL_DIV_BYTE_2     = 0x%02x\n", 0xff & regs[R_CD2]);
 110         dbg_reg("CAL_DIV_BYTE_3     = 0x%02x\n", 0xff & regs[R_CD3]);
 111         dbg_reg("MAIN_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_MPD]);
 112         dbg_reg("MAIN_DIV_BYTE_1    = 0x%02x\n", 0xff & regs[R_MD1]);
 113         dbg_reg("MAIN_DIV_BYTE_2    = 0x%02x\n", 0xff & regs[R_MD2]);
 114         dbg_reg("MAIN_DIV_BYTE_3    = 0x%02x\n", 0xff & regs[R_MD3]);
 115 }
 116
 117 static void tda18271_read_regs(struct dvb_frontend *fe)
 118 {
 119         struct tda18271_priv *priv = fe->tuner_priv;
 120         unsigned char *regs = priv->tda18271_regs;
 121         unsigned char buf = 0x00;
 122         int ret;
 123         struct i2c_msg msg[] = {
 124                 { .addr = priv->i2c_addr, .flags = 0,
 125                   .buf = &buf, .len = 1 },
 126                 { .addr = priv->i2c_addr, .flags = I2C_M_RD,
 127                   .buf = regs, .len = 16 }
 128         };
 129
 130         tda18271_i2c_gate_ctrl(fe, 1);
 131
 132         /* read all registers */
 133         ret = i2c_transfer(priv->i2c_adap, msg, 2);
 134
 135         tda18271_i2c_gate_ctrl(fe, 0);
 136
 137         if (ret != 2)
 138                 printk("ERROR: %s: i2c_transfer returned: %d\n",
 139                        __FUNCTION__, ret);
 140
 141         if (tda18271_debug & DBG_REG)
 142                 tda18271_dump_regs(fe);
 143 }
 144
 145 static void tda18271_write_regs(struct dvb_frontend *fe, int idx, int len)
 146 {
 147         struct tda18271_priv *priv = fe->tuner_priv;
 148         unsigned char *regs = priv->tda18271_regs;
 149         unsigned char buf[TDA18271_NUM_REGS+1];
 150         struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0,
 151                                .buf = buf, .len = len+1 };
 152         int i, ret;
 153
 154         BUG_ON((len == 0) || (idx+len > sizeof(buf)));
 155
 156         buf[0] = idx;
 157         for (i = 1; i <= len; i++) {
 158                 buf[i] = regs[idx-1+i];
 159         }
 160
 161         tda18271_i2c_gate_ctrl(fe, 1);
 162
 163         /* write registers */
 164         ret = i2c_transfer(priv->i2c_adap, &msg, 1);
 165
 166         tda18271_i2c_gate_ctrl(fe, 0);
 167
 168         if (ret != 1)
 169                 printk(KERN_WARNING "ERROR: %s: i2c_transfer returned: %d\n",
 170                        __FUNCTION__, ret);
 171 }
 172
 173 /*---------------------------------------------------------------------*/
 174
 175 static int tda18271_init_regs(struct dvb_frontend *fe)
 176 {
 177         struct tda18271_priv *priv = fe->tuner_priv;
 178         unsigned char *regs = priv->tda18271_regs;
 179
 180         printk(KERN_INFO "tda18271: initializing registers\n");
 181
 182         /* initialize registers */
 183         regs[R_ID]   = 0x83;
 184         regs[R_TM]   = 0x08;
 185         regs[R_PL]   = 0x80;
 186         regs[R_EP1]  = 0xc6;
 187         regs[R_EP2]  = 0xdf;
 188         regs[R_EP3]  = 0x16;
 189         regs[R_EP4]  = 0x60;
 190         regs[R_EP5]  = 0x80;
 191         regs[R_CPD]  = 0x80;
 192         regs[R_CD1]  = 0x00;
 193         regs[R_CD2]  = 0x00;
 194         regs[R_CD3]  = 0x00;
 195         regs[R_MPD]  = 0x00;
 196         regs[R_MD1]  = 0x00;
 197         regs[R_MD2]  = 0x00;
 198         regs[R_MD3]  = 0x00;
 199         regs[R_EB1]  = 0xff;
 200         regs[R_EB2]  = 0x01;
 201         regs[R_EB3]  = 0x84;
 202         regs[R_EB4]  = 0x41;
 203         regs[R_EB5]  = 0x01;
 204         regs[R_EB6]  = 0x84;
 205         regs[R_EB7]  = 0x40;
 206         regs[R_EB8]  = 0x07;
 207         regs[R_EB9]  = 0x00;
 208         regs[R_EB10] = 0x00;
 209         regs[R_EB11] = 0x96;
 210         regs[R_EB12] = 0x0f;
 211         regs[R_EB13] = 0xc1;
 212         regs[R_EB14] = 0x00;
 213         regs[R_EB15] = 0x8f;
 214         regs[R_EB16] = 0x00;
 215         regs[R_EB17] = 0x00;
 216         regs[R_EB18] = 0x00;
 217         regs[R_EB19] = 0x00;
 218         regs[R_EB20] = 0x20;
 219         regs[R_EB21] = 0x33;
 220         regs[R_EB22] = 0x48;
 221         regs[R_EB23] = 0xb0;
 222
 223         tda18271_write_regs(fe, 0x00, TDA18271_NUM_REGS);
 224         /* setup AGC1 & AGC2 */
 225         regs[R_EB17] = 0x00;
 226         tda18271_write_regs(fe, R_EB17, 1);
 227         regs[R_EB17] = 0x03;
 228         tda18271_write_regs(fe, R_EB17, 1);
 229         regs[R_EB17] = 0x43;
 230         tda18271_write_regs(fe, R_EB17, 1);
 231         regs[R_EB17] = 0x4c;
 232         tda18271_write_regs(fe, R_EB17, 1);
 233
 234         regs[R_EB20] = 0xa0;
 235         tda18271_write_regs(fe, R_EB20, 1);
 236         regs[R_EB20] = 0xa7;
 237         tda18271_write_regs(fe, R_EB20, 1);
 238         regs[R_EB20] = 0xe7;
 239         tda18271_write_regs(fe, R_EB20, 1);
 240         regs[R_EB20] = 0xec;
 241         tda18271_write_regs(fe, R_EB20, 1);
 242
 243         /* image rejection calibration */
 244
 245         /* low-band */
 246         regs[R_EP3] = 0x1f;
 247         regs[R_EP4] = 0x66;
 248         regs[R_EP5] = 0x81;
 249         regs[R_CPD] = 0xcc;
 250         regs[R_CD1] = 0x6c;
 251         regs[R_CD2] = 0x00;
 252         regs[R_CD3] = 0x00;
 253         regs[R_MPD] = 0xcd;
 254         regs[R_MD1] = 0x77;
 255         regs[R_MD2] = 0x08;
 256         regs[R_MD3] = 0x00;
 257
 258         tda18271_write_regs(fe, R_EP3, 11);
 259         msleep(5); /* pll locking */
 260
 261         regs[R_EP1] = 0xc6;
 262         tda18271_write_regs(fe, R_EP1, 1);
 263         msleep(5); /* wanted low measurement */
 264
 265         regs[R_EP3] = 0x1f;
 266         regs[R_EP4] = 0x66;
 267         regs[R_EP5] = 0x85;
 268         regs[R_CPD] = 0xcb;
 269         regs[R_CD1] = 0x66;
 270         regs[R_CD2] = 0x70;
 271         regs[R_CD3] = 0x00;
 272
 273         tda18271_write_regs(fe, R_EP3, 7);
 274         msleep(5); /* pll locking */
 275
 276         regs[R_EP2] = 0xdf;
 277         tda18271_write_regs(fe, R_EP2, 1);
 278         msleep(30); /* image low optimization completion */
 279
 280         /* mid-band */
 281         regs[R_EP3] = 0x1f;
 282         regs[R_EP4] = 0x66;
 283         regs[R_EP5] = 0x82;
 284         regs[R_CPD] = 0xa8;
 285         regs[R_CD1] = 0x66;
 286         regs[R_CD2] = 0x00;
 287         regs[R_CD3] = 0x00;
 288         regs[R_MPD] = 0xa9;
 289         regs[R_MD1] = 0x73;
 290         regs[R_MD2] = 0x1a;
 291         regs[R_MD3] = 0x00;
 292
 293         tda18271_write_regs(fe, R_EP3, 11);
 294         msleep(5); /* pll locking */
 295
 296         regs[R_EP1] = 0xc6;
 297         tda18271_write_regs(fe, R_EP1, 1);
 298         msleep(5); /* wanted mid measurement */
 299
 300         regs[R_EP3] = 0x1f;
 301         regs[R_EP4] = 0x66;
 302         regs[R_EP5] = 0x86;
 303         regs[R_CPD] = 0xa8;
 304         regs[R_CD1] = 0x66;
 305         regs[R_CD2] = 0xa0;
 306         regs[R_CD3] = 0x00;
 307
 308         tda18271_write_regs(fe, R_EP3, 7);
 309         msleep(5); /* pll locking */
 310
 311         regs[R_EP2] = 0xdf;
 312         tda18271_write_regs(fe, R_EP2, 1);
 313         msleep(30); /* image mid optimization completion */
 314
 315         /* high-band */
 316         regs[R_EP3] = 0x1f;
 317         regs[R_EP4] = 0x66;
 318         regs[R_EP5] = 0x83;
 319         regs[R_CPD] = 0x98;
 320         regs[R_CD1] = 0x65;
 321         regs[R_CD2] = 0x00;
 322         regs[R_CD3] = 0x00;
 323         regs[R_MPD] = 0x99;
 324         regs[R_MD1] = 0x71;
 325         regs[R_MD2] = 0xcd;
 326         regs[R_MD3] = 0x00;
 327
 328         tda18271_write_regs(fe, R_EP3, 11);
 329         msleep(5); /* pll locking */
 330
 331         regs[R_EP1] = 0xc6;
 332         tda18271_write_regs(fe, R_EP1, 1);
 333         msleep(5); /* wanted high measurement */
 334
 335         regs[R_EP3] = 0x1f;
 336         regs[R_EP4] = 0x66;
 337         regs[R_EP5] = 0x87;
 338         regs[R_CPD] = 0x98;
 339         regs[R_CD1] = 0x65;
 340         regs[R_CD2] = 0x50;
 341         regs[R_CD3] = 0x00;
 342
 343         tda18271_write_regs(fe, R_EP3, 7);
 344         msleep(5); /* pll locking */
 345
 346         regs[R_EP2] = 0xdf;
 347
 348         tda18271_write_regs(fe, R_EP2, 1);
 349         msleep(30); /* image high optimization completion */
 350
 351         regs[R_EP4] = 0x64;
 352         tda18271_write_regs(fe, R_EP4, 1);
 353
 354         regs[R_EP1] = 0xc6;
 355         tda18271_write_regs(fe, R_EP1, 1);
 356
 357         return 0;
 358 }
 359
 360 static int tda18271_init(struct dvb_frontend *fe)
 361 {
 362         struct tda18271_priv *priv = fe->tuner_priv;
 363         unsigned char *regs = priv->tda18271_regs;
 364
 365         tda18271_read_regs(fe);
 366
 367         /* test IR_CAL_OK to see if we need init */
 368         if ((regs[R_EP1] & 0x08) == 0)
 369                 tda18271_init_regs(fe);
 370
 371         return 0;
 372 }
 373
 374 static int tda18271_tune(struct dvb_frontend *fe,
 375                          u32 ifc, u32 freq, u32 bw, u8 std)
 376 {
 377         struct tda18271_priv *priv = fe->tuner_priv;
 378         unsigned char *regs = priv->tda18271_regs;
 379         u32 div, N = 0;
 380         u8 d, pd, val;
 381
 382         tda18271_init(fe);
 383
 384         dbg_info("freq = %d, ifc = %d\n", freq, ifc);
 385
 386         /* RF tracking filter calibration */
 387
 388         /* calculate BP_Filter */
 389         tda18271_calc_bp_filter(&freq, &val);
 390
 391         regs[R_EP1]  &= ~0x07; /* clear bp filter bits */
 392         regs[R_EP1]  |= val;
 393         tda18271_write_regs(fe, R_EP1, 1);
 394
 395         regs[R_EB4]  &= 0x07;
 396         regs[R_EB4]  |= 0x60;
 397         tda18271_write_regs(fe, R_EB4, 1);
 398
 399         regs[R_EB7]   = 0x60;
 400         tda18271_write_regs(fe, R_EB7, 1);
 401
 402         regs[R_EB14]  = 0x00;
 403         tda18271_write_regs(fe, R_EB14, 1);
 404
 405         regs[R_EB20]  = 0xcc;
 406         tda18271_write_regs(fe, R_EB20, 1);
 407
 408         /* set CAL mode to RF tracking filter calibration */
 409         regs[R_EB4]  |= 0x03;
 410
 411         /* calculate CAL PLL */
 412
 413         switch (priv->mode) {
 414         case TDA18271_ANALOG:
 415                 N = freq - 1250000;
 416                 break;
 417         case TDA18271_DIGITAL:
 418                 N = freq + bw / 2;
 419                 break;
 420         }
 421
 422         tda18271_calc_cal_pll(&N, &pd, &d);
 423
 424         regs[R_CPD]   = pd;
 425
 426         div =  ((d * (N / 1000)) << 7) / 125;
 427         regs[R_CD1]   = 0xff & (div >> 16);
 428         regs[R_CD2]   = 0xff & (div >> 8);
 429         regs[R_CD3]   = 0xff & div;
 430
 431         /* calculate MAIN PLL */
 432
 433         switch (priv->mode) {
 434         case TDA18271_ANALOG:
 435                 N = freq - 250000;
 436                 break;
 437         case TDA18271_DIGITAL:
 438                 N = freq + bw / 2 + 1000000;
 439                 break;
 440         }
 441
 442         tda18271_calc_main_pll(&N, &pd, &d);
 443
 444         regs[R_MPD]   = (0x7f & pd);
 445
 446         switch (priv->mode) {
 447         case TDA18271_ANALOG:
 448                 regs[R_MPD]  &= ~0x08;
 449                 break;
 450         case TDA18271_DIGITAL:
 451                 regs[R_MPD]  |=  0x08;
 452                 break;
 453         }
 454
 455         div =  ((d * (N / 1000)) << 7) / 125;
 456         regs[R_MD1]   = 0xff & (div >> 16);
 457         regs[R_MD2]   = 0xff & (div >> 8);
 458         regs[R_MD3]   = 0xff & div;
 459
 460         tda18271_write_regs(fe, R_EP3, 11);
 461         msleep(5); /* RF tracking filter calibration initialization */
 462
 463         /* search for K,M,CO for RF Calibration */
 464         tda18271_calc_km(&freq, &val);
 465
 466         regs[R_EB13] &= 0x83;
 467         regs[R_EB13] |= val;
 468         tda18271_write_regs(fe, R_EB13, 1);
 469
 470         /* search for RF_BAND */
 471         tda18271_calc_rf_band(&freq, &val);
 472
 473         regs[R_EP2]  &= ~0xe0; /* clear rf band bits */
 474         regs[R_EP2]  |= (val << 5);
 475
 476         /* search for Gain_Taper */
 477         tda18271_calc_gain_taper(&freq, &val);
 478
 479         regs[R_EP2]  &= ~0x1f; /* clear gain taper bits */
 480         regs[R_EP2]  |= val;
 481
 482         tda18271_write_regs(fe, R_EP2, 1);
 483         tda18271_write_regs(fe, R_EP1, 1);
 484         tda18271_write_regs(fe, R_EP2, 1);
 485         tda18271_write_regs(fe, R_EP1, 1);
 486
 487         regs[R_EB4]  &= 0x07;
 488         regs[R_EB4]  |= 0x40;
 489         tda18271_write_regs(fe, R_EB4, 1);
 490
 491         regs[R_EB7]   = 0x40;
 492         tda18271_write_regs(fe, R_EB7, 1);
 493         msleep(10);
 494
 495         regs[R_EB20]  = 0xec;
 496         tda18271_write_regs(fe, R_EB20, 1);
 497         msleep(60); /* RF tracking filter calibration completion */
 498
 499         regs[R_EP4]  &= ~0x03; /* set cal mode to normal */
 500         tda18271_write_regs(fe, R_EP4, 1);
 501
 502         tda18271_write_regs(fe, R_EP1, 1);
 503
 504         /* RF tracking filer correction for VHF_Low band */
 505         tda18271_calc_rf_cal(&freq, &val);
 506
 507         /* VHF_Low band only */
 508         if (val != 0) {
 509                 regs[R_EB14] = val;
 510                 tda18271_write_regs(fe, R_EB14, 1);
 511         }
 512
 513         /* Channel Configuration */
 514
 515         switch (priv->mode) {
 516         case TDA18271_ANALOG:
 517                 regs[R_EB22]  = 0x2c;
 518                 break;
 519         case TDA18271_DIGITAL:
 520                 regs[R_EB22]  = 0x37;
 521                 break;
 522         }
 523         tda18271_write_regs(fe, R_EB22, 1);
 524
 525         regs[R_EP1]  |= 0x40; /* set dis power level on */
 526
 527         /* set standard */
 528         regs[R_EP3]  &= ~0x1f; /* clear std bits */
 529
 530         /* see table 22 */
 531         regs[R_EP3]  |= std;
 532
 533         regs[R_EP4]  &= ~0x03; /* set cal mode to normal */
 534
 535         regs[R_EP4]  &= ~0x1c; /* clear if level bits */
 536         switch (priv->mode) {
 537         case TDA18271_ANALOG:
 538                 regs[R_MPD]  &= ~0x80; /* IF notch = 0 */
 539                 break;
 540         case TDA18271_DIGITAL:
 541                 regs[R_EP4]  |= 0x04;
 542                 regs[R_MPD]  |= 0x80;
 543                 break;
 544         }
 545
 546         regs[R_EP4]  &= ~0x80; /* turn this bit on only for fm */
 547
 548         /* image rejection validity EP5[2:0] */
 549         tda18271_calc_ir_measure(&freq, &val);
 550
 551         regs[R_EP5] &= ~0x07;
 552         regs[R_EP5] |= val;
 553
 554         /* calculate MAIN PLL */
 555         N = freq + ifc;
 556
 557         tda18271_calc_main_pll(&N, &pd, &d);
 558
 559         regs[R_MPD]   = (0x7f & pd);
 560         switch (priv->mode) {
 561         case TDA18271_ANALOG:
 562                 regs[R_MPD]  &= ~0x08;
 563                 break;
 564         case TDA18271_DIGITAL:
 565                 regs[R_MPD]  |= 0x08;
 566                 break;
 567         }
 568
 569         div =  ((d * (N / 1000)) << 7) / 125;
 570         regs[R_MD1]   = 0xff & (div >> 16);
 571         regs[R_MD2]   = 0xff & (div >> 8);
 572         regs[R_MD3]   = 0xff & div;
 573
 574         tda18271_write_regs(fe, R_TM, 15);
 575         msleep(5);
 576
 577         return 0;
 578 }
 579
 580 /* ------------------------------------------------------------------ */
 581
 582 static int tda18271_set_params(struct dvb_frontend *fe,
 583                                struct dvb_frontend_parameters *params)
 584 {
 585         struct tda18271_priv *priv = fe->tuner_priv;
 586         u8 std;
 587         u32 bw, sgIF = 0;
 588
 589         u32 freq = params->frequency;
 590
 591         priv->mode = TDA18271_DIGITAL;
 592
 593         /* see table 22 */
 594         if (fe->ops.info.type == FE_ATSC) {
 595                 switch (params->u.vsb.modulation) {
 596                 case VSB_8:
 597                 case VSB_16:
 598                         std = 0x1b; /* device-specific (spec says 0x1c) */
 599                         sgIF = 5380000;
 600                         break;
 601                 case QAM_64:
 602                 case QAM_256:
 603                         std = 0x18; /* device-specific (spec says 0x1d) */
 604                         sgIF = 4000000;
 605                         break;
 606                 default:
 607                         printk(KERN_WARNING "%s: modulation not set!\n",
 608                                __FUNCTION__);
 609                         return -EINVAL;
 610                 }
 611 #if 0
 612                 /* userspace request is already center adjusted */
 613                 freq += 1750000; /* Adjust to center (+1.75MHZ) */
 614 #endif
 615                 bw = 6000000;
 616         } else if (fe->ops.info.type == FE_OFDM) {
 617                 switch (params->u.ofdm.bandwidth) {
 618                 case BANDWIDTH_6_MHZ:
 619                         std = 0x1b; /* device-specific (spec says 0x1c) */
 620                         bw = 6000000;
 621                         sgIF = 3300000;
 622                         break;
 623                 case BANDWIDTH_7_MHZ:
 624                         std = 0x19; /* device-specific (spec says 0x1d) */
 625                         bw = 7000000;
 626                         sgIF = 3800000;
 627                         break;
 628                 case BANDWIDTH_8_MHZ:
 629                         std = 0x1a; /* device-specific (spec says 0x1e) */
 630                         bw = 8000000;
 631                         sgIF = 4300000;
 632                         break;
 633                 default:
 634                         printk(KERN_WARNING "%s: bandwidth not set!\n",
 635                                __FUNCTION__);
 636                         return -EINVAL;
 637                 }
 638         } else {
 639                 printk(KERN_WARNING "%s: modulation type not supported!\n",
 640                        __FUNCTION__);
 641                 return -EINVAL;
 642         }
 643
 644         return tda18271_tune(fe, sgIF, freq, bw, std);
 645 }
 646
 647 static int tda18271_set_analog_params(struct dvb_frontend *fe,
 648                                       struct analog_parameters *params)
 649 {
 650         struct tda18271_priv *priv = fe->tuner_priv;
 651         u8 std;
 652         unsigned int sgIF;
 653         char *mode;
 654
 655         priv->mode = TDA18271_ANALOG;
 656
 657         /* see table 22 */
 658         if (params->std & V4L2_STD_MN) {
 659                 std = 0x0d;
 660                 sgIF =  92;
 661                 mode = "MN";
 662         } else if (params->std & V4L2_STD_B) {
 663                 std = 0x0e;
 664                 sgIF =  108;
 665                 mode = "B";
 666         } else if (params->std & V4L2_STD_GH) {
 667                 std = 0x0f;
 668                 sgIF =  124;
 669                 mode = "GH";
 670         } else if (params->std & V4L2_STD_PAL_I) {
 671                 std = 0x0f;
 672                 sgIF =  124;
 673                 mode = "I";
 674         } else if (params->std & V4L2_STD_DK) {
 675                 std = 0x0f;
 676                 sgIF =  124;
 677                 mode = "DK";
 678         } else if (params->std & V4L2_STD_SECAM_L) {
 679                 std = 0x0f;
 680                 sgIF =  124;
 681                 mode = "L";
 682         } else if (params->std & V4L2_STD_SECAM_LC) {
 683                 std = 0x0f;
 684                 sgIF =  20;
 685                 mode = "LC";
 686         } else {
 687                 std = 0x0f;
 688                 sgIF =  124;
 689                 mode = "xx";
 690         }
 691
 692         if (params->mode == V4L2_TUNER_RADIO)
 693                 sgIF =  88; /* if frequency is 5.5 MHz */
 694
 695         dbg_info("setting tda18271 to system %s\n", mode);
 696
 697         return tda18271_tune(fe, sgIF * 62500, params->frequency * 62500,
 698                              0, std);
 699 }
 700
 701 static int tda18271_release(struct dvb_frontend *fe)
 702 {
 703         kfree(fe->tuner_priv);
 704         fe->tuner_priv = NULL;
 705         return 0;
 706 }
 707
 708 static int tda18271_get_frequency(struct dvb_frontend *fe, u32 *frequency)
 709 {
 710         struct tda18271_priv *priv = fe->tuner_priv;
 711         *frequency = priv->frequency;
 712         return 0;
 713 }
 714
 715 static int tda18271_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
 716 {
 717         struct tda18271_priv *priv = fe->tuner_priv;
 718         *bandwidth = priv->bandwidth;
 719         return 0;
 720 }
 721
 722 static struct dvb_tuner_ops tda18271_tuner_ops = {
 723         .info = {
 724                 .name = "NXP TDA18271HD",
 725                 .frequency_min  =  45000000,
 726                 .frequency_max  = 864000000,
 727                 .frequency_step =     62500
 728         },
 729         .init              = tda18271_init,
 730         .set_params        = tda18271_set_params,
 731         .set_analog_params = tda18271_set_analog_params,
 732         .release           = tda18271_release,
 733         .get_frequency     = tda18271_get_frequency,
 734         .get_bandwidth     = tda18271_get_bandwidth,
 735 };
 736
 737 struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe, u8 addr,
 738                                      struct i2c_adapter *i2c,
 739                                      enum tda18271_i2c_gate gate)
 740 {
 741         struct tda18271_priv *priv = NULL;
 742
 743         dbg_info("@ %d-%04x\n", i2c_adapter_id(i2c), addr);
 744         priv = kzalloc(sizeof(struct tda18271_priv), GFP_KERNEL);
 745         if (priv == NULL)
 746                 return NULL;
 747
 748         priv->i2c_addr = addr;
 749         priv->i2c_adap = i2c;
 750         priv->gate = gate;
 751
 752         memcpy(&fe->ops.tuner_ops, &tda18271_tuner_ops,
 753                sizeof(struct dvb_tuner_ops));
 754
 755         fe->tuner_priv = priv;
 756
 757         tda18271_init_regs(fe);
 758
 759         return fe;
 760 }
 761 EXPORT_SYMBOL_GPL(tda18271_attach);
 762 MODULE_DESCRIPTION("NXP TDA18271HD analog / digital tuner driver");
 763 MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
 764 MODULE_LICENSE("GPL");
 765
 766 /*
 767  * Overrides for Emacs so that we follow Linus's tabbing style.
 768  * ---------------------------------------------------------------------------
 769  * Local variables:
 770  * c-basic-offset: 8
 771  * End:
 772  */