2 Driver for Philips tda1004xh OFDM Demodulator
4 (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * This driver needs external firmware. Please use the commands
24 * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045",
25 * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to
26 * download/extract them, and then copy them to /usr/lib/hotplug/firmware.
28 #define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw"
29 #define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw"
31 #include <linux/init.h>
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/device.h>
35 #include "dvb_frontend.h"
39 TDA1004X_DEMOD_TDA10045,
40 TDA1004X_DEMOD_TDA10046,
43 struct tda1004x_state {
44 struct i2c_adapter* i2c;
45 struct dvb_frontend_ops ops;
46 const struct tda1004x_config* config;
47 struct dvb_frontend frontend;
49 /* private demod data */
51 enum tda1004x_demod demod_type;
56 #define dprintk(args...) \
58 if (debug) printk(KERN_DEBUG "tda1004x: " args); \
61 #define TDA1004X_CHIPID 0x00
62 #define TDA1004X_AUTO 0x01
63 #define TDA1004X_IN_CONF1 0x02
64 #define TDA1004X_IN_CONF2 0x03
65 #define TDA1004X_OUT_CONF1 0x04
66 #define TDA1004X_OUT_CONF2 0x05
67 #define TDA1004X_STATUS_CD 0x06
68 #define TDA1004X_CONFC4 0x07
69 #define TDA1004X_DSSPARE2 0x0C
70 #define TDA10045H_CODE_IN 0x0D
71 #define TDA10045H_FWPAGE 0x0E
72 #define TDA1004X_SCAN_CPT 0x10
73 #define TDA1004X_DSP_CMD 0x11
74 #define TDA1004X_DSP_ARG 0x12
75 #define TDA1004X_DSP_DATA1 0x13
76 #define TDA1004X_DSP_DATA2 0x14
77 #define TDA1004X_CONFADC1 0x15
78 #define TDA1004X_CONFC1 0x16
79 #define TDA10045H_S_AGC 0x1a
80 #define TDA10046H_AGC_TUN_LEVEL 0x1a
81 #define TDA1004X_SNR 0x1c
82 #define TDA1004X_CONF_TS1 0x1e
83 #define TDA1004X_CONF_TS2 0x1f
84 #define TDA1004X_CBER_RESET 0x20
85 #define TDA1004X_CBER_MSB 0x21
86 #define TDA1004X_CBER_LSB 0x22
87 #define TDA1004X_CVBER_LUT 0x23
88 #define TDA1004X_VBER_MSB 0x24
89 #define TDA1004X_VBER_MID 0x25
90 #define TDA1004X_VBER_LSB 0x26
91 #define TDA1004X_UNCOR 0x27
93 #define TDA10045H_CONFPLL_P 0x2D
94 #define TDA10045H_CONFPLL_M_MSB 0x2E
95 #define TDA10045H_CONFPLL_M_LSB 0x2F
96 #define TDA10045H_CONFPLL_N 0x30
98 #define TDA10046H_CONFPLL1 0x2D
99 #define TDA10046H_CONFPLL2 0x2F
100 #define TDA10046H_CONFPLL3 0x30
101 #define TDA10046H_TIME_WREF1 0x31
102 #define TDA10046H_TIME_WREF2 0x32
103 #define TDA10046H_TIME_WREF3 0x33
104 #define TDA10046H_TIME_WREF4 0x34
105 #define TDA10046H_TIME_WREF5 0x35
107 #define TDA10045H_UNSURW_MSB 0x31
108 #define TDA10045H_UNSURW_LSB 0x32
109 #define TDA10045H_WREF_MSB 0x33
110 #define TDA10045H_WREF_MID 0x34
111 #define TDA10045H_WREF_LSB 0x35
112 #define TDA10045H_MUXOUT 0x36
113 #define TDA1004X_CONFADC2 0x37
115 #define TDA10045H_IOFFSET 0x38
117 #define TDA10046H_CONF_TRISTATE1 0x3B
118 #define TDA10046H_CONF_TRISTATE2 0x3C
119 #define TDA10046H_CONF_POLARITY 0x3D
120 #define TDA10046H_FREQ_OFFSET 0x3E
121 #define TDA10046H_GPIO_OUT_SEL 0x41
122 #define TDA10046H_GPIO_SELECT 0x42
123 #define TDA10046H_AGC_CONF 0x43
124 #define TDA10046H_AGC_GAINS 0x46
125 #define TDA10046H_AGC_TUN_MIN 0x47
126 #define TDA10046H_AGC_TUN_MAX 0x48
127 #define TDA10046H_AGC_IF_MIN 0x49
128 #define TDA10046H_AGC_IF_MAX 0x4A
130 #define TDA10046H_FREQ_PHY2_MSB 0x4D
131 #define TDA10046H_FREQ_PHY2_LSB 0x4E
133 #define TDA10046H_CVBER_CTRL 0x4F
134 #define TDA10046H_AGC_IF_LEVEL 0x52
135 #define TDA10046H_CODE_CPT 0x57
136 #define TDA10046H_CODE_IN 0x58
139 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
142 u8 buf[] = { reg, data };
143 struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
145 dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__, reg, data);
147 msg.addr = state->config->demod_address;
148 ret = i2c_transfer(state->i2c, &msg, 1);
151 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
152 __FUNCTION__, reg, data, ret);
154 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
156 return (ret != 1) ? -1 : 0;
159 static int tda1004x_read_byte(struct tda1004x_state *state, int reg)
164 struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
165 { .flags = I2C_M_RD, .buf = b1, .len = 1 }};
167 dprintk("%s: reg=0x%x\n", __FUNCTION__, reg);
169 msg[0].addr = state->config->demod_address;
170 msg[1].addr = state->config->demod_address;
171 ret = i2c_transfer(state->i2c, msg, 2);
174 dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__, reg,
179 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
184 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
187 dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__, reg,
190 // read a byte and check
191 val = tda1004x_read_byte(state, reg);
199 // write it out again
200 return tda1004x_write_byteI(state, reg, val);
203 static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len)
208 dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__, reg, len);
211 for (i = 0; i < len; i++) {
212 result = tda1004x_write_byteI(state, reg + i, buf[i]);
220 static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state)
223 dprintk("%s\n", __FUNCTION__);
225 result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
230 static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
232 dprintk("%s\n", __FUNCTION__);
234 return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
237 static int tda10045h_set_bandwidth(struct tda1004x_state *state,
238 fe_bandwidth_t bandwidth)
240 static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
241 static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
242 static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
245 case BANDWIDTH_6_MHZ:
246 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
249 case BANDWIDTH_7_MHZ:
250 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
253 case BANDWIDTH_8_MHZ:
254 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
261 tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
266 static int tda10046h_set_bandwidth(struct tda1004x_state *state,
267 fe_bandwidth_t bandwidth)
269 static u8 bandwidth_6mhz[] = { 0x80, 0x15, 0xfe, 0xab, 0x8e };
270 static u8 bandwidth_7mhz[] = { 0x6e, 0x02, 0x53, 0xc8, 0x25 };
271 static u8 bandwidth_8mhz[] = { 0x60, 0x12, 0xa8, 0xe4, 0xbd };
274 case BANDWIDTH_6_MHZ:
275 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz, sizeof(bandwidth_6mhz));
278 case BANDWIDTH_7_MHZ:
279 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz, sizeof(bandwidth_7mhz));
282 case BANDWIDTH_8_MHZ:
283 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz, sizeof(bandwidth_8mhz));
293 static int tda1004x_do_upload(struct tda1004x_state *state,
294 unsigned char *mem, unsigned int len,
295 u8 dspCodeCounterReg, u8 dspCodeInReg)
298 struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 };
302 /* clear code counter */
303 tda1004x_write_byteI(state, dspCodeCounterReg, 0);
304 fw_msg.addr = state->config->demod_address;
306 buf[0] = dspCodeInReg;
308 // work out how much to send this time
314 memcpy(buf + 1, mem + pos, tx_size);
315 fw_msg.len = tx_size + 1;
316 if (i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
317 printk("tda1004x: Error during firmware upload\n");
322 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, pos);
328 static int tda1004x_check_upload_ok(struct tda1004x_state *state, u8 dspVersion)
332 // check upload was OK
333 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
334 tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
336 data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
337 data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
338 if ((data1 != 0x67) || (data2 != dspVersion))
344 static int tda10045_fwupload(struct dvb_frontend* fe)
346 struct tda1004x_state* state = fe->demodulator_priv;
348 const struct firmware *fw;
350 /* don't re-upload unless necessary */
351 if (tda1004x_check_upload_ok(state, 0x2c) == 0)
354 /* request the firmware, this will block until someone uploads it */
355 printk("tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE);
356 ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
358 printk("tda1004x: no firmware upload (timeout or file not found?)\n");
363 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
364 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
365 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
369 tda10045h_set_bandwidth(state, BANDWIDTH_8_MHZ);
371 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
374 printk("tda1004x: firmware upload complete\n");
376 /* wait for DSP to initialise */
377 /* DSPREADY doesn't seem to work on the TDA10045H */
380 return tda1004x_check_upload_ok(state, 0x2c);
383 static int tda10046_fwupload(struct dvb_frontend* fe)
385 struct tda1004x_state* state = fe->demodulator_priv;
386 unsigned long timeout;
388 const struct firmware *fw;
390 /* reset + wake up chip */
391 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 0);
392 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
395 /* don't re-upload unless necessary */
396 if (tda1004x_check_upload_ok(state, 0x20) == 0)
399 /* request the firmware, this will block until someone uploads it */
400 printk("tda1004x: waiting for firmware upload (%s)...\n", TDA10046_DEFAULT_FIRMWARE);
401 ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
403 printk("tda1004x: no firmware upload (timeout or file not found?)\n");
408 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 10);
409 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0);
410 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 99);
411 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4);
412 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x2c);
413 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
415 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
418 printk("tda1004x: firmware upload complete\n");
420 /* wait for DSP to initialise */
421 timeout = jiffies + HZ;
422 while (!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
423 if (time_after(jiffies, timeout)) {
424 printk("tda1004x: DSP failed to initialised.\n");
430 return tda1004x_check_upload_ok(state, 0x20);
433 static int tda1004x_encode_fec(int fec)
435 // convert known FEC values
453 static int tda1004x_decode_fec(int tdafec)
455 // convert known FEC values
473 int tda1004x_write_byte(struct dvb_frontend* fe, int reg, int data)
475 struct tda1004x_state* state = fe->demodulator_priv;
477 return tda1004x_write_byteI(state, reg, data);
480 static int tda10045_init(struct dvb_frontend* fe)
482 struct tda1004x_state* state = fe->demodulator_priv;
484 dprintk("%s\n", __FUNCTION__);
486 if (state->initialised)
489 if (tda10045_fwupload(fe)) {
490 printk("tda1004x: firmware upload failed\n");
494 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
497 if (state->config->pll_init) {
498 tda1004x_enable_tuner_i2c(state);
499 state->config->pll_init(fe);
500 tda1004x_disable_tuner_i2c(state);
504 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
505 tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
506 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
507 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
508 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
509 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
510 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
511 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
512 tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
513 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
514 tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
516 tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
518 state->initialised = 1;
522 static int tda10046_init(struct dvb_frontend* fe)
524 struct tda1004x_state* state = fe->demodulator_priv;
525 dprintk("%s\n", __FUNCTION__);
527 if (state->initialised)
530 if (tda10046_fwupload(fe)) {
531 printk("tda1004x: firmware upload failed\n");
535 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 0); // wake up the chip
538 if (state->config->pll_init) {
539 tda1004x_enable_tuner_i2c(state);
540 state->config->pll_init(fe);
541 tda1004x_disable_tuner_i2c(state);
545 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
546 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0x40);
547 tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
548 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0); // disable pulse killer
549 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 10); // PLL M = 10
550 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
551 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 99); // FREQOFFS = 99
552 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4); // } PHY2 = -11221
553 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x2c); // }
554 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0); // AGC setup
555 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x60, 0x60); // set AGC polarities
556 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // }
557 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
558 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // }
559 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // }
560 tda1004x_write_mask(state, TDA10046H_CVBER_CTRL, 0x30, 0x10); // 10^6 VBER measurement bits
561 tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 1); // IF gain 2, TUN gain 1
562 tda1004x_write_mask(state, TDA1004X_AUTO, 0x80, 0); // crystal is 50ppm
563 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
564 tda1004x_write_mask(state, TDA1004X_CONF_TS2, 0x31, 0); // MPEG2 interface config
565 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0x9e, 0); // disable AGC_TUN
566 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0xe1); // tristate setup
567 tda1004x_write_byteI(state, TDA10046H_GPIO_OUT_SEL, 0xcc); // GPIO output config
568 tda1004x_write_mask(state, TDA10046H_GPIO_SELECT, 8, 8); // GPIO select
569 tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
571 tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
573 state->initialised = 1;
577 static int tda1004x_set_fe(struct dvb_frontend* fe,
578 struct dvb_frontend_parameters *fe_params)
580 struct tda1004x_state* state = fe->demodulator_priv;
584 dprintk("%s\n", __FUNCTION__);
586 if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
588 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
589 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
590 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
592 // disable agc_conf[2]
593 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
597 tda1004x_enable_tuner_i2c(state);
598 state->config->pll_set(fe, fe_params);
599 tda1004x_disable_tuner_i2c(state);
601 if (state->demod_type == TDA1004X_DEMOD_TDA10046)
602 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 4);
604 // Hardcoded to use auto as much as possible on the TDA10045 as it
605 // is very unreliable if AUTO mode is _not_ used.
606 if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
607 fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
608 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
609 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
612 // Set standard params.. or put them to auto
613 if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
614 (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
615 (fe_params->u.ofdm.constellation == QAM_AUTO) ||
616 (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
617 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto
618 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits
619 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
620 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
622 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto
625 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP);
628 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
631 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP);
634 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
637 switch (fe_params->u.ofdm.constellation) {
639 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
643 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
647 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
655 switch (fe_params->u.ofdm.hierarchy_information) {
657 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
661 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
665 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
669 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
678 switch (state->demod_type) {
679 case TDA1004X_DEMOD_TDA10045:
680 tda10045h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
683 case TDA1004X_DEMOD_TDA10046:
684 tda10046h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
689 inversion = fe_params->inversion;
690 if (state->config->invert)
691 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
694 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
698 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
705 // set guard interval
706 switch (fe_params->u.ofdm.guard_interval) {
707 case GUARD_INTERVAL_1_32:
708 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
709 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
712 case GUARD_INTERVAL_1_16:
713 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
714 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
717 case GUARD_INTERVAL_1_8:
718 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
719 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
722 case GUARD_INTERVAL_1_4:
723 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
724 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
727 case GUARD_INTERVAL_AUTO:
728 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
729 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
736 // set transmission mode
737 switch (fe_params->u.ofdm.transmission_mode) {
738 case TRANSMISSION_MODE_2K:
739 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
740 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
743 case TRANSMISSION_MODE_8K:
744 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
745 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
748 case TRANSMISSION_MODE_AUTO:
749 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
750 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
758 switch (state->demod_type) {
759 case TDA1004X_DEMOD_TDA10045:
760 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
761 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
764 case TDA1004X_DEMOD_TDA10046:
765 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
774 static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params)
776 struct tda1004x_state* state = fe->demodulator_priv;
777 dprintk("%s\n", __FUNCTION__);
780 fe_params->inversion = INVERSION_OFF;
781 if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20)
782 fe_params->inversion = INVERSION_ON;
783 if (state->config->invert)
784 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
787 switch (state->demod_type) {
788 case TDA1004X_DEMOD_TDA10045:
789 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
791 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
794 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
797 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
802 case TDA1004X_DEMOD_TDA10046:
803 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
805 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
808 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
811 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
818 fe_params->u.ofdm.code_rate_HP =
819 tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
820 fe_params->u.ofdm.code_rate_LP =
821 tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
824 switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
826 fe_params->u.ofdm.constellation = QPSK;
829 fe_params->u.ofdm.constellation = QAM_16;
832 fe_params->u.ofdm.constellation = QAM_64;
837 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
838 if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
839 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
842 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
844 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
847 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
850 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
853 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
858 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
860 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
863 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1;
866 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2;
869 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4;
876 static int tda1004x_read_status(struct dvb_frontend* fe, fe_status_t * fe_status)
878 struct tda1004x_state* state = fe->demodulator_priv;
883 dprintk("%s\n", __FUNCTION__);
886 status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
893 *fe_status |= FE_HAS_SIGNAL;
895 *fe_status |= FE_HAS_CARRIER;
897 *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
899 // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
900 // is getting anything valid
901 if (!(*fe_status & FE_HAS_VITERBI)) {
903 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
906 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
909 cber |= (status << 8);
910 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
913 *fe_status |= FE_HAS_VITERBI;
916 // if we DO have some valid VITERBI output, but don't already have SYNC
917 // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
918 if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
920 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB);
923 status = tda1004x_read_byte(state, TDA1004X_VBER_MID);
926 vber |= (status << 8);
927 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB);
930 vber |= ((status << 16) & 0x0f);
931 tda1004x_read_byte(state, TDA1004X_CVBER_LUT);
933 // if RS has passed some valid TS packets, then we must be
934 // getting some SYNC bytes
936 *fe_status |= FE_HAS_SYNC;
940 dprintk("%s: fe_status=0x%x\n", __FUNCTION__, *fe_status);
944 static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
946 struct tda1004x_state* state = fe->demodulator_priv;
950 dprintk("%s\n", __FUNCTION__);
952 // determine the register to use
953 switch (state->demod_type) {
954 case TDA1004X_DEMOD_TDA10045:
955 reg = TDA10045H_S_AGC;
958 case TDA1004X_DEMOD_TDA10046:
959 reg = TDA10046H_AGC_IF_LEVEL;
964 tmp = tda1004x_read_byte(state, reg);
968 *signal = (tmp << 8) | tmp;
969 dprintk("%s: signal=0x%x\n", __FUNCTION__, *signal);
973 static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr)
975 struct tda1004x_state* state = fe->demodulator_priv;
978 dprintk("%s\n", __FUNCTION__);
981 tmp = tda1004x_read_byte(state, TDA1004X_SNR);
987 *snr = ((tmp << 8) | tmp);
988 dprintk("%s: snr=0x%x\n", __FUNCTION__, *snr);
992 static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
994 struct tda1004x_state* state = fe->demodulator_priv;
999 dprintk("%s\n", __FUNCTION__);
1001 // read the UCBLOCKS and reset
1003 tmp = tda1004x_read_byte(state, TDA1004X_UNCOR);
1007 while (counter++ < 5) {
1008 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1009 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1010 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1012 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR);
1016 if ((tmp2 < tmp) || (tmp2 == 0))
1023 *ucblocks = 0xffffffff;
1025 dprintk("%s: ucblocks=0x%x\n", __FUNCTION__, *ucblocks);
1029 static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber)
1031 struct tda1004x_state* state = fe->demodulator_priv;
1034 dprintk("%s\n", __FUNCTION__);
1037 tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1041 tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1045 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1047 dprintk("%s: ber=0x%x\n", __FUNCTION__, *ber);
1051 static int tda1004x_sleep(struct dvb_frontend* fe)
1053 struct tda1004x_state* state = fe->demodulator_priv;
1055 switch (state->demod_type) {
1056 case TDA1004X_DEMOD_TDA10045:
1057 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
1060 case TDA1004X_DEMOD_TDA10046:
1061 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
1064 state->initialised = 0;
1069 static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
1071 fesettings->min_delay_ms = 800;
1072 fesettings->step_size = 166667;
1073 fesettings->max_drift = 166667*2;
1077 static void tda1004x_release(struct dvb_frontend* fe)
1079 struct tda1004x_state *state = fe->demodulator_priv;
1083 static struct dvb_frontend_ops tda10045_ops = {
1085 .name = "Philips TDA10045H DVB-T",
1087 .frequency_min = 51000000,
1088 .frequency_max = 858000000,
1089 .frequency_stepsize = 166667,
1091 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1092 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1093 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1094 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1097 .release = tda1004x_release,
1099 .init = tda10045_init,
1100 .sleep = tda1004x_sleep,
1102 .set_frontend = tda1004x_set_fe,
1103 .get_frontend = tda1004x_get_fe,
1104 .get_tune_settings = tda1004x_get_tune_settings,
1106 .read_status = tda1004x_read_status,
1107 .read_ber = tda1004x_read_ber,
1108 .read_signal_strength = tda1004x_read_signal_strength,
1109 .read_snr = tda1004x_read_snr,
1110 .read_ucblocks = tda1004x_read_ucblocks,
1113 struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
1114 struct i2c_adapter* i2c)
1116 struct tda1004x_state *state;
1118 /* allocate memory for the internal state */
1119 state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1123 /* setup the state */
1124 state->config = config;
1126 memcpy(&state->ops, &tda10045_ops, sizeof(struct dvb_frontend_ops));
1127 state->initialised = 0;
1128 state->demod_type = TDA1004X_DEMOD_TDA10045;
1130 /* check if the demod is there */
1131 if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x25) {
1136 /* create dvb_frontend */
1137 state->frontend.ops = &state->ops;
1138 state->frontend.demodulator_priv = state;
1139 return &state->frontend;
1142 static struct dvb_frontend_ops tda10046_ops = {
1144 .name = "Philips TDA10046H DVB-T",
1146 .frequency_min = 51000000,
1147 .frequency_max = 858000000,
1148 .frequency_stepsize = 166667,
1150 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1151 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1152 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1153 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1156 .release = tda1004x_release,
1158 .init = tda10046_init,
1159 .sleep = tda1004x_sleep,
1161 .set_frontend = tda1004x_set_fe,
1162 .get_frontend = tda1004x_get_fe,
1163 .get_tune_settings = tda1004x_get_tune_settings,
1165 .read_status = tda1004x_read_status,
1166 .read_ber = tda1004x_read_ber,
1167 .read_signal_strength = tda1004x_read_signal_strength,
1168 .read_snr = tda1004x_read_snr,
1169 .read_ucblocks = tda1004x_read_ucblocks,
1172 struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
1173 struct i2c_adapter* i2c)
1175 struct tda1004x_state *state;
1177 /* allocate memory for the internal state */
1178 state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1182 /* setup the state */
1183 state->config = config;
1185 memcpy(&state->ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
1186 state->initialised = 0;
1187 state->demod_type = TDA1004X_DEMOD_TDA10046;
1189 /* check if the demod is there */
1190 if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x46) {
1195 /* create dvb_frontend */
1196 state->frontend.ops = &state->ops;
1197 state->frontend.demodulator_priv = state;
1198 return &state->frontend;
1201 module_param(debug, int, 0644);
1202 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1204 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
1205 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1206 MODULE_LICENSE("GPL");
1208 EXPORT_SYMBOL(tda10045_attach);
1209 EXPORT_SYMBOL(tda10046_attach);
1210 EXPORT_SYMBOL(tda1004x_write_byte);