err.no Git - linux-2.6/blob - drivers/media/dvb/frontends/tda1004x.c

   1   /*
   2      Driver for Philips tda1004xh OFDM Demodulator
   3
   4      (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
   5
   6      This program is free software; you can redistribute it and/or modify
   7      it under the terms of the GNU General Public License as published by
   8      the Free Software Foundation; either version 2 of the License, or
   9      (at your option) any later version.
  10
  11      This program is distributed in the hope that it will be useful,
  12      but WITHOUT ANY WARRANTY; without even the implied warranty of
  13      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14
  15      GNU General Public License for more details.
  16
  17      You should have received a copy of the GNU General Public License
  18      along with this program; if not, write to the Free Software
  19      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20
  21    */
  22 /*
  23  * This driver needs external firmware. Please use the commands
  24  * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045",
  25  * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to
  26  * download/extract them, and then copy them to /usr/lib/hotplug/firmware.
  27  */
  28 #define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw"
  29 #define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw"
  30
  31 #include <linux/init.h>
  32 #include <linux/module.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/device.h>
  35 #include "dvb_frontend.h"
  36 #include "tda1004x.h"
  37
  38 enum tda1004x_demod {
  39         TDA1004X_DEMOD_TDA10045,
  40         TDA1004X_DEMOD_TDA10046,
  41 };
  42
  43 struct tda1004x_state {
  44         struct i2c_adapter* i2c;
  45         struct dvb_frontend_ops ops;
  46         const struct tda1004x_config* config;
  47         struct dvb_frontend frontend;
  48
  49         /* private demod data */
  50         u8 initialised;
  51         enum tda1004x_demod demod_type;
  52 };
  53
  54 static int debug;
  55 #define dprintk(args...) \
  56         do { \
  57                 if (debug) printk(KERN_DEBUG "tda1004x: " args); \
  58         } while (0)
  59
  60 #define TDA1004X_CHIPID          0x00
  61 #define TDA1004X_AUTO            0x01
  62 #define TDA1004X_IN_CONF1        0x02
  63 #define TDA1004X_IN_CONF2        0x03
  64 #define TDA1004X_OUT_CONF1       0x04
  65 #define TDA1004X_OUT_CONF2       0x05
  66 #define TDA1004X_STATUS_CD       0x06
  67 #define TDA1004X_CONFC4          0x07
  68 #define TDA1004X_DSSPARE2        0x0C
  69 #define TDA10045H_CODE_IN        0x0D
  70 #define TDA10045H_FWPAGE         0x0E
  71 #define TDA1004X_SCAN_CPT        0x10
  72 #define TDA1004X_DSP_CMD         0x11
  73 #define TDA1004X_DSP_ARG         0x12
  74 #define TDA1004X_DSP_DATA1       0x13
  75 #define TDA1004X_DSP_DATA2       0x14
  76 #define TDA1004X_CONFADC1        0x15
  77 #define TDA1004X_CONFC1          0x16
  78 #define TDA10045H_S_AGC          0x1a
  79 #define TDA10046H_AGC_TUN_LEVEL  0x1a
  80 #define TDA1004X_SNR             0x1c
  81 #define TDA1004X_CONF_TS1        0x1e
  82 #define TDA1004X_CONF_TS2        0x1f
  83 #define TDA1004X_CBER_RESET      0x20
  84 #define TDA1004X_CBER_MSB        0x21
  85 #define TDA1004X_CBER_LSB        0x22
  86 #define TDA1004X_CVBER_LUT       0x23
  87 #define TDA1004X_VBER_MSB        0x24
  88 #define TDA1004X_VBER_MID        0x25
  89 #define TDA1004X_VBER_LSB        0x26
  90 #define TDA1004X_UNCOR           0x27
  91
  92 #define TDA10045H_CONFPLL_P      0x2D
  93 #define TDA10045H_CONFPLL_M_MSB  0x2E
  94 #define TDA10045H_CONFPLL_M_LSB  0x2F
  95 #define TDA10045H_CONFPLL_N      0x30
  96
  97 #define TDA10046H_CONFPLL1       0x2D
  98 #define TDA10046H_CONFPLL2       0x2F
  99 #define TDA10046H_CONFPLL3       0x30
 100 #define TDA10046H_TIME_WREF1     0x31
 101 #define TDA10046H_TIME_WREF2     0x32
 102 #define TDA10046H_TIME_WREF3     0x33
 103 #define TDA10046H_TIME_WREF4     0x34
 104 #define TDA10046H_TIME_WREF5     0x35
 105
 106 #define TDA10045H_UNSURW_MSB     0x31
 107 #define TDA10045H_UNSURW_LSB     0x32
 108 #define TDA10045H_WREF_MSB       0x33
 109 #define TDA10045H_WREF_MID       0x34
 110 #define TDA10045H_WREF_LSB       0x35
 111 #define TDA10045H_MUXOUT         0x36
 112 #define TDA1004X_CONFADC2        0x37
 113
 114 #define TDA10045H_IOFFSET        0x38
 115
 116 #define TDA10046H_CONF_TRISTATE1 0x3B
 117 #define TDA10046H_CONF_TRISTATE2 0x3C
 118 #define TDA10046H_CONF_POLARITY  0x3D
 119 #define TDA10046H_FREQ_OFFSET    0x3E
 120 #define TDA10046H_GPIO_OUT_SEL   0x41
 121 #define TDA10046H_GPIO_SELECT    0x42
 122 #define TDA10046H_AGC_CONF       0x43
 123 #define TDA10046H_AGC_GAINS      0x46
 124 #define TDA10046H_AGC_TUN_MIN    0x47
 125 #define TDA10046H_AGC_TUN_MAX    0x48
 126 #define TDA10046H_AGC_IF_MIN     0x49
 127 #define TDA10046H_AGC_IF_MAX     0x4A
 128
 129 #define TDA10046H_FREQ_PHY2_MSB  0x4D
 130 #define TDA10046H_FREQ_PHY2_LSB  0x4E
 131
 132 #define TDA10046H_CVBER_CTRL     0x4F
 133 #define TDA10046H_AGC_IF_LEVEL   0x52
 134 #define TDA10046H_CODE_CPT       0x57
 135 #define TDA10046H_CODE_IN        0x58
 136
 137
 138 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
 139 {
 140         int ret;
 141         u8 buf[] = { reg, data };
 142         struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
 143
 144         dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__, reg, data);
 145
 146         msg.addr = state->config->demod_address;
 147         ret = i2c_transfer(state->i2c, &msg, 1);
 148
 149         if (ret != 1)
 150                 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
 151                         __FUNCTION__, reg, data, ret);
 152
 153         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
 154                 reg, data, ret);
 155         return (ret != 1) ? -1 : 0;
 156 }
 157
 158 static int tda1004x_read_byte(struct tda1004x_state *state, int reg)
 159 {
 160         int ret;
 161         u8 b0[] = { reg };
 162         u8 b1[] = { 0 };
 163         struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
 164                                 { .flags = I2C_M_RD, .buf = b1, .len = 1 }};
 165
 166         dprintk("%s: reg=0x%x\n", __FUNCTION__, reg);
 167
 168         msg[0].addr = state->config->demod_address;
 169         msg[1].addr = state->config->demod_address;
 170         ret = i2c_transfer(state->i2c, msg, 2);
 171
 172         if (ret != 2) {
 173                 dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__, reg,
 174                         ret);
 175                 return -1;
 176         }
 177
 178         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
 179                 reg, b1[0], ret);
 180         return b1[0];
 181 }
 182
 183 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
 184 {
 185         int val;
 186         dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__, reg,
 187                 mask, data);
 188
 189         // read a byte and check
 190         val = tda1004x_read_byte(state, reg);
 191         if (val < 0)
 192                 return val;
 193
 194         // mask if off
 195         val = val & ~mask;
 196         val |= data & 0xff;
 197
 198         // write it out again
 199         return tda1004x_write_byteI(state, reg, val);
 200 }
 201
 202 static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len)
 203 {
 204         int i;
 205         int result;
 206
 207         dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__, reg, len);
 208
 209         result = 0;
 210         for (i = 0; i < len; i++) {
 211                 result = tda1004x_write_byteI(state, reg + i, buf[i]);
 212                 if (result != 0)
 213                         break;
 214         }
 215
 216         return result;
 217 }
 218
 219 static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state)
 220 {
 221         int result;
 222         dprintk("%s\n", __FUNCTION__);
 223
 224         result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
 225         msleep(1);
 226         return result;
 227 }
 228
 229 static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
 230 {
 231         dprintk("%s\n", __FUNCTION__);
 232
 233         return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
 234 }
 235
 236 static int tda10045h_set_bandwidth(struct tda1004x_state *state,
 237                                    fe_bandwidth_t bandwidth)
 238 {
 239         static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
 240         static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
 241         static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
 242
 243         switch (bandwidth) {
 244         case BANDWIDTH_6_MHZ:
 245                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
 246                 break;
 247
 248         case BANDWIDTH_7_MHZ:
 249                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
 250                 break;
 251
 252         case BANDWIDTH_8_MHZ:
 253                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
 254                 break;
 255
 256         default:
 257                 return -EINVAL;
 258         }
 259
 260         tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
 261
 262         return 0;
 263 }
 264
 265 static int tda10046h_set_bandwidth(struct tda1004x_state *state,
 266                                    fe_bandwidth_t bandwidth)
 267 {
 268         static u8 bandwidth_6mhz[] = { 0x80, 0x15, 0xfe, 0xab, 0x8e };
 269         static u8 bandwidth_7mhz[] = { 0x6e, 0x02, 0x53, 0xc8, 0x25 };
 270         static u8 bandwidth_8mhz[] = { 0x60, 0x12, 0xa8, 0xe4, 0xbd };
 271
 272         switch (bandwidth) {
 273         case BANDWIDTH_6_MHZ:
 274                 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz, sizeof(bandwidth_6mhz));
 275                 break;
 276
 277         case BANDWIDTH_7_MHZ:
 278                 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz, sizeof(bandwidth_7mhz));
 279                 break;
 280
 281         case BANDWIDTH_8_MHZ:
 282                 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz, sizeof(bandwidth_8mhz));
 283                 break;
 284
 285         default:
 286                 return -EINVAL;
 287         }
 288
 289         return 0;
 290 }
 291
 292 static int tda1004x_do_upload(struct tda1004x_state *state,
 293                               unsigned char *mem, unsigned int len,
 294                               u8 dspCodeCounterReg, u8 dspCodeInReg)
 295 {
 296         u8 buf[65];
 297         struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 };
 298         int tx_size;
 299         int pos = 0;
 300
 301         /* clear code counter */
 302         tda1004x_write_byteI(state, dspCodeCounterReg, 0);
 303         fw_msg.addr = state->config->demod_address;
 304
 305         buf[0] = dspCodeInReg;
 306         while (pos != len) {
 307                 // work out how much to send this time
 308                 tx_size = len - pos;
 309                 if (tx_size > 0x10)
 310                         tx_size = 0x10;
 311
 312                 // send the chunk
 313                 memcpy(buf + 1, mem + pos, tx_size);
 314                 fw_msg.len = tx_size + 1;
 315                 if (i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
 316                         printk(KERN_ERR "tda1004x: Error during firmware upload\n");
 317                         return -EIO;
 318                 }
 319                 pos += tx_size;
 320
 321                 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, pos);
 322         }
 323         // give the DSP a chance to settle 03/10/05 Hac
 324         msleep(100);
 325
 326         return 0;
 327 }
 328
 329 static int tda1004x_check_upload_ok(struct tda1004x_state *state)
 330 {
 331         u8 data1, data2;
 332         unsigned long timeout;
 333
 334         if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
 335                 timeout = jiffies + 2 * HZ;
 336                 while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
 337                         if (time_after(jiffies, timeout)) {
 338                                 printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n");
 339                                 break;
 340                         }
 341                         msleep(1);
 342                 }
 343         } else
 344                 msleep(100);
 345
 346         // check upload was OK
 347         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
 348         tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
 349
 350         data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
 351         data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
 352         if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2e) {
 353                 printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2);
 354                 return -EIO;
 355         }
 356         printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2);
 357         return 0;
 358 }
 359
 360 static int tda10045_fwupload(struct dvb_frontend* fe)
 361 {
 362         struct tda1004x_state* state = fe->demodulator_priv;
 363         int ret;
 364         const struct firmware *fw;
 365
 366         /* don't re-upload unless necessary */
 367         if (tda1004x_check_upload_ok(state) == 0)
 368                 return 0;
 369
 370         /* request the firmware, this will block until someone uploads it */
 371         printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE);
 372         ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
 373         if (ret) {
 374                 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
 375                 return ret;
 376         }
 377
 378         /* reset chip */
 379         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
 380         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
 381         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
 382         msleep(10);
 383
 384         /* set parameters */
 385         tda10045h_set_bandwidth(state, BANDWIDTH_8_MHZ);
 386
 387         ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
 388         release_firmware(fw);
 389         if (ret)
 390                 return ret;
 391         printk(KERN_INFO "tda1004x: firmware upload complete\n");
 392
 393         /* wait for DSP to initialise */
 394         /* DSPREADY doesn't seem to work on the TDA10045H */
 395         msleep(100);
 396
 397         return tda1004x_check_upload_ok(state);
 398 }
 399
 400 static void tda10046_init_plls(struct dvb_frontend* fe)
 401 {
 402         struct tda1004x_state* state = fe->demodulator_priv;
 403
 404         tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
 405         tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 10); // PLL M = 10
 406         if (state->config->xtal_freq == TDA10046_XTAL_4M ) {
 407                 dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __FUNCTION__);
 408                 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
 409         } else {
 410                 dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __FUNCTION__);
 411                 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
 412         }
 413         tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 99);
 414         switch (state->config->if_freq) {
 415         case TDA10046_FREQ_3617:
 416                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4);
 417                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x2c);
 418                 break;
 419         case TDA10046_FREQ_3613:
 420                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4);
 421                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x13);
 422                 break;
 423         }
 424         tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
 425 }
 426
 427 static int tda10046_fwupload(struct dvb_frontend* fe)
 428 {
 429         struct tda1004x_state* state = fe->demodulator_priv;
 430         int ret;
 431         const struct firmware *fw;
 432
 433         /* reset + wake up chip */
 434         tda1004x_write_byteI(state, TDA1004X_CONFC4, 0);
 435         tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
 436         /* let the clocks recover from sleep */
 437         msleep(5);
 438
 439         /* don't re-upload unless necessary */
 440         if (tda1004x_check_upload_ok(state) == 0)
 441                 return 0;
 442
 443         /* set parameters */
 444         tda10046_init_plls(fe);
 445
 446         if (state->config->request_firmware != NULL) {
 447                 /* request the firmware, this will block until someone uploads it */
 448                 printk(KERN_INFO "tda1004x: waiting for firmware upload...\n");
 449                 ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
 450                 if (ret) {
 451                         printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
 452                         return ret;
 453                 }
 454                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
 455                 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
 456                 release_firmware(fw);
 457                 if (ret)
 458                         return ret;
 459         } else {
 460                 /* boot from firmware eeprom */
 461                 /* Hac Note: we might need to do some GPIO Magic here */
 462                 printk(KERN_INFO "tda1004x: booting from eeprom\n");
 463                 tda1004x_write_mask(state, TDA1004X_CONFC4, 4, 4);
 464                 msleep(300);
 465         }
 466         return tda1004x_check_upload_ok(state);
 467 }
 468
 469 static int tda1004x_encode_fec(int fec)
 470 {
 471         // convert known FEC values
 472         switch (fec) {
 473         case FEC_1_2:
 474                 return 0;
 475         case FEC_2_3:
 476                 return 1;
 477         case FEC_3_4:
 478                 return 2;
 479         case FEC_5_6:
 480                 return 3;
 481         case FEC_7_8:
 482                 return 4;
 483         }
 484
 485         // unsupported
 486         return -EINVAL;
 487 }
 488
 489 static int tda1004x_decode_fec(int tdafec)
 490 {
 491         // convert known FEC values
 492         switch (tdafec) {
 493         case 0:
 494                 return FEC_1_2;
 495         case 1:
 496                 return FEC_2_3;
 497         case 2:
 498                 return FEC_3_4;
 499         case 3:
 500                 return FEC_5_6;
 501         case 4:
 502                 return FEC_7_8;
 503         }
 504
 505         // unsupported
 506         return -1;
 507 }
 508
 509 int tda1004x_write_byte(struct dvb_frontend* fe, int reg, int data)
 510 {
 511         struct tda1004x_state* state = fe->demodulator_priv;
 512
 513         return tda1004x_write_byteI(state, reg, data);
 514 }
 515
 516 static int tda10045_init(struct dvb_frontend* fe)
 517 {
 518         struct tda1004x_state* state = fe->demodulator_priv;
 519
 520         dprintk("%s\n", __FUNCTION__);
 521
 522         if (state->initialised)
 523                 return 0;
 524
 525         if (tda10045_fwupload(fe)) {
 526                 printk("tda1004x: firmware upload failed\n");
 527                 return -EIO;
 528         }
 529
 530         tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
 531
 532         // Init the PLL
 533         if (state->config->pll_init) {
 534                 tda1004x_enable_tuner_i2c(state);
 535                 state->config->pll_init(fe);
 536                 tda1004x_disable_tuner_i2c(state);
 537         }
 538
 539         // tda setup
 540         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 541         tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
 542         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
 543         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
 544         tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
 545         tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
 546         tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
 547         tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
 548         tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
 549         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
 550         tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
 551
 552         tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
 553
 554         state->initialised = 1;
 555         return 0;
 556 }
 557
 558 static int tda10046_init(struct dvb_frontend* fe)
 559 {
 560         struct tda1004x_state* state = fe->demodulator_priv;
 561         dprintk("%s\n", __FUNCTION__);
 562
 563         if (state->initialised)
 564                 return 0;
 565
 566         if (tda10046_fwupload(fe)) {
 567                 printk("tda1004x: firmware upload failed\n");
 568                         return -EIO;
 569         }
 570
 571         // Init the tuner PLL
 572         if (state->config->pll_init) {
 573                 tda1004x_enable_tuner_i2c(state);
 574                 state->config->pll_init(fe);
 575                 tda1004x_disable_tuner_i2c(state);
 576         }
 577
 578         // tda setup
 579         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 580         tda1004x_write_byteI(state, TDA1004X_AUTO, 7); // select HP stream
 581         tda1004x_write_byteI(state, TDA1004X_CONFC1, 8); // disable pulse killer
 582
 583         tda10046_init_plls(fe);
 584         switch (state->config->agc_config) {
 585         case TDA10046_AGC_DEFAULT:
 586                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
 587                 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
 588                 break;
 589         case TDA10046_AGC_IFO_AUTO_NEG:
 590                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
 591                 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
 592                 break;
 593         }
 594         tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0x61); // Turn both AGC outputs on
 595         tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0);    // }
 596         tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
 597         tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0);     // }
 598         tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff);  // }
 599         tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 1); // IF gain 2, TUN gain 1
 600         tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
 601         tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
 602         tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
 603         tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
 604
 605         tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0xe1); // tristate setup
 606         tda1004x_write_byteI(state, TDA10046H_GPIO_OUT_SEL, 0xcc); // GPIO output config
 607         tda1004x_write_byteI(state, TDA10046H_GPIO_SELECT, 8); // GPIO select
 608
 609         state->initialised = 1;
 610         return 0;
 611 }
 612
 613 static int tda1004x_set_fe(struct dvb_frontend* fe,
 614                            struct dvb_frontend_parameters *fe_params)
 615 {
 616         struct tda1004x_state* state = fe->demodulator_priv;
 617         int tmp;
 618         int inversion;
 619
 620         dprintk("%s\n", __FUNCTION__);
 621
 622         if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
 623                 // setup auto offset
 624                 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
 625                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
 626                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
 627
 628                 // disable agc_conf[2]
 629                 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
 630         }
 631
 632         // set frequency
 633         tda1004x_enable_tuner_i2c(state);
 634         state->config->pll_set(fe, fe_params);
 635         tda1004x_disable_tuner_i2c(state);
 636
 637         // Hardcoded to use auto as much as possible on the TDA10045 as it
 638         // is very unreliable if AUTO mode is _not_ used.
 639         if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
 640                 fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
 641                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
 642                 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
 643         }
 644
 645         // Set standard params.. or put them to auto
 646         if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
 647             (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
 648             (fe_params->u.ofdm.constellation == QAM_AUTO) ||
 649             (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
 650                 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1);        // enable auto
 651                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits
 652                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
 653                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
 654         } else {
 655                 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0);        // disable auto
 656
 657                 // set HP FEC
 658                 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP);
 659                 if (tmp < 0)
 660                         return tmp;
 661                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
 662
 663                 // set LP FEC
 664                 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP);
 665                 if (tmp < 0)
 666                         return tmp;
 667                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
 668
 669                 // set constellation
 670                 switch (fe_params->u.ofdm.constellation) {
 671                 case QPSK:
 672                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
 673                         break;
 674
 675                 case QAM_16:
 676                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
 677                         break;
 678
 679                 case QAM_64:
 680                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
 681                         break;
 682
 683                 default:
 684                         return -EINVAL;
 685                 }
 686
 687                 // set hierarchy
 688                 switch (fe_params->u.ofdm.hierarchy_information) {
 689                 case HIERARCHY_NONE:
 690                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
 691                         break;
 692
 693                 case HIERARCHY_1:
 694                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
 695                         break;
 696
 697                 case HIERARCHY_2:
 698                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
 699                         break;
 700
 701                 case HIERARCHY_4:
 702                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
 703                         break;
 704
 705                 default:
 706                         return -EINVAL;
 707                 }
 708         }
 709
 710         // set bandwidth
 711         switch (state->demod_type) {
 712         case TDA1004X_DEMOD_TDA10045:
 713                 tda10045h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
 714                 break;
 715
 716         case TDA1004X_DEMOD_TDA10046:
 717                 tda10046h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
 718                 break;
 719         }
 720
 721         // set inversion
 722         inversion = fe_params->inversion;
 723         if (state->config->invert)
 724                 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
 725         switch (inversion) {
 726         case INVERSION_OFF:
 727                 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
 728                 break;
 729
 730         case INVERSION_ON:
 731                 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
 732                 break;
 733
 734         default:
 735                 return -EINVAL;
 736         }
 737
 738         // set guard interval
 739         switch (fe_params->u.ofdm.guard_interval) {
 740         case GUARD_INTERVAL_1_32:
 741                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 742                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 743                 break;
 744
 745         case GUARD_INTERVAL_1_16:
 746                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 747                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
 748                 break;
 749
 750         case GUARD_INTERVAL_1_8:
 751                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 752                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
 753                 break;
 754
 755         case GUARD_INTERVAL_1_4:
 756                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 757                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
 758                 break;
 759
 760         case GUARD_INTERVAL_AUTO:
 761                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
 762                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 763                 break;
 764
 765         default:
 766                 return -EINVAL;
 767         }
 768
 769         // set transmission mode
 770         switch (fe_params->u.ofdm.transmission_mode) {
 771         case TRANSMISSION_MODE_2K:
 772                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
 773                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
 774                 break;
 775
 776         case TRANSMISSION_MODE_8K:
 777                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
 778                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
 779                 break;
 780
 781         case TRANSMISSION_MODE_AUTO:
 782                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
 783                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
 784                 break;
 785
 786         default:
 787                 return -EINVAL;
 788         }
 789
 790         // start the lock
 791         switch (state->demod_type) {
 792         case TDA1004X_DEMOD_TDA10045:
 793                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
 794                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
 795                 break;
 796
 797         case TDA1004X_DEMOD_TDA10046:
 798                 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
 799                 break;
 800         }
 801
 802         msleep(10);
 803
 804         return 0;
 805 }
 806
 807 static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params)
 808 {
 809         struct tda1004x_state* state = fe->demodulator_priv;
 810         dprintk("%s\n", __FUNCTION__);
 811
 812         // inversion status
 813         fe_params->inversion = INVERSION_OFF;
 814         if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20)
 815                 fe_params->inversion = INVERSION_ON;
 816         if (state->config->invert)
 817                 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
 818
 819         // bandwidth
 820         switch (state->demod_type) {
 821         case TDA1004X_DEMOD_TDA10045:
 822                 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
 823                 case 0x14:
 824                         fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
 825                         break;
 826                 case 0xdb:
 827                         fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
 828                         break;
 829                 case 0x4f:
 830                         fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
 831                         break;
 832                 }
 833                 break;
 834
 835         case TDA1004X_DEMOD_TDA10046:
 836                 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
 837                 case 0x60:
 838                         fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
 839                         break;
 840                 case 0x6e:
 841                         fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
 842                         break;
 843                 case 0x80:
 844                         fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
 845                         break;
 846                 }
 847                 break;
 848         }
 849
 850         // FEC
 851         fe_params->u.ofdm.code_rate_HP =
 852             tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
 853         fe_params->u.ofdm.code_rate_LP =
 854             tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
 855
 856         // constellation
 857         switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
 858         case 0:
 859                 fe_params->u.ofdm.constellation = QPSK;
 860                 break;
 861         case 1:
 862                 fe_params->u.ofdm.constellation = QAM_16;
 863                 break;
 864         case 2:
 865                 fe_params->u.ofdm.constellation = QAM_64;
 866                 break;
 867         }
 868
 869         // transmission mode
 870         fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
 871         if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
 872                 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
 873
 874         // guard interval
 875         switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
 876         case 0:
 877                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
 878                 break;
 879         case 1:
 880                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
 881                 break;
 882         case 2:
 883                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
 884                 break;
 885         case 3:
 886                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
 887                 break;
 888         }
 889
 890         // hierarchy
 891         switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
 892         case 0:
 893                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
 894                 break;
 895         case 1:
 896                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1;
 897                 break;
 898         case 2:
 899                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2;
 900                 break;
 901         case 3:
 902                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4;
 903                 break;
 904         }
 905
 906         return 0;
 907 }
 908
 909 static int tda1004x_read_status(struct dvb_frontend* fe, fe_status_t * fe_status)
 910 {
 911         struct tda1004x_state* state = fe->demodulator_priv;
 912         int status;
 913         int cber;
 914         int vber;
 915
 916         dprintk("%s\n", __FUNCTION__);
 917
 918         // read status
 919         status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
 920         if (status == -1)
 921                 return -EIO;
 922
 923         // decode
 924         *fe_status = 0;
 925         if (status & 4)
 926                 *fe_status |= FE_HAS_SIGNAL;
 927         if (status & 2)
 928                 *fe_status |= FE_HAS_CARRIER;
 929         if (status & 8)
 930                 *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
 931
 932         // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
 933         // is getting anything valid
 934         if (!(*fe_status & FE_HAS_VITERBI)) {
 935                 // read the CBER
 936                 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
 937                 if (cber == -1)
 938                         return -EIO;
 939                 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
 940                 if (status == -1)
 941                         return -EIO;
 942                 cber |= (status << 8);
 943                 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
 944
 945                 if (cber != 65535)
 946                         *fe_status |= FE_HAS_VITERBI;
 947         }
 948
 949         // if we DO have some valid VITERBI output, but don't already have SYNC
 950         // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
 951         if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
 952                 // read the VBER
 953                 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB);
 954                 if (vber == -1)
 955                         return -EIO;
 956                 status = tda1004x_read_byte(state, TDA1004X_VBER_MID);
 957                 if (status == -1)
 958                         return -EIO;
 959                 vber |= (status << 8);
 960                 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB);
 961                 if (status == -1)
 962                         return -EIO;
 963                 vber |= ((status << 16) & 0x0f);
 964                 tda1004x_read_byte(state, TDA1004X_CVBER_LUT);
 965
 966                 // if RS has passed some valid TS packets, then we must be
 967                 // getting some SYNC bytes
 968                 if (vber < 16632)
 969                         *fe_status |= FE_HAS_SYNC;
 970         }
 971
 972         // success
 973         dprintk("%s: fe_status=0x%x\n", __FUNCTION__, *fe_status);
 974         return 0;
 975 }
 976
 977 static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
 978 {
 979         struct tda1004x_state* state = fe->demodulator_priv;
 980         int tmp;
 981         int reg = 0;
 982
 983         dprintk("%s\n", __FUNCTION__);
 984
 985         // determine the register to use
 986         switch (state->demod_type) {
 987         case TDA1004X_DEMOD_TDA10045:
 988                 reg = TDA10045H_S_AGC;
 989                 break;
 990
 991         case TDA1004X_DEMOD_TDA10046:
 992                 reg = TDA10046H_AGC_IF_LEVEL;
 993                 break;
 994         }
 995
 996         // read it
 997         tmp = tda1004x_read_byte(state, reg);
 998         if (tmp < 0)
 999                 return -EIO;
1000
1001         *signal = (tmp << 8) | tmp;
1002         dprintk("%s: signal=0x%x\n", __FUNCTION__, *signal);
1003         return 0;
1004 }
1005
1006 static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr)
1007 {
1008         struct tda1004x_state* state = fe->demodulator_priv;
1009         int tmp;
1010
1011         dprintk("%s\n", __FUNCTION__);
1012
1013         // read it
1014         tmp = tda1004x_read_byte(state, TDA1004X_SNR);
1015         if (tmp < 0)
1016                 return -EIO;
1017         if (tmp)
1018                 tmp = 255 - tmp;
1019
1020         *snr = ((tmp << 8) | tmp);
1021         dprintk("%s: snr=0x%x\n", __FUNCTION__, *snr);
1022         return 0;
1023 }
1024
1025 static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
1026 {
1027         struct tda1004x_state* state = fe->demodulator_priv;
1028         int tmp;
1029         int tmp2;
1030         int counter;
1031
1032         dprintk("%s\n", __FUNCTION__);
1033
1034         // read the UCBLOCKS and reset
1035         counter = 0;
1036         tmp = tda1004x_read_byte(state, TDA1004X_UNCOR);
1037         if (tmp < 0)
1038                 return -EIO;
1039         tmp &= 0x7f;
1040         while (counter++ < 5) {
1041                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1042                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1043                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1044
1045                 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR);
1046                 if (tmp2 < 0)
1047                         return -EIO;
1048                 tmp2 &= 0x7f;
1049                 if ((tmp2 < tmp) || (tmp2 == 0))
1050                         break;
1051         }
1052
1053         if (tmp != 0x7f)
1054                 *ucblocks = tmp;
1055         else
1056                 *ucblocks = 0xffffffff;
1057
1058         dprintk("%s: ucblocks=0x%x\n", __FUNCTION__, *ucblocks);
1059         return 0;
1060 }
1061
1062 static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber)
1063 {
1064         struct tda1004x_state* state = fe->demodulator_priv;
1065         int tmp;
1066
1067         dprintk("%s\n", __FUNCTION__);
1068
1069         // read it in
1070         tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1071         if (tmp < 0)
1072                 return -EIO;
1073         *ber = tmp << 1;
1074         tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1075         if (tmp < 0)
1076                 return -EIO;
1077         *ber |= (tmp << 9);
1078         tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1079
1080         dprintk("%s: ber=0x%x\n", __FUNCTION__, *ber);
1081         return 0;
1082 }
1083
1084 static int tda1004x_sleep(struct dvb_frontend* fe)
1085 {
1086         struct tda1004x_state* state = fe->demodulator_priv;
1087
1088         switch (state->demod_type) {
1089         case TDA1004X_DEMOD_TDA10045:
1090                 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
1091                 break;
1092
1093         case TDA1004X_DEMOD_TDA10046:
1094                 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
1095                 if (state->config->pll_sleep != NULL)
1096                         state->config->pll_sleep(fe);
1097                 break;
1098         }
1099         state->initialised = 0;
1100
1101         return 0;
1102 }
1103
1104 static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
1105 {
1106         fesettings->min_delay_ms = 800;
1107         fesettings->step_size = 166667;
1108         fesettings->max_drift = 166667*2;
1109         return 0;
1110 }
1111
1112 static void tda1004x_release(struct dvb_frontend* fe)
1113 {
1114         struct tda1004x_state *state = fe->demodulator_priv;
1115         kfree(state);
1116 }
1117
1118 static struct dvb_frontend_ops tda10045_ops = {
1119         .info = {
1120                 .name = "Philips TDA10045H DVB-T",
1121                 .type = FE_OFDM,
1122                 .frequency_min = 51000000,
1123                 .frequency_max = 858000000,
1124                 .frequency_stepsize = 166667,
1125                 .caps =
1126                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1127                     FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1128                     FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1129                     FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1130         },
1131
1132         .release = tda1004x_release,
1133
1134         .init = tda10045_init,
1135         .sleep = tda1004x_sleep,
1136
1137         .set_frontend = tda1004x_set_fe,
1138         .get_frontend = tda1004x_get_fe,
1139         .get_tune_settings = tda1004x_get_tune_settings,
1140
1141         .read_status = tda1004x_read_status,
1142         .read_ber = tda1004x_read_ber,
1143         .read_signal_strength = tda1004x_read_signal_strength,
1144         .read_snr = tda1004x_read_snr,
1145         .read_ucblocks = tda1004x_read_ucblocks,
1146 };
1147
1148 struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
1149                                      struct i2c_adapter* i2c)
1150 {
1151         struct tda1004x_state *state;
1152
1153         /* allocate memory for the internal state */
1154         state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1155         if (!state)
1156                 return NULL;
1157
1158         /* setup the state */
1159         state->config = config;
1160         state->i2c = i2c;
1161         memcpy(&state->ops, &tda10045_ops, sizeof(struct dvb_frontend_ops));
1162         state->initialised = 0;
1163         state->demod_type = TDA1004X_DEMOD_TDA10045;
1164
1165         /* check if the demod is there */
1166         if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x25) {
1167                 kfree(state);
1168                 return NULL;
1169         }
1170
1171         /* create dvb_frontend */
1172         state->frontend.ops = &state->ops;
1173         state->frontend.demodulator_priv = state;
1174         return &state->frontend;
1175 }
1176
1177 static struct dvb_frontend_ops tda10046_ops = {
1178         .info = {
1179                 .name = "Philips TDA10046H DVB-T",
1180                 .type = FE_OFDM,
1181                 .frequency_min = 51000000,
1182                 .frequency_max = 858000000,
1183                 .frequency_stepsize = 166667,
1184                 .caps =
1185                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1186                     FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1187                     FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1188                     FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1189         },
1190
1191         .release = tda1004x_release,
1192
1193         .init = tda10046_init,
1194         .sleep = tda1004x_sleep,
1195
1196         .set_frontend = tda1004x_set_fe,
1197         .get_frontend = tda1004x_get_fe,
1198         .get_tune_settings = tda1004x_get_tune_settings,
1199
1200         .read_status = tda1004x_read_status,
1201         .read_ber = tda1004x_read_ber,
1202         .read_signal_strength = tda1004x_read_signal_strength,
1203         .read_snr = tda1004x_read_snr,
1204         .read_ucblocks = tda1004x_read_ucblocks,
1205 };
1206
1207 struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
1208                                      struct i2c_adapter* i2c)
1209 {
1210         struct tda1004x_state *state;
1211
1212         /* allocate memory for the internal state */
1213         state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1214         if (!state)
1215                 return NULL;
1216
1217         /* setup the state */
1218         state->config = config;
1219         state->i2c = i2c;
1220         memcpy(&state->ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
1221         state->initialised = 0;
1222         state->demod_type = TDA1004X_DEMOD_TDA10046;
1223
1224         /* check if the demod is there */
1225         if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x46) {
1226                 kfree(state);
1227                 return NULL;
1228         }
1229
1230         /* create dvb_frontend */
1231         state->frontend.ops = &state->ops;
1232         state->frontend.demodulator_priv = state;
1233         return &state->frontend;
1234 }
1235
1236 module_param(debug, int, 0644);
1237 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1238
1239 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
1240 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1241 MODULE_LICENSE("GPL");
1242
1243 EXPORT_SYMBOL(tda10045_attach);
1244 EXPORT_SYMBOL(tda10046_attach);
1245 EXPORT_SYMBOL(tda1004x_write_byte);