2 NXP TDA10048HN DVB OFDM demodulator driver
4 Copyright (C) 2008 Steven Toth <stoth@hauppauge.com>
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/slab.h>
27 #include <linux/delay.h>
28 #include "dvb_frontend.h"
31 #define TDA10048_DEFAULT_FIRMWARE "dvb-fe-tda10048-1.0.fw"
32 #define TDA10048_DEFAULT_FIRMWARE_SIZE 24878
34 /* Register name definitions */
35 #define TDA10048_IDENTITY 0x00
36 #define TDA10048_VERSION 0x01
37 #define TDA10048_DSP_CODE_CPT 0x0C
38 #define TDA10048_DSP_CODE_IN 0x0E
39 #define TDA10048_IN_CONF1 0x10
40 #define TDA10048_IN_CONF2 0x11
41 #define TDA10048_IN_CONF3 0x12
42 #define TDA10048_OUT_CONF1 0x14
43 #define TDA10048_OUT_CONF2 0x15
44 #define TDA10048_OUT_CONF3 0x16
45 #define TDA10048_AUTO 0x18
46 #define TDA10048_SYNC_STATUS 0x1A
47 #define TDA10048_CONF_C4_1 0x1E
48 #define TDA10048_CONF_C4_2 0x1F
49 #define TDA10048_CODE_IN_RAM 0x20
50 #define TDA10048_CHANNEL_INFO_1_R 0x22
51 #define TDA10048_CHANNEL_INFO_2_R 0x23
52 #define TDA10048_CHANNEL_INFO1 0x24
53 #define TDA10048_CHANNEL_INFO2 0x25
54 #define TDA10048_TIME_ERROR_R 0x26
55 #define TDA10048_TIME_ERROR 0x27
56 #define TDA10048_FREQ_ERROR_LSB_R 0x28
57 #define TDA10048_FREQ_ERROR_MSB_R 0x29
58 #define TDA10048_FREQ_ERROR_LSB 0x2A
59 #define TDA10048_FREQ_ERROR_MSB 0x2B
60 #define TDA10048_IT_SEL 0x30
61 #define TDA10048_IT_STAT 0x32
62 #define TDA10048_DSP_AD_LSB 0x3C
63 #define TDA10048_DSP_AD_MSB 0x3D
64 #define TDA10048_DSP_REF_LSB 0x3E
65 #define TDA10048_DSP_REF_MSB 0x3F
66 #define TDA10048_CONF_TRISTATE1 0x44
67 #define TDA10048_CONF_TRISTATE2 0x45
68 #define TDA10048_CONF_POLARITY 0x46
69 #define TDA10048_GPIO_SP_DS0 0x48
70 #define TDA10048_GPIO_SP_DS1 0x49
71 #define TDA10048_GPIO_SP_DS2 0x4A
72 #define TDA10048_GPIO_SP_DS3 0x4B
73 #define TDA10048_GPIO_OUT_SEL 0x4C
74 #define TDA10048_GPIO_SELECT 0x4D
75 #define TDA10048_IC_MODE 0x4E
76 #define TDA10048_CONF_XO 0x50
77 #define TDA10048_CONF_PLL1 0x51
78 #define TDA10048_CONF_PLL2 0x52
79 #define TDA10048_CONF_PLL3 0x53
80 #define TDA10048_CONF_ADC 0x54
81 #define TDA10048_CONF_ADC_2 0x55
82 #define TDA10048_CONF_C1_1 0x60
83 #define TDA10048_CONF_C1_3 0x62
84 #define TDA10048_AGC_CONF 0x70
85 #define TDA10048_AGC_THRESHOLD_LSB 0x72
86 #define TDA10048_AGC_THRESHOLD_MSB 0x73
87 #define TDA10048_AGC_RENORM 0x74
88 #define TDA10048_AGC_GAINS 0x76
89 #define TDA10048_AGC_TUN_MIN 0x78
90 #define TDA10048_AGC_TUN_MAX 0x79
91 #define TDA10048_AGC_IF_MIN 0x7A
92 #define TDA10048_AGC_IF_MAX 0x7B
93 #define TDA10048_AGC_TUN_LEVEL 0x7E
94 #define TDA10048_AGC_IF_LEVEL 0x7F
95 #define TDA10048_DIG_AGC_LEVEL 0x81
96 #define TDA10048_FREQ_PHY2_LSB 0x86
97 #define TDA10048_FREQ_PHY2_MSB 0x87
98 #define TDA10048_TIME_INVWREF_LSB 0x88
99 #define TDA10048_TIME_INVWREF_MSB 0x89
100 #define TDA10048_TIME_WREF_LSB 0x8A
101 #define TDA10048_TIME_WREF_MID1 0x8B
102 #define TDA10048_TIME_WREF_MID2 0x8C
103 #define TDA10048_TIME_WREF_MSB 0x8D
104 #define TDA10048_NP_OUT 0xA2
105 #define TDA10048_CELL_ID_LSB 0xA4
106 #define TDA10048_CELL_ID_MSB 0xA5
107 #define TDA10048_EXTTPS_ODD 0xAA
108 #define TDA10048_EXTTPS_EVEN 0xAB
109 #define TDA10048_TPS_LENGTH 0xAC
110 #define TDA10048_FREE_REG_1 0xB2
111 #define TDA10048_FREE_REG_2 0xB3
112 #define TDA10048_CONF_C3_1 0xC0
113 #define TDA10048_CYBER_CTRL 0xC2
114 #define TDA10048_CBER_NMAX_LSB 0xC4
115 #define TDA10048_CBER_NMAX_MSB 0xC5
116 #define TDA10048_CBER_LSB 0xC6
117 #define TDA10048_CBER_MSB 0xC7
118 #define TDA10048_VBER_LSB 0xC8
119 #define TDA10048_VBER_MID 0xC9
120 #define TDA10048_VBER_MSB 0xCA
121 #define TDA10048_CYBER_LUT 0xCC
122 #define TDA10048_UNCOR_CTRL 0xCD
123 #define TDA10048_UNCOR_CPT_LSB 0xCE
124 #define TDA10048_UNCOR_CPT_MSB 0xCF
125 #define TDA10048_SOFT_IT_C3 0xD6
126 #define TDA10048_CONF_TS2 0xE0
127 #define TDA10048_CONF_TS1 0xE1
129 static unsigned int debug;
131 #define dprintk(level, fmt, arg...)\
132 do { if (debug >= level)\
133 printk(KERN_DEBUG "tda10048: " fmt, ## arg);\
136 struct tda10048_state {
138 struct i2c_adapter *i2c;
140 /* configuration settings */
141 const struct tda10048_config *config;
142 struct dvb_frontend frontend;
147 static struct init_tab {
151 { TDA10048_CONF_PLL1, 0x08 },
152 { TDA10048_CONF_ADC_2, 0x00 },
153 { TDA10048_CONF_C4_1, 0x00 },
154 { TDA10048_CONF_PLL1, 0x0f },
155 { TDA10048_CONF_PLL2, 0x0a },
156 { TDA10048_CONF_PLL3, 0x43 },
157 { TDA10048_FREQ_PHY2_LSB, 0x02 },
158 { TDA10048_FREQ_PHY2_MSB, 0x0a },
159 { TDA10048_TIME_WREF_LSB, 0xbd },
160 { TDA10048_TIME_WREF_MID1, 0xe4 },
161 { TDA10048_TIME_WREF_MID2, 0xa8 },
162 { TDA10048_TIME_WREF_MSB, 0x02 },
163 { TDA10048_TIME_INVWREF_LSB, 0x04 },
164 { TDA10048_TIME_INVWREF_MSB, 0x06 },
165 { TDA10048_CONF_C4_1, 0x00 },
166 { TDA10048_CONF_C1_1, 0xa8 },
167 { TDA10048_AGC_CONF, 0x16 },
168 { TDA10048_CONF_C1_3, 0x0b },
169 { TDA10048_AGC_TUN_MIN, 0x00 },
170 { TDA10048_AGC_TUN_MAX, 0xff },
171 { TDA10048_AGC_IF_MIN, 0x00 },
172 { TDA10048_AGC_IF_MAX, 0xff },
173 { TDA10048_AGC_THRESHOLD_MSB, 0x00 },
174 { TDA10048_AGC_THRESHOLD_LSB, 0x70 },
175 { TDA10048_CYBER_CTRL, 0x38 },
176 { TDA10048_AGC_GAINS, 0x12 },
177 { TDA10048_CONF_XO, 0x00 },
178 { TDA10048_CONF_TS1, 0x07 },
179 { TDA10048_IC_MODE, 0x00 },
180 { TDA10048_CONF_TS2, 0xc0 },
181 { TDA10048_CONF_TRISTATE1, 0x21 },
182 { TDA10048_CONF_TRISTATE2, 0x00 },
183 { TDA10048_CONF_POLARITY, 0x00 },
184 { TDA10048_CONF_C4_2, 0x04 },
185 { TDA10048_CONF_ADC, 0x60 },
186 { TDA10048_CONF_ADC_2, 0x10 },
187 { TDA10048_CONF_ADC, 0x60 },
188 { TDA10048_CONF_ADC_2, 0x00 },
189 { TDA10048_CONF_C1_1, 0xa8 },
190 { TDA10048_UNCOR_CTRL, 0x00 },
191 { TDA10048_CONF_C4_2, 0x04 },
194 static int tda10048_writereg(struct tda10048_state *state, u8 reg, u8 data)
197 u8 buf [] = { reg, data };
198 struct i2c_msg msg = {
199 .addr = state->config->demod_address,
200 .flags = 0, .buf = buf, .len = 2 };
202 dprintk(2, "%s(reg = 0x%02x, data = 0x%02x)\n", __func__, reg, data);
204 ret = i2c_transfer(state->i2c, &msg, 1);
207 printk("%s: writereg error (ret == %i)\n", __func__, ret);
209 return (ret != 1) ? -1 : 0;
212 static u8 tda10048_readreg(struct tda10048_state *state, u8 reg)
217 struct i2c_msg msg [] = {
218 { .addr = state->config->demod_address,
219 .flags = 0, .buf = b0, .len = 1 },
220 { .addr = state->config->demod_address,
221 .flags = I2C_M_RD, .buf = b1, .len = 1 } };
223 dprintk(2, "%s(reg = 0x%02x)\n", __func__, reg);
225 ret = i2c_transfer(state->i2c, msg, 2);
228 printk(KERN_ERR "%s: readreg error (ret == %i)\n",
234 static int tda10048_writeregbulk(struct tda10048_state *state, u8 reg,
237 int ret = -EREMOTEIO;
241 dprintk(2, "%s(%d, ?, len = %d)\n", __func__, reg, len);
243 buf = kmalloc(len + 1, GFP_KERNEL);
250 memcpy(buf + 1, data, len);
252 msg.addr = state->config->demod_address;
257 dprintk(2, "%s(): write len = %d\n",
260 ret = i2c_transfer(state->i2c, &msg, 1);
262 printk(KERN_ERR "%s(): writereg error err %i\n",
273 static int tda10048_firmware_upload(struct dvb_frontend *fe)
275 struct tda10048_state *state = fe->demodulator_priv;
276 const struct firmware *fw;
280 u8 wlen = state->config->fwbulkwritelen;
282 if ((wlen != TDA10048_BULKWRITE_200) && (wlen != TDA10048_BULKWRITE_50))
283 wlen = TDA10048_BULKWRITE_200;
285 /* request the firmware, this will block and timeout */
286 printk(KERN_INFO "%s: waiting for firmware upload (%s)...\n",
288 TDA10048_DEFAULT_FIRMWARE);
290 ret = request_firmware(&fw, TDA10048_DEFAULT_FIRMWARE,
293 printk(KERN_ERR "%s: Upload failed. (file not found?)\n",
297 printk(KERN_INFO "%s: firmware read %Zu bytes.\n",
303 if (fw->size != TDA10048_DEFAULT_FIRMWARE_SIZE) {
304 printk(KERN_ERR "%s: firmware incorrect size\n", __func__);
307 printk(KERN_INFO "%s: firmware uploading\n", __func__);
310 tda10048_writereg(state, TDA10048_CONF_TRISTATE1,
311 tda10048_readreg(state, TDA10048_CONF_TRISTATE1)
313 tda10048_writereg(state, TDA10048_CONF_TRISTATE1,
314 tda10048_readreg(state, TDA10048_CONF_TRISTATE1)
317 /* Put the demod into host download mode */
318 tda10048_writereg(state, TDA10048_CONF_C4_1,
319 tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xf9);
322 tda10048_writereg(state, TDA10048_CONF_C4_1,
323 tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x08);
325 /* Prepare for download */
326 tda10048_writereg(state, TDA10048_DSP_CODE_CPT, 0);
328 /* Download the firmware payload */
329 while (pos < fw->size) {
331 if ((fw->size - pos) > wlen)
334 cnt = fw->size - pos;
336 tda10048_writeregbulk(state, TDA10048_DSP_CODE_IN,
337 &fw->data[pos], cnt);
343 /* Wait up to 250ms for the DSP to boot */
344 for (cnt = 0; cnt < 250 ; cnt += 10) {
348 if (tda10048_readreg(state, TDA10048_SYNC_STATUS)
356 release_firmware(fw);
359 printk(KERN_INFO "%s: firmware uploaded\n", __func__);
362 printk(KERN_ERR "%s: firmware upload failed\n", __func__);
367 static int tda10048_set_inversion(struct dvb_frontend *fe, int inversion)
369 struct tda10048_state *state = fe->demodulator_priv;
371 dprintk(1, "%s(%d)\n", __func__, inversion);
373 if (inversion == TDA10048_INVERSION_ON)
374 tda10048_writereg(state, TDA10048_CONF_C1_1,
375 tda10048_readreg(state, TDA10048_CONF_C1_1) | 0x20);
377 tda10048_writereg(state, TDA10048_CONF_C1_1,
378 tda10048_readreg(state, TDA10048_CONF_C1_1) & 0xdf);
383 /* Retrieve the demod settings */
384 static int tda10048_get_tps(struct tda10048_state *state,
385 struct dvb_ofdm_parameters *p)
389 /* Make sure the TPS regs are valid */
390 if (!(tda10048_readreg(state, TDA10048_AUTO) & 0x01))
393 val = tda10048_readreg(state, TDA10048_OUT_CONF2);
394 switch ((val & 0x60) >> 5) {
395 case 0: p->constellation = QPSK; break;
396 case 1: p->constellation = QAM_16; break;
397 case 2: p->constellation = QAM_64; break;
399 switch ((val & 0x18) >> 3) {
400 case 0: p->hierarchy_information = HIERARCHY_NONE; break;
401 case 1: p->hierarchy_information = HIERARCHY_1; break;
402 case 2: p->hierarchy_information = HIERARCHY_2; break;
403 case 3: p->hierarchy_information = HIERARCHY_4; break;
405 switch (val & 0x07) {
406 case 0: p->code_rate_HP = FEC_1_2; break;
407 case 1: p->code_rate_HP = FEC_2_3; break;
408 case 2: p->code_rate_HP = FEC_3_4; break;
409 case 3: p->code_rate_HP = FEC_5_6; break;
410 case 4: p->code_rate_HP = FEC_7_8; break;
413 val = tda10048_readreg(state, TDA10048_OUT_CONF3);
414 switch (val & 0x07) {
415 case 0: p->code_rate_LP = FEC_1_2; break;
416 case 1: p->code_rate_LP = FEC_2_3; break;
417 case 2: p->code_rate_LP = FEC_3_4; break;
418 case 3: p->code_rate_LP = FEC_5_6; break;
419 case 4: p->code_rate_LP = FEC_7_8; break;
422 val = tda10048_readreg(state, TDA10048_OUT_CONF1);
423 switch ((val & 0x0c) >> 2) {
424 case 0: p->guard_interval = GUARD_INTERVAL_1_32; break;
425 case 1: p->guard_interval = GUARD_INTERVAL_1_16; break;
426 case 2: p->guard_interval = GUARD_INTERVAL_1_8; break;
427 case 3: p->guard_interval = GUARD_INTERVAL_1_4; break;
429 switch (val & 0x02) {
430 case 0: p->transmission_mode = TRANSMISSION_MODE_2K; break;
431 case 1: p->transmission_mode = TRANSMISSION_MODE_8K; break;
437 static int tda10048_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
439 struct tda10048_state *state = fe->demodulator_priv;
440 dprintk(1, "%s(%d)\n", __func__, enable);
443 return tda10048_writereg(state, TDA10048_CONF_C4_1,
444 tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x02);
446 return tda10048_writereg(state, TDA10048_CONF_C4_1,
447 tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xfd);
450 static int tda10048_output_mode(struct dvb_frontend *fe, int serial)
452 struct tda10048_state *state = fe->demodulator_priv;
453 dprintk(1, "%s(%d)\n", __func__, serial);
455 /* Ensure pins are out of tri-state */
456 tda10048_writereg(state, TDA10048_CONF_TRISTATE1, 0x21);
457 tda10048_writereg(state, TDA10048_CONF_TRISTATE2, 0x00);
460 tda10048_writereg(state, TDA10048_IC_MODE, 0x80 | 0x20);
461 tda10048_writereg(state, TDA10048_CONF_TS2, 0xc0);
463 tda10048_writereg(state, TDA10048_IC_MODE, 0x00);
464 tda10048_writereg(state, TDA10048_CONF_TS2, 0x01);
470 /* Talk to the demod, set the FEC, GUARD, QAM settings etc */
471 /* TODO: Support manual tuning with specific params */
472 static int tda10048_set_frontend(struct dvb_frontend *fe,
473 struct dvb_frontend_parameters *p)
475 struct tda10048_state *state = fe->demodulator_priv;
477 dprintk(1, "%s(frequency=%d)\n", __func__, p->frequency);
479 if (fe->ops.tuner_ops.set_params) {
481 if (fe->ops.i2c_gate_ctrl)
482 fe->ops.i2c_gate_ctrl(fe, 1);
484 fe->ops.tuner_ops.set_params(fe, p);
486 if (fe->ops.i2c_gate_ctrl)
487 fe->ops.i2c_gate_ctrl(fe, 0);
490 /* Enable demod TPS auto detection and begin acquisition */
491 tda10048_writereg(state, TDA10048_AUTO, 0x57);
496 /* Establish sane defaults and load firmware. */
497 static int tda10048_init(struct dvb_frontend *fe)
499 struct tda10048_state *state = fe->demodulator_priv;
502 dprintk(1, "%s()\n", __func__);
504 /* Apply register defaults */
505 for (i = 0; i < ARRAY_SIZE(init_tab); i++)
506 tda10048_writereg(state, init_tab[i].reg, init_tab[i].data);
508 if (state->fwloaded == 0)
509 ret = tda10048_firmware_upload(fe);
511 /* Set either serial or parallel */
512 tda10048_output_mode(fe, state->config->output_mode);
515 tda10048_set_inversion(fe, state->config->inversion);
517 /* Ensure we leave the gate closed */
518 tda10048_i2c_gate_ctrl(fe, 0);
523 static int tda10048_read_status(struct dvb_frontend *fe, fe_status_t *status)
525 struct tda10048_state *state = fe->demodulator_priv;
530 reg = tda10048_readreg(state, TDA10048_SYNC_STATUS);
532 dprintk(1, "%s() status =0x%02x\n", __func__, reg);
535 *status |= FE_HAS_CARRIER;
538 *status |= FE_HAS_SIGNAL;
541 *status |= FE_HAS_LOCK;
542 *status |= FE_HAS_VITERBI;
543 *status |= FE_HAS_SYNC;
549 static int tda10048_read_ber(struct dvb_frontend *fe, u32 *ber)
551 struct tda10048_state *state = fe->demodulator_priv;
553 dprintk(1, "%s()\n", __func__);
555 /* TODO: A reset may be required here */
556 *ber = tda10048_readreg(state, TDA10048_CBER_MSB) << 8 |
557 tda10048_readreg(state, TDA10048_CBER_LSB);
562 static int tda10048_read_signal_strength(struct dvb_frontend *fe,
563 u16 *signal_strength)
565 struct tda10048_state *state = fe->demodulator_priv;
568 dprintk(1, "%s()\n", __func__);
570 v = tda10048_readreg(state, TDA10048_NP_OUT);
572 *signal_strength = 100;
574 /* TODO: Apply .db math for correct values */
575 *signal_strength = v;
581 static int tda10048_read_snr(struct dvb_frontend *fe, u16 *snr)
583 struct tda10048_state *state = fe->demodulator_priv;
585 dprintk(1, "%s()\n", __func__);
587 /* TODO: This result should be the same as signal strength */
588 *snr = tda10048_readreg(state, TDA10048_NP_OUT);
593 static int tda10048_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
595 struct tda10048_state *state = fe->demodulator_priv;
597 dprintk(1, "%s()\n", __func__);
599 *ucblocks = tda10048_readreg(state, TDA10048_UNCOR_CPT_MSB) << 8 |
600 tda10048_readreg(state, TDA10048_UNCOR_CPT_LSB);
605 static int tda10048_get_frontend(struct dvb_frontend *fe,
606 struct dvb_frontend_parameters *p)
608 struct tda10048_state *state = fe->demodulator_priv;
610 dprintk(1, "%s()\n", __func__);
612 p->inversion = tda10048_readreg(state, TDA10048_CONF_C1_1)
613 & 0x20 ? INVERSION_ON : INVERSION_OFF;
615 return tda10048_get_tps(state, &p->u.ofdm);
618 static int tda10048_get_tune_settings(struct dvb_frontend *fe,
619 struct dvb_frontend_tune_settings *tune)
621 tune->min_delay_ms = 1000;
625 static void tda10048_release(struct dvb_frontend *fe)
627 struct tda10048_state *state = fe->demodulator_priv;
628 dprintk(1, "%s()\n", __func__);
632 static struct dvb_frontend_ops tda10048_ops;
634 struct dvb_frontend *tda10048_attach(const struct tda10048_config *config,
635 struct i2c_adapter *i2c)
637 struct tda10048_state *state = NULL;
639 dprintk(1, "%s()\n", __func__);
641 /* allocate memory for the internal state */
642 state = kmalloc(sizeof(struct tda10048_state), GFP_KERNEL);
646 /* setup the state */
647 state->config = config;
651 /* check if the demod is present */
652 if (tda10048_readreg(state, TDA10048_IDENTITY) != 0x048)
655 /* create dvb_frontend */
656 memcpy(&state->frontend.ops, &tda10048_ops,
657 sizeof(struct dvb_frontend_ops));
658 state->frontend.demodulator_priv = state;
660 /* Leave the gate closed */
661 tda10048_i2c_gate_ctrl(&state->frontend, 0);
663 return &state->frontend;
669 EXPORT_SYMBOL(tda10048_attach);
671 static struct dvb_frontend_ops tda10048_ops = {
674 .name = "NXP TDA10048HN DVB-T",
676 .frequency_min = 177000000,
677 .frequency_max = 858000000,
678 .frequency_stepsize = 166666,
679 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
680 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
681 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
682 FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
683 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER
686 .release = tda10048_release,
687 .init = tda10048_init,
688 .i2c_gate_ctrl = tda10048_i2c_gate_ctrl,
689 .set_frontend = tda10048_set_frontend,
690 .get_frontend = tda10048_get_frontend,
691 .get_tune_settings = tda10048_get_tune_settings,
692 .read_status = tda10048_read_status,
693 .read_ber = tda10048_read_ber,
694 .read_signal_strength = tda10048_read_signal_strength,
695 .read_snr = tda10048_read_snr,
696 .read_ucblocks = tda10048_read_ucblocks,
699 module_param(debug, int, 0644);
700 MODULE_PARM_DESC(debug, "Enable verbose debug messages");
702 MODULE_DESCRIPTION("NXP TDA10048HN DVB-T Demodulator driver");
703 MODULE_AUTHOR("Steven Toth");
704 MODULE_LICENSE("GPL");