err.no Git - linux-2.6/blob - drivers/media/dvb/frontends/dib7000p.c

   1 /*
   2  * Linux-DVB Driver for DiBcom's second generation DiB7000P (PC).
   3  *
   4  * Copyright (C) 2005-6 DiBcom (http://www.dibcom.fr/)
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License as
   8  *      published by the Free Software Foundation, version 2.
   9  */
  10 #include <linux/kernel.h>
  11 #include <linux/i2c.h>
  12
  13 #include "dvb_frontend.h"
  14
  15 #include "dib7000p.h"
  16
  17 static int debug;
  18 module_param(debug, int, 0644);
  19 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
  20
  21 #define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB7000P:"); printk(args); } } while (0)
  22
  23 struct dib7000p_state {
  24         struct dvb_frontend demod;
  25     struct dib7000p_config cfg;
  26
  27         u8 i2c_addr;
  28         struct i2c_adapter   *i2c_adap;
  29
  30         struct dibx000_i2c_master i2c_master;
  31
  32         u16 wbd_ref;
  33
  34         u8 current_band;
  35         fe_bandwidth_t current_bandwidth;
  36         struct dibx000_agc_config *current_agc;
  37         u32 timf;
  38
  39         u16 gpio_dir;
  40         u16 gpio_val;
  41 };
  42
  43 enum dib7000p_power_mode {
  44         DIB7000P_POWER_ALL = 0,
  45         DIB7000P_POWER_INTERFACE_ONLY,
  46 };
  47
  48 static u16 dib7000p_read_word(struct dib7000p_state *state, u16 reg)
  49 {
  50         u8 wb[2] = { reg >> 8, reg & 0xff };
  51         u8 rb[2];
  52         struct i2c_msg msg[2] = {
  53                 { .addr = state->i2c_addr >> 1, .flags = 0,        .buf = wb, .len = 2 },
  54                 { .addr = state->i2c_addr >> 1, .flags = I2C_M_RD, .buf = rb, .len = 2 },
  55         };
  56
  57         if (i2c_transfer(state->i2c_adap, msg, 2) != 2)
  58                 dprintk("i2c read error on %d\n",reg);
  59
  60         return (rb[0] << 8) | rb[1];
  61 }
  62
  63 static int dib7000p_write_word(struct dib7000p_state *state, u16 reg, u16 val)
  64 {
  65         u8 b[4] = {
  66                 (reg >> 8) & 0xff, reg & 0xff,
  67                 (val >> 8) & 0xff, val & 0xff,
  68         };
  69         struct i2c_msg msg = {
  70                 .addr = state->i2c_addr >> 1, .flags = 0, .buf = b, .len = 4
  71         };
  72         return i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
  73 }
  74 static int dib7000p_set_output_mode(struct dib7000p_state *state, int mode)
  75 {
  76         int    ret = 0;
  77         u16 outreg, fifo_threshold, smo_mode;
  78
  79         outreg = 0;
  80         fifo_threshold = 1792;
  81         smo_mode = (dib7000p_read_word(state, 235) & 0x0010) | (1 << 1);
  82
  83         dprintk("-I-  Setting output mode for demod %p to %d\n",
  84                         &state->demod, mode);
  85
  86         switch (mode) {
  87                 case OUTMODE_MPEG2_PAR_GATED_CLK:   // STBs with parallel gated clock
  88                         outreg = (1 << 10);  /* 0x0400 */
  89                         break;
  90                 case OUTMODE_MPEG2_PAR_CONT_CLK:    // STBs with parallel continues clock
  91                         outreg = (1 << 10) | (1 << 6); /* 0x0440 */
  92                         break;
  93                 case OUTMODE_MPEG2_SERIAL:          // STBs with serial input
  94                         outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0480 */
  95                         break;
  96                 case OUTMODE_DIVERSITY:
  97                         if (state->cfg.hostbus_diversity)
  98                                 outreg = (1 << 10) | (4 << 6); /* 0x0500 */
  99                         else
 100                                 outreg = (1 << 11);
 101                         break;
 102                 case OUTMODE_MPEG2_FIFO:            // e.g. USB feeding
 103                         smo_mode |= (3 << 1);
 104                         fifo_threshold = 512;
 105                         outreg = (1 << 10) | (5 << 6);
 106                         break;
 107                 case OUTMODE_HIGH_Z:  // disable
 108                         outreg = 0;
 109                         break;
 110                 default:
 111                         dprintk("Unhandled output_mode passed to be set for demod %p\n",&state->demod);
 112                         break;
 113         }
 114
 115         if (state->cfg.hostbus_diversity) {
 116                 ret |= dib7000p_write_word(state,  204, 1); // Diversity ?
 117                 ret |= dib7000p_write_word(state,  205, 0); // Diversity ?
 118         }
 119
 120         if (state->cfg.output_mpeg2_in_188_bytes)
 121                 smo_mode |= (1 << 5) ;
 122
 123         ret |= dib7000p_write_word(state,  235, smo_mode);
 124         ret |= dib7000p_write_word(state,  236, fifo_threshold); /* synchronous fread */
 125         ret |= dib7000p_write_word(state, 1286, outreg);         /* P_Div_active */
 126
 127         return ret;
 128 }
 129
 130 static int dib7000p_set_power_mode(struct dib7000p_state *state, enum dib7000p_power_mode mode)
 131 {
 132         /* by default everything is powered off */
 133         u16 reg_774 = 0xffff, reg_775 = 0xffff, reg_776 = 0x0007, reg_899  = 0x0003,
 134                 reg_1280 = (0xfe00) | (dib7000p_read_word(state, 1280) & 0x01ff);
 135
 136         /* now, depending on the requested mode, we power on */
 137         switch (mode) {
 138                 /* power up everything in the demod */
 139                 case DIB7000P_POWER_ALL:
 140                         reg_774 = 0x0000; reg_775 = 0x0000; reg_776 = 0x0; reg_899 = 0x0; reg_1280 &= 0x01ff;
 141                         break;
 142                 /* just leave power on the control-interfaces: GPIO and (I2C or SDIO) */
 143                 case DIB7000P_POWER_INTERFACE_ONLY: /* TODO power up either SDIO or I2C */
 144                         reg_1280 &= ~((1 << 14) | (1 << 13) | (1 << 12) | (1 << 10));
 145                         break;
 146 /* TODO following stuff is just converted from the dib7000-driver - check when is used what */
 147         }
 148
 149         dib7000p_write_word(state,  774,  reg_774);
 150         dib7000p_write_word(state,  775,  reg_775);
 151         dib7000p_write_word(state,  776,  reg_776);
 152         dib7000p_write_word(state,  899,  reg_899);
 153         dib7000p_write_word(state, 1280, reg_1280);
 154
 155         return 0;
 156 }
 157
 158 static void dib7000p_set_adc_state(struct dib7000p_state *state, enum dibx000_adc_states no)
 159 {
 160         u16 reg_908 = dib7000p_read_word(state, 908),
 161                reg_909 = dib7000p_read_word(state, 909);
 162
 163         switch (no) {
 164                 case DIBX000_SLOW_ADC_ON:
 165                         reg_909 |= (1 << 1) | (1 << 0);
 166                         dib7000p_write_word(state, 909, reg_909);
 167                         reg_909 &= ~(1 << 1);
 168                         break;
 169
 170                 case DIBX000_SLOW_ADC_OFF:
 171                         reg_909 |=  (1 << 1) | (1 << 0);
 172                         break;
 173
 174                 case DIBX000_ADC_ON:
 175                         reg_908 &= 0x0fff;
 176                         reg_909 &= 0x0003;
 177                         break;
 178
 179                 case DIBX000_ADC_OFF: // leave the VBG voltage on
 180                         reg_908 |= (1 << 14) | (1 << 13) | (1 << 12);
 181                         reg_909 |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2);
 182                         break;
 183
 184                 case DIBX000_VBG_ENABLE:
 185                         reg_908 &= ~(1 << 15);
 186                         break;
 187
 188                 case DIBX000_VBG_DISABLE:
 189                         reg_908 |= (1 << 15);
 190                         break;
 191
 192                 default:
 193                         break;
 194         }
 195
 196 //      dprintk("908: %x, 909: %x\n", reg_908, reg_909);
 197
 198         dib7000p_write_word(state, 908, reg_908);
 199         dib7000p_write_word(state, 909, reg_909);
 200 }
 201
 202 static int dib7000p_set_bandwidth(struct dvb_frontend *demod, u8 BW_Idx)
 203 {
 204         struct dib7000p_state *state = demod->demodulator_priv;
 205         u32 timf;
 206
 207         // store the current bandwidth for later use
 208         state->current_bandwidth = BW_Idx;
 209
 210         if (state->timf == 0) {
 211                 dprintk("-D-  Using default timf\n");
 212                 timf = state->cfg.bw->timf;
 213         } else {
 214                 dprintk("-D-  Using updated timf\n");
 215                 timf = state->timf;
 216         }
 217
 218         timf = timf * (BW_INDEX_TO_KHZ(BW_Idx) / 100) / 80;
 219
 220         dprintk("timf: %d\n",timf);
 221
 222         dib7000p_write_word(state, 23, (timf >> 16) & 0xffff);
 223         dib7000p_write_word(state, 24, (timf      ) & 0xffff);
 224
 225         return 0;
 226 }
 227
 228 static int dib7000p_sad_calib(struct dib7000p_state *state)
 229 {
 230 /* internal */
 231 //      dib7000p_write_word(state, 72, (3 << 14) | (1 << 12) | (524 << 0)); // sampling clock of the SAD is written in set_bandwidth
 232         dib7000p_write_word(state, 73, (0 << 1) | (0 << 0));
 233         dib7000p_write_word(state, 74, 776); // 0.625*3.3 / 4096
 234
 235         /* do the calibration */
 236         dib7000p_write_word(state, 73, (1 << 0));
 237         dib7000p_write_word(state, 73, (0 << 0));
 238
 239         msleep(1);
 240
 241         return 0;
 242 }
 243
 244 static void dib7000p_reset_pll(struct dib7000p_state *state)
 245 {
 246         struct dibx000_bandwidth_config *bw = &state->cfg.bw[0];
 247
 248         dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset);
 249         dib7000p_write_word(state, 900, ((bw->pll_ratio & 0x3f) << 9) | (bw->pll_bypass << 15) | (bw->modulo << 7) | (bw->ADClkSrc << 6) |
 250                 (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) | (bw->enable_refdiv << 1) | (0 << 0));
 251
 252         dib7000p_write_word(state, 18, ((bw->internal*1000) >> 16) & 0xffff);
 253         dib7000p_write_word(state, 19,  (bw->internal*1000       ) & 0xffff);
 254         dib7000p_write_word(state, 21,  (bw->ifreq          >> 16) & 0xffff);
 255         dib7000p_write_word(state, 22,  (bw->ifreq               ) & 0xffff);
 256
 257         dib7000p_write_word(state, 72, bw->sad_cfg);
 258 }
 259
 260 static int dib7000p_reset_gpio(struct dib7000p_state *st)
 261 {
 262         /* reset the GPIOs */
 263         dprintk("-D-  gpio dir: %x: gpio val: %x, gpio pwm pos: %x\n",st->gpio_dir, st->gpio_val,st->cfg.gpio_pwm_pos);
 264
 265         dib7000p_write_word(st, 1029, st->gpio_dir);
 266         dib7000p_write_word(st, 1030, st->gpio_val);
 267
 268         /* TODO 1031 is P_gpio_od */
 269
 270         dib7000p_write_word(st, 1032, st->cfg.gpio_pwm_pos);
 271
 272         dib7000p_write_word(st, 1037, st->cfg.pwm_freq_div);
 273         return 0;
 274 }
 275
 276 static int dib7000p_demod_reset(struct dib7000p_state *state)
 277 {
 278         dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
 279
 280         dib7000p_set_adc_state(state, DIBX000_VBG_ENABLE);
 281
 282         /* restart all parts */
 283         dib7000p_write_word(state,  770, 0xffff);
 284         dib7000p_write_word(state,  771, 0xffff);
 285         dib7000p_write_word(state,  772, 0x001f);
 286         dib7000p_write_word(state,  898, 0x0003);
 287         /* except i2c, sdio, gpio - control interfaces */
 288         dib7000p_write_word(state, 1280, 0x01fc - ((1 << 7) | (1 << 6) | (1 << 5)) );
 289
 290         dib7000p_write_word(state,  770, 0);
 291         dib7000p_write_word(state,  771, 0);
 292         dib7000p_write_word(state,  772, 0);
 293         dib7000p_write_word(state,  898, 0);
 294         dib7000p_write_word(state, 1280, 0);
 295
 296         /* default */
 297         dib7000p_reset_pll(state);
 298
 299         if (dib7000p_reset_gpio(state) != 0)
 300                 dprintk("-E-  GPIO reset was not successful.\n");
 301
 302         if (dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) != 0)
 303                 dprintk("-E-  OUTPUT_MODE could not be resetted.\n");
 304
 305         /* unforce divstr regardless whether i2c enumeration was done or not */
 306         dib7000p_write_word(state, 1285, dib7000p_read_word(state, 1285) & ~(1 << 1) );
 307
 308         dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
 309
 310         return 0;
 311 }
 312
 313 static void dib7000p_restart_agc(struct dib7000p_state *state)
 314 {
 315         // P_restart_iqc & P_restart_agc
 316         dib7000p_write_word(state, 770, 0x0c00);
 317         dib7000p_write_word(state, 770, 0x0000);
 318 }
 319
 320 static void dib7000p_update_lna(struct dib7000p_state *state)
 321 {
 322         int i;
 323         u16 dyn_gain;
 324
 325         // when there is no LNA to program return immediatly
 326         if (state->cfg.update_lna == NULL)
 327                 return;
 328
 329         for (i = 0; i < 5; i++) {
 330                 // read dyn_gain here (because it is demod-dependent and not tuner)
 331                 dyn_gain = dib7000p_read_word(state, 394);
 332
 333                 if (state->cfg.update_lna(&state->demod,dyn_gain)) { // LNA has changed
 334                         dib7000p_restart_agc(state);
 335                         msleep(5);
 336                 } else
 337                         break;
 338         }
 339 }
 340
 341 static void dib7000p_pll_clk_cfg(struct dib7000p_state *state)
 342 {
 343         u16 tmp = 0;
 344         tmp = dib7000p_read_word(state, 903);
 345         dib7000p_write_word(state, 903, (tmp | 0x1));   //pwr-up pll
 346         tmp = dib7000p_read_word(state, 900);
 347         dib7000p_write_word(state, 900, (tmp & 0x7fff) | (1 << 6));     //use High freq clock
 348 }
 349
 350 static void dib7000p_update_timf_freq(struct dib7000p_state *state)
 351 {
 352         u32 timf = (dib7000p_read_word(state, 427) << 16) | dib7000p_read_word(state, 428);
 353         state->timf = timf * 80 / (BW_INDEX_TO_KHZ(state->current_bandwidth) / 100);
 354         dib7000p_write_word(state, 23, (u16) (timf >> 16));
 355         dib7000p_write_word(state, 24, (u16) (timf & 0xffff));
 356         dprintk("-D-  Updated timf_frequency: %d (default: %d)\n",state->timf, state->cfg.bw->timf);
 357 }
 358
 359 static void dib7000p_set_channel(struct dib7000p_state *state, struct dibx000_ofdm_channel *ch, u8 seq)
 360 {
 361         u16 tmp, est[4]; // reg_26, reg_32, reg_33, reg_187, reg_188, reg_189, reg_190, reg_207, reg_208;
 362
 363         /* nfft, guard, qam, alpha */
 364         dib7000p_write_word(state, 0, (ch->nfft << 7) | (ch->guard << 5) | (ch->nqam << 3) | (ch->vit_alpha));
 365         dib7000p_write_word(state, 5, (seq << 4) | 1); /* do not force tps, search list 0 */
 366
 367         /* P_dintl_native, P_dintlv_inv, P_vit_hrch, P_vit_code_rate, P_vit_select_hp */
 368         tmp = (ch->intlv_native << 6) | (ch->vit_hrch << 4) | (ch->vit_select_hp & 0x1);
 369         if (ch->vit_hrch == 0 || ch->vit_select_hp == 1)
 370                 tmp |= (ch->vit_code_rate_hp << 1);
 371         else
 372                 tmp |= (ch->vit_code_rate_lp << 1);
 373         dib7000p_write_word(state, 208, tmp);
 374
 375         /* P_dvsy_sync_wait */
 376         switch (ch->nfft) {
 377                 case 1: tmp = 256; break;
 378                 case 2: tmp = 128; break;
 379                 case 0:
 380                 default: tmp = 64; break;
 381         }
 382         tmp *= ((1 << (ch->guard)) * 3 / 2); // add 50% SFN margin
 383         tmp <<= 4;
 384
 385         /* deactive the possibility of diversity reception if extended interleave */
 386         /* P_dvsy_sync_mode = 0, P_dvsy_sync_enable=1, P_dvcb_comb_mode=2 */
 387         if (ch->intlv_native || ch->nfft == 1)
 388                 tmp |= (1 << 2) | (2 << 0);
 389         dib7000p_write_word(state, 207, tmp);
 390
 391         dib7000p_write_word(state, 26, 0x6680);   // timf(6xxx)
 392         dib7000p_write_word(state, 29, 0x1273);   // isi inh1273 on1073
 393         dib7000p_write_word(state, 32, 0x0003);   // pha_off_max(xxx3)
 394         dib7000p_write_word(state, 33, 0x0005);   // sfreq(xxx5)
 395
 396         /* channel estimation fine configuration */
 397         switch (ch->nqam) {
 398                 case 2:
 399                         est[0] = 0x0148;       /* P_adp_regul_cnt 0.04 */
 400                         est[1] = 0xfff0;       /* P_adp_noise_cnt -0.002 */
 401                         est[2] = 0x00a4;       /* P_adp_regul_ext 0.02 */
 402                         est[3] = 0xfff8;       /* P_adp_noise_ext -0.001 */
 403                         break;
 404                 case 1:
 405                         est[0] = 0x023d;       /* P_adp_regul_cnt 0.07 */
 406                         est[1] = 0xffdf;       /* P_adp_noise_cnt -0.004 */
 407                         est[2] = 0x00a4;       /* P_adp_regul_ext 0.02 */
 408                         est[3] = 0xfff0;       /* P_adp_noise_ext -0.002 */
 409                         break;
 410                 default:
 411                         est[0] = 0x099a;       /* P_adp_regul_cnt 0.3 */
 412                         est[1] = 0xffae;       /* P_adp_noise_cnt -0.01 */
 413                         est[2] = 0x0333;       /* P_adp_regul_ext 0.1 */
 414                         est[3] = 0xfff8;       /* P_adp_noise_ext -0.002 */
 415                         break;
 416         }
 417         for (tmp = 0; tmp < 4; tmp++)
 418                 dib7000p_write_word(state, 187 + tmp, est[tmp]);
 419
 420         // set power-up level: interf+analog+AGC
 421         dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
 422         dib7000p_set_adc_state(state, DIBX000_ADC_ON);
 423         dib7000p_pll_clk_cfg(state);
 424         msleep(7);
 425
 426         // AGC initialization
 427         if (state->cfg.agc_control)
 428                 state->cfg.agc_control(&state->demod, 1);
 429
 430         dib7000p_restart_agc(state);
 431
 432         // wait AGC rough lock time
 433         msleep(5);
 434
 435         dib7000p_update_lna(state);
 436
 437         // wait AGC accurate lock time
 438         msleep(7);
 439         if (state->cfg.agc_control)
 440                 state->cfg.agc_control(&state->demod, 0);
 441 }
 442
 443 static int dib7000p_autosearch_start(struct dvb_frontend *demod, struct dibx000_ofdm_channel *ch)
 444 {
 445         struct dib7000p_state *state = demod->demodulator_priv;
 446         struct dibx000_ofdm_channel auto_ch;
 447         u32 value;
 448
 449         INIT_OFDM_CHANNEL(&auto_ch);
 450         auto_ch.RF_kHz           = ch->RF_kHz;
 451         auto_ch.Bw               = ch->Bw;
 452         auto_ch.nqam             = 2;
 453         auto_ch.guard            = 0;
 454         auto_ch.nfft             = 1;
 455         auto_ch.vit_alpha        = 1;
 456         auto_ch.vit_select_hp    = 1;
 457         auto_ch.vit_code_rate_hp = 2;
 458         auto_ch.vit_code_rate_lp = 3;
 459         auto_ch.vit_hrch         = 0;
 460         auto_ch.intlv_native     = 1;
 461
 462         dib7000p_set_channel(state, &auto_ch, 7);
 463
 464         // always use the setting for 8MHz here lock_time for 7,6 MHz are longer
 465         value = 30 * state->cfg.bw->internal;
 466         dib7000p_write_word(state, 6,  (u16) ((value >> 16) & 0xffff)); // lock0 wait time
 467         dib7000p_write_word(state, 7,  (u16)  (value        & 0xffff)); // lock0 wait time
 468         value = 100 * state->cfg.bw->internal;
 469         dib7000p_write_word(state, 8,  (u16) ((value >> 16) & 0xffff)); // lock1 wait time
 470         dib7000p_write_word(state, 9,  (u16)  (value        & 0xffff)); // lock1 wait time
 471         value = 500 * state->cfg.bw->internal;
 472         dib7000p_write_word(state, 10, (u16) ((value >> 16) & 0xffff)); // lock2 wait time
 473         dib7000p_write_word(state, 11, (u16)  (value        & 0xffff)); // lock2 wait time
 474
 475         value = dib7000p_read_word(state, 0);
 476         dib7000p_write_word(state, 0, (1 << 9) | value);
 477         dib7000p_read_word(state, 1284);
 478         dib7000p_write_word(state, 0, (u16) value);
 479
 480         return 0;
 481 }
 482
 483 static int dib7000p_autosearch_is_irq(struct dvb_frontend *demod)
 484 {
 485         struct dib7000p_state *state = demod->demodulator_priv;
 486         u16 irq_pending = dib7000p_read_word(state, 1284);
 487
 488         if (irq_pending & 0x1) // failed
 489                 return 1;
 490
 491         if (irq_pending & 0x2) // succeeded
 492                 return 2;
 493
 494         return 0; // still pending
 495 }
 496
 497 static int dib7000p_tune(struct dvb_frontend *demod, struct dibx000_ofdm_channel *ch)
 498 {
 499         struct dib7000p_state *state = demod->demodulator_priv;
 500         u16 tmp = 0;
 501
 502         if (ch != NULL)
 503                 dib7000p_set_channel(state, ch, 0);
 504         else
 505                 return -EINVAL;
 506
 507         // restart demod
 508         dib7000p_write_word(state, 770, 0x4000);
 509         dib7000p_write_word(state, 770, 0x0000);
 510         msleep(45);
 511
 512         /* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3, P_ctrl_inh_cor4=1, P_ctrl_alpha_cor4=3 */
 513         dib7000p_write_word(state, 29, (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x3));
 514
 515         // never achieved a lock with that bandwidth so far - wait for osc-freq to update
 516         if (state->timf == 0)
 517                 msleep(200);
 518
 519         /* offset loop parameters */
 520
 521         /* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */
 522         tmp = (6 << 8) | 0x80;
 523         switch (ch->nfft) {
 524                 case 0: tmp |= (7 << 12); break;
 525                 case 1: tmp |= (9 << 12); break;
 526                 case 2: tmp |= (8 << 12); break;
 527         }
 528         dib7000p_write_word(state, 26, tmp);  /* timf_a(6xxx) */
 529
 530         /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */
 531         tmp = (0 << 4);
 532         switch (ch->nfft) {
 533                 case 0: tmp |= 0x6; break;
 534                 case 1: tmp |= 0x8; break;
 535                 case 2: tmp |= 0x7; break;
 536         }
 537         dib7000p_write_word(state, 32,  tmp);
 538
 539         /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */
 540         tmp = (0 << 4);
 541         switch (ch->nfft) {
 542                 case 0: tmp |= 0x6; break;
 543                 case 1: tmp |= 0x8; break;
 544                 case 2: tmp |= 0x7; break;
 545         }
 546         dib7000p_write_word(state, 33,  tmp);
 547
 548         tmp = dib7000p_read_word(state,509);
 549         if (!((tmp >> 6) & 0x1)) {
 550                 /* restart the fec */
 551                 tmp = dib7000p_read_word(state,771);
 552                 dib7000p_write_word(state, 771, tmp | (1 << 1));
 553                 dib7000p_write_word(state, 771, tmp);
 554                 msleep(10);
 555                 tmp = dib7000p_read_word(state,509);
 556         }
 557
 558         // we achieved a lock - it's time to update the osc freq
 559         if ((tmp >> 6) & 0x1)
 560                 dib7000p_update_timf_freq(state);
 561
 562         return 0;
 563 }
 564
 565 static int dib7000p_init(struct dvb_frontend *demod)
 566 {
 567         struct dibx000_agc_config *agc;
 568         struct dib7000p_state *state = demod->demodulator_priv;
 569         int ret = 0;
 570
 571         // Demodulator default configuration
 572         agc = state->cfg.agc;
 573
 574         dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
 575         dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON);
 576
 577         /* AGC */
 578         ret |= dib7000p_write_word(state, 75 ,  agc->setup );
 579         ret |= dib7000p_write_word(state, 76 ,  agc->inv_gain );
 580         ret |= dib7000p_write_word(state, 77 ,  agc->time_stabiliz );
 581         ret |= dib7000p_write_word(state, 100, (agc->alpha_level << 12) | agc->thlock);
 582
 583         // Demod AGC loop configuration
 584         ret |= dib7000p_write_word(state, 101, (agc->alpha_mant << 5) | agc->alpha_exp);
 585         ret |= dib7000p_write_word(state, 102, (agc->beta_mant << 6)  | agc->beta_exp);
 586
 587         /* AGC continued */
 588         dprintk("-D-  WBD: ref: %d, sel: %d, active: %d, alpha: %d\n",
 589                 state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
 590
 591         if (state->wbd_ref != 0)
 592                 ret |= dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | state->wbd_ref);
 593         else
 594                 ret |= dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | agc->wbd_ref);
 595
 596         ret |= dib7000p_write_word(state, 106, (agc->wbd_sel << 13) | (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8) );
 597
 598         ret |= dib7000p_write_word(state, 107,  agc->agc1_max);
 599         ret |= dib7000p_write_word(state, 108,  agc->agc1_min);
 600         ret |= dib7000p_write_word(state, 109,  agc->agc2_max);
 601         ret |= dib7000p_write_word(state, 110,  agc->agc2_min);
 602         ret |= dib7000p_write_word(state, 111, (agc->agc1_pt1 << 8) | agc->agc1_pt2 );
 603         ret |= dib7000p_write_word(state, 112,  agc->agc1_pt3);
 604         ret |= dib7000p_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
 605         ret |= dib7000p_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
 606         ret |= dib7000p_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
 607
 608         /* disable power smoothing */
 609         ret |= dib7000p_write_word(state, 145, 0);
 610         ret |= dib7000p_write_word(state, 146, 0);
 611         ret |= dib7000p_write_word(state, 147, 0);
 612         ret |= dib7000p_write_word(state, 148, 0);
 613         ret |= dib7000p_write_word(state, 149, 0);
 614         ret |= dib7000p_write_word(state, 150, 0);
 615         ret |= dib7000p_write_word(state, 151, 0);
 616         ret |= dib7000p_write_word(state, 152, 0);
 617
 618         // P_timf_alpha=6, P_corm_alpha=6, P_corm_thres=128 default: 6,4,26
 619         ret |= dib7000p_write_word(state, 26 ,0x6680);
 620
 621         // P_palf_filter_on=1, P_palf_filter_freeze=0, P_palf_alpha_regul=16
 622         ret |= dib7000p_write_word(state, 142,0x0410);
 623         // P_fft_freq_dir=1, P_fft_nb_to_cut=0
 624         ret |= dib7000p_write_word(state, 154,1 << 13);
 625         // P_pha3_thres, default 0x3000
 626         ret |= dib7000p_write_word(state, 168,0x0ccd);
 627         // P_cti_use_cpe=0, P_cti_use_prog=0, P_cti_win_len=16, default: 0x0010
 628         //ret |= dib7000p_write_word(state, 169,0x0010);
 629         // P_cspu_regul=512, P_cspu_win_cut=15, default: 0x2005
 630         ret |= dib7000p_write_word(state, 183,0x200f);
 631         // P_adp_regul_cnt=573, default: 410
 632         ret |= dib7000p_write_word(state, 187,0x023d);
 633         // P_adp_noise_cnt=
 634         ret |= dib7000p_write_word(state, 188,0x00a4);
 635         // P_adp_regul_ext
 636         ret |= dib7000p_write_word(state, 189,0x00a4);
 637         // P_adp_noise_ext
 638         ret |= dib7000p_write_word(state, 190,0x7ff0);
 639         // P_adp_fil
 640         ret |= dib7000p_write_word(state, 191,0x3ccc);
 641
 642         ret |= dib7000p_write_word(state, 222,0x0010);
 643         // P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard
 644         ret |= dib7000p_write_word(state, 235,0x0062);
 645
 646         // P_iqc_alpha_pha, P_iqc_alpha_amp_dcc_alpha, ...
 647         if(state->cfg.tuner_is_baseband)
 648                 ret |= dib7000p_write_word(state, 36,0x0755);
 649         else
 650                 ret |= dib7000p_write_word(state, 36,0x1f55);
 651
 652         // auto search configuration
 653         ret |= dib7000p_write_word(state, 2  ,0x0004);
 654         ret |= dib7000p_write_word(state, 3  ,0x1000);
 655
 656         /* Equal Lock */
 657         ret |= dib7000p_write_word(state, 4   ,0x0814);
 658
 659         ret |= dib7000p_write_word(state, 6  ,0x001b);
 660         ret |= dib7000p_write_word(state, 7  ,0x7740);
 661         ret |= dib7000p_write_word(state, 8  ,0x005b);
 662         ret |= dib7000p_write_word(state, 9  ,0x8d80);
 663         ret |= dib7000p_write_word(state, 10 ,0x01c9);
 664         ret |= dib7000p_write_word(state, 11 ,0xc380);
 665         ret |= dib7000p_write_word(state, 12 ,0x0000);
 666         ret |= dib7000p_write_word(state, 13 ,0x0080);
 667         ret |= dib7000p_write_word(state, 14 ,0x0000);
 668         ret |= dib7000p_write_word(state, 15 ,0x0090);
 669         ret |= dib7000p_write_word(state, 16 ,0x0001);
 670         ret |= dib7000p_write_word(state, 17 ,0xd4c0);
 671
 672         // P_clk_cfg1
 673         ret |= dib7000p_write_word(state, 901, 0x0006);
 674
 675         // P_divclksel=3 P_divbitsel=1
 676         ret |= dib7000p_write_word(state, 902, (3 << 10) | (1 << 6));
 677
 678         // Tuner IO bank: max drive (14mA) + divout pads max drive
 679         ret |= dib7000p_write_word(state, 905, 0x2c8e);
 680
 681         ret |= dib7000p_set_bandwidth(&state->demod, BANDWIDTH_8_MHZ);
 682         dib7000p_sad_calib(state);
 683
 684         return ret;
 685 }
 686
 687 static int dib7000p_sleep(struct dvb_frontend *demod)
 688 {
 689         struct dib7000p_state *state = demod->demodulator_priv;
 690         return dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
 691 }
 692
 693 static int dib7000p_identify(struct dib7000p_state *st)
 694 {
 695         u16 value;
 696         dprintk("-I-  DiB7000PC: checking demod on I2C address: %d (%x)\n",
 697                 st->i2c_addr, st->i2c_addr);
 698
 699         if ((value = dib7000p_read_word(st, 768)) != 0x01b3) {
 700                 dprintk("-E-  DiB7000PC: wrong Vendor ID (read=0x%x)\n",value);
 701                 return -EREMOTEIO;
 702         }
 703
 704         if ((value = dib7000p_read_word(st, 769)) != 0x4000) {
 705                 dprintk("-E-  DiB7000PC: wrong Device ID (%x)\n",value);
 706                 return -EREMOTEIO;
 707         }
 708
 709         return 0;
 710 }
 711
 712
 713 static int dib7000p_get_frontend(struct dvb_frontend* fe,
 714                                 struct dvb_frontend_parameters *fep)
 715 {
 716         struct dib7000p_state *state = fe->demodulator_priv;
 717         u16 tps = dib7000p_read_word(state,463);
 718
 719         fep->inversion = INVERSION_AUTO;
 720
 721         fep->u.ofdm.bandwidth = state->current_bandwidth;
 722
 723         switch ((tps >> 8) & 0x3) {
 724                 case 0: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K; break;
 725                 case 1: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; break;
 726                 /* case 2: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_4K; break; */
 727         }
 728
 729         switch (tps & 0x3) {
 730                 case 0: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_32; break;
 731                 case 1: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_16; break;
 732                 case 2: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_8; break;
 733                 case 3: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_4; break;
 734         }
 735
 736         switch ((tps >> 14) & 0x3) {
 737                 case 0: fep->u.ofdm.constellation = QPSK; break;
 738                 case 1: fep->u.ofdm.constellation = QAM_16; break;
 739                 case 2:
 740                 default: fep->u.ofdm.constellation = QAM_64; break;
 741         }
 742
 743         /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */
 744         /* (tps >> 13) & 0x1 == hrch is used, (tps >> 10) & 0x7 == alpha */
 745
 746         fep->u.ofdm.hierarchy_information = HIERARCHY_NONE;
 747         switch ((tps >> 5) & 0x7) {
 748                 case 1: fep->u.ofdm.code_rate_HP = FEC_1_2; break;
 749                 case 2: fep->u.ofdm.code_rate_HP = FEC_2_3; break;
 750                 case 3: fep->u.ofdm.code_rate_HP = FEC_3_4; break;
 751                 case 5: fep->u.ofdm.code_rate_HP = FEC_5_6; break;
 752                 case 7:
 753                 default: fep->u.ofdm.code_rate_HP = FEC_7_8; break;
 754
 755         }
 756
 757         switch ((tps >> 2) & 0x7) {
 758                 case 1: fep->u.ofdm.code_rate_LP = FEC_1_2; break;
 759                 case 2: fep->u.ofdm.code_rate_LP = FEC_2_3; break;
 760                 case 3: fep->u.ofdm.code_rate_LP = FEC_3_4; break;
 761                 case 5: fep->u.ofdm.code_rate_LP = FEC_5_6; break;
 762                 case 7:
 763                 default: fep->u.ofdm.code_rate_LP = FEC_7_8; break;
 764         }
 765
 766         /* native interleaver: (dib7000p_read_word(state, 464) >>  5) & 0x1 */
 767
 768         return 0;
 769 }
 770
 771 static int dib7000p_set_frontend(struct dvb_frontend* fe,
 772                                 struct dvb_frontend_parameters *fep)
 773 {
 774         struct dib7000p_state *state = fe->demodulator_priv;
 775         struct dibx000_ofdm_channel ch;
 776
 777         INIT_OFDM_CHANNEL(&ch);
 778         FEP2DIB(fep,&ch);
 779
 780         state->current_bandwidth = fep->u.ofdm.bandwidth;
 781         dib7000p_set_bandwidth(fe, fep->u.ofdm.bandwidth);
 782
 783         if (fe->ops.tuner_ops.set_params)
 784                 fe->ops.tuner_ops.set_params(fe, fep);
 785
 786         if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO ||
 787                 fep->u.ofdm.guard_interval    == GUARD_INTERVAL_AUTO ||
 788                 fep->u.ofdm.constellation     == QAM_AUTO ||
 789                 fep->u.ofdm.code_rate_HP      == FEC_AUTO) {
 790                 int i = 800, found;
 791
 792                 dib7000p_autosearch_start(fe, &ch);
 793                 do {
 794                         msleep(1);
 795                         found = dib7000p_autosearch_is_irq(fe);
 796                 } while (found == 0 && i--);
 797
 798                 dprintk("autosearch returns: %d\n",found);
 799                 if (found == 0 || found == 1)
 800                         return 0; // no channel found
 801
 802                 dib7000p_get_frontend(fe, fep);
 803                 FEP2DIB(fep, &ch);
 804         }
 805
 806         /* make this a config parameter */
 807         dib7000p_set_output_mode(state, OUTMODE_MPEG2_FIFO);
 808
 809         return dib7000p_tune(fe, &ch);
 810 }
 811
 812 static int dib7000p_read_status(struct dvb_frontend *fe, fe_status_t *stat)
 813 {
 814         struct dib7000p_state *state = fe->demodulator_priv;
 815         u16 lock = dib7000p_read_word(state, 509);
 816
 817         *stat = 0;
 818
 819         if (lock & 0x8000)
 820                 *stat |= FE_HAS_SIGNAL;
 821         if (lock & 0x3000)
 822                 *stat |= FE_HAS_CARRIER;
 823         if (lock & 0x0100)
 824                 *stat |= FE_HAS_VITERBI;
 825         if (lock & 0x0010)
 826                 *stat |= FE_HAS_SYNC;
 827         if (lock & 0x0008)
 828                 *stat |= FE_HAS_LOCK;
 829
 830         return 0;
 831 }
 832
 833 static int dib7000p_read_ber(struct dvb_frontend *fe, u32 *ber)
 834 {
 835         struct dib7000p_state *state = fe->demodulator_priv;
 836         *ber = (dib7000p_read_word(state, 500) << 16) | dib7000p_read_word(state, 501);
 837         return 0;
 838 }
 839
 840 static int dib7000p_read_unc_blocks(struct dvb_frontend *fe, u32 *unc)
 841 {
 842         struct dib7000p_state *state = fe->demodulator_priv;
 843         *unc = dib7000p_read_word(state, 506);
 844         return 0;
 845 }
 846
 847 static int dib7000p_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
 848 {
 849         struct dib7000p_state *state = fe->demodulator_priv;
 850         u16 val = dib7000p_read_word(state, 394);
 851         *strength = 65535 - val;
 852         return 0;
 853 }
 854
 855 static int dib7000p_read_snr(struct dvb_frontend* fe, u16 *snr)
 856 {
 857         *snr = 0x0000;
 858         return 0;
 859 }
 860
 861 static int dib7000p_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
 862 {
 863         tune->min_delay_ms = 1000;
 864         return 0;
 865 }
 866
 867 static void dib7000p_release(struct dvb_frontend *demod)
 868 {
 869         struct dib7000p_state *st = demod->demodulator_priv;
 870         dibx000_exit_i2c_master(&st->i2c_master);
 871         kfree(st);
 872 }
 873
 874 int dib7000pc_detection(struct i2c_adapter *i2c_adap)
 875 {
 876         u8 tx[2], rx[2];
 877         struct i2c_msg msg[2] = {
 878                 { .addr = 18 >> 1, .flags = 0,        .buf = tx, .len = 2 },
 879                 { .addr = 18 >> 1, .flags = I2C_M_RD, .buf = rx, .len = 2 },
 880         };
 881
 882         tx[0] = 0x03;
 883         tx[1] = 0x00;
 884
 885         if (i2c_transfer(i2c_adap, msg, 2) == 2)
 886                 if (rx[0] == 0x01 && rx[1] == 0xb3) {
 887                         dprintk("-D-  DiB7000PC detected\n");
 888                         return 1;
 889                 }
 890
 891         msg[0].addr = msg[1].addr = 0x40;
 892
 893         if (i2c_transfer(i2c_adap, msg, 2) == 2)
 894                 if (rx[0] == 0x01 && rx[1] == 0xb3) {
 895                         dprintk("-D-  DiB7000PC detected\n");
 896                         return 1;
 897                 }
 898
 899         dprintk("-D-  DiB7000PC not detected\n");
 900         return 0;
 901 }
 902 EXPORT_SYMBOL(dib7000pc_detection);
 903
 904 struct i2c_adapter * dib7000p_get_i2c_master(struct dvb_frontend *demod, enum dibx000_i2c_interface intf, int gating)
 905 {
 906         struct dib7000p_state *st = demod->demodulator_priv;
 907         return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
 908 }
 909 EXPORT_SYMBOL(dib7000p_get_i2c_master);
 910
 911 int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib7000p_config cfg[])
 912 {
 913         struct dib7000p_state st = { .i2c_adap = i2c };
 914         int k = 0;
 915         u8 new_addr = 0;
 916
 917         for (k = no_of_demods-1; k >= 0; k--) {
 918                 st.cfg = cfg[k];
 919
 920                 /* designated i2c address */
 921                 new_addr          = (0x40 + k) << 1;
 922                 st.i2c_addr = new_addr;
 923                 if (dib7000p_identify(&st) != 0) {
 924                         st.i2c_addr = default_addr;
 925                         if (dib7000p_identify(&st) != 0) {
 926                                 dprintk("DiB7000P #%d: not identified\n", k);
 927                                 return -EIO;
 928                         }
 929                 }
 930
 931                 /* start diversity to pull_down div_str - just for i2c-enumeration */
 932                 dib7000p_set_output_mode(&st, OUTMODE_DIVERSITY);
 933
 934                 /* set new i2c address and force divstart */
 935                 dib7000p_write_word(&st, 1285, (new_addr << 2) | 0x2);
 936
 937                 dprintk("IC %d initialized (to i2c_address 0x%x)\n", k, new_addr);
 938         }
 939
 940         for (k = 0; k < no_of_demods; k++) {
 941                 st.cfg = cfg[k];
 942                 st.i2c_addr = (0x40 + k) << 1;
 943
 944                 // unforce divstr
 945                 dib7000p_write_word(&st, 1285, st.i2c_addr << 2);
 946
 947                 /* deactivate div - it was just for i2c-enumeration */
 948                 dib7000p_set_output_mode(&st, OUTMODE_HIGH_Z);
 949         }
 950
 951         return 0;
 952 }
 953 EXPORT_SYMBOL(dib7000p_i2c_enumeration);
 954
 955 static struct dvb_frontend_ops dib7000p_ops;
 956 struct dvb_frontend * dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg)
 957 {
 958         struct dvb_frontend *demod;
 959         struct dib7000p_state *st;
 960         st = kzalloc(sizeof(struct dib7000p_state), GFP_KERNEL);
 961         if (st == NULL)
 962                 return NULL;
 963
 964         memcpy(&st->cfg, cfg, sizeof(struct dib7000p_config));
 965         st->i2c_adap = i2c_adap;
 966         st->i2c_addr = i2c_addr;
 967         st->gpio_val = cfg->gpio_val;
 968         st->gpio_dir = cfg->gpio_dir;
 969
 970         demod                   = &st->demod;
 971         demod->demodulator_priv = st;
 972         memcpy(&st->demod.ops, &dib7000p_ops, sizeof(struct dvb_frontend_ops));
 973
 974         if (dib7000p_identify(st) != 0)
 975                 goto error;
 976
 977         dibx000_init_i2c_master(&st->i2c_master, DIB7000P, st->i2c_adap, st->i2c_addr);
 978
 979         dib7000p_demod_reset(st);
 980
 981         return demod;
 982
 983 error:
 984         kfree(st);
 985         return NULL;
 986 }
 987 EXPORT_SYMBOL(dib7000p_attach);
 988
 989 static struct dvb_frontend_ops dib7000p_ops = {
 990         .info = {
 991                 .name = "DiBcom 7000PC",
 992                 .type = FE_OFDM,
 993                 .frequency_min      = 44250000,
 994                 .frequency_max      = 867250000,
 995                 .frequency_stepsize = 62500,
 996                 .caps = FE_CAN_INVERSION_AUTO |
 997                         FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
 998                         FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
 999                         FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1000                         FE_CAN_TRANSMISSION_MODE_AUTO |
1001                         FE_CAN_GUARD_INTERVAL_AUTO |
1002                         FE_CAN_RECOVER |
1003                         FE_CAN_HIERARCHY_AUTO,
1004         },
1005
1006         .release              = dib7000p_release,
1007
1008         .init                 = dib7000p_init,
1009         .sleep                = dib7000p_sleep,
1010
1011         .set_frontend         = dib7000p_set_frontend,
1012         .get_tune_settings    = dib7000p_fe_get_tune_settings,
1013         .get_frontend         = dib7000p_get_frontend,
1014
1015         .read_status          = dib7000p_read_status,
1016         .read_ber             = dib7000p_read_ber,
1017         .read_signal_strength = dib7000p_read_signal_strength,
1018         .read_snr             = dib7000p_read_snr,
1019         .read_ucblocks        = dib7000p_read_unc_blocks,
1020 };
1021
1022 MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
1023 MODULE_DESCRIPTION("Driver for the DiBcom 7000PC COFDM demodulator");
1024 MODULE_LICENSE("GPL");