2 * Driver for DiBcom DiB3000MC/P-demodulator.
4 * Copyright (C) 2004-7 DiBcom (http://www.dibcom.fr/)
5 * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@desy.de)
7 * This code is partially based on the previous dib3000mc.c .
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation, version 2.
14 #include <linux/kernel.h>
15 #include <linux/i2c.h>
16 //#include <linux/init.h>
17 //#include <linux/delay.h>
18 //#include <linux/string.h>
19 //#include <linux/slab.h>
21 #include "dvb_frontend.h"
23 #include "dib3000mc.h"
26 module_param(debug, int, 0644);
27 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
29 #define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB3000MC/P:"); printk(args); printk("\n"); } } while (0)
31 struct dib3000mc_state {
32 struct dvb_frontend demod;
33 struct dib3000mc_config *cfg;
36 struct i2c_adapter *i2c_adap;
38 struct dibx000_i2c_master i2c_master;
42 fe_bandwidth_t current_bandwidth;
47 static u16 dib3000mc_read_word(struct dib3000mc_state *state, u16 reg)
49 u8 wb[2] = { (reg >> 8) | 0x80, reg & 0xff };
51 struct i2c_msg msg[2] = {
52 { .addr = state->i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2 },
53 { .addr = state->i2c_addr >> 1, .flags = I2C_M_RD, .buf = rb, .len = 2 },
56 if (i2c_transfer(state->i2c_adap, msg, 2) != 2)
57 dprintk("i2c read error on %d\n",reg);
59 return (rb[0] << 8) | rb[1];
62 static int dib3000mc_write_word(struct dib3000mc_state *state, u16 reg, u16 val)
65 (reg >> 8) & 0xff, reg & 0xff,
66 (val >> 8) & 0xff, val & 0xff,
68 struct i2c_msg msg = {
69 .addr = state->i2c_addr >> 1, .flags = 0, .buf = b, .len = 4
71 return i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
74 static int dib3000mc_identify(struct dib3000mc_state *state)
77 if ((value = dib3000mc_read_word(state, 1025)) != 0x01b3) {
78 dprintk("-E- DiB3000MC/P: wrong Vendor ID (read=0x%x)\n",value);
82 value = dib3000mc_read_word(state, 1026);
83 if (value != 0x3001 && value != 0x3002) {
84 dprintk("-E- DiB3000MC/P: wrong Device ID (%x)\n",value);
87 state->dev_id = value;
89 dprintk("-I- found DiB3000MC/P: %x\n",state->dev_id);
94 static int dib3000mc_set_timing(struct dib3000mc_state *state, s16 nfft, u32 bw, u8 update_offset)
98 if (state->timf == 0) {
99 timf = 1384402; // default value for 8MHz
101 msleep(200); // first time we do an update
108 s16 tim_offs = dib3000mc_read_word(state, 416);
110 if (tim_offs & 0x2000)
113 if (nfft == TRANSMISSION_MODE_2K)
117 state->timf = timf / (bw / 1000);
120 dprintk("timf: %d\n", timf);
122 dib3000mc_write_word(state, 23, (u16) (timf >> 16));
123 dib3000mc_write_word(state, 24, (u16) (timf ) & 0xffff);
128 static int dib3000mc_setup_pwm_state(struct dib3000mc_state *state)
130 u16 reg_51, reg_52 = state->cfg->agc->setup & 0xfefb;
131 if (state->cfg->pwm3_inversion) {
132 reg_51 = (2 << 14) | (0 << 10) | (7 << 6) | (2 << 2) | (2 << 0);
135 reg_51 = (2 << 14) | (4 << 10) | (7 << 6) | (2 << 2) | (2 << 0);
138 dib3000mc_write_word(state, 51, reg_51);
139 dib3000mc_write_word(state, 52, reg_52);
141 if (state->cfg->use_pwm3)
142 dib3000mc_write_word(state, 245, (1 << 3) | (1 << 0));
144 dib3000mc_write_word(state, 245, 0);
146 dib3000mc_write_word(state, 1040, 0x3);
150 static int dib3000mc_set_output_mode(struct dib3000mc_state *state, int mode)
153 u16 fifo_threshold = 1792;
157 u16 smo_reg = dib3000mc_read_word(state, 206) & 0x0010; /* keep the pid_parse bit */
159 dprintk("-I- Setting output mode for demod %p to %d\n",
160 &state->demod, mode);
163 case OUTMODE_HIGH_Z: // disable
166 case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock
169 case OUTMODE_MPEG2_PAR_CONT_CLK: // STBs with parallel continues clock
172 case OUTMODE_MPEG2_SERIAL: // STBs with serial input
175 case OUTMODE_MPEG2_FIFO: // e.g. USB feeding
178 P_smo_error_discard [1;6:6] = 0
179 P_smo_rs_discard [1;5:5] = 0
180 P_smo_pid_parse [1;4:4] = 0
181 P_smo_fifo_flush [1;3:3] = 0
182 P_smo_mode [2;2:1] = 11
183 P_smo_ovf_prot [1;0:0] = 0
186 fifo_threshold = 512;
189 case OUTMODE_DIVERSITY:
194 dprintk("Unhandled output_mode passed to be set for demod %p\n",&state->demod);
199 if ((state->cfg->output_mpeg2_in_188_bytes))
200 smo_reg |= (1 << 5); // P_smo_rs_discard [1;5:5] = 1
202 outreg = dib3000mc_read_word(state, 244) & 0x07FF;
203 outreg |= (outmode << 11);
204 ret |= dib3000mc_write_word(state, 244, outreg);
205 ret |= dib3000mc_write_word(state, 206, smo_reg); /*smo_ mode*/
206 ret |= dib3000mc_write_word(state, 207, fifo_threshold); /* synchronous fread */
207 ret |= dib3000mc_write_word(state, 1040, elecout); /* P_out_cfg */
211 static int dib3000mc_set_bandwidth(struct dib3000mc_state *state, u32 bw)
213 u16 bw_cfg[6] = { 0 };
214 u16 imp_bw_cfg[3] = { 0 };
217 /* settings here are for 27.7MHz */
220 bw_cfg[0] = 0x0019; bw_cfg[1] = 0x5c30; bw_cfg[2] = 0x0054; bw_cfg[3] = 0x88a0; bw_cfg[4] = 0x01a6; bw_cfg[5] = 0xab20;
221 imp_bw_cfg[0] = 0x04db; imp_bw_cfg[1] = 0x00db; imp_bw_cfg[2] = 0x00b7;
225 bw_cfg[0] = 0x001c; bw_cfg[1] = 0xfba5; bw_cfg[2] = 0x0060; bw_cfg[3] = 0x9c25; bw_cfg[4] = 0x01e3; bw_cfg[5] = 0x0cb7;
226 imp_bw_cfg[0] = 0x04c0; imp_bw_cfg[1] = 0x00c0; imp_bw_cfg[2] = 0x00a0;
230 bw_cfg[0] = 0x0021; bw_cfg[1] = 0xd040; bw_cfg[2] = 0x0070; bw_cfg[3] = 0xb62b; bw_cfg[4] = 0x0233; bw_cfg[5] = 0x8ed5;
231 imp_bw_cfg[0] = 0x04a5; imp_bw_cfg[1] = 0x00a5; imp_bw_cfg[2] = 0x0089;
235 bw_cfg[0] = 0x0028; bw_cfg[1] = 0x9380; bw_cfg[2] = 0x0087; bw_cfg[3] = 0x4100; bw_cfg[4] = 0x02a4; bw_cfg[5] = 0x4500;
236 imp_bw_cfg[0] = 0x0489; imp_bw_cfg[1] = 0x0089; imp_bw_cfg[2] = 0x0072;
239 default: return -EINVAL;
242 for (reg = 6; reg < 12; reg++)
243 dib3000mc_write_word(state, reg, bw_cfg[reg - 6]);
244 dib3000mc_write_word(state, 12, 0x0000);
245 dib3000mc_write_word(state, 13, 0x03e8);
246 dib3000mc_write_word(state, 14, 0x0000);
247 dib3000mc_write_word(state, 15, 0x03f2);
248 dib3000mc_write_word(state, 16, 0x0001);
249 dib3000mc_write_word(state, 17, 0xb0d0);
251 dib3000mc_write_word(state, 18, 0x0393);
252 dib3000mc_write_word(state, 19, 0x8700);
254 for (reg = 55; reg < 58; reg++)
255 dib3000mc_write_word(state, reg, imp_bw_cfg[reg - 55]);
257 // Timing configuration
258 dib3000mc_set_timing(state, TRANSMISSION_MODE_2K, bw, 0);
263 static u16 impulse_noise_val[29] =
266 0x38, 0x6d9, 0x3f28, 0x7a7, 0x3a74, 0x196, 0x32a, 0x48c, 0x3ffe, 0x7f3,
267 0x2d94, 0x76, 0x53d, 0x3ff8, 0x7e3, 0x3320, 0x76, 0x5b3, 0x3feb, 0x7d2,
268 0x365e, 0x76, 0x48c, 0x3ffe, 0x5b3, 0x3feb, 0x76, 0x0000, 0xd
271 static void dib3000mc_set_impulse_noise(struct dib3000mc_state *state, u8 mode, s16 nfft)
274 for (i = 58; i < 87; i++)
275 dib3000mc_write_word(state, i, impulse_noise_val[i-58]);
277 if (nfft == TRANSMISSION_MODE_8K) {
278 dib3000mc_write_word(state, 58, 0x3b);
279 dib3000mc_write_word(state, 84, 0x00);
280 dib3000mc_write_word(state, 85, 0x8200);
283 dib3000mc_write_word(state, 34, 0x1294);
284 dib3000mc_write_word(state, 35, 0x1ff8);
286 dib3000mc_write_word(state, 55, dib3000mc_read_word(state, 55) | (1 << 10));
289 static int dib3000mc_init(struct dvb_frontend *demod)
291 struct dib3000mc_state *state = demod->demodulator_priv;
292 struct dibx000_agc_config *agc = state->cfg->agc;
294 // Restart Configuration
295 dib3000mc_write_word(state, 1027, 0x8000);
296 dib3000mc_write_word(state, 1027, 0x0000);
298 // power up the demod + mobility configuration
299 dib3000mc_write_word(state, 140, 0x0000);
300 dib3000mc_write_word(state, 1031, 0);
302 if (state->cfg->mobile_mode) {
303 dib3000mc_write_word(state, 139, 0x0000);
304 dib3000mc_write_word(state, 141, 0x0000);
305 dib3000mc_write_word(state, 175, 0x0002);
306 dib3000mc_write_word(state, 1032, 0x0000);
308 dib3000mc_write_word(state, 139, 0x0001);
309 dib3000mc_write_word(state, 141, 0x0000);
310 dib3000mc_write_word(state, 175, 0x0000);
311 dib3000mc_write_word(state, 1032, 0x012C);
313 dib3000mc_write_word(state, 1033, 0x0000);
316 dib3000mc_write_word(state, 1037, 0x3130);
318 // other configurations
321 dib3000mc_write_word(state, 33, (5 << 0));
322 dib3000mc_write_word(state, 88, (1 << 10) | (0x10 << 0));
324 // Phase noise control
325 // P_fft_phacor_inh, P_fft_phacor_cpe, P_fft_powrange
326 dib3000mc_write_word(state, 99, (1 << 9) | (0x20 << 0));
328 if (state->cfg->phase_noise_mode == 0)
329 dib3000mc_write_word(state, 111, 0x00);
331 dib3000mc_write_word(state, 111, 0x02);
334 dib3000mc_write_word(state, 50, 0x8000);
337 dib3000mc_setup_pwm_state(state);
339 // P_agc_counter_lock
340 dib3000mc_write_word(state, 53, 0x87);
341 // P_agc_counter_unlock
342 dib3000mc_write_word(state, 54, 0x87);
345 dib3000mc_write_word(state, 36, state->cfg->max_time);
346 dib3000mc_write_word(state, 37, (state->cfg->agc_command1 << 13) | (state->cfg->agc_command2 << 12) | (0x1d << 0));
347 dib3000mc_write_word(state, 38, state->cfg->pwm3_value);
348 dib3000mc_write_word(state, 39, state->cfg->ln_adc_level);
351 dib3000mc_write_word(state, 40, 0x0179);
352 dib3000mc_write_word(state, 41, 0x03f0);
354 dib3000mc_write_word(state, 42, agc->agc1_max);
355 dib3000mc_write_word(state, 43, agc->agc1_min);
356 dib3000mc_write_word(state, 44, agc->agc2_max);
357 dib3000mc_write_word(state, 45, agc->agc2_min);
358 dib3000mc_write_word(state, 46, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
359 dib3000mc_write_word(state, 47, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
360 dib3000mc_write_word(state, 48, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
361 dib3000mc_write_word(state, 49, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
363 // Begin: TimeOut registers
365 dib3000mc_write_word(state, 110, 3277);
366 // P_timf_alpha = 6, P_corm_alpha = 6, P_corm_thres = 0x80
367 dib3000mc_write_word(state, 26, 0x6680);
369 dib3000mc_write_word(state, 1, 4);
371 dib3000mc_write_word(state, 2, 4);
373 dib3000mc_write_word(state, 3, 0x1000);
374 // P_search_maxtrial=1
375 dib3000mc_write_word(state, 5, 1);
377 dib3000mc_set_bandwidth(state, 8000);
380 dib3000mc_write_word(state, 4, 0x814);
382 dib3000mc_write_word(state, 21, (1 << 9) | 0x164);
383 dib3000mc_write_word(state, 22, 0x463d);
386 // P_cspu_regul, P_cspu_win_cut
387 dib3000mc_write_word(state, 120, 0x200f);
389 dib3000mc_write_word(state, 134, 0);
392 dib3000mc_write_word(state, 195, 0x10);
394 // diversity register: P_dvsy_sync_wait..
395 dib3000mc_write_word(state, 180, 0x2FF0);
397 // Impulse noise configuration
398 dib3000mc_set_impulse_noise(state, 0, TRANSMISSION_MODE_8K);
400 // output mode set-up
401 dib3000mc_set_output_mode(state, OUTMODE_HIGH_Z);
403 /* close the i2c-gate */
404 dib3000mc_write_word(state, 769, (1 << 7) );
409 static int dib3000mc_sleep(struct dvb_frontend *demod)
411 struct dib3000mc_state *state = demod->demodulator_priv;
413 dib3000mc_write_word(state, 1031, 0xFFFF);
414 dib3000mc_write_word(state, 1032, 0xFFFF);
415 dib3000mc_write_word(state, 1033, 0xFFF0);
420 static void dib3000mc_set_adp_cfg(struct dib3000mc_state *state, s16 qam)
422 u16 cfg[4] = { 0 },reg;
425 cfg[0] = 0x099a; cfg[1] = 0x7fae; cfg[2] = 0x0333; cfg[3] = 0x7ff0;
428 cfg[0] = 0x023d; cfg[1] = 0x7fdf; cfg[2] = 0x00a4; cfg[3] = 0x7ff0;
431 cfg[0] = 0x0148; cfg[1] = 0x7ff0; cfg[2] = 0x00a4; cfg[3] = 0x7ff8;
434 for (reg = 129; reg < 133; reg++)
435 dib3000mc_write_word(state, reg, cfg[reg - 129]);
438 static void dib3000mc_set_channel_cfg(struct dib3000mc_state *state, struct dvb_frontend_parameters *ch, u16 seq)
441 dib3000mc_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
442 dib3000mc_set_timing(state, ch->u.ofdm.transmission_mode, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth), 0);
445 // dib3000mc_write_word(state, 100, (11 << 6) + 6);
447 dib3000mc_write_word(state, 100, (16 << 6) + 9);
449 dib3000mc_write_word(state, 1027, 0x0800);
450 dib3000mc_write_word(state, 1027, 0x0000);
452 //Default cfg isi offset adp
453 dib3000mc_write_word(state, 26, 0x6680);
454 dib3000mc_write_word(state, 29, 0x1273);
455 dib3000mc_write_word(state, 33, 5);
456 dib3000mc_set_adp_cfg(state, QAM_16);
457 dib3000mc_write_word(state, 133, 15564);
459 dib3000mc_write_word(state, 12 , 0x0);
460 dib3000mc_write_word(state, 13 , 0x3e8);
461 dib3000mc_write_word(state, 14 , 0x0);
462 dib3000mc_write_word(state, 15 , 0x3f2);
464 dib3000mc_write_word(state, 93,0);
465 dib3000mc_write_word(state, 94,0);
466 dib3000mc_write_word(state, 95,0);
467 dib3000mc_write_word(state, 96,0);
468 dib3000mc_write_word(state, 97,0);
469 dib3000mc_write_word(state, 98,0);
471 dib3000mc_set_impulse_noise(state, 0, ch->u.ofdm.transmission_mode);
474 switch (ch->u.ofdm.transmission_mode) {
475 case TRANSMISSION_MODE_2K: value |= (0 << 7); break;
477 case TRANSMISSION_MODE_8K: value |= (1 << 7); break;
479 switch (ch->u.ofdm.guard_interval) {
480 case GUARD_INTERVAL_1_32: value |= (0 << 5); break;
481 case GUARD_INTERVAL_1_16: value |= (1 << 5); break;
482 case GUARD_INTERVAL_1_4: value |= (3 << 5); break;
484 case GUARD_INTERVAL_1_8: value |= (2 << 5); break;
486 switch (ch->u.ofdm.constellation) {
487 case QPSK: value |= (0 << 3); break;
488 case QAM_16: value |= (1 << 3); break;
490 case QAM_64: value |= (2 << 3); break;
492 switch (HIERARCHY_1) {
493 case HIERARCHY_2: value |= 2; break;
494 case HIERARCHY_4: value |= 4; break;
496 case HIERARCHY_1: value |= 1; break;
498 dib3000mc_write_word(state, 0, value);
499 dib3000mc_write_word(state, 5, (1 << 8) | ((seq & 0xf) << 4));
502 if (ch->u.ofdm.hierarchy_information == 1)
506 switch ((ch->u.ofdm.hierarchy_information == 0 || 1 == 1) ? ch->u.ofdm.code_rate_HP : ch->u.ofdm.code_rate_LP) {
507 case FEC_2_3: value |= (2 << 1); break;
508 case FEC_3_4: value |= (3 << 1); break;
509 case FEC_5_6: value |= (5 << 1); break;
510 case FEC_7_8: value |= (7 << 1); break;
512 case FEC_1_2: value |= (1 << 1); break;
514 dib3000mc_write_word(state, 181, value);
516 // diversity synchro delay add 50% SFN margin
517 switch (ch->u.ofdm.transmission_mode) {
518 case TRANSMISSION_MODE_8K: value = 256; break;
519 case TRANSMISSION_MODE_2K:
520 default: value = 64; break;
522 switch (ch->u.ofdm.guard_interval) {
523 case GUARD_INTERVAL_1_16: value *= 2; break;
524 case GUARD_INTERVAL_1_8: value *= 4; break;
525 case GUARD_INTERVAL_1_4: value *= 8; break;
527 case GUARD_INTERVAL_1_32: value *= 1; break;
530 value |= dib3000mc_read_word(state, 180) & 0x000f;
531 dib3000mc_write_word(state, 180, value);
534 value = dib3000mc_read_word(state, 0);
535 dib3000mc_write_word(state, 0, value | (1 << 9));
536 dib3000mc_write_word(state, 0, value);
540 dib3000mc_set_impulse_noise(state, state->cfg->impulse_noise_mode, ch->u.ofdm.transmission_mode);
543 static int dib3000mc_autosearch_start(struct dvb_frontend *demod, struct dvb_frontend_parameters *chan)
545 struct dib3000mc_state *state = demod->demodulator_priv;
548 struct dvb_frontend_parameters schan;
552 /* TODO what is that ? */
554 /* a channel for autosearch */
555 schan.u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
556 schan.u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
557 schan.u.ofdm.constellation = QAM_64;
558 schan.u.ofdm.code_rate_HP = FEC_2_3;
559 schan.u.ofdm.code_rate_LP = FEC_2_3;
560 schan.u.ofdm.hierarchy_information = 0;
562 dib3000mc_set_channel_cfg(state, &schan, 11);
564 reg = dib3000mc_read_word(state, 0);
565 dib3000mc_write_word(state, 0, reg | (1 << 8));
566 dib3000mc_read_word(state, 511);
567 dib3000mc_write_word(state, 0, reg);
572 static int dib3000mc_autosearch_is_irq(struct dvb_frontend *demod)
574 struct dib3000mc_state *state = demod->demodulator_priv;
575 u16 irq_pending = dib3000mc_read_word(state, 511);
577 if (irq_pending & 0x1) // failed
580 if (irq_pending & 0x2) // succeeded
583 return 0; // still pending
586 static int dib3000mc_tune(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch)
588 struct dib3000mc_state *state = demod->demodulator_priv;
590 // ** configure demod **
591 dib3000mc_set_channel_cfg(state, ch, 0);
594 dib3000mc_write_word(state, 29, 0x1073);
596 dib3000mc_set_adp_cfg(state, (uint8_t)ch->u.ofdm.constellation);
597 if (ch->u.ofdm.transmission_mode == TRANSMISSION_MODE_8K) {
598 dib3000mc_write_word(state, 26, 38528);
599 dib3000mc_write_word(state, 33, 8);
601 dib3000mc_write_word(state, 26, 30336);
602 dib3000mc_write_word(state, 33, 6);
605 if (dib3000mc_read_word(state, 509) & 0x80)
606 dib3000mc_set_timing(state, ch->u.ofdm.transmission_mode, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth), 1);
611 struct i2c_adapter * dib3000mc_get_tuner_i2c_master(struct dvb_frontend *demod, int gating)
613 struct dib3000mc_state *st = demod->demodulator_priv;
614 return dibx000_get_i2c_adapter(&st->i2c_master, DIBX000_I2C_INTERFACE_TUNER, gating);
617 EXPORT_SYMBOL(dib3000mc_get_tuner_i2c_master);
619 static int dib3000mc_get_frontend(struct dvb_frontend* fe,
620 struct dvb_frontend_parameters *fep)
622 struct dib3000mc_state *state = fe->demodulator_priv;
623 u16 tps = dib3000mc_read_word(state,458);
625 fep->inversion = INVERSION_AUTO;
627 fep->u.ofdm.bandwidth = state->current_bandwidth;
629 switch ((tps >> 8) & 0x1) {
630 case 0: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K; break;
631 case 1: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; break;
635 case 0: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_32; break;
636 case 1: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_16; break;
637 case 2: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_8; break;
638 case 3: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_4; break;
641 switch ((tps >> 13) & 0x3) {
642 case 0: fep->u.ofdm.constellation = QPSK; break;
643 case 1: fep->u.ofdm.constellation = QAM_16; break;
645 default: fep->u.ofdm.constellation = QAM_64; break;
648 /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */
649 /* (tps >> 12) & 0x1 == hrch is used, (tps >> 9) & 0x7 == alpha */
651 fep->u.ofdm.hierarchy_information = HIERARCHY_NONE;
652 switch ((tps >> 5) & 0x7) {
653 case 1: fep->u.ofdm.code_rate_HP = FEC_1_2; break;
654 case 2: fep->u.ofdm.code_rate_HP = FEC_2_3; break;
655 case 3: fep->u.ofdm.code_rate_HP = FEC_3_4; break;
656 case 5: fep->u.ofdm.code_rate_HP = FEC_5_6; break;
658 default: fep->u.ofdm.code_rate_HP = FEC_7_8; break;
662 switch ((tps >> 2) & 0x7) {
663 case 1: fep->u.ofdm.code_rate_LP = FEC_1_2; break;
664 case 2: fep->u.ofdm.code_rate_LP = FEC_2_3; break;
665 case 3: fep->u.ofdm.code_rate_LP = FEC_3_4; break;
666 case 5: fep->u.ofdm.code_rate_LP = FEC_5_6; break;
668 default: fep->u.ofdm.code_rate_LP = FEC_7_8; break;
674 static int dib3000mc_set_frontend(struct dvb_frontend* fe,
675 struct dvb_frontend_parameters *fep)
677 struct dib3000mc_state *state = fe->demodulator_priv;
679 state->current_bandwidth = fep->u.ofdm.bandwidth;
680 dib3000mc_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->u.ofdm.bandwidth));
682 if (fe->ops.tuner_ops.set_params) {
683 fe->ops.tuner_ops.set_params(fe, fep);
687 if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO ||
688 fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO ||
689 fep->u.ofdm.constellation == QAM_AUTO ||
690 fep->u.ofdm.code_rate_HP == FEC_AUTO) {
693 dib3000mc_autosearch_start(fe, fep);
696 found = dib3000mc_autosearch_is_irq(fe);
697 } while (found == 0 && i--);
699 dprintk("autosearch returns: %d\n",found);
700 if (found == 0 || found == 1)
701 return 0; // no channel found
703 dib3000mc_get_frontend(fe, fep);
706 /* make this a config parameter */
707 dib3000mc_set_output_mode(state, OUTMODE_MPEG2_FIFO);
709 return dib3000mc_tune(fe, fep);
712 static int dib3000mc_read_status(struct dvb_frontend *fe, fe_status_t *stat)
714 struct dib3000mc_state *state = fe->demodulator_priv;
715 u16 lock = dib3000mc_read_word(state, 509);
720 *stat |= FE_HAS_SIGNAL;
722 *stat |= FE_HAS_CARRIER;
724 *stat |= FE_HAS_VITERBI;
726 *stat |= FE_HAS_SYNC;
728 *stat |= FE_HAS_LOCK;
733 static int dib3000mc_read_ber(struct dvb_frontend *fe, u32 *ber)
735 struct dib3000mc_state *state = fe->demodulator_priv;
736 *ber = (dib3000mc_read_word(state, 500) << 16) | dib3000mc_read_word(state, 501);
740 static int dib3000mc_read_unc_blocks(struct dvb_frontend *fe, u32 *unc)
742 struct dib3000mc_state *state = fe->demodulator_priv;
743 *unc = dib3000mc_read_word(state, 508);
747 static int dib3000mc_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
749 struct dib3000mc_state *state = fe->demodulator_priv;
750 u16 val = dib3000mc_read_word(state, 392);
751 *strength = 65535 - val;
755 static int dib3000mc_read_snr(struct dvb_frontend* fe, u16 *snr)
761 static int dib3000mc_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
763 tune->min_delay_ms = 1000;
767 static void dib3000mc_release(struct dvb_frontend *fe)
769 struct dib3000mc_state *state = fe->demodulator_priv;
770 dibx000_exit_i2c_master(&state->i2c_master);
774 int dib3000mc_pid_control(struct dvb_frontend *fe, int index, int pid,int onoff)
776 struct dib3000mc_state *state = fe->demodulator_priv;
777 dib3000mc_write_word(state, 212 + index, onoff ? (1 << 13) | pid : 0);
780 EXPORT_SYMBOL(dib3000mc_pid_control);
782 int dib3000mc_pid_parse(struct dvb_frontend *fe, int onoff)
784 struct dib3000mc_state *state = fe->demodulator_priv;
785 u16 tmp = dib3000mc_read_word(state, 206) & ~(1 << 4);
787 return dib3000mc_write_word(state, 206, tmp);
789 EXPORT_SYMBOL(dib3000mc_pid_parse);
791 void dib3000mc_set_config(struct dvb_frontend *fe, struct dib3000mc_config *cfg)
793 struct dib3000mc_state *state = fe->demodulator_priv;
796 EXPORT_SYMBOL(dib3000mc_set_config);
798 int dib3000mc_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib3000mc_config cfg[])
800 struct dib3000mc_state st = { .i2c_adap = i2c };
804 static u8 DIB3000MC_I2C_ADDRESS[] = {20,22,24,26};
806 for (k = no_of_demods-1; k >= 0; k--) {
809 /* designated i2c address */
810 new_addr = DIB3000MC_I2C_ADDRESS[k];
811 st.i2c_addr = new_addr;
812 if (dib3000mc_identify(&st) != 0) {
813 st.i2c_addr = default_addr;
814 if (dib3000mc_identify(&st) != 0) {
815 dprintk("-E- DiB3000P/MC #%d: not identified\n", k);
820 dib3000mc_set_output_mode(&st, OUTMODE_MPEG2_PAR_CONT_CLK);
822 // set new i2c address and force divstr (Bit 1) to value 0 (Bit 0)
823 dib3000mc_write_word(&st, 1024, (new_addr << 3) | 0x1);
824 st.i2c_addr = new_addr;
827 for (k = 0; k < no_of_demods; k++) {
829 st.i2c_addr = DIB3000MC_I2C_ADDRESS[k];
831 dib3000mc_write_word(&st, 1024, st.i2c_addr << 3);
833 /* turn off data output */
834 dib3000mc_set_output_mode(&st, OUTMODE_HIGH_Z);
838 EXPORT_SYMBOL(dib3000mc_i2c_enumeration);
840 static struct dvb_frontend_ops dib3000mc_ops;
842 struct dvb_frontend * dib3000mc_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib3000mc_config *cfg)
844 struct dvb_frontend *demod;
845 struct dib3000mc_state *st;
846 st = kzalloc(sizeof(struct dib3000mc_state), GFP_KERNEL);
851 st->i2c_adap = i2c_adap;
852 st->i2c_addr = i2c_addr;
855 demod->demodulator_priv = st;
856 memcpy(&st->demod.ops, &dib3000mc_ops, sizeof(struct dvb_frontend_ops));
858 if (dib3000mc_identify(st) != 0)
861 dibx000_init_i2c_master(&st->i2c_master, DIB3000MC, st->i2c_adap, st->i2c_addr);
863 dib3000mc_write_word(st, 1037, 0x3130);
871 EXPORT_SYMBOL(dib3000mc_attach);
873 static struct dvb_frontend_ops dib3000mc_ops = {
875 .name = "DiBcom 3000MC/P",
877 .frequency_min = 44250000,
878 .frequency_max = 867250000,
879 .frequency_stepsize = 62500,
880 .caps = FE_CAN_INVERSION_AUTO |
881 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
882 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
883 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
884 FE_CAN_TRANSMISSION_MODE_AUTO |
885 FE_CAN_GUARD_INTERVAL_AUTO |
887 FE_CAN_HIERARCHY_AUTO,
890 .release = dib3000mc_release,
892 .init = dib3000mc_init,
893 .sleep = dib3000mc_sleep,
895 .set_frontend = dib3000mc_set_frontend,
896 .get_tune_settings = dib3000mc_fe_get_tune_settings,
897 .get_frontend = dib3000mc_get_frontend,
899 .read_status = dib3000mc_read_status,
900 .read_ber = dib3000mc_read_ber,
901 .read_signal_strength = dib3000mc_read_signal_strength,
902 .read_snr = dib3000mc_read_snr,
903 .read_ucblocks = dib3000mc_read_unc_blocks,
906 MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
907 MODULE_DESCRIPTION("Driver for the DiBcom 3000MC/P COFDM demodulator");
908 MODULE_LICENSE("GPL");