2 * For the Realtek RTL chip RTL2831U
3 * Realtek Release Date: 2008-03-14, ver 080314
4 * Realtek version RTL2831 Linux driver version 080314
7 * for linux kernel version 2.6.21.4 - 2.6.22-14
8 * support MXL5005s and MT2060 tuners (support tuner auto-detecting)
9 * support two IR types -- RC5 and NEC
11 * Known boards with Realtek RTL chip RTL2821U
12 * Freecom USB stick 14aa:0160 (version 4)
13 * Conceptronic CTVDIGRCU
15 * Copyright (c) 2008 Realtek
16 * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper
17 * This code is placed under the terms of the GNU General Public License
19 * Released by Realtek under GPLv2.
20 * Thanks to Realtek for a lot of support we received !
22 * Revision: 080314 - original version
26 #ifndef __TUNER_MXL5005S_H
27 #define __TUNER_MXL5005S_H
31 // The following context is source code provided by MaxLinear.
34 // MaxLinear source code - Common.h
40 typedef unsigned char _u8; // At least 1 Byte
41 typedef unsigned short _u16; // At least 2 Bytes
42 typedef signed short _s16;
43 typedef unsigned long _u32; // At least 4 Bytes
44 typedef void * HANDLE; // Pointer to memory location
46 #define TUNER_REGS_NUM 104
47 #define INITCTRL_NUM 40
48 #ifdef _MXL_PRODUCTION
54 #define MXLCTRL_NUM 189
56 #define MASTER_CONTROL_ADDR 9
61 // Enumeration of AGC Mode
69 // Enumeration of Master Control Register State
77 } Master_Control_State ;
80 // Enumeration of MXL5005 Tuner Mode
90 // Enumeration of MXL5005 Tuner IF Mode
100 // Enumeration of MXL5005 Tuner Clock Out Mode
104 MXL_CLOCK_OUT_DISABLE = 0 ,
109 // Enumeration of MXL5005 Tuner Div Out Mode
119 // Enumeration of MXL5005 Tuner Pull-up Cap Select Mode
123 MXL_CAP_SEL_DISABLE = 0 ,
129 // Enumeration of MXL5005 Tuner RSSI Mode
133 MXL_RSSI_DISABLE = 0 ,
139 // Enumeration of MXL5005 Tuner Modulation Type
143 MXL_DEFAULT_MODULATION = 0 ,
153 // Enumeration of MXL5005 Tuner Tracking Filter Type
174 // MXL5005 Tuner Register Struct
176 typedef struct _TunerReg_struct
178 _u16 Reg_Num ; // Tuner Register Address
179 _u16 Reg_Val ; // Current sofware programmed value waiting to be writen
183 // MXL5005 Tuner Control Struct
185 typedef struct _TunerControl_struct {
186 _u16 Ctrl_Num ; // Control Number
187 _u16 size ; // Number of bits to represent Value
188 _u16 addr[25] ; // Array of Tuner Register Address for each bit position
189 _u16 bit[25] ; // Array of bit position in Register Address for each bit position
190 _u16 val[25] ; // Binary representation of Value
191 } TunerControl_struct ;
194 // MXL5005 Tuner Struct
196 typedef struct _Tuner_struct
198 _u8 Mode ; // 0: Analog Mode ; 1: Digital Mode
199 _u8 IF_Mode ; // for Analog Mode, 0: zero IF; 1: low IF
200 _u32 Chan_Bandwidth ; // filter channel bandwidth (6, 7, 8)
201 _u32 IF_OUT ; // Desired IF Out Frequency
202 _u16 IF_OUT_LOAD ; // IF Out Load Resistor (200/300 Ohms)
203 _u32 RF_IN ; // RF Input Frequency
204 _u32 Fxtal ; // XTAL Frequency
205 _u8 AGC_Mode ; // AGC Mode 0: Dual AGC; 1: Single AGC
206 _u16 TOP ; // Value: take over point
207 _u8 CLOCK_OUT ; // 0: turn off clock out; 1: turn on clock out
208 _u8 DIV_OUT ; // 4MHz or 16MHz
209 _u8 CAPSELECT ; // 0: disable On-Chip pulling cap; 1: enable
210 _u8 EN_RSSI ; // 0: disable RSSI; 1: enable RSSI
211 _u8 Mod_Type ; // Modulation Type;
212 // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable
213 _u8 TF_Type ; // Tracking Filter Type
214 // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H
216 // Calculated Settings
217 _u32 RF_LO ; // Synth RF LO Frequency
218 _u32 IF_LO ; // Synth IF LO Frequency
219 _u32 TG_LO ; // Synth TG_LO Frequency
221 // Pointers to ControlName Arrays
222 _u16 Init_Ctrl_Num ; // Number of INIT Control Names
223 TunerControl_struct Init_Ctrl[INITCTRL_NUM] ; // INIT Control Names Array Pointer
224 _u16 CH_Ctrl_Num ; // Number of CH Control Names
225 TunerControl_struct CH_Ctrl[CHCTRL_NUM] ; // CH Control Name Array Pointer
226 _u16 MXL_Ctrl_Num ; // Number of MXL Control Names
227 TunerControl_struct MXL_Ctrl[MXLCTRL_NUM] ; // MXL Control Name Array Pointer
229 // Pointer to Tuner Register Array
230 _u16 TunerRegs_Num ; // Number of Tuner Registers
231 TunerReg_struct TunerRegs[TUNER_REGS_NUM] ; // Tuner Register Array Pointer
239 // Initialization Control Names
241 DN_IQTN_AMP_CUT = 1 , // 1
245 BB_ALPF_BANDSELECT , // 5
247 BB_DLPF_BANDSEL , // 7
248 RFSYN_CHP_GAIN , // 8
249 RFSYN_EN_CHP_HIGAIN , // 9
254 CHCAL_INT_MOD_IF , // 14
255 CHCAL_FRAC_MOD_IF , // 15
262 SEQ_ENCLK16_CLK_OUT , // 22
264 XTAL_CAPSELECT , // 24
267 SEQ_EXTSYNTHCALIF , // 27
270 RFA_ENCLKRFAGC , // 30
271 RFA_RSSI_REFH , // 31
273 RFA_RSSI_REFL , // 33
276 SEQ_EXTIQFSMPULSE , // 36
278 BB_INITSTATE_DLPF_TUNE, // 38
283 // Channel Change Control Names
288 DN_EN_VHFUHFBAR , // 54
289 DN_GAIN_ADJUST , // 55
290 DN_IQTNBUF_AMP , // 56
291 DN_IQTNGNBFBIAS_BST , // 57
292 RFSYN_EN_OUTMUX , // 58
293 RFSYN_SEL_VCO_OUT , // 59
294 RFSYN_SEL_VCO_HI , // 60
295 RFSYN_SEL_DIVM , // 61
296 RFSYN_RF_DIV_BIAS , // 62
298 RFSYN_VCO_BIAS , // 64
299 CHCAL_INT_MOD_RF , // 65
300 CHCAL_FRAC_MOD_RF , // 66
302 CHCAL_EN_INT_RF , // 68
307 SEQ_EXTPOWERUP , // 73
311 SEQ_FSM_PULSE , // 77
321 #ifdef _MXL_PRODUCTION
324 DN_BYPASS_AGC_I2C // 89
327 } MXL5005_ControlName ;
343 // MaxLinear source code - MXL5005_c.h
347 // MXL5005.h : main header file for the MXL5005 DLL
351 //#include "Common.h"
353 #include "Common_MXL.h"
356 void InitTunerControls( Tuner_struct *Tuner) ;
358 _u16 MXL_BlockInit( Tuner_struct *Tuner ) ;
360 _u16 MXL5005_RegisterInit (Tuner_struct * Tuner) ;
361 _u16 MXL5005_ControlInit (Tuner_struct *Tuner) ;
364 _u16 MXL5005_MXLControlInit(Tuner_struct *Tuner) ;
367 _u16 MXL5005_TunerConfig(Tuner_struct *Tuner,
368 _u8 Mode, // 0: Analog Mode ; 1: Digital Mode
369 _u8 IF_mode, // for Analog Mode, 0: zero IF; 1: low IF
370 _u32 Bandwidth, // filter channel bandwidth (6, 7, 8)
371 _u32 IF_out, // Desired IF Out Frequency
372 _u32 Fxtal, // XTAL Frequency
373 _u8 AGC_Mode, // AGC Mode - Dual AGC: 0, Single AGC: 1
374 _u16 TOP, // 0: Dual AGC; Value: take over point
375 _u16 IF_OUT_LOAD,// IF Out Load Resistor (200 / 300 Ohms)
376 _u8 CLOCK_OUT, // 0: turn off clock out; 1: turn on clock out
377 _u8 DIV_OUT, // 4MHz or 16MHz
378 _u8 CAPSELECT, // 0: disable On-Chip pulling cap; 1: enable
379 _u8 EN_RSSI, // 0: disable RSSI; 1: enable RSSI
380 _u8 Mod_Type, // Modulation Type;
381 // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable
382 _u8 TF_Type // Tracking Filter Type
383 // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H
386 void MXL_SynthIFLO_Calc(Tuner_struct *Tuner) ;
387 void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner) ;
388 _u16 MXL_RegWrite(Tuner_struct *Tuner, _u8 RegNum, _u8 RegVal) ;
389 _u16 MXL_RegRead(Tuner_struct *Tuner, _u8 RegNum, _u8 *RegVal) ;
390 _u16 MXL_ControlWrite(Tuner_struct *Tuner, _u16 ControlNum, _u32 value) ;
391 _u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 ControlNum, _u32 value, _u16 controlGroup) ;
392 _u16 MXL_ControlRead(Tuner_struct *Tuner, _u16 ControlNum, _u32 * value) ;
393 _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 ControlNum, _u8 *RegNum, int * count) ;
394 void MXL_RegWriteBit(Tuner_struct *Tuner, _u8 address, _u8 bit, _u8 bitVal);
395 _u16 MXL_IFSynthInit( Tuner_struct * Tuner ) ;
396 _u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq) ;
397 _u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) ;
398 _u16 MXL_SetGPIO(Tuner_struct *Tuner, _u8 GPIO_Num, _u8 GPIO_Val) ;
399 _u32 MXL_Ceiling( _u32 value, _u32 resolution ) ;
400 _u32 MXL_GetXtalInt(_u32 Xtal_Freq) ;
402 _u16 MXL_GetInitRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) ;
403 _u16 MXL_GetCHRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) ;
404 _u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) ;
405 _u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) ;
406 _u16 MXL_GetMasterControl(_u8 *MasterReg, int state) ;
408 #ifdef _MXL_PRODUCTION
409 _u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range) ;
410 _u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis) ;
435 // The following context is MxL5005S tuner API source code
445 @brief MxL5005S tuner module declaration
447 One can manipulate MxL5005S tuner through MxL5005S module.
448 MxL5005S module is derived from tuner module.
454 #include "tuner_base.h"
463 #define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104
464 #define MXL5005S_LATCH_BYTE 0xfe
466 // Register address, MSB, and LSB
467 #define MXL5005S_BB_IQSWAP_ADDR 59
468 #define MXL5005S_BB_IQSWAP_MSB 0
469 #define MXL5005S_BB_IQSWAP_LSB 0
471 #define MXL5005S_BB_DLPF_BANDSEL_ADDR 53
472 #define MXL5005S_BB_DLPF_BANDSEL_MSB 4
473 #define MXL5005S_BB_DLPF_BANDSEL_LSB 3
480 MXL5005S_STANDARD_DVBT,
481 MXL5005S_STANDARD_ATSC,
483 #define MXL5005S_STANDARD_MODE_NUM 2
489 MXL5005S_BANDWIDTH_6MHZ = 6000000,
490 MXL5005S_BANDWIDTH_7MHZ = 7000000,
491 MXL5005S_BANDWIDTH_8MHZ = 8000000,
493 #define MXL5005S_BANDWIDTH_MODE_NUM 3
499 MXL5005S_TOP_5P5 = 55,
500 MXL5005S_TOP_7P2 = 72,
501 MXL5005S_TOP_9P2 = 92,
502 MXL5005S_TOP_11P0 = 110,
503 MXL5005S_TOP_12P9 = 129,
504 MXL5005S_TOP_14P7 = 147,
505 MXL5005S_TOP_16P8 = 168,
506 MXL5005S_TOP_19P4 = 194,
507 MXL5005S_TOP_21P2 = 212,
508 MXL5005S_TOP_23P2 = 232,
509 MXL5005S_TOP_25P2 = 252,
510 MXL5005S_TOP_27P1 = 271,
511 MXL5005S_TOP_29P2 = 292,
512 MXL5005S_TOP_31P7 = 317,
513 MXL5005S_TOP_34P9 = 349,
520 MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200,
521 MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300,
528 /// MxL5005S extra module alias
529 typedef struct MXL5005S_EXTRA_MODULE_TAG MXL5005S_EXTRA_MODULE;
535 // MxL5005S register setting function pointer
537 (*MXL5005S_FP_SET_REGS_WITH_TABLE)(
538 struct dvb_usb_device* dib,
539 TUNER_MODULE *pTuner,
540 unsigned char *pAddrTable,
541 unsigned char *pByteTable,
546 // MxL5005S register mask bits setting function pointer
548 (*MXL5005S_FP_SET_REG_MASK_BITS)(
549 struct dvb_usb_device* dib,
550 TUNER_MODULE *pTuner,
551 unsigned char RegAddr,
554 const unsigned char WritingValue
558 // MxL5005S spectrum mode setting function pointer
560 (*MXL5005S_FP_SET_SPECTRUM_MODE)(
561 struct dvb_usb_device* dib,
562 TUNER_MODULE *pTuner,
567 // MxL5005S bandwidth setting function pointer
569 (*MXL5005S_FP_SET_BANDWIDTH_HZ)(
570 struct dvb_usb_device* dib,
571 TUNER_MODULE *pTuner,
572 unsigned long BandwidthHz
579 // MxL5005S extra module
580 struct MXL5005S_EXTRA_MODULE_TAG
582 // MxL5005S function pointers
583 MXL5005S_FP_SET_REGS_WITH_TABLE SetRegsWithTable;
584 MXL5005S_FP_SET_REG_MASK_BITS SetRegMaskBits;
585 MXL5005S_FP_SET_SPECTRUM_MODE SetSpectrumMode;
586 MXL5005S_FP_SET_BANDWIDTH_HZ SetBandwidthHz;
589 // MxL5005S extra data
590 unsigned char AgcMasterByte; // Variable name in MaxLinear source code: AGC_MASTER_BYTE
592 // MaxLinear defined struct
593 Tuner_struct MxlDefinedTunerStructure;
603 TUNER_MODULE **ppTuner,
604 TUNER_MODULE *pTunerModuleMemory,
605 MXL5005S_EXTRA_MODULE *pMxl5005sExtraModuleMemory,
606 BASE_INTERFACE_MODULE *pBaseInterfaceModuleMemory,
607 I2C_BRIDGE_MODULE *pI2cBridgeModuleMemory,
608 unsigned char DeviceAddr,
616 // Manipulaing functions
618 mxl5005s_SetDeviceAddr(
619 TUNER_MODULE *pTuner,
620 unsigned char DeviceAddr
624 mxl5005s_GetTunerType(
625 TUNER_MODULE *pTuner,
630 mxl5005s_GetDeviceAddr(
631 TUNER_MODULE *pTuner,
632 unsigned char *pDeviceAddr
637 struct dvb_usb_device* dib,
642 mxl5005s_SetRfFreqHz(
643 struct dvb_usb_device* dib,
644 TUNER_MODULE *pTuner,
645 unsigned long RfFreqHz
649 mxl5005s_GetRfFreqHz(
650 struct dvb_usb_device* dib,
651 TUNER_MODULE *pTuner,
652 unsigned long *pRfFreqHz
659 // Extra manipulaing functions
661 mxl5005s_SetRegsWithTable(
662 struct dvb_usb_device* dib,
663 TUNER_MODULE *pTuner,
664 unsigned char *pAddrTable,
665 unsigned char *pByteTable,
670 mxl5005s_SetRegMaskBits(
671 struct dvb_usb_device* dib,
672 TUNER_MODULE *pTuner,
673 unsigned char RegAddr,
676 const unsigned char WritingValue
680 mxl5005s_SetSpectrumMode(
681 struct dvb_usb_device* dib,
682 TUNER_MODULE *pTuner,
687 mxl5005s_SetBandwidthHz(
688 struct dvb_usb_device* dib,
689 TUNER_MODULE *pTuner,
690 unsigned long BandwidthHz
697 // I2C birdge module demod argument setting
699 mxl5005s_SetI2cBridgeModuleTunerArg(