2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
20 #include "segment_descriptor.h"
22 #include <linux/module.h>
23 #include <linux/kernel.h>
25 #include <linux/highmem.h>
26 #include <linux/profile.h>
27 #include <linux/sched.h>
32 MODULE_AUTHOR("Qumranet");
33 MODULE_LICENSE("GPL");
42 struct kvm_vcpu *vcpu;
44 struct kvm_msr_entry *guest_msrs;
45 struct kvm_msr_entry *host_msrs;
50 int msr_offset_kernel_gs_base;
55 u16 fs_sel, gs_sel, ldt_sel;
56 int fs_gs_ldt_reload_needed;
61 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
63 return (struct vcpu_vmx*)vcpu->_priv;
66 static int init_rmode_tss(struct kvm *kvm);
68 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
69 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
71 static struct page *vmx_io_bitmap_a;
72 static struct page *vmx_io_bitmap_b;
79 #define EFER_SAVE_RESTORE_BITS ((u64)EFER_SCE)
81 static struct vmcs_descriptor {
87 #define VMX_SEGMENT_FIELD(seg) \
88 [VCPU_SREG_##seg] = { \
89 .selector = GUEST_##seg##_SELECTOR, \
90 .base = GUEST_##seg##_BASE, \
91 .limit = GUEST_##seg##_LIMIT, \
92 .ar_bytes = GUEST_##seg##_AR_BYTES, \
95 static struct kvm_vmx_segment_field {
100 } kvm_vmx_segment_fields[] = {
101 VMX_SEGMENT_FIELD(CS),
102 VMX_SEGMENT_FIELD(DS),
103 VMX_SEGMENT_FIELD(ES),
104 VMX_SEGMENT_FIELD(FS),
105 VMX_SEGMENT_FIELD(GS),
106 VMX_SEGMENT_FIELD(SS),
107 VMX_SEGMENT_FIELD(TR),
108 VMX_SEGMENT_FIELD(LDTR),
112 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
113 * away by decrementing the array size.
115 static const u32 vmx_msr_index[] = {
117 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
119 MSR_EFER, MSR_K6_STAR,
121 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
123 static void load_msrs(struct kvm_msr_entry *e, int n)
127 for (i = 0; i < n; ++i)
128 wrmsrl(e[i].index, e[i].data);
131 static void save_msrs(struct kvm_msr_entry *e, int n)
135 for (i = 0; i < n; ++i)
136 rdmsrl(e[i].index, e[i].data);
139 static inline u64 msr_efer_save_restore_bits(struct kvm_msr_entry msr)
141 return (u64)msr.data & EFER_SAVE_RESTORE_BITS;
144 static inline int msr_efer_need_save_restore(struct kvm_vcpu *vcpu)
146 struct vcpu_vmx *vmx = to_vmx(vcpu);
147 int efer_offset = vmx->msr_offset_efer;
148 return msr_efer_save_restore_bits(vmx->host_msrs[efer_offset]) !=
149 msr_efer_save_restore_bits(vmx->guest_msrs[efer_offset]);
152 static inline int is_page_fault(u32 intr_info)
154 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
155 INTR_INFO_VALID_MASK)) ==
156 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
159 static inline int is_no_device(u32 intr_info)
161 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
162 INTR_INFO_VALID_MASK)) ==
163 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
166 static inline int is_external_interrupt(u32 intr_info)
168 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
169 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
172 static int __find_msr_index(struct kvm_vcpu *vcpu, u32 msr)
174 struct vcpu_vmx *vmx = to_vmx(vcpu);
177 for (i = 0; i < vmx->nmsrs; ++i)
178 if (vmx->guest_msrs[i].index == msr)
183 static struct kvm_msr_entry *find_msr_entry(struct kvm_vcpu *vcpu, u32 msr)
185 struct vcpu_vmx *vmx = to_vmx(vcpu);
188 i = __find_msr_index(vcpu, msr);
190 return &vmx->guest_msrs[i];
194 static void vmcs_clear(struct vmcs *vmcs)
196 u64 phys_addr = __pa(vmcs);
199 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
200 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
203 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
207 static void __vcpu_clear(void *arg)
209 struct kvm_vcpu *vcpu = arg;
210 struct vcpu_vmx *vmx = to_vmx(vcpu);
211 int cpu = raw_smp_processor_id();
213 if (vcpu->cpu == cpu)
214 vmcs_clear(vmx->vmcs);
215 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
216 per_cpu(current_vmcs, cpu) = NULL;
217 rdtscll(vcpu->host_tsc);
220 static void vcpu_clear(struct kvm_vcpu *vcpu)
222 if (vcpu->cpu != raw_smp_processor_id() && vcpu->cpu != -1)
223 smp_call_function_single(vcpu->cpu, __vcpu_clear, vcpu, 0, 1);
226 to_vmx(vcpu)->launched = 0;
229 static unsigned long vmcs_readl(unsigned long field)
233 asm volatile (ASM_VMX_VMREAD_RDX_RAX
234 : "=a"(value) : "d"(field) : "cc");
238 static u16 vmcs_read16(unsigned long field)
240 return vmcs_readl(field);
243 static u32 vmcs_read32(unsigned long field)
245 return vmcs_readl(field);
248 static u64 vmcs_read64(unsigned long field)
251 return vmcs_readl(field);
253 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
257 static noinline void vmwrite_error(unsigned long field, unsigned long value)
259 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
260 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
264 static void vmcs_writel(unsigned long field, unsigned long value)
268 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
269 : "=q"(error) : "a"(value), "d"(field) : "cc" );
271 vmwrite_error(field, value);
274 static void vmcs_write16(unsigned long field, u16 value)
276 vmcs_writel(field, value);
279 static void vmcs_write32(unsigned long field, u32 value)
281 vmcs_writel(field, value);
284 static void vmcs_write64(unsigned long field, u64 value)
287 vmcs_writel(field, value);
289 vmcs_writel(field, value);
291 vmcs_writel(field+1, value >> 32);
295 static void vmcs_clear_bits(unsigned long field, u32 mask)
297 vmcs_writel(field, vmcs_readl(field) & ~mask);
300 static void vmcs_set_bits(unsigned long field, u32 mask)
302 vmcs_writel(field, vmcs_readl(field) | mask);
305 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
309 eb = 1u << PF_VECTOR;
310 if (!vcpu->fpu_active)
311 eb |= 1u << NM_VECTOR;
312 if (vcpu->guest_debug.enabled)
314 if (vcpu->rmode.active)
316 vmcs_write32(EXCEPTION_BITMAP, eb);
319 static void reload_tss(void)
321 #ifndef CONFIG_X86_64
324 * VT restores TR but not its size. Useless.
326 struct descriptor_table gdt;
327 struct segment_descriptor *descs;
330 descs = (void *)gdt.base;
331 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
336 static void load_transition_efer(struct kvm_vcpu *vcpu)
339 struct vcpu_vmx *vmx = to_vmx(vcpu);
340 int efer_offset = vmx->msr_offset_efer;
342 trans_efer = vmx->host_msrs[efer_offset].data;
343 trans_efer &= ~EFER_SAVE_RESTORE_BITS;
344 trans_efer |= msr_efer_save_restore_bits(vmx->guest_msrs[efer_offset]);
345 wrmsrl(MSR_EFER, trans_efer);
346 vcpu->stat.efer_reload++;
349 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
351 struct vcpu_vmx *vmx = to_vmx(vcpu);
353 if (vmx->host_state.loaded)
356 vmx->host_state.loaded = 1;
358 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
359 * allow segment selectors with cpl > 0 or ti == 1.
361 vmx->host_state.ldt_sel = read_ldt();
362 vmx->host_state.fs_gs_ldt_reload_needed = vmx->host_state.ldt_sel;
363 vmx->host_state.fs_sel = read_fs();
364 if (!(vmx->host_state.fs_sel & 7))
365 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
367 vmcs_write16(HOST_FS_SELECTOR, 0);
368 vmx->host_state.fs_gs_ldt_reload_needed = 1;
370 vmx->host_state.gs_sel = read_gs();
371 if (!(vmx->host_state.gs_sel & 7))
372 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
374 vmcs_write16(HOST_GS_SELECTOR, 0);
375 vmx->host_state.fs_gs_ldt_reload_needed = 1;
379 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
380 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
382 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
383 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
387 if (is_long_mode(vcpu)) {
388 save_msrs(vmx->host_msrs +
389 vmx->msr_offset_kernel_gs_base, 1);
392 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
393 if (msr_efer_need_save_restore(vcpu))
394 load_transition_efer(vcpu);
397 static void vmx_load_host_state(struct kvm_vcpu *vcpu)
399 struct vcpu_vmx *vmx = to_vmx(vcpu);
401 if (!vmx->host_state.loaded)
404 vmx->host_state.loaded = 0;
405 if (vmx->host_state.fs_gs_ldt_reload_needed) {
406 load_ldt(vmx->host_state.ldt_sel);
407 load_fs(vmx->host_state.fs_sel);
409 * If we have to reload gs, we must take care to
410 * preserve our gs base.
413 load_gs(vmx->host_state.gs_sel);
415 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
421 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
422 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
423 if (msr_efer_need_save_restore(vcpu))
424 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
428 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
429 * vcpu mutex is already taken.
431 static void vmx_vcpu_load(struct kvm_vcpu *vcpu)
433 struct vcpu_vmx *vmx = to_vmx(vcpu);
434 u64 phys_addr = __pa(vmx->vmcs);
440 if (vcpu->cpu != cpu)
443 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
446 per_cpu(current_vmcs, cpu) = vmx->vmcs;
447 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
448 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
451 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
452 vmx->vmcs, phys_addr);
455 if (vcpu->cpu != cpu) {
456 struct descriptor_table dt;
457 unsigned long sysenter_esp;
461 * Linux uses per-cpu TSS and GDT, so set these when switching
464 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
466 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
468 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
469 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
472 * Make sure the time stamp counter is monotonous.
475 delta = vcpu->host_tsc - tsc_this;
476 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
480 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
482 vmx_load_host_state(vcpu);
483 kvm_put_guest_fpu(vcpu);
487 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
489 if (vcpu->fpu_active)
491 vcpu->fpu_active = 1;
492 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
493 if (vcpu->cr0 & X86_CR0_TS)
494 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
495 update_exception_bitmap(vcpu);
498 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
500 if (!vcpu->fpu_active)
502 vcpu->fpu_active = 0;
503 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
504 update_exception_bitmap(vcpu);
507 static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
512 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
514 return vmcs_readl(GUEST_RFLAGS);
517 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
519 vmcs_writel(GUEST_RFLAGS, rflags);
522 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
525 u32 interruptibility;
527 rip = vmcs_readl(GUEST_RIP);
528 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
529 vmcs_writel(GUEST_RIP, rip);
532 * We emulated an instruction, so temporary interrupt blocking
533 * should be removed, if set.
535 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
536 if (interruptibility & 3)
537 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
538 interruptibility & ~3);
539 vcpu->interrupt_window_open = 1;
542 static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
544 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
545 vmcs_readl(GUEST_RIP));
546 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
547 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
549 INTR_TYPE_EXCEPTION |
550 INTR_INFO_DELIEVER_CODE_MASK |
551 INTR_INFO_VALID_MASK);
555 * Swap MSR entry in host/guest MSR entry array.
557 void move_msr_up(struct kvm_vcpu *vcpu, int from, int to)
559 struct vcpu_vmx *vmx = to_vmx(vcpu);
560 struct kvm_msr_entry tmp;
562 tmp = vmx->guest_msrs[to];
563 vmx->guest_msrs[to] = vmx->guest_msrs[from];
564 vmx->guest_msrs[from] = tmp;
565 tmp = vmx->host_msrs[to];
566 vmx->host_msrs[to] = vmx->host_msrs[from];
567 vmx->host_msrs[from] = tmp;
571 * Set up the vmcs to automatically save and restore system
572 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
573 * mode, as fiddling with msrs is very expensive.
575 static void setup_msrs(struct kvm_vcpu *vcpu)
577 struct vcpu_vmx *vmx = to_vmx(vcpu);
582 if (is_long_mode(vcpu)) {
585 index = __find_msr_index(vcpu, MSR_SYSCALL_MASK);
587 move_msr_up(vcpu, index, save_nmsrs++);
588 index = __find_msr_index(vcpu, MSR_LSTAR);
590 move_msr_up(vcpu, index, save_nmsrs++);
591 index = __find_msr_index(vcpu, MSR_CSTAR);
593 move_msr_up(vcpu, index, save_nmsrs++);
594 index = __find_msr_index(vcpu, MSR_KERNEL_GS_BASE);
596 move_msr_up(vcpu, index, save_nmsrs++);
598 * MSR_K6_STAR is only needed on long mode guests, and only
599 * if efer.sce is enabled.
601 index = __find_msr_index(vcpu, MSR_K6_STAR);
602 if ((index >= 0) && (vcpu->shadow_efer & EFER_SCE))
603 move_msr_up(vcpu, index, save_nmsrs++);
606 vmx->save_nmsrs = save_nmsrs;
609 vmx->msr_offset_kernel_gs_base =
610 __find_msr_index(vcpu, MSR_KERNEL_GS_BASE);
612 vmx->msr_offset_efer = __find_msr_index(vcpu, MSR_EFER);
616 * reads and returns guest's timestamp counter "register"
617 * guest_tsc = host_tsc + tsc_offset -- 21.3
619 static u64 guest_read_tsc(void)
621 u64 host_tsc, tsc_offset;
624 tsc_offset = vmcs_read64(TSC_OFFSET);
625 return host_tsc + tsc_offset;
629 * writes 'guest_tsc' into guest's timestamp counter "register"
630 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
632 static void guest_write_tsc(u64 guest_tsc)
637 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
641 * Reads an msr value (of 'msr_index') into 'pdata'.
642 * Returns 0 on success, non-0 otherwise.
643 * Assumes vcpu_load() was already called.
645 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
648 struct kvm_msr_entry *msr;
651 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
658 data = vmcs_readl(GUEST_FS_BASE);
661 data = vmcs_readl(GUEST_GS_BASE);
664 return kvm_get_msr_common(vcpu, msr_index, pdata);
666 case MSR_IA32_TIME_STAMP_COUNTER:
667 data = guest_read_tsc();
669 case MSR_IA32_SYSENTER_CS:
670 data = vmcs_read32(GUEST_SYSENTER_CS);
672 case MSR_IA32_SYSENTER_EIP:
673 data = vmcs_readl(GUEST_SYSENTER_EIP);
675 case MSR_IA32_SYSENTER_ESP:
676 data = vmcs_readl(GUEST_SYSENTER_ESP);
679 msr = find_msr_entry(vcpu, msr_index);
684 return kvm_get_msr_common(vcpu, msr_index, pdata);
692 * Writes msr value into into the appropriate "register".
693 * Returns 0 on success, non-0 otherwise.
694 * Assumes vcpu_load() was already called.
696 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
698 struct vcpu_vmx *vmx = to_vmx(vcpu);
699 struct kvm_msr_entry *msr;
705 ret = kvm_set_msr_common(vcpu, msr_index, data);
706 if (vmx->host_state.loaded)
707 load_transition_efer(vcpu);
710 vmcs_writel(GUEST_FS_BASE, data);
713 vmcs_writel(GUEST_GS_BASE, data);
716 case MSR_IA32_SYSENTER_CS:
717 vmcs_write32(GUEST_SYSENTER_CS, data);
719 case MSR_IA32_SYSENTER_EIP:
720 vmcs_writel(GUEST_SYSENTER_EIP, data);
722 case MSR_IA32_SYSENTER_ESP:
723 vmcs_writel(GUEST_SYSENTER_ESP, data);
725 case MSR_IA32_TIME_STAMP_COUNTER:
726 guest_write_tsc(data);
729 msr = find_msr_entry(vcpu, msr_index);
732 if (vmx->host_state.loaded)
733 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
736 ret = kvm_set_msr_common(vcpu, msr_index, data);
743 * Sync the rsp and rip registers into the vcpu structure. This allows
744 * registers to be accessed by indexing vcpu->regs.
746 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
748 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
749 vcpu->rip = vmcs_readl(GUEST_RIP);
753 * Syncs rsp and rip back into the vmcs. Should be called after possible
756 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
758 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
759 vmcs_writel(GUEST_RIP, vcpu->rip);
762 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
764 unsigned long dr7 = 0x400;
767 old_singlestep = vcpu->guest_debug.singlestep;
769 vcpu->guest_debug.enabled = dbg->enabled;
770 if (vcpu->guest_debug.enabled) {
773 dr7 |= 0x200; /* exact */
774 for (i = 0; i < 4; ++i) {
775 if (!dbg->breakpoints[i].enabled)
777 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
778 dr7 |= 2 << (i*2); /* global enable */
779 dr7 |= 0 << (i*4+16); /* execution breakpoint */
782 vcpu->guest_debug.singlestep = dbg->singlestep;
784 vcpu->guest_debug.singlestep = 0;
786 if (old_singlestep && !vcpu->guest_debug.singlestep) {
789 flags = vmcs_readl(GUEST_RFLAGS);
790 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
791 vmcs_writel(GUEST_RFLAGS, flags);
794 update_exception_bitmap(vcpu);
795 vmcs_writel(GUEST_DR7, dr7);
800 static __init int cpu_has_kvm_support(void)
802 unsigned long ecx = cpuid_ecx(1);
803 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
806 static __init int vmx_disabled_by_bios(void)
810 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
811 return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
812 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
813 == MSR_IA32_FEATURE_CONTROL_LOCKED;
814 /* locked but not enabled */
817 static void hardware_enable(void *garbage)
819 int cpu = raw_smp_processor_id();
820 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
823 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
824 if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
825 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
826 != (MSR_IA32_FEATURE_CONTROL_LOCKED |
827 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
828 /* enable and lock */
829 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
830 MSR_IA32_FEATURE_CONTROL_LOCKED |
831 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
832 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
833 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
837 static void hardware_disable(void *garbage)
839 asm volatile (ASM_VMX_VMXOFF : : : "cc");
842 static __init void setup_vmcs_descriptor(void)
844 u32 vmx_msr_low, vmx_msr_high;
846 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
847 vmcs_descriptor.size = vmx_msr_high & 0x1fff;
848 vmcs_descriptor.order = get_order(vmcs_descriptor.size);
849 vmcs_descriptor.revision_id = vmx_msr_low;
852 static struct vmcs *alloc_vmcs_cpu(int cpu)
854 int node = cpu_to_node(cpu);
858 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_descriptor.order);
861 vmcs = page_address(pages);
862 memset(vmcs, 0, vmcs_descriptor.size);
863 vmcs->revision_id = vmcs_descriptor.revision_id; /* vmcs revision id */
867 static struct vmcs *alloc_vmcs(void)
869 return alloc_vmcs_cpu(raw_smp_processor_id());
872 static void free_vmcs(struct vmcs *vmcs)
874 free_pages((unsigned long)vmcs, vmcs_descriptor.order);
877 static void free_kvm_area(void)
881 for_each_online_cpu(cpu)
882 free_vmcs(per_cpu(vmxarea, cpu));
885 extern struct vmcs *alloc_vmcs_cpu(int cpu);
887 static __init int alloc_kvm_area(void)
891 for_each_online_cpu(cpu) {
894 vmcs = alloc_vmcs_cpu(cpu);
900 per_cpu(vmxarea, cpu) = vmcs;
905 static __init int hardware_setup(void)
907 setup_vmcs_descriptor();
908 return alloc_kvm_area();
911 static __exit void hardware_unsetup(void)
916 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
918 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
920 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
921 vmcs_write16(sf->selector, save->selector);
922 vmcs_writel(sf->base, save->base);
923 vmcs_write32(sf->limit, save->limit);
924 vmcs_write32(sf->ar_bytes, save->ar);
926 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
928 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
932 static void enter_pmode(struct kvm_vcpu *vcpu)
936 vcpu->rmode.active = 0;
938 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
939 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
940 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
942 flags = vmcs_readl(GUEST_RFLAGS);
943 flags &= ~(IOPL_MASK | X86_EFLAGS_VM);
944 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
945 vmcs_writel(GUEST_RFLAGS, flags);
947 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
948 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
950 update_exception_bitmap(vcpu);
952 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
953 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
954 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
955 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
957 vmcs_write16(GUEST_SS_SELECTOR, 0);
958 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
960 vmcs_write16(GUEST_CS_SELECTOR,
961 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
962 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
965 static int rmode_tss_base(struct kvm* kvm)
967 gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3;
968 return base_gfn << PAGE_SHIFT;
971 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
973 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
975 save->selector = vmcs_read16(sf->selector);
976 save->base = vmcs_readl(sf->base);
977 save->limit = vmcs_read32(sf->limit);
978 save->ar = vmcs_read32(sf->ar_bytes);
979 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
980 vmcs_write32(sf->limit, 0xffff);
981 vmcs_write32(sf->ar_bytes, 0xf3);
984 static void enter_rmode(struct kvm_vcpu *vcpu)
988 vcpu->rmode.active = 1;
990 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
991 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
993 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
994 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
996 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
997 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
999 flags = vmcs_readl(GUEST_RFLAGS);
1000 vcpu->rmode.save_iopl = (flags & IOPL_MASK) >> IOPL_SHIFT;
1002 flags |= IOPL_MASK | X86_EFLAGS_VM;
1004 vmcs_writel(GUEST_RFLAGS, flags);
1005 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1006 update_exception_bitmap(vcpu);
1008 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1009 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1010 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1012 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1013 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1014 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1015 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1016 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1018 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
1019 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
1020 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
1021 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
1023 init_rmode_tss(vcpu->kvm);
1026 #ifdef CONFIG_X86_64
1028 static void enter_lmode(struct kvm_vcpu *vcpu)
1032 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1033 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1034 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1036 vmcs_write32(GUEST_TR_AR_BYTES,
1037 (guest_tr_ar & ~AR_TYPE_MASK)
1038 | AR_TYPE_BUSY_64_TSS);
1041 vcpu->shadow_efer |= EFER_LMA;
1043 find_msr_entry(vcpu, MSR_EFER)->data |= EFER_LMA | EFER_LME;
1044 vmcs_write32(VM_ENTRY_CONTROLS,
1045 vmcs_read32(VM_ENTRY_CONTROLS)
1046 | VM_ENTRY_CONTROLS_IA32E_MASK);
1049 static void exit_lmode(struct kvm_vcpu *vcpu)
1051 vcpu->shadow_efer &= ~EFER_LMA;
1053 vmcs_write32(VM_ENTRY_CONTROLS,
1054 vmcs_read32(VM_ENTRY_CONTROLS)
1055 & ~VM_ENTRY_CONTROLS_IA32E_MASK);
1060 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1062 vcpu->cr4 &= KVM_GUEST_CR4_MASK;
1063 vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1066 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1068 vmx_fpu_deactivate(vcpu);
1070 if (vcpu->rmode.active && (cr0 & X86_CR0_PE))
1073 if (!vcpu->rmode.active && !(cr0 & X86_CR0_PE))
1076 #ifdef CONFIG_X86_64
1077 if (vcpu->shadow_efer & EFER_LME) {
1078 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1080 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1085 vmcs_writel(CR0_READ_SHADOW, cr0);
1086 vmcs_writel(GUEST_CR0,
1087 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1090 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1091 vmx_fpu_activate(vcpu);
1094 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1096 vmcs_writel(GUEST_CR3, cr3);
1097 if (vcpu->cr0 & X86_CR0_PE)
1098 vmx_fpu_deactivate(vcpu);
1101 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1103 vmcs_writel(CR4_READ_SHADOW, cr4);
1104 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
1105 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1109 #ifdef CONFIG_X86_64
1111 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1113 struct kvm_msr_entry *msr = find_msr_entry(vcpu, MSR_EFER);
1115 vcpu->shadow_efer = efer;
1116 if (efer & EFER_LMA) {
1117 vmcs_write32(VM_ENTRY_CONTROLS,
1118 vmcs_read32(VM_ENTRY_CONTROLS) |
1119 VM_ENTRY_CONTROLS_IA32E_MASK);
1123 vmcs_write32(VM_ENTRY_CONTROLS,
1124 vmcs_read32(VM_ENTRY_CONTROLS) &
1125 ~VM_ENTRY_CONTROLS_IA32E_MASK);
1127 msr->data = efer & ~EFER_LME;
1134 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1136 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1138 return vmcs_readl(sf->base);
1141 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1142 struct kvm_segment *var, int seg)
1144 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1147 var->base = vmcs_readl(sf->base);
1148 var->limit = vmcs_read32(sf->limit);
1149 var->selector = vmcs_read16(sf->selector);
1150 ar = vmcs_read32(sf->ar_bytes);
1151 if (ar & AR_UNUSABLE_MASK)
1153 var->type = ar & 15;
1154 var->s = (ar >> 4) & 1;
1155 var->dpl = (ar >> 5) & 3;
1156 var->present = (ar >> 7) & 1;
1157 var->avl = (ar >> 12) & 1;
1158 var->l = (ar >> 13) & 1;
1159 var->db = (ar >> 14) & 1;
1160 var->g = (ar >> 15) & 1;
1161 var->unusable = (ar >> 16) & 1;
1164 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1171 ar = var->type & 15;
1172 ar |= (var->s & 1) << 4;
1173 ar |= (var->dpl & 3) << 5;
1174 ar |= (var->present & 1) << 7;
1175 ar |= (var->avl & 1) << 12;
1176 ar |= (var->l & 1) << 13;
1177 ar |= (var->db & 1) << 14;
1178 ar |= (var->g & 1) << 15;
1180 if (ar == 0) /* a 0 value means unusable */
1181 ar = AR_UNUSABLE_MASK;
1186 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1187 struct kvm_segment *var, int seg)
1189 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1192 if (vcpu->rmode.active && seg == VCPU_SREG_TR) {
1193 vcpu->rmode.tr.selector = var->selector;
1194 vcpu->rmode.tr.base = var->base;
1195 vcpu->rmode.tr.limit = var->limit;
1196 vcpu->rmode.tr.ar = vmx_segment_access_rights(var);
1199 vmcs_writel(sf->base, var->base);
1200 vmcs_write32(sf->limit, var->limit);
1201 vmcs_write16(sf->selector, var->selector);
1202 if (vcpu->rmode.active && var->s) {
1204 * Hack real-mode segments into vm86 compatibility.
1206 if (var->base == 0xffff0000 && var->selector == 0xf000)
1207 vmcs_writel(sf->base, 0xf0000);
1210 ar = vmx_segment_access_rights(var);
1211 vmcs_write32(sf->ar_bytes, ar);
1214 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1216 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1218 *db = (ar >> 14) & 1;
1219 *l = (ar >> 13) & 1;
1222 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1224 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1225 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1228 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1230 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1231 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1234 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1236 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1237 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1240 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1242 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1243 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1246 static int init_rmode_tss(struct kvm* kvm)
1248 struct page *p1, *p2, *p3;
1249 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1252 p1 = gfn_to_page(kvm, fn++);
1253 p2 = gfn_to_page(kvm, fn++);
1254 p3 = gfn_to_page(kvm, fn);
1256 if (!p1 || !p2 || !p3) {
1257 kvm_printf(kvm,"%s: gfn_to_page failed\n", __FUNCTION__);
1261 page = kmap_atomic(p1, KM_USER0);
1263 *(u16*)(page + 0x66) = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1264 kunmap_atomic(page, KM_USER0);
1266 page = kmap_atomic(p2, KM_USER0);
1268 kunmap_atomic(page, KM_USER0);
1270 page = kmap_atomic(p3, KM_USER0);
1272 *(page + RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1) = ~0;
1273 kunmap_atomic(page, KM_USER0);
1278 static void vmcs_write32_fixedbits(u32 msr, u32 vmcs_field, u32 val)
1280 u32 msr_high, msr_low;
1282 rdmsr(msr, msr_low, msr_high);
1286 vmcs_write32(vmcs_field, val);
1289 static void seg_setup(int seg)
1291 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1293 vmcs_write16(sf->selector, 0);
1294 vmcs_writel(sf->base, 0);
1295 vmcs_write32(sf->limit, 0xffff);
1296 vmcs_write32(sf->ar_bytes, 0x93);
1300 * Sets up the vmcs for emulated real mode.
1302 static int vmx_vcpu_setup(struct kvm_vcpu *vcpu)
1304 struct vcpu_vmx *vmx = to_vmx(vcpu);
1305 u32 host_sysenter_cs;
1308 struct descriptor_table dt;
1311 unsigned long kvm_vmx_return;
1313 if (!init_rmode_tss(vcpu->kvm)) {
1318 memset(vcpu->regs, 0, sizeof(vcpu->regs));
1319 vcpu->regs[VCPU_REGS_RDX] = get_rdx_init_val();
1321 vcpu->apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1322 if (vcpu->vcpu_id == 0)
1323 vcpu->apic_base |= MSR_IA32_APICBASE_BSP;
1328 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1329 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1331 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1332 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1333 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1334 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1336 seg_setup(VCPU_SREG_DS);
1337 seg_setup(VCPU_SREG_ES);
1338 seg_setup(VCPU_SREG_FS);
1339 seg_setup(VCPU_SREG_GS);
1340 seg_setup(VCPU_SREG_SS);
1342 vmcs_write16(GUEST_TR_SELECTOR, 0);
1343 vmcs_writel(GUEST_TR_BASE, 0);
1344 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1345 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1347 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1348 vmcs_writel(GUEST_LDTR_BASE, 0);
1349 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1350 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1352 vmcs_write32(GUEST_SYSENTER_CS, 0);
1353 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1354 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1356 vmcs_writel(GUEST_RFLAGS, 0x02);
1357 vmcs_writel(GUEST_RIP, 0xfff0);
1358 vmcs_writel(GUEST_RSP, 0);
1360 //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0
1361 vmcs_writel(GUEST_DR7, 0x400);
1363 vmcs_writel(GUEST_GDTR_BASE, 0);
1364 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1366 vmcs_writel(GUEST_IDTR_BASE, 0);
1367 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1369 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1370 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1371 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1374 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1375 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1379 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1381 /* Special registers */
1382 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1385 vmcs_write32_fixedbits(MSR_IA32_VMX_PINBASED_CTLS,
1386 PIN_BASED_VM_EXEC_CONTROL,
1387 PIN_BASED_EXT_INTR_MASK /* 20.6.1 */
1388 | PIN_BASED_NMI_EXITING /* 20.6.1 */
1390 vmcs_write32_fixedbits(MSR_IA32_VMX_PROCBASED_CTLS,
1391 CPU_BASED_VM_EXEC_CONTROL,
1392 CPU_BASED_HLT_EXITING /* 20.6.2 */
1393 | CPU_BASED_CR8_LOAD_EXITING /* 20.6.2 */
1394 | CPU_BASED_CR8_STORE_EXITING /* 20.6.2 */
1395 | CPU_BASED_USE_IO_BITMAPS /* 20.6.2 */
1396 | CPU_BASED_MOV_DR_EXITING
1397 | CPU_BASED_USE_TSC_OFFSETING /* 21.3 */
1400 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
1401 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
1402 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1404 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1405 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1406 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1408 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1409 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1410 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1411 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1412 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1413 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1414 #ifdef CONFIG_X86_64
1415 rdmsrl(MSR_FS_BASE, a);
1416 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1417 rdmsrl(MSR_GS_BASE, a);
1418 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1420 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1421 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1424 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1427 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1429 asm ("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1430 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1431 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1432 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1433 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1435 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1436 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1437 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1438 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1439 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1440 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1442 for (i = 0; i < NR_VMX_MSR; ++i) {
1443 u32 index = vmx_msr_index[i];
1444 u32 data_low, data_high;
1448 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1450 if (wrmsr_safe(index, data_low, data_high) < 0)
1452 data = data_low | ((u64)data_high << 32);
1453 vmx->host_msrs[j].index = index;
1454 vmx->host_msrs[j].reserved = 0;
1455 vmx->host_msrs[j].data = data;
1456 vmx->guest_msrs[j] = vmx->host_msrs[j];
1462 vmcs_write32_fixedbits(MSR_IA32_VMX_EXIT_CTLS, VM_EXIT_CONTROLS,
1463 (HOST_IS_64 << 9)); /* 22.2,1, 20.7.1 */
1465 /* 22.2.1, 20.8.1 */
1466 vmcs_write32_fixedbits(MSR_IA32_VMX_ENTRY_CTLS,
1467 VM_ENTRY_CONTROLS, 0);
1468 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1470 #ifdef CONFIG_X86_64
1471 vmcs_writel(VIRTUAL_APIC_PAGE_ADDR, 0);
1472 vmcs_writel(TPR_THRESHOLD, 0);
1475 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1476 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1478 vcpu->cr0 = 0x60000010;
1479 vmx_set_cr0(vcpu, vcpu->cr0); // enter rmode
1480 vmx_set_cr4(vcpu, 0);
1481 #ifdef CONFIG_X86_64
1482 vmx_set_efer(vcpu, 0);
1484 vmx_fpu_activate(vcpu);
1485 update_exception_bitmap(vcpu);
1493 static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1498 unsigned long flags;
1499 unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1500 u16 sp = vmcs_readl(GUEST_RSP);
1501 u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1503 if (sp > ss_limit || sp < 6 ) {
1504 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1506 vmcs_readl(GUEST_RSP),
1507 vmcs_readl(GUEST_SS_BASE),
1508 vmcs_read32(GUEST_SS_LIMIT));
1512 if (kvm_read_guest(vcpu, irq * sizeof(ent), sizeof(ent), &ent) !=
1514 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1518 flags = vmcs_readl(GUEST_RFLAGS);
1519 cs = vmcs_readl(GUEST_CS_BASE) >> 4;
1520 ip = vmcs_readl(GUEST_RIP);
1523 if (kvm_write_guest(vcpu, ss_base + sp - 2, 2, &flags) != 2 ||
1524 kvm_write_guest(vcpu, ss_base + sp - 4, 2, &cs) != 2 ||
1525 kvm_write_guest(vcpu, ss_base + sp - 6, 2, &ip) != 2) {
1526 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1530 vmcs_writel(GUEST_RFLAGS, flags &
1531 ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1532 vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1533 vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1534 vmcs_writel(GUEST_RIP, ent[0]);
1535 vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1538 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1540 int word_index = __ffs(vcpu->irq_summary);
1541 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1542 int irq = word_index * BITS_PER_LONG + bit_index;
1544 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1545 if (!vcpu->irq_pending[word_index])
1546 clear_bit(word_index, &vcpu->irq_summary);
1548 if (vcpu->rmode.active) {
1549 inject_rmode_irq(vcpu, irq);
1552 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1553 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1557 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1558 struct kvm_run *kvm_run)
1560 u32 cpu_based_vm_exec_control;
1562 vcpu->interrupt_window_open =
1563 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1564 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1566 if (vcpu->interrupt_window_open &&
1567 vcpu->irq_summary &&
1568 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1570 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1572 kvm_do_inject_irq(vcpu);
1574 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1575 if (!vcpu->interrupt_window_open &&
1576 (vcpu->irq_summary || kvm_run->request_interrupt_window))
1578 * Interrupts blocked. Wait for unblock.
1580 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1582 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1583 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
1586 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1588 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1590 set_debugreg(dbg->bp[0], 0);
1591 set_debugreg(dbg->bp[1], 1);
1592 set_debugreg(dbg->bp[2], 2);
1593 set_debugreg(dbg->bp[3], 3);
1595 if (dbg->singlestep) {
1596 unsigned long flags;
1598 flags = vmcs_readl(GUEST_RFLAGS);
1599 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1600 vmcs_writel(GUEST_RFLAGS, flags);
1604 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1605 int vec, u32 err_code)
1607 if (!vcpu->rmode.active)
1611 * Instruction with address size override prefix opcode 0x67
1612 * Cause the #SS fault with 0 error code in VM86 mode.
1614 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
1615 if (emulate_instruction(vcpu, NULL, 0, 0) == EMULATE_DONE)
1620 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1622 u32 intr_info, error_code;
1623 unsigned long cr2, rip;
1625 enum emulation_result er;
1628 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1629 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1631 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1632 !is_page_fault(intr_info)) {
1633 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1634 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1637 if (is_external_interrupt(vect_info)) {
1638 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1639 set_bit(irq, vcpu->irq_pending);
1640 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1643 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
1648 if (is_no_device(intr_info)) {
1649 vmx_fpu_activate(vcpu);
1654 rip = vmcs_readl(GUEST_RIP);
1655 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1656 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1657 if (is_page_fault(intr_info)) {
1658 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1660 spin_lock(&vcpu->kvm->lock);
1661 r = kvm_mmu_page_fault(vcpu, cr2, error_code);
1663 spin_unlock(&vcpu->kvm->lock);
1667 spin_unlock(&vcpu->kvm->lock);
1671 er = emulate_instruction(vcpu, kvm_run, cr2, error_code);
1672 spin_unlock(&vcpu->kvm->lock);
1677 case EMULATE_DO_MMIO:
1678 ++vcpu->stat.mmio_exits;
1681 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
1688 if (vcpu->rmode.active &&
1689 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1691 if (vcpu->halt_request) {
1692 vcpu->halt_request = 0;
1693 return kvm_emulate_halt(vcpu);
1698 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) {
1699 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1702 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1703 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1704 kvm_run->ex.error_code = error_code;
1708 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1709 struct kvm_run *kvm_run)
1711 ++vcpu->stat.irq_exits;
1715 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1717 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1721 static int get_io_count(struct kvm_vcpu *vcpu, unsigned long *count)
1728 if ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_VM)) {
1731 u32 cs_ar = vmcs_read32(GUEST_CS_AR_BYTES);
1733 countr_size = (cs_ar & AR_L_MASK) ? 8:
1734 (cs_ar & AR_DB_MASK) ? 4: 2;
1737 rip = vmcs_readl(GUEST_RIP);
1738 if (countr_size != 8)
1739 rip += vmcs_readl(GUEST_CS_BASE);
1741 n = kvm_read_guest(vcpu, rip, sizeof(inst), &inst);
1743 for (i = 0; i < n; i++) {
1744 switch (((u8*)&inst)[i]) {
1757 countr_size = (countr_size == 2) ? 4: (countr_size >> 1);
1765 *count = vcpu->regs[VCPU_REGS_RCX] & (~0ULL >> (64 - countr_size));
1766 //printk("cx: %lx\n", vcpu->regs[VCPU_REGS_RCX]);
1770 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1772 u64 exit_qualification;
1773 int size, down, in, string, rep;
1775 unsigned long count;
1778 ++vcpu->stat.io_exits;
1779 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1780 in = (exit_qualification & 8) != 0;
1781 size = (exit_qualification & 7) + 1;
1782 string = (exit_qualification & 16) != 0;
1783 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1785 rep = (exit_qualification & 32) != 0;
1786 port = exit_qualification >> 16;
1789 if (rep && !get_io_count(vcpu, &count))
1791 address = vmcs_readl(GUEST_LINEAR_ADDRESS);
1793 return kvm_setup_pio(vcpu, kvm_run, in, size, count, string, down,
1794 address, rep, port);
1798 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1801 * Patch in the VMCALL instruction:
1803 hypercall[0] = 0x0f;
1804 hypercall[1] = 0x01;
1805 hypercall[2] = 0xc1;
1806 hypercall[3] = 0xc3;
1809 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1811 u64 exit_qualification;
1815 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1816 cr = exit_qualification & 15;
1817 reg = (exit_qualification >> 8) & 15;
1818 switch ((exit_qualification >> 4) & 3) {
1819 case 0: /* mov to cr */
1822 vcpu_load_rsp_rip(vcpu);
1823 set_cr0(vcpu, vcpu->regs[reg]);
1824 skip_emulated_instruction(vcpu);
1827 vcpu_load_rsp_rip(vcpu);
1828 set_cr3(vcpu, vcpu->regs[reg]);
1829 skip_emulated_instruction(vcpu);
1832 vcpu_load_rsp_rip(vcpu);
1833 set_cr4(vcpu, vcpu->regs[reg]);
1834 skip_emulated_instruction(vcpu);
1837 vcpu_load_rsp_rip(vcpu);
1838 set_cr8(vcpu, vcpu->regs[reg]);
1839 skip_emulated_instruction(vcpu);
1844 vcpu_load_rsp_rip(vcpu);
1845 vmx_fpu_deactivate(vcpu);
1846 vcpu->cr0 &= ~X86_CR0_TS;
1847 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
1848 vmx_fpu_activate(vcpu);
1849 skip_emulated_instruction(vcpu);
1851 case 1: /*mov from cr*/
1854 vcpu_load_rsp_rip(vcpu);
1855 vcpu->regs[reg] = vcpu->cr3;
1856 vcpu_put_rsp_rip(vcpu);
1857 skip_emulated_instruction(vcpu);
1860 vcpu_load_rsp_rip(vcpu);
1861 vcpu->regs[reg] = vcpu->cr8;
1862 vcpu_put_rsp_rip(vcpu);
1863 skip_emulated_instruction(vcpu);
1868 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1870 skip_emulated_instruction(vcpu);
1875 kvm_run->exit_reason = 0;
1876 printk(KERN_ERR "kvm: unhandled control register: op %d cr %d\n",
1877 (int)(exit_qualification >> 4) & 3, cr);
1881 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1883 u64 exit_qualification;
1888 * FIXME: this code assumes the host is debugging the guest.
1889 * need to deal with guest debugging itself too.
1891 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1892 dr = exit_qualification & 7;
1893 reg = (exit_qualification >> 8) & 15;
1894 vcpu_load_rsp_rip(vcpu);
1895 if (exit_qualification & 16) {
1907 vcpu->regs[reg] = val;
1911 vcpu_put_rsp_rip(vcpu);
1912 skip_emulated_instruction(vcpu);
1916 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1918 kvm_emulate_cpuid(vcpu);
1922 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1924 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1927 if (vmx_get_msr(vcpu, ecx, &data)) {
1928 vmx_inject_gp(vcpu, 0);
1932 /* FIXME: handling of bits 32:63 of rax, rdx */
1933 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
1934 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
1935 skip_emulated_instruction(vcpu);
1939 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1941 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1942 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
1943 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1945 if (vmx_set_msr(vcpu, ecx, data) != 0) {
1946 vmx_inject_gp(vcpu, 0);
1950 skip_emulated_instruction(vcpu);
1954 static void post_kvm_run_save(struct kvm_vcpu *vcpu,
1955 struct kvm_run *kvm_run)
1957 kvm_run->if_flag = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) != 0;
1958 kvm_run->cr8 = vcpu->cr8;
1959 kvm_run->apic_base = vcpu->apic_base;
1960 kvm_run->ready_for_interrupt_injection = (vcpu->interrupt_window_open &&
1961 vcpu->irq_summary == 0);
1964 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
1965 struct kvm_run *kvm_run)
1968 * If the user space waits to inject interrupts, exit as soon as
1971 if (kvm_run->request_interrupt_window &&
1972 !vcpu->irq_summary) {
1973 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1974 ++vcpu->stat.irq_window_exits;
1980 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1982 skip_emulated_instruction(vcpu);
1983 return kvm_emulate_halt(vcpu);
1986 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1988 skip_emulated_instruction(vcpu);
1989 return kvm_hypercall(vcpu, kvm_run);
1993 * The exit handlers return 1 if the exit was handled fully and guest execution
1994 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
1995 * to be done to userspace and return 0.
1997 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
1998 struct kvm_run *kvm_run) = {
1999 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2000 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
2001 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
2002 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
2003 [EXIT_REASON_CR_ACCESS] = handle_cr,
2004 [EXIT_REASON_DR_ACCESS] = handle_dr,
2005 [EXIT_REASON_CPUID] = handle_cpuid,
2006 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2007 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2008 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2009 [EXIT_REASON_HLT] = handle_halt,
2010 [EXIT_REASON_VMCALL] = handle_vmcall,
2013 static const int kvm_vmx_max_exit_handlers =
2014 ARRAY_SIZE(kvm_vmx_exit_handlers);
2017 * The guest has exited. See if we can fix it or if we need userspace
2020 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2022 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2023 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2025 if ( (vectoring_info & VECTORING_INFO_VALID_MASK) &&
2026 exit_reason != EXIT_REASON_EXCEPTION_NMI )
2027 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2028 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
2029 if (exit_reason < kvm_vmx_max_exit_handlers
2030 && kvm_vmx_exit_handlers[exit_reason])
2031 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2033 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2034 kvm_run->hw.hardware_exit_reason = exit_reason;
2040 * Check if userspace requested an interrupt window, and that the
2041 * interrupt window is open.
2043 * No need to exit to userspace if we already have an interrupt queued.
2045 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
2046 struct kvm_run *kvm_run)
2048 return (!vcpu->irq_summary &&
2049 kvm_run->request_interrupt_window &&
2050 vcpu->interrupt_window_open &&
2051 (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF));
2054 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2058 static int vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2060 struct vcpu_vmx *vmx = to_vmx(vcpu);
2065 if (vcpu->guest_debug.enabled)
2066 kvm_guest_debug_pre(vcpu);
2069 r = kvm_mmu_reload(vcpu);
2073 if (!vcpu->mmio_read_completed)
2074 do_interrupt_requests(vcpu, kvm_run);
2076 vmx_save_host_state(vcpu);
2077 kvm_load_guest_fpu(vcpu);
2080 * Loading guest fpu may have cleared host cr0.ts
2082 vmcs_writel(HOST_CR0, read_cr0());
2084 local_irq_disable();
2086 vcpu->guest_mode = 1;
2088 if (test_and_clear_bit(KVM_TLB_FLUSH, &vcpu->requests))
2089 vmx_flush_tlb(vcpu);
2092 /* Store host registers */
2093 #ifdef CONFIG_X86_64
2094 "push %%rax; push %%rbx; push %%rdx;"
2095 "push %%rsi; push %%rdi; push %%rbp;"
2096 "push %%r8; push %%r9; push %%r10; push %%r11;"
2097 "push %%r12; push %%r13; push %%r14; push %%r15;"
2099 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2101 "pusha; push %%ecx \n\t"
2102 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2104 /* Check if vmlaunch of vmresume is needed */
2106 /* Load guest registers. Don't clobber flags. */
2107 #ifdef CONFIG_X86_64
2108 "mov %c[cr2](%3), %%rax \n\t"
2109 "mov %%rax, %%cr2 \n\t"
2110 "mov %c[rax](%3), %%rax \n\t"
2111 "mov %c[rbx](%3), %%rbx \n\t"
2112 "mov %c[rdx](%3), %%rdx \n\t"
2113 "mov %c[rsi](%3), %%rsi \n\t"
2114 "mov %c[rdi](%3), %%rdi \n\t"
2115 "mov %c[rbp](%3), %%rbp \n\t"
2116 "mov %c[r8](%3), %%r8 \n\t"
2117 "mov %c[r9](%3), %%r9 \n\t"
2118 "mov %c[r10](%3), %%r10 \n\t"
2119 "mov %c[r11](%3), %%r11 \n\t"
2120 "mov %c[r12](%3), %%r12 \n\t"
2121 "mov %c[r13](%3), %%r13 \n\t"
2122 "mov %c[r14](%3), %%r14 \n\t"
2123 "mov %c[r15](%3), %%r15 \n\t"
2124 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
2126 "mov %c[cr2](%3), %%eax \n\t"
2127 "mov %%eax, %%cr2 \n\t"
2128 "mov %c[rax](%3), %%eax \n\t"
2129 "mov %c[rbx](%3), %%ebx \n\t"
2130 "mov %c[rdx](%3), %%edx \n\t"
2131 "mov %c[rsi](%3), %%esi \n\t"
2132 "mov %c[rdi](%3), %%edi \n\t"
2133 "mov %c[rbp](%3), %%ebp \n\t"
2134 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
2136 /* Enter guest mode */
2137 "jne .Llaunched \n\t"
2138 ASM_VMX_VMLAUNCH "\n\t"
2139 "jmp .Lkvm_vmx_return \n\t"
2140 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2141 ".Lkvm_vmx_return: "
2142 /* Save guest registers, load host registers, keep flags */
2143 #ifdef CONFIG_X86_64
2144 "xchg %3, (%%rsp) \n\t"
2145 "mov %%rax, %c[rax](%3) \n\t"
2146 "mov %%rbx, %c[rbx](%3) \n\t"
2147 "pushq (%%rsp); popq %c[rcx](%3) \n\t"
2148 "mov %%rdx, %c[rdx](%3) \n\t"
2149 "mov %%rsi, %c[rsi](%3) \n\t"
2150 "mov %%rdi, %c[rdi](%3) \n\t"
2151 "mov %%rbp, %c[rbp](%3) \n\t"
2152 "mov %%r8, %c[r8](%3) \n\t"
2153 "mov %%r9, %c[r9](%3) \n\t"
2154 "mov %%r10, %c[r10](%3) \n\t"
2155 "mov %%r11, %c[r11](%3) \n\t"
2156 "mov %%r12, %c[r12](%3) \n\t"
2157 "mov %%r13, %c[r13](%3) \n\t"
2158 "mov %%r14, %c[r14](%3) \n\t"
2159 "mov %%r15, %c[r15](%3) \n\t"
2160 "mov %%cr2, %%rax \n\t"
2161 "mov %%rax, %c[cr2](%3) \n\t"
2162 "mov (%%rsp), %3 \n\t"
2164 "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
2165 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
2166 "pop %%rbp; pop %%rdi; pop %%rsi;"
2167 "pop %%rdx; pop %%rbx; pop %%rax \n\t"
2169 "xchg %3, (%%esp) \n\t"
2170 "mov %%eax, %c[rax](%3) \n\t"
2171 "mov %%ebx, %c[rbx](%3) \n\t"
2172 "pushl (%%esp); popl %c[rcx](%3) \n\t"
2173 "mov %%edx, %c[rdx](%3) \n\t"
2174 "mov %%esi, %c[rsi](%3) \n\t"
2175 "mov %%edi, %c[rdi](%3) \n\t"
2176 "mov %%ebp, %c[rbp](%3) \n\t"
2177 "mov %%cr2, %%eax \n\t"
2178 "mov %%eax, %c[cr2](%3) \n\t"
2179 "mov (%%esp), %3 \n\t"
2181 "pop %%ecx; popa \n\t"
2185 : "r"(vmx->launched), "d"((unsigned long)HOST_RSP),
2187 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
2188 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
2189 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
2190 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
2191 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
2192 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
2193 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
2194 #ifdef CONFIG_X86_64
2195 [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
2196 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
2197 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
2198 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
2199 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
2200 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
2201 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
2202 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
2204 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
2207 vcpu->guest_mode = 0;
2212 vcpu->interrupt_window_open = (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
2214 asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
2216 if (unlikely(fail)) {
2217 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2218 kvm_run->fail_entry.hardware_entry_failure_reason
2219 = vmcs_read32(VM_INSTRUCTION_ERROR);
2224 * Profile KVM exit RIPs:
2226 if (unlikely(prof_on == KVM_PROFILING))
2227 profile_hit(KVM_PROFILING, (void *)vmcs_readl(GUEST_RIP));
2230 r = kvm_handle_exit(kvm_run, vcpu);
2232 /* Give scheduler a change to reschedule. */
2233 if (signal_pending(current)) {
2235 kvm_run->exit_reason = KVM_EXIT_INTR;
2236 ++vcpu->stat.signal_exits;
2240 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
2242 kvm_run->exit_reason = KVM_EXIT_INTR;
2243 ++vcpu->stat.request_irq_exits;
2246 if (!need_resched()) {
2247 ++vcpu->stat.light_exits;
2258 post_kvm_run_save(vcpu, kvm_run);
2262 static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
2266 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2268 ++vcpu->stat.pf_guest;
2270 if (is_page_fault(vect_info)) {
2271 printk(KERN_DEBUG "inject_page_fault: "
2272 "double fault 0x%lx @ 0x%lx\n",
2273 addr, vmcs_readl(GUEST_RIP));
2274 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
2275 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2277 INTR_TYPE_EXCEPTION |
2278 INTR_INFO_DELIEVER_CODE_MASK |
2279 INTR_INFO_VALID_MASK);
2283 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
2284 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2286 INTR_TYPE_EXCEPTION |
2287 INTR_INFO_DELIEVER_CODE_MASK |
2288 INTR_INFO_VALID_MASK);
2292 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2294 struct vcpu_vmx *vmx = to_vmx(vcpu);
2297 on_each_cpu(__vcpu_clear, vcpu, 0, 1);
2298 free_vmcs(vmx->vmcs);
2303 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2305 vmx_free_vmcs(vcpu);
2308 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
2310 struct vcpu_vmx *vmx;
2312 vmx = kzalloc(sizeof(*vmx), GFP_KERNEL);
2316 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2317 if (!vmx->guest_msrs)
2320 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2321 if (!vmx->host_msrs)
2324 vmx->vmcs = alloc_vmcs();
2328 vmcs_clear(vmx->vmcs);
2337 kfree(vmx->host_msrs);
2339 if (vmx->guest_msrs)
2340 kfree(vmx->guest_msrs);
2347 static struct kvm_arch_ops vmx_arch_ops = {
2348 .cpu_has_kvm_support = cpu_has_kvm_support,
2349 .disabled_by_bios = vmx_disabled_by_bios,
2350 .hardware_setup = hardware_setup,
2351 .hardware_unsetup = hardware_unsetup,
2352 .hardware_enable = hardware_enable,
2353 .hardware_disable = hardware_disable,
2355 .vcpu_create = vmx_create_vcpu,
2356 .vcpu_free = vmx_free_vcpu,
2358 .vcpu_load = vmx_vcpu_load,
2359 .vcpu_put = vmx_vcpu_put,
2360 .vcpu_decache = vmx_vcpu_decache,
2362 .set_guest_debug = set_guest_debug,
2363 .get_msr = vmx_get_msr,
2364 .set_msr = vmx_set_msr,
2365 .get_segment_base = vmx_get_segment_base,
2366 .get_segment = vmx_get_segment,
2367 .set_segment = vmx_set_segment,
2368 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
2369 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
2370 .set_cr0 = vmx_set_cr0,
2371 .set_cr3 = vmx_set_cr3,
2372 .set_cr4 = vmx_set_cr4,
2373 #ifdef CONFIG_X86_64
2374 .set_efer = vmx_set_efer,
2376 .get_idt = vmx_get_idt,
2377 .set_idt = vmx_set_idt,
2378 .get_gdt = vmx_get_gdt,
2379 .set_gdt = vmx_set_gdt,
2380 .cache_regs = vcpu_load_rsp_rip,
2381 .decache_regs = vcpu_put_rsp_rip,
2382 .get_rflags = vmx_get_rflags,
2383 .set_rflags = vmx_set_rflags,
2385 .tlb_flush = vmx_flush_tlb,
2386 .inject_page_fault = vmx_inject_page_fault,
2388 .inject_gp = vmx_inject_gp,
2390 .run = vmx_vcpu_run,
2391 .skip_emulated_instruction = skip_emulated_instruction,
2392 .vcpu_setup = vmx_vcpu_setup,
2393 .patch_hypercall = vmx_patch_hypercall,
2396 static int __init vmx_init(void)
2401 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2402 if (!vmx_io_bitmap_a)
2405 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2406 if (!vmx_io_bitmap_b) {
2412 * Allow direct access to the PC debug port (it is often used for I/O
2413 * delays, but the vmexits simply slow things down).
2415 iova = kmap(vmx_io_bitmap_a);
2416 memset(iova, 0xff, PAGE_SIZE);
2417 clear_bit(0x80, iova);
2418 kunmap(vmx_io_bitmap_a);
2420 iova = kmap(vmx_io_bitmap_b);
2421 memset(iova, 0xff, PAGE_SIZE);
2422 kunmap(vmx_io_bitmap_b);
2424 r = kvm_init_arch(&vmx_arch_ops, THIS_MODULE);
2431 __free_page(vmx_io_bitmap_b);
2433 __free_page(vmx_io_bitmap_a);
2437 static void __exit vmx_exit(void)
2439 __free_page(vmx_io_bitmap_b);
2440 __free_page(vmx_io_bitmap_a);
2445 module_init(vmx_init)
2446 module_exit(vmx_exit)