err.no Git - linux-2.6/blob - drivers/kvm/paging_tmpl.h

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * MMU support
   8  *
   9  * Copyright (C) 2006 Qumranet, Inc.
  10  *
  11  * Authors:
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *   Avi Kivity   <avi@qumranet.com>
  14  *
  15  * This work is licensed under the terms of the GNU GPL, version 2.  See
  16  * the COPYING file in the top-level directory.
  17  *
  18  */
  19
  20 /*
  21  * We need the mmu code to access both 32-bit and 64-bit guest ptes,
  22  * so the code in this file is compiled twice, once per pte size.
  23  */
  24
  25 #if PTTYPE == 64
  26         #define pt_element_t u64
  27         #define guest_walker guest_walker64
  28         #define FNAME(name) paging##64_##name
  29         #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
  30         #define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
  31         #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
  32         #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
  33         #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
  34         #define PT_PTE_COPY_MASK PT64_PTE_COPY_MASK
  35         #ifdef CONFIG_X86_64
  36         #define PT_MAX_FULL_LEVELS 4
  37         #else
  38         #define PT_MAX_FULL_LEVELS 2
  39         #endif
  40 #elif PTTYPE == 32
  41         #define pt_element_t u32
  42         #define guest_walker guest_walker32
  43         #define FNAME(name) paging##32_##name
  44         #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
  45         #define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
  46         #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
  47         #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
  48         #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
  49         #define PT_PTE_COPY_MASK PT32_PTE_COPY_MASK
  50         #define PT_MAX_FULL_LEVELS 2
  51 #else
  52         #error Invalid PTTYPE value
  53 #endif
  54
  55 /*
  56  * The guest_walker structure emulates the behavior of the hardware page
  57  * table walker.
  58  */
  59 struct guest_walker {
  60         int level;
  61         gfn_t table_gfn[PT_MAX_FULL_LEVELS];
  62         pt_element_t *table;
  63         pt_element_t *ptep;
  64         pt_element_t inherited_ar;
  65         gfn_t gfn;
  66         u32 error_code;
  67 };
  68
  69 /*
  70  * Fetch a guest pte for a guest virtual address
  71  */
  72 static int FNAME(walk_addr)(struct guest_walker *walker,
  73                             struct kvm_vcpu *vcpu, gva_t addr,
  74                             int write_fault, int user_fault, int fetch_fault)
  75 {
  76         hpa_t hpa;
  77         struct kvm_memory_slot *slot;
  78         pt_element_t *ptep;
  79         pt_element_t root;
  80         gfn_t table_gfn;
  81
  82         pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
  83         walker->level = vcpu->mmu.root_level;
  84         walker->table = NULL;
  85         root = vcpu->cr3;
  86 #if PTTYPE == 64
  87         if (!is_long_mode(vcpu)) {
  88                 walker->ptep = &vcpu->pdptrs[(addr >> 30) & 3];
  89                 root = *walker->ptep;
  90                 if (!(root & PT_PRESENT_MASK))
  91                         goto not_present;
  92                 --walker->level;
  93         }
  94 #endif
  95         table_gfn = (root & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
  96         walker->table_gfn[walker->level - 1] = table_gfn;
  97         pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
  98                  walker->level - 1, table_gfn);
  99         slot = gfn_to_memslot(vcpu->kvm, table_gfn);
 100         hpa = safe_gpa_to_hpa(vcpu, root & PT64_BASE_ADDR_MASK);
 101         walker->table = kmap_atomic(pfn_to_page(hpa >> PAGE_SHIFT), KM_USER0);
 102
 103         ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
 104                (vcpu->cr3 & ~(PAGE_MASK | CR3_FLAGS_MASK)) == 0);
 105
 106         walker->inherited_ar = PT_USER_MASK | PT_WRITABLE_MASK;
 107
 108         for (;;) {
 109                 int index = PT_INDEX(addr, walker->level);
 110                 hpa_t paddr;
 111
 112                 ptep = &walker->table[index];
 113                 ASSERT(((unsigned long)walker->table & PAGE_MASK) ==
 114                        ((unsigned long)ptep & PAGE_MASK));
 115
 116                 if (!is_present_pte(*ptep))
 117                         goto not_present;
 118
 119                 if (write_fault && !is_writeble_pte(*ptep))
 120                         if (user_fault || is_write_protection(vcpu))
 121                                 goto access_error;
 122
 123                 if (user_fault && !(*ptep & PT_USER_MASK))
 124                         goto access_error;
 125
 126 #if PTTYPE == 64
 127                 if (fetch_fault && is_nx(vcpu) && (*ptep & PT64_NX_MASK))
 128                         goto access_error;
 129 #endif
 130
 131                 if (!(*ptep & PT_ACCESSED_MASK)) {
 132                         mark_page_dirty(vcpu->kvm, table_gfn);
 133                         *ptep |= PT_ACCESSED_MASK;
 134                 }
 135
 136                 if (walker->level == PT_PAGE_TABLE_LEVEL) {
 137                         walker->gfn = (*ptep & PT_BASE_ADDR_MASK)
 138                                 >> PAGE_SHIFT;
 139                         break;
 140                 }
 141
 142                 if (walker->level == PT_DIRECTORY_LEVEL
 143                     && (*ptep & PT_PAGE_SIZE_MASK)
 144                     && (PTTYPE == 64 || is_pse(vcpu))) {
 145                         walker->gfn = (*ptep & PT_DIR_BASE_ADDR_MASK)
 146                                 >> PAGE_SHIFT;
 147                         walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
 148                         break;
 149                 }
 150
 151                 walker->inherited_ar &= walker->table[index];
 152                 table_gfn = (*ptep & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
 153                 paddr = safe_gpa_to_hpa(vcpu, *ptep & PT_BASE_ADDR_MASK);
 154                 kunmap_atomic(walker->table, KM_USER0);
 155                 walker->table = kmap_atomic(pfn_to_page(paddr >> PAGE_SHIFT),
 156                                             KM_USER0);
 157                 --walker->level;
 158                 walker->table_gfn[walker->level - 1 ] = table_gfn;
 159                 pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
 160                          walker->level - 1, table_gfn);
 161         }
 162         walker->ptep = ptep;
 163         pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)*ptep);
 164         return 1;
 165
 166 not_present:
 167         walker->error_code = 0;
 168         goto err;
 169
 170 access_error:
 171         walker->error_code = PFERR_PRESENT_MASK;
 172
 173 err:
 174         if (write_fault)
 175                 walker->error_code |= PFERR_WRITE_MASK;
 176         if (user_fault)
 177                 walker->error_code |= PFERR_USER_MASK;
 178         if (fetch_fault)
 179                 walker->error_code |= PFERR_FETCH_MASK;
 180         return 0;
 181 }
 182
 183 static void FNAME(release_walker)(struct guest_walker *walker)
 184 {
 185         if (walker->table)
 186                 kunmap_atomic(walker->table, KM_USER0);
 187 }
 188
 189 static void FNAME(mark_pagetable_dirty)(struct kvm *kvm,
 190                                         struct guest_walker *walker)
 191 {
 192         mark_page_dirty(kvm, walker->table_gfn[walker->level - 1]);
 193 }
 194
 195 static void FNAME(set_pte_common)(struct kvm_vcpu *vcpu,
 196                                   u64 *shadow_pte,
 197                                   gpa_t gaddr,
 198                                   pt_element_t *gpte,
 199                                   u64 access_bits,
 200                                   int write_fault,
 201                                   gfn_t gfn)
 202 {
 203         hpa_t paddr;
 204         int dirty = *gpte & PT_DIRTY_MASK;
 205
 206         *shadow_pte |= access_bits << PT_SHADOW_BITS_OFFSET;
 207         if (!dirty)
 208                 access_bits &= ~PT_WRITABLE_MASK;
 209
 210         paddr = gpa_to_hpa(vcpu, gaddr & PT64_BASE_ADDR_MASK);
 211
 212         *shadow_pte |= access_bits;
 213
 214         if (is_error_hpa(paddr)) {
 215                 *shadow_pte |= gaddr;
 216                 *shadow_pte |= PT_SHADOW_IO_MARK;
 217                 *shadow_pte &= ~PT_PRESENT_MASK;
 218                 return;
 219         }
 220
 221         *shadow_pte |= paddr;
 222
 223         if (!write_fault && (*shadow_pte & PT_SHADOW_USER_MASK) &&
 224             !(*shadow_pte & PT_USER_MASK)) {
 225                 /*
 226                  * If supervisor write protect is disabled, we shadow kernel
 227                  * pages as user pages so we can trap the write access.
 228                  */
 229                 *shadow_pte |= PT_USER_MASK;
 230                 *shadow_pte &= ~PT_WRITABLE_MASK;
 231                 access_bits &= ~PT_WRITABLE_MASK;
 232         }
 233
 234         if (access_bits & PT_WRITABLE_MASK) {
 235                 struct kvm_mmu_page *shadow;
 236
 237                 shadow = kvm_mmu_lookup_page(vcpu, gfn);
 238                 if (shadow) {
 239                         pgprintk("%s: found shadow page for %lx, marking ro\n",
 240                                  __FUNCTION__, gfn);
 241                         access_bits &= ~PT_WRITABLE_MASK;
 242                         if (is_writeble_pte(*shadow_pte)) {
 243                                     *shadow_pte &= ~PT_WRITABLE_MASK;
 244                                     kvm_arch_ops->tlb_flush(vcpu);
 245                         }
 246                 }
 247         }
 248
 249         if (access_bits & PT_WRITABLE_MASK)
 250                 mark_page_dirty(vcpu->kvm, gaddr >> PAGE_SHIFT);
 251
 252         page_header_update_slot(vcpu->kvm, shadow_pte, gaddr);
 253         rmap_add(vcpu, shadow_pte);
 254 }
 255
 256 static void FNAME(set_pte)(struct kvm_vcpu *vcpu, pt_element_t *gpte,
 257                            u64 *shadow_pte, u64 access_bits,
 258                            int write_fault, gfn_t gfn)
 259 {
 260         ASSERT(*shadow_pte == 0);
 261         access_bits &= *gpte;
 262         *shadow_pte = (*gpte & PT_PTE_COPY_MASK);
 263         FNAME(set_pte_common)(vcpu, shadow_pte, *gpte & PT_BASE_ADDR_MASK,
 264                               gpte, access_bits, write_fault, gfn);
 265 }
 266
 267 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
 268                               u64 *spte, const void *pte, int bytes)
 269 {
 270         pt_element_t gpte;
 271
 272         if (bytes < sizeof(pt_element_t))
 273                 return;
 274         gpte = *(const pt_element_t *)pte;
 275         if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK))
 276                 return;
 277         pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte);
 278         FNAME(set_pte)(vcpu, &gpte, spte, PT_USER_MASK | PT_WRITABLE_MASK, 0,
 279                        (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT);
 280 }
 281
 282 static void FNAME(set_pde)(struct kvm_vcpu *vcpu, pt_element_t *gpde,
 283                            u64 *shadow_pte, u64 access_bits, int write_fault,
 284                            gfn_t gfn)
 285 {
 286         gpa_t gaddr;
 287
 288         ASSERT(*shadow_pte == 0);
 289         access_bits &= *gpde;
 290         gaddr = (gpa_t)gfn << PAGE_SHIFT;
 291         if (PTTYPE == 32 && is_cpuid_PSE36())
 292                 gaddr |= (*gpde & PT32_DIR_PSE36_MASK) <<
 293                         (32 - PT32_DIR_PSE36_SHIFT);
 294         *shadow_pte = *gpde & PT_PTE_COPY_MASK;
 295         FNAME(set_pte_common)(vcpu, shadow_pte, gaddr,
 296                               gpde, access_bits, write_fault, gfn);
 297 }
 298
 299 /*
 300  * Fetch a shadow pte for a specific level in the paging hierarchy.
 301  */
 302 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
 303                          struct guest_walker *walker, int write_fault)
 304 {
 305         hpa_t shadow_addr;
 306         int level;
 307         u64 *shadow_ent;
 308         u64 *prev_shadow_ent = NULL;
 309         pt_element_t *guest_ent = walker->ptep;
 310
 311         if (!is_present_pte(*guest_ent))
 312                 return NULL;
 313
 314         shadow_addr = vcpu->mmu.root_hpa;
 315         level = vcpu->mmu.shadow_root_level;
 316         if (level == PT32E_ROOT_LEVEL) {
 317                 shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3];
 318                 shadow_addr &= PT64_BASE_ADDR_MASK;
 319                 --level;
 320         }
 321
 322         for (; ; level--) {
 323                 u32 index = SHADOW_PT_INDEX(addr, level);
 324                 struct kvm_mmu_page *shadow_page;
 325                 u64 shadow_pte;
 326                 int metaphysical;
 327                 gfn_t table_gfn;
 328                 unsigned hugepage_access = 0;
 329
 330                 shadow_ent = ((u64 *)__va(shadow_addr)) + index;
 331                 if (is_present_pte(*shadow_ent) || is_io_pte(*shadow_ent)) {
 332                         if (level == PT_PAGE_TABLE_LEVEL)
 333                                 return shadow_ent;
 334                         shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
 335                         prev_shadow_ent = shadow_ent;
 336                         continue;
 337                 }
 338
 339                 if (level == PT_PAGE_TABLE_LEVEL)
 340                         break;
 341
 342                 if (level - 1 == PT_PAGE_TABLE_LEVEL
 343                     && walker->level == PT_DIRECTORY_LEVEL) {
 344                         metaphysical = 1;
 345                         hugepage_access = *guest_ent;
 346                         hugepage_access &= PT_USER_MASK | PT_WRITABLE_MASK;
 347                         hugepage_access >>= PT_WRITABLE_SHIFT;
 348                         table_gfn = (*guest_ent & PT_BASE_ADDR_MASK)
 349                                 >> PAGE_SHIFT;
 350                 } else {
 351                         metaphysical = 0;
 352                         table_gfn = walker->table_gfn[level - 2];
 353                 }
 354                 shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
 355                                                metaphysical, hugepage_access,
 356                                                shadow_ent);
 357                 shadow_addr = __pa(shadow_page->spt);
 358                 shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK
 359                         | PT_WRITABLE_MASK | PT_USER_MASK;
 360                 *shadow_ent = shadow_pte;
 361                 prev_shadow_ent = shadow_ent;
 362         }
 363
 364         if (walker->level == PT_DIRECTORY_LEVEL) {
 365                 if (prev_shadow_ent)
 366                         *prev_shadow_ent |= PT_SHADOW_PS_MARK;
 367                 FNAME(set_pde)(vcpu, guest_ent, shadow_ent,
 368                                walker->inherited_ar, write_fault, walker->gfn);
 369         } else {
 370                 ASSERT(walker->level == PT_PAGE_TABLE_LEVEL);
 371                 FNAME(set_pte)(vcpu, guest_ent, shadow_ent,
 372                                walker->inherited_ar,
 373                                write_fault, walker->gfn);
 374         }
 375         return shadow_ent;
 376 }
 377
 378 /*
 379  * The guest faulted for write.  We need to
 380  *
 381  * - check write permissions
 382  * - update the guest pte dirty bit
 383  * - update our own dirty page tracking structures
 384  */
 385 static int FNAME(fix_write_pf)(struct kvm_vcpu *vcpu,
 386                                u64 *shadow_ent,
 387                                struct guest_walker *walker,
 388                                gva_t addr,
 389                                int user,
 390                                int *write_pt)
 391 {
 392         pt_element_t *guest_ent;
 393         int writable_shadow;
 394         gfn_t gfn;
 395         struct kvm_mmu_page *page;
 396
 397         if (is_writeble_pte(*shadow_ent))
 398                 return !user || (*shadow_ent & PT_USER_MASK);
 399
 400         writable_shadow = *shadow_ent & PT_SHADOW_WRITABLE_MASK;
 401         if (user) {
 402                 /*
 403                  * User mode access.  Fail if it's a kernel page or a read-only
 404                  * page.
 405                  */
 406                 if (!(*shadow_ent & PT_SHADOW_USER_MASK) || !writable_shadow)
 407                         return 0;
 408                 ASSERT(*shadow_ent & PT_USER_MASK);
 409         } else
 410                 /*
 411                  * Kernel mode access.  Fail if it's a read-only page and
 412                  * supervisor write protection is enabled.
 413                  */
 414                 if (!writable_shadow) {
 415                         if (is_write_protection(vcpu))
 416                                 return 0;
 417                         *shadow_ent &= ~PT_USER_MASK;
 418                 }
 419
 420         guest_ent = walker->ptep;
 421
 422         if (!is_present_pte(*guest_ent)) {
 423                 *shadow_ent = 0;
 424                 return 0;
 425         }
 426
 427         gfn = walker->gfn;
 428
 429         if (user) {
 430                 /*
 431                  * Usermode page faults won't be for page table updates.
 432                  */
 433                 while ((page = kvm_mmu_lookup_page(vcpu, gfn)) != NULL) {
 434                         pgprintk("%s: zap %lx %x\n",
 435                                  __FUNCTION__, gfn, page->role.word);
 436                         kvm_mmu_zap_page(vcpu, page);
 437                 }
 438         } else if (kvm_mmu_lookup_page(vcpu, gfn)) {
 439                 pgprintk("%s: found shadow page for %lx, marking ro\n",
 440                          __FUNCTION__, gfn);
 441                 mark_page_dirty(vcpu->kvm, gfn);
 442                 FNAME(mark_pagetable_dirty)(vcpu->kvm, walker);
 443                 *guest_ent |= PT_DIRTY_MASK;
 444                 *write_pt = 1;
 445                 return 0;
 446         }
 447         mark_page_dirty(vcpu->kvm, gfn);
 448         *shadow_ent |= PT_WRITABLE_MASK;
 449         FNAME(mark_pagetable_dirty)(vcpu->kvm, walker);
 450         *guest_ent |= PT_DIRTY_MASK;
 451         rmap_add(vcpu, shadow_ent);
 452
 453         return 1;
 454 }
 455
 456 /*
 457  * Page fault handler.  There are several causes for a page fault:
 458  *   - there is no shadow pte for the guest pte
 459  *   - write access through a shadow pte marked read only so that we can set
 460  *     the dirty bit
 461  *   - write access to a shadow pte marked read only so we can update the page
 462  *     dirty bitmap, when userspace requests it
 463  *   - mmio access; in this case we will never install a present shadow pte
 464  *   - normal guest page fault due to the guest pte marked not present, not
 465  *     writable, or not executable
 466  *
 467  *  Returns: 1 if we need to emulate the instruction, 0 otherwise, or
 468  *           a negative value on error.
 469  */
 470 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
 471                                u32 error_code)
 472 {
 473         int write_fault = error_code & PFERR_WRITE_MASK;
 474         int user_fault = error_code & PFERR_USER_MASK;
 475         int fetch_fault = error_code & PFERR_FETCH_MASK;
 476         struct guest_walker walker;
 477         u64 *shadow_pte;
 478         int fixed;
 479         int write_pt = 0;
 480         int r;
 481
 482         pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
 483         kvm_mmu_audit(vcpu, "pre page fault");
 484
 485         r = mmu_topup_memory_caches(vcpu);
 486         if (r)
 487                 return r;
 488
 489         /*
 490          * Look up the shadow pte for the faulting address.
 491          */
 492         r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
 493                              fetch_fault);
 494
 495         /*
 496          * The page is not mapped by the guest.  Let the guest handle it.
 497          */
 498         if (!r) {
 499                 pgprintk("%s: guest page fault\n", __FUNCTION__);
 500                 inject_page_fault(vcpu, addr, walker.error_code);
 501                 FNAME(release_walker)(&walker);
 502                 vcpu->last_pt_write_count = 0; /* reset fork detector */
 503                 return 0;
 504         }
 505
 506         shadow_pte = FNAME(fetch)(vcpu, addr, &walker, write_fault);
 507         pgprintk("%s: shadow pte %p %llx\n", __FUNCTION__,
 508                  shadow_pte, *shadow_pte);
 509
 510         /*
 511          * Update the shadow pte.
 512          */
 513         if (write_fault)
 514                 fixed = FNAME(fix_write_pf)(vcpu, shadow_pte, &walker, addr,
 515                                             user_fault, &write_pt);
 516
 517         pgprintk("%s: updated shadow pte %p %llx\n", __FUNCTION__,
 518                  shadow_pte, *shadow_pte);
 519
 520         FNAME(release_walker)(&walker);
 521
 522         if (!write_pt)
 523                 vcpu->last_pt_write_count = 0; /* reset fork detector */
 524
 525         /*
 526          * mmio: emulate if accessible, otherwise its a guest fault.
 527          */
 528         if (is_io_pte(*shadow_pte))
 529                 return 1;
 530
 531         ++vcpu->stat.pf_fixed;
 532         kvm_mmu_audit(vcpu, "post page fault (fixed)");
 533
 534         return write_pt;
 535 }
 536
 537 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
 538 {
 539         struct guest_walker walker;
 540         gpa_t gpa = UNMAPPED_GVA;
 541         int r;
 542
 543         r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
 544
 545         if (r) {
 546                 gpa = (gpa_t)walker.gfn << PAGE_SHIFT;
 547                 gpa |= vaddr & ~PAGE_MASK;
 548         }
 549
 550         FNAME(release_walker)(&walker);
 551         return gpa;
 552 }
 553
 554 #undef pt_element_t
 555 #undef guest_walker
 556 #undef FNAME
 557 #undef PT_BASE_ADDR_MASK
 558 #undef PT_INDEX
 559 #undef SHADOW_PT_INDEX
 560 #undef PT_LEVEL_MASK
 561 #undef PT_PTE_COPY_MASK
 562 #undef PT_NON_PTE_COPY_MASK
 563 #undef PT_DIR_BASE_ADDR_MASK
 564 #undef PT_MAX_FULL_LEVELS