2 * see notice in hfc_multi.c
5 extern void ztdummy_extern_interrupt(void);
6 extern void ztdummy_register_interrupt(void);
7 extern int ztdummy_unregister_interrupt(void);
9 #define DEBUG_HFCMULTI_FIFO 0x00010000
10 #define DEBUG_HFCMULTI_CRC 0x00020000
11 #define DEBUG_HFCMULTI_INIT 0x00040000
12 #define DEBUG_HFCMULTI_PLXSD 0x00080000
13 #define DEBUG_HFCMULTI_MODE 0x00100000
14 #define DEBUG_HFCMULTI_MSG 0x00200000
15 #define DEBUG_HFCMULTI_STATE 0x00400000
16 #define DEBUG_HFCMULTI_SYNC 0x01000000
17 #define DEBUG_HFCMULTI_DTMF 0x02000000
18 #define DEBUG_HFCMULTI_LOCK 0x80000000
20 #define PCI_ENA_REGIO 0x01
21 #define PCI_ENA_MEMIO 0x02
24 * NOTE: some registers are assigned multiple times due to different modes
25 * also registers are assigned differen for HFC-4s/8s and HFC-E1
29 #define MAX_FRAME_SIZE 2048
33 struct dchannel *dch; /* link if channel is a D-channel */
34 struct bchannel *bch; /* link if channel is a B-channel */
35 int port; /* the interface port this */
36 /* channel is associated with */
37 int nt_timer; /* -1 if off, 0 if elapsed, >0 if running */
38 int los, ais, slip_tx, slip_rx, rdi; /* current alarms */
40 u_long cfg; /* port configuration */
41 int sync; /* sync state (used by E1) */
42 u_int protocol; /* current protocol */
43 int slot_tx; /* current pcm slot */
44 int bank_tx; /* current pcm bank */
47 int conf; /* conference setting of TX slot */
48 int txpending; /* if there is currently data in */
49 /* the FIFO 0=no, 1=yes, 2=splloop */
50 int rx_off; /* set to turn fifo receive off */
51 int coeff_count; /* curren coeff block */
52 s32 *coeff; /* memory pointer to 8 coeff blocks */
72 /* for each stack these flags are used (cfg) */
73 #define HFC_CFG_NONCAP_TX 1 /* S/T TX interface has less capacity */
74 #define HFC_CFG_DIS_ECHANNEL 2 /* disable E-channel processing */
75 #define HFC_CFG_REG_ECHANNEL 3 /* register E-channel */
76 #define HFC_CFG_OPTICAL 4 /* the E1 interface is optical */
77 #define HFC_CFG_REPORT_LOS 5 /* the card should report loss of signal */
78 #define HFC_CFG_REPORT_AIS 6 /* the card should report alarm ind. sign. */
79 #define HFC_CFG_REPORT_SLIP 7 /* the card should report bit slips */
80 #define HFC_CFG_REPORT_RDI 8 /* the card should report remote alarm */
81 #define HFC_CFG_DTMF 9 /* enable DTMF-detection */
82 #define HFC_CFG_CRC4 10 /* disable CRC-4 Multiframe mode, */
83 /* use double frame instead. */
85 #define HFC_CHIP_EXRAM_128 0 /* external ram 128k */
86 #define HFC_CHIP_EXRAM_512 1 /* external ram 256k */
87 #define HFC_CHIP_REVISION0 2 /* old fifo handling */
88 #define HFC_CHIP_PCM_SLAVE 3 /* PCM is slave */
89 #define HFC_CHIP_PCM_MASTER 4 /* PCM is master */
90 #define HFC_CHIP_RX_SYNC 5 /* disable pll sync for pcm */
91 #define HFC_CHIP_DTMF 6 /* DTMF decoding is enabled */
92 #define HFC_CHIP_ULAW 7 /* ULAW mode */
93 #define HFC_CHIP_CLOCK2 8 /* double clock mode */
94 #define HFC_CHIP_E1CLOCK_GET 9 /* always get clock from E1 interface */
95 #define HFC_CHIP_E1CLOCK_PUT 10 /* always put clock from E1 interface */
96 #define HFC_CHIP_WATCHDOG 11 /* whether we should send signals */
98 #define HFC_CHIP_B410P 12 /* whether we have a b410p with echocan in */
100 #define HFC_CHIP_PLXSD 13 /* whether we have a Speech-Design PLX */
102 #define HFC_IO_MODE_PCIMEM 0x00 /* normal memory mapped IO */
103 #define HFC_IO_MODE_REGIO 0x01 /* PCI io access */
104 #define HFC_IO_MODE_PLXSD 0x02 /* access HFC via PLX9030 */
106 /* table entry in the PCI devices list */
120 struct list_head list;
123 int pcm; /* id of pcm bus */
127 u_int irq; /* irq used by card */
129 struct pci_dev *pci_dev;
130 int io_mode; /* selects mode */
131 #ifdef HFC_REGISTER_DEBUG
132 void (*HFC_outb)(struct hfc_multi *hc, u_char reg,
133 u_char val, const char *function, int line);
134 void (*HFC_outb_nodebug)(struct hfc_multi *hc, u_char reg,
135 u_char val, const char *function, int line);
136 u_char (*HFC_inb)(struct hfc_multi *hc, u_char reg,
137 const char *function, int line);
138 u_char (*HFC_inb_nodebug)(struct hfc_multi *hc, u_char reg,
139 const char *function, int line);
140 u_short (*HFC_inw)(struct hfc_multi *hc, u_char reg,
141 const char *function, int line);
142 u_short (*HFC_inw_nodebug)(struct hfc_multi *hc, u_char reg,
143 const char *function, int line);
144 void (*HFC_wait)(struct hfc_multi *hc,
145 const char *function, int line);
146 void (*HFC_wait_nodebug)(struct hfc_multi *hc,
147 const char *function, int line);
149 void (*HFC_outb)(struct hfc_multi *hc, u_char reg,
151 void (*HFC_outb_nodebug)(struct hfc_multi *hc, u_char reg,
153 u_char (*HFC_inb)(struct hfc_multi *hc, u_char reg);
154 u_char (*HFC_inb_nodebug)(struct hfc_multi *hc, u_char reg);
155 u_short (*HFC_inw)(struct hfc_multi *hc, u_char reg);
156 u_short (*HFC_inw_nodebug)(struct hfc_multi *hc, u_char reg);
157 void (*HFC_wait)(struct hfc_multi *hc);
158 void (*HFC_wait_nodebug)(struct hfc_multi *hc);
160 void (*read_fifo)(struct hfc_multi *hc, u_char *data,
162 void (*write_fifo)(struct hfc_multi *hc, u_char *data,
164 u_long pci_origmembase, plx_origmembase, dsp_origmembase;
165 u_char *pci_membase; /* PCI memory (MUST BE BYTE POINTER) */
166 u_char *plx_membase; /* PLX memory */
167 u_char *dsp_membase; /* DSP on PLX */
168 u_long pci_iobase; /* PCI IO */
169 struct hfcm_hw hw; /* remember data of write-only-registers */
171 u_long chip; /* chip configuration */
172 int masterclk; /* port that provides master clock -1=off */
173 int dtmf; /* flag that dtmf is currently in process */
174 int Flen; /* F-buffer size */
175 int Zlen; /* Z-buffer size (must be int for calculation)*/
176 int max_trans; /* maximum transparent fifo fill */
177 int Zmin; /* Z-buffer offset */
178 int DTMFbase; /* base address of DTMF coefficients */
180 u_int slots; /* number of PCM slots */
181 u_int leds; /* type of leds */
182 u_int ledcount; /* used to animate leds */
183 u_long ledstate; /* save last state of leds */
184 int opticalsupport; /* has the e1 board */
185 /* an optical Interface */
186 int dslot; /* channel # of d-channel (E1) default 16 */
188 u_long wdcount; /* every 500 ms we need to */
189 /* send the watchdog a signal */
190 u_char wdbyte; /* watchdog toggle byte */
191 u_int activity[8]; /* if there is any action on this */
192 /* port (will be cleared after */
193 /* showing led-states) */
194 int e1_state; /* keep track of last state */
195 int e1_getclock; /* if sync is retrieved from interface */
196 int syncronized; /* keep track of existing sync interface */
197 int e1_resync; /* resync jobs */
199 spinlock_t lock; /* the lock */
202 * the channel index is counted from 0, regardless where the channel
203 * is located on the hfc-channel.
204 * the bch->channel is equvalent to the hfc-channel
206 struct hfc_chan chan[32];
207 u_char created[8]; /* what port is created */
208 signed char slot_owner[256]; /* owner channel of slot */
212 #define PLX_GPIO4_DIR_BIT 13
213 #define PLX_GPIO4_BIT 14
214 #define PLX_GPIO5_DIR_BIT 16
215 #define PLX_GPIO5_BIT 17
216 #define PLX_GPIO6_DIR_BIT 19
217 #define PLX_GPIO6_BIT 20
218 #define PLX_GPIO7_DIR_BIT 22
219 #define PLX_GPIO7_BIT 23
220 #define PLX_GPIO8_DIR_BIT 25
221 #define PLX_GPIO8_BIT 26
223 #define PLX_GPIO4 (1 << PLX_GPIO4_BIT)
224 #define PLX_GPIO5 (1 << PLX_GPIO5_BIT)
225 #define PLX_GPIO6 (1 << PLX_GPIO6_BIT)
226 #define PLX_GPIO7 (1 << PLX_GPIO7_BIT)
227 #define PLX_GPIO8 (1 << PLX_GPIO8_BIT)
229 #define PLX_GPIO4_DIR (1 << PLX_GPIO4_DIR_BIT)
230 #define PLX_GPIO5_DIR (1 << PLX_GPIO5_DIR_BIT)
231 #define PLX_GPIO6_DIR (1 << PLX_GPIO6_DIR_BIT)
232 #define PLX_GPIO7_DIR (1 << PLX_GPIO7_DIR_BIT)
233 #define PLX_GPIO8_DIR (1 << PLX_GPIO8_DIR_BIT)
235 #define PLX_TERM_ON PLX_GPIO7
236 #define PLX_SLAVE_EN_N PLX_GPIO5
237 #define PLX_MASTER_EN PLX_GPIO6
238 #define PLX_SYNC_O_EN PLX_GPIO4
239 #define PLX_DSP_RES_N PLX_GPIO8
240 /* GPIO4..8 Enable & Set to OUT, SLAVE_EN_N = 1 */
241 #define PLX_GPIOC_INIT (PLX_GPIO4_DIR | PLX_GPIO5_DIR | PLX_GPIO6_DIR \
242 | PLX_GPIO7_DIR | PLX_GPIO8_DIR | PLX_SLAVE_EN_N)
244 /* PLX Interrupt Control/STATUS */
245 #define PLX_INTCSR_LINTI1_ENABLE 0x01
246 #define PLX_INTCSR_LINTI1_STATUS 0x04
247 #define PLX_INTCSR_LINTI2_ENABLE 0x08
248 #define PLX_INTCSR_LINTI2_STATUS 0x20
249 #define PLX_INTCSR_PCIINT_ENABLE 0x40
252 #define PLX_INTCSR 0x4c
253 #define PLX_CNTRL 0x50
254 #define PLX_GPIOC 0x54
258 * REGISTER SETTING FOR HFC-4S/8S AND HFC-E1
261 /* write only registers */
264 #define R_BRG_PCM_CFG 0x02
265 #define R_RAM_ADDR0 0x08
266 #define R_RAM_ADDR1 0x09
267 #define R_RAM_ADDR2 0x0A
268 #define R_FIRST_FIFO 0x0B
269 #define R_RAM_SZ 0x0C
270 #define R_FIFO_MD 0x0D
271 #define R_INC_RES_FIFO 0x0E
272 #define R_FSM_IDX 0x0F
275 #define R_IRQMSK_MISC 0x11
276 #define R_SCI_MSK 0x12
277 #define R_IRQ_CTRL 0x13
278 #define R_PCM_MD0 0x14
279 #define R_PCM_MD1 0x15
280 #define R_PCM_MD2 0x15
285 #define R_SL_SEL0 0x15
286 #define R_SL_SEL1 0x15
287 #define R_SL_SEL2 0x15
288 #define R_SL_SEL3 0x15
289 #define R_SL_SEL4 0x15
290 #define R_SL_SEL5 0x15
291 #define R_SL_SEL6 0x15
292 #define R_SL_SEL7 0x15
293 #define R_ST_SEL 0x16
294 #define R_ST_SYNC 0x17
295 #define R_CONF_EN 0x18
297 #define R_BERT_WD_MD 0x1B
299 #define R_DTMF_N 0x1D
300 #define R_E1_WR_STA 0x20
301 #define R_E1_RD_STA 0x20
305 #define R_RX_FR0 0x25
306 #define R_RX_FR1 0x26
309 #define R_TX_FR0 0x2C
311 #define R_TX_FR1 0x2D
312 #define R_TX_FR2 0x2E
313 #define R_JATT_ATT 0x2F /* undocumented */
314 #define A_ST_RD_STATE 0x30
315 #define A_ST_WR_STATE 0x30
316 #define R_RX_OFF 0x30
317 #define A_ST_CTRL0 0x31
318 #define R_SYNC_OUT 0x31
319 #define A_ST_CTRL1 0x32
320 #define A_ST_CTRL2 0x33
321 #define A_ST_SQ_WR 0x34
322 #define R_TX_OFF 0x34
323 #define R_SYNC_CTRL 0x35
324 #define A_ST_CLK_DLY 0x37
327 #define A_ST_B1_TX 0x3C
328 #define A_ST_B2_TX 0x3D
329 #define A_ST_D_TX 0x3E
330 #define R_GPIO_OUT0 0x40
331 #define R_GPIO_OUT1 0x41
332 #define R_GPIO_EN0 0x42
333 #define R_GPIO_EN1 0x43
334 #define R_GPIO_SEL 0x44
335 #define R_BRG_CTRL 0x45
336 #define R_PWM_MD 0x46
337 #define R_BRG_MD 0x47
338 #define R_BRG_TIM0 0x48
339 #define R_BRG_TIM1 0x49
340 #define R_BRG_TIM2 0x4A
341 #define R_BRG_TIM3 0x4B
342 #define R_BRG_TIM_SEL01 0x4C
343 #define R_BRG_TIM_SEL23 0x4D
344 #define R_BRG_TIM_SEL45 0x4E
345 #define R_BRG_TIM_SEL67 0x4F
346 #define A_SL_CFG 0xD0
348 #define A_CH_MSK 0xF4
349 #define A_CON_HDLC 0xFA
350 #define A_SUBCH_CFG 0xFB
351 #define A_CHANNEL 0xFC
352 #define A_FIFO_SEQ 0xFD
353 #define A_IRQ_MSK 0xFF
355 /* read only registers */
366 #define R_IRQ_OVIEW 0x10
367 #define R_IRQ_MISC 0x11
368 #define R_IRQ_STATECH 0x12
369 #define R_CONF_OFLOW 0x14
370 #define R_RAM_USE 0x15
371 #define R_CHIP_ID 0x16
372 #define R_BERT_STA 0x17
373 #define R_F0_CNTL 0x18
374 #define R_F0_CNTH 0x19
375 #define R_BERT_EC 0x1A
376 #define R_BERT_ECL 0x1A
377 #define R_BERT_ECH 0x1B
378 #define R_STATUS 0x1C
379 #define R_CHIP_RV 0x1F
381 #define R_SYNC_STA 0x24
382 #define R_RX_SL0_0 0x25
383 #define R_RX_SL0_1 0x26
384 #define R_RX_SL0_2 0x27
385 #define R_JATT_DIR 0x2b /* undocumented */
387 #define A_ST_RD_STA 0x30
388 #define R_FAS_EC 0x30
389 #define R_FAS_ECL 0x30
390 #define R_FAS_ECH 0x31
391 #define R_VIO_EC 0x32
392 #define R_VIO_ECL 0x32
393 #define R_VIO_ECH 0x33
394 #define A_ST_SQ_RD 0x34
395 #define R_CRC_EC 0x34
396 #define R_CRC_ECL 0x34
397 #define R_CRC_ECH 0x35
401 #define R_SA6_SA13_EC 0x38
402 #define R_SA6_SA13_ECL 0x38
403 #define R_SA6_SA13_ECH 0x39
404 #define R_SA6_SA23_EC 0x3A
405 #define R_SA6_SA23_ECL 0x3A
406 #define R_SA6_SA23_ECH 0x3B
407 #define A_ST_B1_RX 0x3C
408 #define A_ST_B2_RX 0x3D
409 #define A_ST_D_RX 0x3E
410 #define A_ST_E_RX 0x3F
411 #define R_GPIO_IN0 0x40
412 #define R_GPIO_IN1 0x41
413 #define R_GPI_IN0 0x44
414 #define R_GPI_IN1 0x45
415 #define R_GPI_IN2 0x46
416 #define R_GPI_IN3 0x47
417 #define R_INT_DATA 0x88
418 #define R_IRQ_FIFO_BL0 0xC8
419 #define R_IRQ_FIFO_BL1 0xC9
420 #define R_IRQ_FIFO_BL2 0xCA
421 #define R_IRQ_FIFO_BL3 0xCB
422 #define R_IRQ_FIFO_BL4 0xCC
423 #define R_IRQ_FIFO_BL5 0xCD
424 #define R_IRQ_FIFO_BL6 0xCE
425 #define R_IRQ_FIFO_BL7 0xCF
427 /* read and write registers */
428 #define A_FIFO_DATA0 0x80
429 #define A_FIFO_DATA1 0x80
430 #define A_FIFO_DATA2 0x80
431 #define A_FIFO_DATA0_NOINC 0x84
432 #define A_FIFO_DATA1_NOINC 0x84
433 #define A_FIFO_DATA2_NOINC 0x84
434 #define R_RAM_DATA 0xC0
438 * BIT SETTING FOR HFC-4S/8S AND HFC-E1
441 /* chapter 2: universal bus interface */
443 #define V_IRQ_SEL 0x01
445 #define V_HFCRES 0x10
446 #define V_PCMRES 0x20
449 #define V_RLD_EPR 0x80
451 #define V_FIFO_LPRIO 0x02
452 #define V_SLOW_RD 0x04
453 #define V_EXT_RAM 0x08
454 #define V_CLK_OFF 0x20
455 #define V_ST_CLK 0x40
457 #define V_RAM_ADDR2 0x01
458 #define V_ADDR_RES 0x40
459 #define V_ADDR_INC 0x80
461 #define V_RAM_SZ 0x01
462 #define V_PWM0_16KHZ 0x10
463 #define V_PWM1_16KHZ 0x20
466 #define V_PNP_IRQ 0x01
467 #define V_CHIP_ID 0x10
469 /* chapter 3: data flow */
471 #define V_FIRST_FIRO_DIR 0x01
472 #define V_FIRST_FIFO_NUM 0x02
474 #define V_FIFO_MD 0x01
475 #define V_CSM_MD 0x04
476 #define V_FSM_MD 0x08
477 #define V_FIFO_SZ 0x10
479 #define V_FIFO_DIR 0x01
480 #define V_FIFO_NUM 0x02
483 #define V_SL_DIR 0x01
484 #define V_SL_NUM 0x02
486 #define V_CH_DIR 0x01
487 #define V_CH_SEL 0x02
488 #define V_ROUTING 0x40
491 #define V_HDLC_TRP 0x02
492 #define V_TRP_IRQ 0x04
493 #define V_DATA_FLOW 0x20
495 #define V_BIT_CNT 0x01
496 #define V_START_BIT 0x08
497 #define V_LOOP_FIFO 0x40
498 #define V_INV_DATA 0x80
500 #define V_CH_DIR0 0x01
501 #define V_CH_NUM0 0x02
503 #define V_NEXT_FIFO_DIR 0x01
504 #define V_NEXT_FIFO_NUM 0x02
505 #define V_SEQ_END 0x40
507 /* chapter 4: FIFO handling and HDLC controller */
511 #define V_RES_LOST 0x04
513 /* chapter 5: S/T interface */
515 #define V_SCI_MSK_ST0 0x01
516 #define V_SCI_MSK_ST1 0x02
517 #define V_SCI_MSK_ST2 0x04
518 #define V_SCI_MSK_ST3 0x08
519 #define V_SCI_MSK_ST4 0x10
520 #define V_SCI_MSK_ST5 0x20
521 #define V_SCI_MSK_ST6 0x40
522 #define V_SCI_MSK_ST7 0x80
524 #define V_ST_SEL 0x01
525 #define V_MULT_ST 0x08
527 #define V_SYNC_SEL 0x01
528 #define V_AUTO_SYNC 0x08
530 #define V_ST_SET_STA 0x01
531 #define V_ST_LD_STA 0x10
532 #define V_ST_ACT 0x20
533 #define V_SET_G2_G3 0x80
538 #define V_D_PRIO 0x08
542 #define V_ST_STOP 0x80
544 #define V_G2_G3_EN 0x01
546 #define V_E_IGNO 0x08
548 #define V_B12_SWAP 0x80
550 #define V_B1_RX_EN 0x01
551 #define V_B2_RX_EN 0x02
552 #define V_ST_TRIS 0x40
554 #define V_ST_CK_DLY 0x01
555 #define V_ST_SMPL 0x10
557 #define V_ST_D_TX 0x40
559 #define V_SCI_ST0 0x01
560 #define V_SCI_ST1 0x02
561 #define V_SCI_ST2 0x04
562 #define V_SCI_ST3 0x08
563 #define V_SCI_ST4 0x10
564 #define V_SCI_ST5 0x20
565 #define V_SCI_ST6 0x40
566 #define V_SCI_ST7 0x80
568 #define V_ST_STA 0x01
569 #define V_FR_SYNC_ST 0x10
570 #define V_TI2_EXP 0x20
575 #define V_MF_RX_RDY 0x10
576 #define V_MF_TX_RDY 0x80
578 #define V_ST_D_RX 0x40
580 #define V_ST_E_RX 0x40
582 /* chapter 5: E1 interface */
585 #define V_E1_SET_STA 0x01
586 #define V_E1_LD_STA 0x10
588 #define V_RX_CODE 0x01
589 #define V_RX_FBAUD 0x04
590 #define V_RX_CMI 0x08
591 #define V_RX_INV_CMI 0x10
592 #define V_RX_INV_CLK 0x20
593 #define V_RX_INV_DATA 0x40
594 #define V_AIS_ITU 0x80
596 #define V_NO_INSYNC 0x01
597 #define V_AUTO_RESYNC 0x02
598 #define V_AUTO_RECO 0x04
599 #define V_SWORD_COND 0x08
600 #define V_SYNC_LOSS 0x10
601 #define V_XCRC_SYNC 0x20
602 #define V_MF_RESYNC 0x40
603 #define V_RESYNC 0x80
606 #define V_RX_MF_SYNC 0x02
607 #define V_RX_SL0_RAM 0x04
608 #define V_ERR_SIM 0x20
609 #define V_RES_NMF 0x40
611 #define V_TX_CODE 0x01
612 #define V_TX_FBAUD 0x04
613 #define V_TX_CMI_CODE 0x08
614 #define V_TX_INV_CMI_CODE 0x10
615 #define V_TX_INV_CLK 0x20
616 #define V_TX_INV_DATA 0x40
617 #define V_OUT_EN 0x80
619 #define V_INV_CLK 0x01
620 #define V_EXCHG_DATA_LI 0x02
621 #define V_AIS_OUT 0x04
624 #define V_AUTO_ERR_RES 0x80
626 #define V_TRP_FAS 0x01
627 #define V_TRP_NFAS 0x02
628 #define V_TRP_RAL 0x04
629 #define V_TRP_SA 0x08
631 #define V_TX_FAS 0x01
632 #define V_TX_NFAS 0x02
633 #define V_TX_RAL 0x04
637 #define V_TRP_SL0 0x02
638 #define V_TX_SL0_RAM 0x04
641 #define V_XS12_ON 0x40
642 #define V_XS15_ON 0x80
645 #define V_RX_INIT 0x04
647 #define V_SYNC_E1_RX 0x01
648 #define V_IPATS0 0x20
649 #define V_IPATS1 0x40
650 #define V_IPATS2 0x80
653 #define V_TX_INIT 0x04
655 #define V_EXT_CLK_SYNC 0x01
656 #define V_SYNC_OFFS 0x02
657 #define V_PCM_SYNC 0x04
658 #define V_NEG_CLK 0x08
661 #define V_JATT_AUTO_DEL 0x20
662 #define V_JATT_AUTO 0x40
664 #define V_JATT_OFF 0x80
666 #define V_E1_STA 0x01
667 #define V_ALT_FR_RX 0x40
668 #define V_ALT_FR_TX 0x80
670 #define V_RX_STA 0x01
671 #define V_FR_SYNC_E1 0x04
672 #define V_SIG_LOS 0x08
673 #define V_MFA_STA 0x10
675 #define V_NO_MF_SYNC 0x80
677 #define V_SI_FAS 0x01
678 #define V_SI_NFAS 0x02
680 #define V_CRC_OK 0x08
686 #define V_SLIP_RX 0x01
687 #define V_FOSLIP_RX 0x08
688 #define V_SLIP_TX 0x10
689 #define V_FOSLIP_TX 0x80
691 /* chapter 6: PCM interface */
693 #define V_PCM_MD 0x01
694 #define V_C4_POL 0x02
695 #define V_F0_NEG 0x04
696 #define V_F0_LEN 0x08
697 #define V_PCM_ADDR 0x10
699 #define V_SL_SEL0 0x01
700 #define V_SH_SEL0 0x80
702 #define V_SL_SEL1 0x01
703 #define V_SH_SEL1 0x80
705 #define V_SL_SEL2 0x01
706 #define V_SH_SEL2 0x80
708 #define V_SL_SEL3 0x01
709 #define V_SH_SEL3 0x80
711 #define V_SL_SEL4 0x01
712 #define V_SH_SEL4 0x80
714 #define V_SL_SEL5 0x01
715 #define V_SH_SEL5 0x80
717 #define V_SL_SEL6 0x01
718 #define V_SH_SEL6 0x80
720 #define V_SL_SEL7 0x01
721 #define V_SH_SEL7 0x80
723 #define V_ODEC_CON 0x01
724 #define V_PLL_ADJ 0x04
725 #define V_PCM_DR 0x10
726 #define V_PCM_LOOP 0x40
728 #define V_SYNC_PLL 0x02
729 #define V_SYNC_SRC 0x04
730 #define V_SYNC_OUT 0x08
731 #define V_ICR_FR_TIME 0x40
732 #define V_EN_PLL 0x80
734 /* chapter 7: pulse width modulation */
736 #define V_EXT_IRQ_EN 0x08
737 #define V_PWM0_MD 0x10
738 #define V_PWM1_MD 0x40
740 /* chapter 8: multiparty audio conferences */
742 #define V_CONF_EN 0x01
745 #define V_CONF_NUM 0x01
746 #define V_NOISE_SUPPR 0x08
747 #define V_ATT_LEV 0x20
748 #define V_CONF_SL 0x80
750 #define V_CONF_OFLOW0 0x01
751 #define V_CONF_OFLOW1 0x02
752 #define V_CONF_OFLOW2 0x04
753 #define V_CONF_OFLOW3 0x08
754 #define V_CONF_OFLOW4 0x10
755 #define V_CONF_OFLOW5 0x20
756 #define V_CONF_OFLOW6 0x40
757 #define V_CONF_OFLOW7 0x80
759 /* chapter 9: DTMF contoller */
761 #define V_DTMF_EN 0x01
762 #define V_HARM_SEL 0x02
763 #define V_DTMF_RX_CH 0x04
764 #define V_DTMF_STOP 0x08
765 #define V_CHBL_SEL 0x10
766 #define V_RST_DTMF 0x40
767 #define V_ULAW_SEL 0x80
769 /* chapter 10: BERT */
771 #define V_PAT_SEQ 0x01
772 #define V_BERT_ERR 0x08
773 #define V_AUTO_WD_RES 0x20
774 #define V_WD_RES 0x80
776 #define V_BERT_SYNC_SRC 0x01
777 #define V_BERT_SYNC 0x10
778 #define V_BERT_INV_DATA 0x20
780 /* chapter 11: auxiliary interface */
782 #define V_BRG_EN 0x01
783 #define V_BRG_MD 0x02
784 #define V_PCM_CLK 0x20
785 #define V_ADDR_WRDLY 0x40
787 #define V_BRG_CS 0x01
788 #define V_BRG_ADDR 0x08
789 #define V_BRG_CS_SRC 0x80
791 #define V_BRG_MD0 0x01
792 #define V_BRG_MD1 0x02
793 #define V_BRG_MD2 0x04
794 #define V_BRG_MD3 0x08
795 #define V_BRG_MD4 0x10
796 #define V_BRG_MD5 0x20
797 #define V_BRG_MD6 0x40
798 #define V_BRG_MD7 0x80
800 #define V_BRG_TIM0_IDLE 0x01
801 #define V_BRG_TIM0_CLK 0x10
803 #define V_BRG_TIM1_IDLE 0x01
804 #define V_BRG_TIM1_CLK 0x10
806 #define V_BRG_TIM2_IDLE 0x01
807 #define V_BRG_TIM2_CLK 0x10
809 #define V_BRG_TIM3_IDLE 0x01
810 #define V_BRG_TIM3_CLK 0x10
811 /* R_BRG_TIM_SEL01 */
812 #define V_BRG_WR_SEL0 0x01
813 #define V_BRG_RD_SEL0 0x04
814 #define V_BRG_WR_SEL1 0x10
815 #define V_BRG_RD_SEL1 0x40
816 /* R_BRG_TIM_SEL23 */
817 #define V_BRG_WR_SEL2 0x01
818 #define V_BRG_RD_SEL2 0x04
819 #define V_BRG_WR_SEL3 0x10
820 #define V_BRG_RD_SEL3 0x40
821 /* R_BRG_TIM_SEL45 */
822 #define V_BRG_WR_SEL4 0x01
823 #define V_BRG_RD_SEL4 0x04
824 #define V_BRG_WR_SEL5 0x10
825 #define V_BRG_RD_SEL5 0x40
826 /* R_BRG_TIM_SEL67 */
827 #define V_BRG_WR_SEL6 0x01
828 #define V_BRG_RD_SEL6 0x04
829 #define V_BRG_WR_SEL7 0x10
830 #define V_BRG_RD_SEL7 0x40
832 /* chapter 12: clock, reset, interrupt, timer and watchdog */
834 #define V_STA_IRQMSK 0x01
835 #define V_TI_IRQMSK 0x02
836 #define V_PROC_IRQMSK 0x04
837 #define V_DTMF_IRQMSK 0x08
838 #define V_IRQ1S_MSK 0x10
839 #define V_SA6_IRQMSK 0x20
840 #define V_RX_EOMF_MSK 0x40
841 #define V_TX_EOMF_MSK 0x80
843 #define V_FIFO_IRQ 0x01
844 #define V_GLOB_IRQ_EN 0x08
845 #define V_IRQ_POL 0x10
851 #define V_BERT_EN 0x02
852 #define V_MIX_IRQ 0x04
854 #define V_IRQ_FIFO_BL0 0x01
855 #define V_IRQ_FIFO_BL1 0x02
856 #define V_IRQ_FIFO_BL2 0x04
857 #define V_IRQ_FIFO_BL3 0x08
858 #define V_IRQ_FIFO_BL4 0x10
859 #define V_IRQ_FIFO_BL5 0x20
860 #define V_IRQ_FIFO_BL6 0x40
861 #define V_IRQ_FIFO_BL7 0x80
863 #define V_STA_IRQ 0x01
864 #define V_TI_IRQ 0x02
865 #define V_IRQ_PROC 0x04
866 #define V_DTMF_IRQ 0x08
868 #define V_SA6_IRQ 0x20
869 #define V_RX_EOMF 0x40
870 #define V_TX_EOMF 0x80
874 #define V_DTMF_STA 0x04
875 #define V_LOST_STA 0x08
876 #define V_SYNC_IN 0x10
877 #define V_EXT_IRQSTA 0x20
878 #define V_MISC_IRQSTA 0x40
879 #define V_FR_IRQSTA 0x80
881 #define V_IRQ_FIFO0_TX 0x01
882 #define V_IRQ_FIFO0_RX 0x02
883 #define V_IRQ_FIFO1_TX 0x04
884 #define V_IRQ_FIFO1_RX 0x08
885 #define V_IRQ_FIFO2_TX 0x10
886 #define V_IRQ_FIFO2_RX 0x20
887 #define V_IRQ_FIFO3_TX 0x40
888 #define V_IRQ_FIFO3_RX 0x80
890 #define V_IRQ_FIFO4_TX 0x01
891 #define V_IRQ_FIFO4_RX 0x02
892 #define V_IRQ_FIFO5_TX 0x04
893 #define V_IRQ_FIFO5_RX 0x08
894 #define V_IRQ_FIFO6_TX 0x10
895 #define V_IRQ_FIFO6_RX 0x20
896 #define V_IRQ_FIFO7_TX 0x40
897 #define V_IRQ_FIFO7_RX 0x80
899 #define V_IRQ_FIFO8_TX 0x01
900 #define V_IRQ_FIFO8_RX 0x02
901 #define V_IRQ_FIFO9_TX 0x04
902 #define V_IRQ_FIFO9_RX 0x08
903 #define V_IRQ_FIFO10_TX 0x10
904 #define V_IRQ_FIFO10_RX 0x20
905 #define V_IRQ_FIFO11_TX 0x40
906 #define V_IRQ_FIFO11_RX 0x80
908 #define V_IRQ_FIFO12_TX 0x01
909 #define V_IRQ_FIFO12_RX 0x02
910 #define V_IRQ_FIFO13_TX 0x04
911 #define V_IRQ_FIFO13_RX 0x08
912 #define V_IRQ_FIFO14_TX 0x10
913 #define V_IRQ_FIFO14_RX 0x20
914 #define V_IRQ_FIFO15_TX 0x40
915 #define V_IRQ_FIFO15_RX 0x80
917 #define V_IRQ_FIFO16_TX 0x01
918 #define V_IRQ_FIFO16_RX 0x02
919 #define V_IRQ_FIFO17_TX 0x04
920 #define V_IRQ_FIFO17_RX 0x08
921 #define V_IRQ_FIFO18_TX 0x10
922 #define V_IRQ_FIFO18_RX 0x20
923 #define V_IRQ_FIFO19_TX 0x40
924 #define V_IRQ_FIFO19_RX 0x80
926 #define V_IRQ_FIFO20_TX 0x01
927 #define V_IRQ_FIFO20_RX 0x02
928 #define V_IRQ_FIFO21_TX 0x04
929 #define V_IRQ_FIFO21_RX 0x08
930 #define V_IRQ_FIFO22_TX 0x10
931 #define V_IRQ_FIFO22_RX 0x20
932 #define V_IRQ_FIFO23_TX 0x40
933 #define V_IRQ_FIFO23_RX 0x80
935 #define V_IRQ_FIFO24_TX 0x01
936 #define V_IRQ_FIFO24_RX 0x02
937 #define V_IRQ_FIFO25_TX 0x04
938 #define V_IRQ_FIFO25_RX 0x08
939 #define V_IRQ_FIFO26_TX 0x10
940 #define V_IRQ_FIFO26_RX 0x20
941 #define V_IRQ_FIFO27_TX 0x40
942 #define V_IRQ_FIFO27_RX 0x80
944 #define V_IRQ_FIFO28_TX 0x01
945 #define V_IRQ_FIFO28_RX 0x02
946 #define V_IRQ_FIFO29_TX 0x04
947 #define V_IRQ_FIFO29_RX 0x08
948 #define V_IRQ_FIFO30_TX 0x10
949 #define V_IRQ_FIFO30_RX 0x20
950 #define V_IRQ_FIFO31_TX 0x40
951 #define V_IRQ_FIFO31_RX 0x80
953 /* chapter 13: general purpose I/O pins (GPIO) and input pins (GPI) */
955 #define V_GPIO_OUT0 0x01
956 #define V_GPIO_OUT1 0x02
957 #define V_GPIO_OUT2 0x04
958 #define V_GPIO_OUT3 0x08
959 #define V_GPIO_OUT4 0x10
960 #define V_GPIO_OUT5 0x20
961 #define V_GPIO_OUT6 0x40
962 #define V_GPIO_OUT7 0x80
964 #define V_GPIO_OUT8 0x01
965 #define V_GPIO_OUT9 0x02
966 #define V_GPIO_OUT10 0x04
967 #define V_GPIO_OUT11 0x08
968 #define V_GPIO_OUT12 0x10
969 #define V_GPIO_OUT13 0x20
970 #define V_GPIO_OUT14 0x40
971 #define V_GPIO_OUT15 0x80
973 #define V_GPIO_EN0 0x01
974 #define V_GPIO_EN1 0x02
975 #define V_GPIO_EN2 0x04
976 #define V_GPIO_EN3 0x08
977 #define V_GPIO_EN4 0x10
978 #define V_GPIO_EN5 0x20
979 #define V_GPIO_EN6 0x40
980 #define V_GPIO_EN7 0x80
982 #define V_GPIO_EN8 0x01
983 #define V_GPIO_EN9 0x02
984 #define V_GPIO_EN10 0x04
985 #define V_GPIO_EN11 0x08
986 #define V_GPIO_EN12 0x10
987 #define V_GPIO_EN13 0x20
988 #define V_GPIO_EN14 0x40
989 #define V_GPIO_EN15 0x80
991 #define V_GPIO_SEL0 0x01
992 #define V_GPIO_SEL1 0x02
993 #define V_GPIO_SEL2 0x04
994 #define V_GPIO_SEL3 0x08
995 #define V_GPIO_SEL4 0x10
996 #define V_GPIO_SEL5 0x20
997 #define V_GPIO_SEL6 0x40
998 #define V_GPIO_SEL7 0x80
1000 #define V_GPIO_IN0 0x01
1001 #define V_GPIO_IN1 0x02
1002 #define V_GPIO_IN2 0x04
1003 #define V_GPIO_IN3 0x08
1004 #define V_GPIO_IN4 0x10
1005 #define V_GPIO_IN5 0x20
1006 #define V_GPIO_IN6 0x40
1007 #define V_GPIO_IN7 0x80
1009 #define V_GPIO_IN8 0x01
1010 #define V_GPIO_IN9 0x02
1011 #define V_GPIO_IN10 0x04
1012 #define V_GPIO_IN11 0x08
1013 #define V_GPIO_IN12 0x10
1014 #define V_GPIO_IN13 0x20
1015 #define V_GPIO_IN14 0x40
1016 #define V_GPIO_IN15 0x80
1018 #define V_GPI_IN0 0x01
1019 #define V_GPI_IN1 0x02
1020 #define V_GPI_IN2 0x04
1021 #define V_GPI_IN3 0x08
1022 #define V_GPI_IN4 0x10
1023 #define V_GPI_IN5 0x20
1024 #define V_GPI_IN6 0x40
1025 #define V_GPI_IN7 0x80
1027 #define V_GPI_IN8 0x01
1028 #define V_GPI_IN9 0x02
1029 #define V_GPI_IN10 0x04
1030 #define V_GPI_IN11 0x08
1031 #define V_GPI_IN12 0x10
1032 #define V_GPI_IN13 0x20
1033 #define V_GPI_IN14 0x40
1034 #define V_GPI_IN15 0x80
1036 #define V_GPI_IN16 0x01
1037 #define V_GPI_IN17 0x02
1038 #define V_GPI_IN18 0x04
1039 #define V_GPI_IN19 0x08
1040 #define V_GPI_IN20 0x10
1041 #define V_GPI_IN21 0x20
1042 #define V_GPI_IN22 0x40
1043 #define V_GPI_IN23 0x80
1045 #define V_GPI_IN24 0x01
1046 #define V_GPI_IN25 0x02
1047 #define V_GPI_IN26 0x04
1048 #define V_GPI_IN27 0x08
1049 #define V_GPI_IN28 0x10
1050 #define V_GPI_IN29 0x20
1051 #define V_GPI_IN30 0x40
1052 #define V_GPI_IN31 0x80
1054 /* map of all registers, used for debugging */
1056 #ifdef HFC_REGISTER_DEBUG
1057 struct hfc_register_names {
1060 } hfc_register_names[] = {
1061 /* write registers */
1064 {"R_BRG_PCM_CFG ", 0x02},
1065 {"R_RAM_ADDR0", 0x08},
1066 {"R_RAM_ADDR1", 0x09},
1067 {"R_RAM_ADDR2", 0x0A},
1068 {"R_FIRST_FIFO", 0x0B},
1070 {"R_FIFO_MD", 0x0D},
1071 {"R_INC_RES_FIFO", 0x0E},
1072 {"R_FIFO / R_FSM_IDX", 0x0F},
1074 {"R_IRQMSK_MISC", 0x11},
1075 {"R_SCI_MSK", 0x12},
1076 {"R_IRQ_CTRL", 0x13},
1077 {"R_PCM_MD0", 0x14},
1080 {"R_ST_SYNC", 0x17},
1081 {"R_CONF_EN", 0x18},
1083 {"R_BERT_WD_MD", 0x1B},
1086 {"R_E1_XX_STA", 0x20},
1097 {"R_JATT_ATT", 0x2F},
1098 {"A_ST_xx_STA/R_RX_OFF", 0x30},
1099 {"A_ST_CTRL0/R_SYNC_OUT", 0x31},
1100 {"A_ST_CTRL1", 0x32},
1101 {"A_ST_CTRL2", 0x33},
1102 {"A_ST_SQ_WR", 0x34},
1104 {"R_SYNC_CTRL", 0x35},
1105 {"A_ST_CLK_DLY", 0x37},
1108 {"A_ST_B1_TX", 0x3C},
1109 {"A_ST_B2_TX", 0x3D},
1110 {"A_ST_D_TX", 0x3E},
1111 {"R_GPIO_OUT0", 0x40},
1112 {"R_GPIO_OUT1", 0x41},
1113 {"R_GPIO_EN0", 0x42},
1114 {"R_GPIO_EN1", 0x43},
1115 {"R_GPIO_SEL", 0x44},
1116 {"R_BRG_CTRL", 0x45},
1119 {"R_BRG_TIM0", 0x48},
1120 {"R_BRG_TIM1", 0x49},
1121 {"R_BRG_TIM2", 0x4A},
1122 {"R_BRG_TIM3", 0x4B},
1123 {"R_BRG_TIM_SEL01", 0x4C},
1124 {"R_BRG_TIM_SEL23", 0x4D},
1125 {"R_BRG_TIM_SEL45", 0x4E},
1126 {"R_BRG_TIM_SEL67", 0x4F},
1127 {"A_FIFO_DATA0-2", 0x80},
1128 {"A_FIFO_DATA0-2_NOINC", 0x84},
1129 {"R_RAM_DATA", 0xC0},
1133 {"A_CON_HDLC", 0xFA},
1134 {"A_SUBCH_CFG", 0xFB},
1135 {"A_CHANNEL", 0xFC},
1136 {"A_FIFO_SEQ", 0xFD},
1137 {"A_IRQ_MSK", 0xFF},
1140 /* read registers */
1147 {"R_IRQ_OVIEW", 0x10},
1148 {"R_IRQ_MISC", 0x11},
1149 {"R_IRQ_STATECH", 0x12},
1150 {"R_CONF_OFLOW", 0x14},
1151 {"R_RAM_USE", 0x15},
1152 {"R_CHIP_ID", 0x16},
1153 {"R_BERT_STA", 0x17},
1154 {"R_F0_CNTL", 0x18},
1155 {"R_F0_CNTH", 0x19},
1156 {"R_BERT_ECL", 0x1A},
1157 {"R_BERT_ECH", 0x1B},
1159 {"R_CHIP_RV", 0x1F},
1161 {"R_SYNC_STA", 0x24},
1162 {"R_RX_SL0_0", 0x25},
1163 {"R_RX_SL0_1", 0x26},
1164 {"R_RX_SL0_2", 0x27},
1165 {"R_JATT_DIR", 0x2b},
1167 {"A_ST_RD_STA", 0x30},
1168 {"R_FAS_ECL", 0x30},
1169 {"R_FAS_ECH", 0x31},
1170 {"R_VIO_ECL", 0x32},
1171 {"R_VIO_ECH", 0x33},
1172 {"R_CRC_ECL / A_ST_SQ_RD", 0x34},
1173 {"R_CRC_ECH", 0x35},
1176 {"R_SA6_SA13_ECL", 0x38},
1177 {"R_SA6_SA13_ECH", 0x39},
1178 {"R_SA6_SA23_ECL", 0x3A},
1179 {"R_SA6_SA23_ECH", 0x3B},
1180 {"A_ST_B1_RX", 0x3C},
1181 {"A_ST_B2_RX", 0x3D},
1182 {"A_ST_D_RX", 0x3E},
1183 {"A_ST_E_RX", 0x3F},
1184 {"R_GPIO_IN0", 0x40},
1185 {"R_GPIO_IN1", 0x41},
1186 {"R_GPI_IN0", 0x44},
1187 {"R_GPI_IN1", 0x45},
1188 {"R_GPI_IN2", 0x46},
1189 {"R_GPI_IN3", 0x47},
1190 {"A_FIFO_DATA0-2", 0x80},
1191 {"A_FIFO_DATA0-2_NOINC", 0x84},
1192 {"R_INT_DATA", 0x88},
1193 {"R_RAM_DATA", 0xC0},
1194 {"R_IRQ_FIFO_BL0", 0xC8},
1195 {"R_IRQ_FIFO_BL1", 0xC9},
1196 {"R_IRQ_FIFO_BL2", 0xCA},
1197 {"R_IRQ_FIFO_BL3", 0xCB},
1198 {"R_IRQ_FIFO_BL4", 0xCC},
1199 {"R_IRQ_FIFO_BL5", 0xCD},
1200 {"R_IRQ_FIFO_BL6", 0xCE},
1201 {"R_IRQ_FIFO_BL7", 0xCF},
1203 #endif /* HFC_REGISTER_DEBUG */