2 * i8042 keyboard and mouse controller driver for Linux
4 * Copyright (c) 1999-2004 Vojtech Pavlik
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
13 #include <linux/delay.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/interrupt.h>
17 #include <linux/ioport.h>
18 #include <linux/config.h>
19 #include <linux/init.h>
20 #include <linux/serio.h>
21 #include <linux/err.h>
22 #include <linux/rcupdate.h>
26 MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>");
27 MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver");
28 MODULE_LICENSE("GPL");
30 static unsigned int i8042_noaux;
31 module_param_named(noaux, i8042_noaux, bool, 0);
32 MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port.");
34 static unsigned int i8042_nomux;
35 module_param_named(nomux, i8042_nomux, bool, 0);
36 MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing conrtoller is present.");
38 static unsigned int i8042_unlock;
39 module_param_named(unlock, i8042_unlock, bool, 0);
40 MODULE_PARM_DESC(unlock, "Ignore keyboard lock.");
42 static unsigned int i8042_reset;
43 module_param_named(reset, i8042_reset, bool, 0);
44 MODULE_PARM_DESC(reset, "Reset controller during init and cleanup.");
46 static unsigned int i8042_direct;
47 module_param_named(direct, i8042_direct, bool, 0);
48 MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode.");
50 static unsigned int i8042_dumbkbd;
51 module_param_named(dumbkbd, i8042_dumbkbd, bool, 0);
52 MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard");
54 static unsigned int i8042_noloop;
55 module_param_named(noloop, i8042_noloop, bool, 0);
56 MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port");
58 static unsigned int i8042_blink_frequency = 500;
59 module_param_named(panicblink, i8042_blink_frequency, uint, 0600);
60 MODULE_PARM_DESC(panicblink, "Frequency with which keyboard LEDs should blink when kernel panics");
63 static int i8042_nopnp;
64 module_param_named(nopnp, i8042_nopnp, bool, 0);
65 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings");
70 static int i8042_debug;
71 module_param_named(debug, i8042_debug, bool, 0600);
72 MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off");
75 __obsolete_setup("i8042_noaux");
76 __obsolete_setup("i8042_nomux");
77 __obsolete_setup("i8042_unlock");
78 __obsolete_setup("i8042_reset");
79 __obsolete_setup("i8042_direct");
80 __obsolete_setup("i8042_dumbkbd");
84 static DEFINE_SPINLOCK(i8042_lock);
89 unsigned char disable;
96 #define I8042_KBD_PORT_NO 0
97 #define I8042_AUX_PORT_NO 1
98 #define I8042_MUX_PORT_NO 2
99 #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2)
100 static struct i8042_port i8042_ports[I8042_NUM_PORTS] = {
102 .disable = I8042_CTR_KBDDIS,
103 .irqen = I8042_CTR_KBDINT,
108 .disable = I8042_CTR_AUXDIS,
109 .irqen = I8042_CTR_AUXINT,
115 static unsigned char i8042_initial_ctr;
116 static unsigned char i8042_ctr;
117 static unsigned char i8042_mux_open;
118 static unsigned char i8042_mux_present;
119 static struct timer_list i8042_timer;
120 static struct platform_device *i8042_platform_device;
124 * Shared IRQ's require a device pointer, but this driver doesn't support
127 #define i8042_request_irq_cookie (&i8042_timer)
129 static irqreturn_t i8042_interrupt(int irq, void *dev_id, struct pt_regs *regs);
132 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to
133 * be ready for reading values from it / writing values to it.
134 * Called always with i8042_lock held.
137 static int i8042_wait_read(void)
140 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) {
144 return -(i == I8042_CTL_TIMEOUT);
147 static int i8042_wait_write(void)
150 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) {
154 return -(i == I8042_CTL_TIMEOUT);
158 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers
159 * of the i8042 down the toilet.
162 static int i8042_flush(void)
165 unsigned char data, str;
168 spin_lock_irqsave(&i8042_lock, flags);
170 while (((str = i8042_read_status()) & I8042_STR_OBF) && (i < I8042_BUFFER_SIZE)) {
172 data = i8042_read_data();
174 dbg("%02x <- i8042 (flush, %s)", data,
175 str & I8042_STR_AUXDATA ? "aux" : "kbd");
178 spin_unlock_irqrestore(&i8042_lock, flags);
184 * i8042_command() executes a command on the i8042. It also sends the input
185 * parameter(s) of the commands to it, and receives the output value(s). The
186 * parameters are to be stored in the param array, and the output is placed
187 * into the same array. The number of the parameters and output values is
188 * encoded in bits 8-11 of the command number.
191 static int i8042_command(unsigned char *param, int command)
194 int i, retval, auxerr = 0;
196 if (i8042_noloop && command == I8042_CMD_AUX_LOOP)
199 spin_lock_irqsave(&i8042_lock, flags);
201 if ((retval = i8042_wait_write()))
204 dbg("%02x -> i8042 (command)", command & 0xff);
205 i8042_write_command(command & 0xff);
207 for (i = 0; i < ((command >> 12) & 0xf); i++) {
208 if ((retval = i8042_wait_write()))
210 dbg("%02x -> i8042 (parameter)", param[i]);
211 i8042_write_data(param[i]);
214 for (i = 0; i < ((command >> 8) & 0xf); i++) {
215 if ((retval = i8042_wait_read()))
218 if (command == I8042_CMD_AUX_LOOP &&
219 !(i8042_read_status() & I8042_STR_AUXDATA)) {
220 retval = auxerr = -1;
224 param[i] = i8042_read_data();
225 dbg("%02x <- i8042 (return)", param[i]);
229 dbg(" -- i8042 (%s)", auxerr ? "auxerr" : "timeout");
232 spin_unlock_irqrestore(&i8042_lock, flags);
237 * i8042_kbd_write() sends a byte out through the keyboard interface.
240 static int i8042_kbd_write(struct serio *port, unsigned char c)
245 spin_lock_irqsave(&i8042_lock, flags);
247 if(!(retval = i8042_wait_write())) {
248 dbg("%02x -> i8042 (kbd-data)", c);
252 spin_unlock_irqrestore(&i8042_lock, flags);
258 * i8042_aux_write() sends a byte out through the aux interface.
261 static int i8042_aux_write(struct serio *serio, unsigned char c)
263 struct i8042_port *port = serio->port_data;
271 retval = i8042_command(&c, I8042_CMD_AUX_SEND);
273 retval = i8042_command(&c, I8042_CMD_MUX_SEND + port->mux);
276 * Make sure the interrupt happens and the character is received even
277 * in the case the IRQ isn't wired, so that we can receive further
281 i8042_interrupt(0, NULL, NULL);
286 * i8042_activate_port() enables port on a chip.
289 static int i8042_activate_port(struct i8042_port *port)
297 * Enable port again here because it is disabled if we are
298 * resuming (normally it is enabled already).
300 i8042_ctr &= ~port->disable;
302 i8042_ctr |= port->irqen;
304 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
305 i8042_ctr &= ~port->irqen;
314 * i8042_open() is called when a port is open by the higher layer.
315 * It allocates the interrupt and calls i8042_enable_port.
318 static int i8042_open(struct serio *serio)
320 struct i8042_port *port = serio->port_data;
323 if (i8042_mux_open++)
326 if (request_irq(port->irq, i8042_interrupt,
327 SA_SHIRQ, "i8042", i8042_request_irq_cookie)) {
328 printk(KERN_ERR "i8042.c: Can't get irq %d for %s, unregistering the port.\n", port->irq, port->name);
332 if (i8042_activate_port(port)) {
333 printk(KERN_ERR "i8042.c: Can't activate %s, unregistering the port\n", port->name);
337 i8042_interrupt(0, NULL, NULL);
342 free_irq(port->irq, i8042_request_irq_cookie);
345 serio_unregister_port_delayed(serio);
351 * i8042_close() frees the interrupt, so that it can possibly be used
352 * by another driver. We never know - if the user doesn't have a mouse,
353 * the BIOS could have used the AUX interrupt for PCI.
356 static void i8042_close(struct serio *serio)
358 struct i8042_port *port = serio->port_data;
361 if (--i8042_mux_open)
364 i8042_ctr &= ~port->irqen;
366 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
367 printk(KERN_WARNING "i8042.c: Can't write CTR while closing %s.\n", port->name);
369 * We still want to continue and free IRQ so if more data keeps coming in
370 * kernel will just ignore the irq.
374 free_irq(port->irq, i8042_request_irq_cookie);
380 * i8042_start() is called by serio core when port is about to finish
381 * registering. It will mark port as existing so i8042_interrupt can
382 * start sending data through it.
384 static int i8042_start(struct serio *serio)
386 struct i8042_port *port = serio->port_data;
394 * i8042_stop() marks serio port as non-existing so i8042_interrupt
395 * will not try to send data to the port that is about to go away.
396 * The function is called by serio core as part of unregister procedure.
398 static void i8042_stop(struct serio *serio)
400 struct i8042_port *port = serio->port_data;
408 * i8042_interrupt() is the most important function in this driver -
409 * it handles the interrupts from the i8042, and sends incoming bytes
410 * to the upper layers.
413 static irqreturn_t i8042_interrupt(int irq, void *dev_id, struct pt_regs *regs)
415 struct i8042_port *port;
417 unsigned char str, data;
419 unsigned int port_no;
422 mod_timer(&i8042_timer, jiffies + I8042_POLL_PERIOD);
424 spin_lock_irqsave(&i8042_lock, flags);
425 str = i8042_read_status();
426 if (unlikely(~str & I8042_STR_OBF)) {
427 spin_unlock_irqrestore(&i8042_lock, flags);
428 if (irq) dbg("Interrupt %d, without any data", irq);
432 data = i8042_read_data();
433 spin_unlock_irqrestore(&i8042_lock, flags);
435 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) {
436 static unsigned long last_transmit;
437 static unsigned char last_str;
440 if (str & I8042_STR_MUXERR) {
441 dbg("MUX error, status is %02x, data is %02x", str, data);
445 * When MUXERR condition is signalled the data register can only contain
446 * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately
447 * it is not always the case. Some KBC just get confused which port the
448 * data came from and signal error leaving the data intact. They _do not_
449 * revert to legacy mode (actually I've never seen KBC reverting to legacy
450 * mode yet, when we see one we'll add proper handling).
451 * Anyway, we will assume that the data came from the same serio last byte
452 * was transmitted (if transmission happened not too long ago).
454 if (time_before(jiffies, last_transmit + HZ/10)) {
458 /* fall through - report timeout */
460 case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break;
461 case 0xff: dfl = SERIO_PARITY; data = 0xfe; break;
465 port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3);
467 last_transmit = jiffies;
470 dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) |
471 ((str & I8042_STR_TIMEOUT) ? SERIO_TIMEOUT : 0);
473 port_no = (str & I8042_STR_AUXDATA) ?
474 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO;
477 port = &i8042_ports[port_no];
479 dbg("%02x <- i8042 (interrupt, %s, %d%s%s)",
480 data, port->name, irq,
481 dfl & SERIO_PARITY ? ", bad parity" : "",
482 dfl & SERIO_TIMEOUT ? ", timeout" : "");
484 if (likely(port->exists))
485 serio_interrupt(port->serio, data, dfl, regs);
489 return IRQ_RETVAL(ret);
493 * i8042_set_mux_mode checks whether the controller has an active
494 * multiplexor and puts the chip into Multiplexed (1) or Legacy (0) mode.
497 static int i8042_set_mux_mode(unsigned int mode, unsigned char *mux_version)
502 * Get rid of bytes in the queue.
508 * Internal loopback test - send three bytes, they should come back from the
509 * mouse interface, the last should be version. Note that we negate mouseport
510 * command responses for the i8042_check_aux() routine.
514 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != 0xf0)
516 param = mode ? 0x56 : 0xf6;
517 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != (mode ? 0x56 : 0xf6))
519 param = mode ? 0xa4 : 0xa5;
520 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == (mode ? 0xa4 : 0xa5))
524 *mux_version = param;
531 * i8042_enable_mux_ports enables 4 individual AUX ports after
532 * the controller has been switched into Multiplexed mode
535 static int i8042_enable_mux_ports(void)
540 * Disable all muxed ports by disabling AUX.
543 i8042_ctr |= I8042_CTR_AUXDIS;
544 i8042_ctr &= ~I8042_CTR_AUXINT;
546 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
547 printk(KERN_ERR "i8042.c: Failed to disable AUX port, can't use MUX.\n");
552 * Enable all muxed ports.
555 for (i = 0; i < 4; i++) {
556 i8042_command(¶m, I8042_CMD_MUX_PFX + i);
557 i8042_command(¶m, I8042_CMD_AUX_ENABLE);
565 * i8042_check_mux() checks whether the controller supports the PS/2 Active
566 * Multiplexing specification by Synaptics, Phoenix, Insyde and
570 static int __init i8042_check_mux(void)
572 unsigned char mux_version;
574 if (i8042_set_mux_mode(1, &mux_version))
577 /* Workaround for interference with USB Legacy emulation */
578 /* that causes a v10.12 MUX to be found. */
579 if (mux_version == 0xAC)
582 printk(KERN_INFO "i8042.c: Detected active multiplexing controller, rev %d.%d.\n",
583 (mux_version >> 4) & 0xf, mux_version & 0xf);
585 if (i8042_enable_mux_ports())
588 i8042_mux_present = 1;
594 * i8042_check_aux() applies as much paranoia as it can at detecting
595 * the presence of an AUX interface.
598 static int __init i8042_check_aux(void)
601 static int i8042_check_aux_cookie;
604 * Check if AUX irq is available. If it isn't, then there is no point
605 * in trying to detect AUX presence.
608 if (request_irq(i8042_ports[I8042_AUX_PORT_NO].irq, i8042_interrupt,
609 SA_SHIRQ, "i8042", &i8042_check_aux_cookie))
611 free_irq(i8042_ports[I8042_AUX_PORT_NO].irq, &i8042_check_aux_cookie);
614 * Get rid of bytes in the queue.
620 * Internal loopback test - filters out AT-type i8042's. Unfortunately
621 * SiS screwed up and their 5597 doesn't support the LOOP command even
622 * though it has an AUX port.
626 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != 0x5a) {
629 * External connection test - filters out AT-soldered PS/2 i8042's
630 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error
631 * 0xfa - no error on some notebooks which ignore the spec
632 * Because it's common for chipsets to return error on perfectly functioning
633 * AUX ports, we test for this only when the LOOP command failed.
636 if (i8042_command(¶m, I8042_CMD_AUX_TEST)
637 || (param && param != 0xfa && param != 0xff))
642 * Bit assignment test - filters out PS/2 i8042's in AT mode
645 if (i8042_command(¶m, I8042_CMD_AUX_DISABLE))
647 if (i8042_command(¶m, I8042_CMD_CTL_RCTR) || (~param & I8042_CTR_AUXDIS)) {
648 printk(KERN_WARNING "Failed to disable AUX port, but continuing anyway... Is this a SiS?\n");
649 printk(KERN_WARNING "If AUX port is really absent please use the 'i8042.noaux' option.\n");
652 if (i8042_command(¶m, I8042_CMD_AUX_ENABLE))
654 if (i8042_command(¶m, I8042_CMD_CTL_RCTR) || (param & I8042_CTR_AUXDIS))
658 * Disable the interface.
661 i8042_ctr |= I8042_CTR_AUXDIS;
662 i8042_ctr &= ~I8042_CTR_AUXINT;
664 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
672 * i8042_port_register() marks the device as existing,
673 * registers it, and reports to the user.
676 static int __init i8042_port_register(struct i8042_port *port)
678 i8042_ctr &= ~port->disable;
680 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
681 printk(KERN_WARNING "i8042.c: Can't write CTR while registering.\n");
684 i8042_ctr |= port->disable;
688 printk(KERN_INFO "serio: i8042 %s port at %#lx,%#lx irq %d\n",
690 (unsigned long) I8042_DATA_REG,
691 (unsigned long) I8042_COMMAND_REG,
694 serio_register_port(port->serio);
700 static void i8042_timer_func(unsigned long data)
702 i8042_interrupt(0, NULL, NULL);
705 static int i8042_ctl_test(void)
712 if (i8042_command(¶m, I8042_CMD_CTL_TEST)) {
713 printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n");
717 if (param != I8042_RET_CTL_TEST) {
718 printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n",
719 param, I8042_RET_CTL_TEST);
727 * i8042_controller init initializes the i8042 controller, and,
728 * most importantly, sets it into non-xlated mode if that's
732 static int i8042_controller_init(void)
737 * Test the i8042. We need to know if it thinks it's working correctly
738 * before doing anything else.
741 if (i8042_flush() == I8042_BUFFER_SIZE) {
742 printk(KERN_ERR "i8042.c: No controller found.\n");
746 if (i8042_ctl_test())
750 * Save the CTR for restoral on unload / reboot.
753 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_RCTR)) {
754 printk(KERN_ERR "i8042.c: Can't read CTR while initializing i8042.\n");
758 i8042_initial_ctr = i8042_ctr;
761 * Disable the keyboard interface and interrupt.
764 i8042_ctr |= I8042_CTR_KBDDIS;
765 i8042_ctr &= ~I8042_CTR_KBDINT;
771 spin_lock_irqsave(&i8042_lock, flags);
772 if (~i8042_read_status() & I8042_STR_KEYLOCK) {
774 i8042_ctr |= I8042_CTR_IGNKEYLOCK;
776 printk(KERN_WARNING "i8042.c: Warning: Keylock active.\n");
778 spin_unlock_irqrestore(&i8042_lock, flags);
781 * If the chip is configured into nontranslated mode by the BIOS, don't
782 * bother enabling translating and be happy.
785 if (~i8042_ctr & I8042_CTR_XLATE)
789 * Set nontranslated mode for the kbd interface if requested by an option.
790 * After this the kbd interface becomes a simple serial in/out, like the aux
791 * interface is. We don't do this by default, since it can confuse notebook
796 i8042_ctr &= ~I8042_CTR_XLATE;
802 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
803 printk(KERN_ERR "i8042.c: Can't write CTR while initializing i8042.\n");
812 * Reset the controller.
814 static void i8042_controller_reset(void)
817 * Reset the controller if requested.
823 * Disable MUX mode if present.
826 if (i8042_mux_present)
827 i8042_set_mux_mode(0, NULL);
830 * Restore the original control register setting.
833 i8042_ctr = i8042_initial_ctr;
835 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
836 printk(KERN_WARNING "i8042.c: Can't restore CTR.\n");
841 * Here we try to reset everything back to a state in which the BIOS will be
842 * able to talk to the hardware when rebooting.
845 static void i8042_controller_cleanup(void)
852 * Reset anything that is connected to the ports.
855 for (i = 0; i < I8042_NUM_PORTS; i++)
856 if (i8042_ports[i].exists)
857 serio_cleanup(i8042_ports[i].serio);
859 i8042_controller_reset();
864 * i8042_panic_blink() will flash the keyboard LEDs and is called when
865 * kernel panics. Flashing LEDs is useful for users running X who may
866 * not see the console and will help distingushing panics from "real"
869 * Note that DELAY has a limit of 10ms so we will not get stuck here
870 * waiting for KBC to free up even if KBD interrupt is off
873 #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0)
875 static long i8042_panic_blink(long count)
878 static long last_blink;
882 * We expect frequency to be about 1/2s. KDB uses about 1s.
883 * Make sure they are different.
885 if (!i8042_blink_frequency)
887 if (count - last_blink < i8042_blink_frequency)
891 while (i8042_read_status() & I8042_STR_IBF)
893 i8042_write_data(0xed); /* set leds */
895 while (i8042_read_status() & I8042_STR_IBF)
898 i8042_write_data(led);
907 * Here we try to restore the original BIOS settings
910 static int i8042_suspend(struct device *dev, pm_message_t state, u32 level)
912 if (level == SUSPEND_DISABLE) {
913 del_timer_sync(&i8042_timer);
914 i8042_controller_reset();
922 * Here we try to reset everything back to a state in which suspended
925 static int i8042_resume(struct device *dev, u32 level)
929 if (level != RESUME_ENABLE)
932 if (i8042_ctl_test())
935 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
936 printk(KERN_ERR "i8042: Can't write CTR\n");
940 if (i8042_mux_present)
941 if (i8042_set_mux_mode(1, NULL) || i8042_enable_mux_ports())
942 printk(KERN_WARNING "i8042: failed to resume active multiplexor, mouse won't work.\n");
945 * Activate all ports.
948 for (i = 0; i < I8042_NUM_PORTS; i++)
949 i8042_activate_port(&i8042_ports[i]);
952 * Restart timer (for polling "stuck" data)
954 mod_timer(&i8042_timer, jiffies + I8042_POLL_PERIOD);
956 panic_blink = i8042_panic_blink;
963 * We need to reset the 8042 back to original mode on system shutdown,
964 * because otherwise BIOSes will be confused.
967 static void i8042_shutdown(struct device *dev)
969 i8042_controller_cleanup();
972 static struct device_driver i8042_driver = {
974 .bus = &platform_bus_type,
975 .suspend = i8042_suspend,
976 .resume = i8042_resume,
977 .shutdown = i8042_shutdown,
980 static void __init i8042_create_kbd_port(void)
983 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO];
985 serio = kmalloc(sizeof(struct serio), GFP_KERNEL);
987 memset(serio, 0, sizeof(struct serio));
988 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL;
989 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write;
990 serio->open = i8042_open;
991 serio->close = i8042_close;
992 serio->start = i8042_start;
993 serio->stop = i8042_stop;
994 serio->port_data = port;
995 serio->dev.parent = &i8042_platform_device->dev;
996 strlcpy(serio->name, "i8042 Kbd Port", sizeof(serio->name));
997 strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys));
1000 i8042_port_register(port);
1004 static void __init i8042_create_aux_port(void)
1006 struct serio *serio;
1007 struct i8042_port *port = &i8042_ports[I8042_AUX_PORT_NO];
1009 serio = kmalloc(sizeof(struct serio), GFP_KERNEL);
1011 memset(serio, 0, sizeof(struct serio));
1012 serio->id.type = SERIO_8042;
1013 serio->write = i8042_aux_write;
1014 serio->open = i8042_open;
1015 serio->close = i8042_close;
1016 serio->start = i8042_start;
1017 serio->stop = i8042_stop;
1018 serio->port_data = port;
1019 serio->dev.parent = &i8042_platform_device->dev;
1020 strlcpy(serio->name, "i8042 Aux Port", sizeof(serio->name));
1021 strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys));
1023 port->serio = serio;
1024 i8042_port_register(port);
1028 static void __init i8042_create_mux_port(int index)
1030 struct serio *serio;
1031 struct i8042_port *port = &i8042_ports[I8042_MUX_PORT_NO + index];
1033 serio = kmalloc(sizeof(struct serio), GFP_KERNEL);
1035 memset(serio, 0, sizeof(struct serio));
1036 serio->id.type = SERIO_8042;
1037 serio->write = i8042_aux_write;
1038 serio->open = i8042_open;
1039 serio->close = i8042_close;
1040 serio->start = i8042_start;
1041 serio->stop = i8042_stop;
1042 serio->port_data = port;
1043 serio->dev.parent = &i8042_platform_device->dev;
1044 snprintf(serio->name, sizeof(serio->name), "i8042 Aux-%d Port", index);
1045 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, index + 1);
1047 *port = i8042_ports[I8042_AUX_PORT_NO];
1049 snprintf(port->name, sizeof(port->name), "AUX%d", index);
1051 port->serio = serio;
1052 i8042_port_register(port);
1056 static int __init i8042_init(void)
1063 init_timer(&i8042_timer);
1064 i8042_timer.function = i8042_timer_func;
1066 if (i8042_platform_init())
1069 i8042_ports[I8042_AUX_PORT_NO].irq = I8042_AUX_IRQ;
1070 i8042_ports[I8042_KBD_PORT_NO].irq = I8042_KBD_IRQ;
1072 if (i8042_controller_init()) {
1073 i8042_platform_exit();
1077 err = driver_register(&i8042_driver);
1079 i8042_platform_exit();
1083 i8042_platform_device = platform_device_register_simple("i8042", -1, NULL, 0);
1084 if (IS_ERR(i8042_platform_device)) {
1085 driver_unregister(&i8042_driver);
1086 i8042_platform_exit();
1087 return PTR_ERR(i8042_platform_device);
1090 if (!i8042_noaux && !i8042_check_aux()) {
1091 if (!i8042_nomux && !i8042_check_mux())
1092 for (i = 0; i < I8042_NUM_MUX_PORTS; i++)
1093 i8042_create_mux_port(i);
1095 i8042_create_aux_port();
1098 i8042_create_kbd_port();
1100 mod_timer(&i8042_timer, jiffies + I8042_POLL_PERIOD);
1105 static void __exit i8042_exit(void)
1109 i8042_controller_cleanup();
1111 for (i = 0; i < I8042_NUM_PORTS; i++)
1112 if (i8042_ports[i].exists)
1113 serio_unregister_port(i8042_ports[i].serio);
1115 del_timer_sync(&i8042_timer);
1117 platform_device_unregister(i8042_platform_device);
1118 driver_unregister(&i8042_driver);
1120 i8042_platform_exit();
1125 module_init(i8042_init);
1126 module_exit(i8042_exit);