2 * i8042 keyboard and mouse controller driver for Linux
4 * Copyright (c) 1999-2004 Vojtech Pavlik
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
13 #include <linux/delay.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/interrupt.h>
17 #include <linux/ioport.h>
18 #include <linux/config.h>
19 #include <linux/init.h>
20 #include <linux/serio.h>
21 #include <linux/err.h>
22 #include <linux/rcupdate.h>
26 MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>");
27 MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver");
28 MODULE_LICENSE("GPL");
30 static unsigned int i8042_noaux;
31 module_param_named(noaux, i8042_noaux, bool, 0);
32 MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port.");
34 static unsigned int i8042_nomux;
35 module_param_named(nomux, i8042_nomux, bool, 0);
36 MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing conrtoller is present.");
38 static unsigned int i8042_unlock;
39 module_param_named(unlock, i8042_unlock, bool, 0);
40 MODULE_PARM_DESC(unlock, "Ignore keyboard lock.");
42 static unsigned int i8042_reset;
43 module_param_named(reset, i8042_reset, bool, 0);
44 MODULE_PARM_DESC(reset, "Reset controller during init and cleanup.");
46 static unsigned int i8042_direct;
47 module_param_named(direct, i8042_direct, bool, 0);
48 MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode.");
50 static unsigned int i8042_dumbkbd;
51 module_param_named(dumbkbd, i8042_dumbkbd, bool, 0);
52 MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard");
54 static unsigned int i8042_noloop;
55 module_param_named(noloop, i8042_noloop, bool, 0);
56 MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port");
58 static unsigned int i8042_blink_frequency = 500;
59 module_param_named(panicblink, i8042_blink_frequency, uint, 0600);
60 MODULE_PARM_DESC(panicblink, "Frequency with which keyboard LEDs should blink when kernel panics");
63 static int i8042_nopnp;
64 module_param_named(nopnp, i8042_nopnp, bool, 0);
65 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings");
70 static int i8042_debug;
71 module_param_named(debug, i8042_debug, bool, 0600);
72 MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off");
75 __obsolete_setup("i8042_noaux");
76 __obsolete_setup("i8042_nomux");
77 __obsolete_setup("i8042_unlock");
78 __obsolete_setup("i8042_reset");
79 __obsolete_setup("i8042_direct");
80 __obsolete_setup("i8042_dumbkbd");
84 static DEFINE_SPINLOCK(i8042_lock);
89 unsigned char disable;
96 #define I8042_KBD_PORT_NO 0
97 #define I8042_AUX_PORT_NO 1
98 #define I8042_MUX_PORT_NO 2
99 #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2)
100 static struct i8042_port i8042_ports[I8042_NUM_PORTS] = {
102 .disable = I8042_CTR_KBDDIS,
103 .irqen = I8042_CTR_KBDINT,
108 .disable = I8042_CTR_AUXDIS,
109 .irqen = I8042_CTR_AUXINT,
115 static unsigned char i8042_initial_ctr;
116 static unsigned char i8042_ctr;
117 static unsigned char i8042_mux_open;
118 static unsigned char i8042_mux_present;
119 static struct timer_list i8042_timer;
120 static struct platform_device *i8042_platform_device;
124 * Shared IRQ's require a device pointer, but this driver doesn't support
127 #define i8042_request_irq_cookie (&i8042_timer)
129 static irqreturn_t i8042_interrupt(int irq, void *dev_id, struct pt_regs *regs);
132 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to
133 * be ready for reading values from it / writing values to it.
134 * Called always with i8042_lock held.
137 static int i8042_wait_read(void)
140 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) {
144 return -(i == I8042_CTL_TIMEOUT);
147 static int i8042_wait_write(void)
150 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) {
154 return -(i == I8042_CTL_TIMEOUT);
158 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers
159 * of the i8042 down the toilet.
162 static int i8042_flush(void)
165 unsigned char data, str;
168 spin_lock_irqsave(&i8042_lock, flags);
170 while (((str = i8042_read_status()) & I8042_STR_OBF) && (i < I8042_BUFFER_SIZE)) {
172 data = i8042_read_data();
174 dbg("%02x <- i8042 (flush, %s)", data,
175 str & I8042_STR_AUXDATA ? "aux" : "kbd");
178 spin_unlock_irqrestore(&i8042_lock, flags);
184 * i8042_command() executes a command on the i8042. It also sends the input
185 * parameter(s) of the commands to it, and receives the output value(s). The
186 * parameters are to be stored in the param array, and the output is placed
187 * into the same array. The number of the parameters and output values is
188 * encoded in bits 8-11 of the command number.
191 static int i8042_command(unsigned char *param, int command)
194 int retval = 0, i = 0;
196 if (i8042_noloop && command == I8042_CMD_AUX_LOOP)
199 spin_lock_irqsave(&i8042_lock, flags);
201 retval = i8042_wait_write();
203 dbg("%02x -> i8042 (command)", command & 0xff);
204 i8042_write_command(command & 0xff);
208 for (i = 0; i < ((command >> 12) & 0xf); i++) {
209 if ((retval = i8042_wait_write())) break;
210 dbg("%02x -> i8042 (parameter)", param[i]);
211 i8042_write_data(param[i]);
215 for (i = 0; i < ((command >> 8) & 0xf); i++) {
216 if ((retval = i8042_wait_read())) break;
217 if (i8042_read_status() & I8042_STR_AUXDATA)
218 param[i] = ~i8042_read_data();
220 param[i] = i8042_read_data();
221 dbg("%02x <- i8042 (return)", param[i]);
224 spin_unlock_irqrestore(&i8042_lock, flags);
227 dbg(" -- i8042 (timeout)");
233 * i8042_kbd_write() sends a byte out through the keyboard interface.
236 static int i8042_kbd_write(struct serio *port, unsigned char c)
241 spin_lock_irqsave(&i8042_lock, flags);
243 if(!(retval = i8042_wait_write())) {
244 dbg("%02x -> i8042 (kbd-data)", c);
248 spin_unlock_irqrestore(&i8042_lock, flags);
254 * i8042_aux_write() sends a byte out through the aux interface.
257 static int i8042_aux_write(struct serio *serio, unsigned char c)
259 struct i8042_port *port = serio->port_data;
267 retval = i8042_command(&c, I8042_CMD_AUX_SEND);
269 retval = i8042_command(&c, I8042_CMD_MUX_SEND + port->mux);
272 * Make sure the interrupt happens and the character is received even
273 * in the case the IRQ isn't wired, so that we can receive further
277 i8042_interrupt(0, NULL, NULL);
282 * i8042_activate_port() enables port on a chip.
285 static int i8042_activate_port(struct i8042_port *port)
293 * Enable port again here because it is disabled if we are
294 * resuming (normally it is enabled already).
296 i8042_ctr &= ~port->disable;
298 i8042_ctr |= port->irqen;
300 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
301 i8042_ctr &= ~port->irqen;
310 * i8042_open() is called when a port is open by the higher layer.
311 * It allocates the interrupt and calls i8042_enable_port.
314 static int i8042_open(struct serio *serio)
316 struct i8042_port *port = serio->port_data;
319 if (i8042_mux_open++)
322 if (request_irq(port->irq, i8042_interrupt,
323 SA_SHIRQ, "i8042", i8042_request_irq_cookie)) {
324 printk(KERN_ERR "i8042.c: Can't get irq %d for %s, unregistering the port.\n", port->irq, port->name);
328 if (i8042_activate_port(port)) {
329 printk(KERN_ERR "i8042.c: Can't activate %s, unregistering the port\n", port->name);
333 i8042_interrupt(0, NULL, NULL);
338 free_irq(port->irq, i8042_request_irq_cookie);
341 serio_unregister_port_delayed(serio);
347 * i8042_close() frees the interrupt, so that it can possibly be used
348 * by another driver. We never know - if the user doesn't have a mouse,
349 * the BIOS could have used the AUX interrupt for PCI.
352 static void i8042_close(struct serio *serio)
354 struct i8042_port *port = serio->port_data;
357 if (--i8042_mux_open)
360 i8042_ctr &= ~port->irqen;
362 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
363 printk(KERN_WARNING "i8042.c: Can't write CTR while closing %s.\n", port->name);
365 * We still want to continue and free IRQ so if more data keeps coming in
366 * kernel will just ignore the irq.
370 free_irq(port->irq, i8042_request_irq_cookie);
376 * i8042_start() is called by serio core when port is about to finish
377 * registering. It will mark port as existing so i8042_interrupt can
378 * start sending data through it.
380 static int i8042_start(struct serio *serio)
382 struct i8042_port *port = serio->port_data;
390 * i8042_stop() marks serio port as non-existing so i8042_interrupt
391 * will not try to send data to the port that is about to go away.
392 * The function is called by serio core as part of unregister procedure.
394 static void i8042_stop(struct serio *serio)
396 struct i8042_port *port = serio->port_data;
399 synchronize_kernel();
404 * i8042_interrupt() is the most important function in this driver -
405 * it handles the interrupts from the i8042, and sends incoming bytes
406 * to the upper layers.
409 static irqreturn_t i8042_interrupt(int irq, void *dev_id, struct pt_regs *regs)
411 struct i8042_port *port;
413 unsigned char str, data;
415 unsigned int port_no;
418 mod_timer(&i8042_timer, jiffies + I8042_POLL_PERIOD);
420 spin_lock_irqsave(&i8042_lock, flags);
421 str = i8042_read_status();
422 if (unlikely(~str & I8042_STR_OBF)) {
423 spin_unlock_irqrestore(&i8042_lock, flags);
424 if (irq) dbg("Interrupt %d, without any data", irq);
428 data = i8042_read_data();
429 spin_unlock_irqrestore(&i8042_lock, flags);
431 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) {
432 static unsigned long last_transmit;
433 static unsigned char last_str;
436 if (str & I8042_STR_MUXERR) {
437 dbg("MUX error, status is %02x, data is %02x", str, data);
441 * When MUXERR condition is signalled the data register can only contain
442 * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately
443 * it is not always the case. Some KBC just get confused which port the
444 * data came from and signal error leaving the data intact. They _do not_
445 * revert to legacy mode (actually I've never seen KBC reverting to legacy
446 * mode yet, when we see one we'll add proper handling).
447 * Anyway, we will assume that the data came from the same serio last byte
448 * was transmitted (if transmission happened not too long ago).
450 if (time_before(jiffies, last_transmit + HZ/10)) {
454 /* fall through - report timeout */
456 case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break;
457 case 0xff: dfl = SERIO_PARITY; data = 0xfe; break;
461 port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3);
463 last_transmit = jiffies;
466 dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) |
467 ((str & I8042_STR_TIMEOUT) ? SERIO_TIMEOUT : 0);
469 port_no = (str & I8042_STR_AUXDATA) ?
470 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO;
473 port = &i8042_ports[port_no];
475 dbg("%02x <- i8042 (interrupt, %s, %d%s%s)",
476 data, port->name, irq,
477 dfl & SERIO_PARITY ? ", bad parity" : "",
478 dfl & SERIO_TIMEOUT ? ", timeout" : "");
480 if (likely(port->exists))
481 serio_interrupt(port->serio, data, dfl, regs);
485 return IRQ_RETVAL(ret);
489 * i8042_set_mux_mode checks whether the controller has an active
490 * multiplexor and puts the chip into Multiplexed (1) or Legacy (0) mode.
493 static int i8042_set_mux_mode(unsigned int mode, unsigned char *mux_version)
498 * Get rid of bytes in the queue.
504 * Internal loopback test - send three bytes, they should come back from the
505 * mouse interface, the last should be version. Note that we negate mouseport
506 * command responses for the i8042_check_aux() routine.
510 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != 0x0f)
512 param = mode ? 0x56 : 0xf6;
513 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != (mode ? 0xa9 : 0x09))
515 param = mode ? 0xa4 : 0xa5;
516 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == (mode ? 0x5b : 0x5a))
520 *mux_version = ~param;
527 * i8042_enable_mux_ports enables 4 individual AUX ports after
528 * the controller has been switched into Multiplexed mode
531 static int i8042_enable_mux_ports(void)
536 * Disable all muxed ports by disabling AUX.
539 i8042_ctr |= I8042_CTR_AUXDIS;
540 i8042_ctr &= ~I8042_CTR_AUXINT;
542 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
543 printk(KERN_ERR "i8042.c: Failed to disable AUX port, can't use MUX.\n");
548 * Enable all muxed ports.
551 for (i = 0; i < 4; i++) {
552 i8042_command(¶m, I8042_CMD_MUX_PFX + i);
553 i8042_command(¶m, I8042_CMD_AUX_ENABLE);
561 * i8042_check_mux() checks whether the controller supports the PS/2 Active
562 * Multiplexing specification by Synaptics, Phoenix, Insyde and
566 static int __init i8042_check_mux(void)
568 unsigned char mux_version;
570 if (i8042_set_mux_mode(1, &mux_version))
573 /* Workaround for interference with USB Legacy emulation */
574 /* that causes a v10.12 MUX to be found. */
575 if (mux_version == 0xAC)
578 printk(KERN_INFO "i8042.c: Detected active multiplexing controller, rev %d.%d.\n",
579 (mux_version >> 4) & 0xf, mux_version & 0xf);
581 if (i8042_enable_mux_ports())
584 i8042_mux_present = 1;
590 * i8042_check_aux() applies as much paranoia as it can at detecting
591 * the presence of an AUX interface.
594 static int __init i8042_check_aux(void)
597 static int i8042_check_aux_cookie;
600 * Check if AUX irq is available. If it isn't, then there is no point
601 * in trying to detect AUX presence.
604 if (request_irq(i8042_ports[I8042_AUX_PORT_NO].irq, i8042_interrupt,
605 SA_SHIRQ, "i8042", &i8042_check_aux_cookie))
607 free_irq(i8042_ports[I8042_AUX_PORT_NO].irq, &i8042_check_aux_cookie);
610 * Get rid of bytes in the queue.
616 * Internal loopback test - filters out AT-type i8042's. Unfortunately
617 * SiS screwed up and their 5597 doesn't support the LOOP command even
618 * though it has an AUX port.
622 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != 0xa5) {
625 * External connection test - filters out AT-soldered PS/2 i8042's
626 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error
627 * 0xfa - no error on some notebooks which ignore the spec
628 * Because it's common for chipsets to return error on perfectly functioning
629 * AUX ports, we test for this only when the LOOP command failed.
632 if (i8042_command(¶m, I8042_CMD_AUX_TEST)
633 || (param && param != 0xfa && param != 0xff))
638 * Bit assignment test - filters out PS/2 i8042's in AT mode
641 if (i8042_command(¶m, I8042_CMD_AUX_DISABLE))
643 if (i8042_command(¶m, I8042_CMD_CTL_RCTR) || (~param & I8042_CTR_AUXDIS)) {
644 printk(KERN_WARNING "Failed to disable AUX port, but continuing anyway... Is this a SiS?\n");
645 printk(KERN_WARNING "If AUX port is really absent please use the 'i8042.noaux' option.\n");
648 if (i8042_command(¶m, I8042_CMD_AUX_ENABLE))
650 if (i8042_command(¶m, I8042_CMD_CTL_RCTR) || (param & I8042_CTR_AUXDIS))
654 * Disable the interface.
657 i8042_ctr |= I8042_CTR_AUXDIS;
658 i8042_ctr &= ~I8042_CTR_AUXINT;
660 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
668 * i8042_port_register() marks the device as existing,
669 * registers it, and reports to the user.
672 static int __init i8042_port_register(struct i8042_port *port)
674 i8042_ctr &= ~port->disable;
676 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
677 printk(KERN_WARNING "i8042.c: Can't write CTR while registering.\n");
680 i8042_ctr |= port->disable;
684 printk(KERN_INFO "serio: i8042 %s port at %#lx,%#lx irq %d\n",
686 (unsigned long) I8042_DATA_REG,
687 (unsigned long) I8042_COMMAND_REG,
690 serio_register_port(port->serio);
696 static void i8042_timer_func(unsigned long data)
698 i8042_interrupt(0, NULL, NULL);
701 static int i8042_ctl_test(void)
708 if (i8042_command(¶m, I8042_CMD_CTL_TEST)) {
709 printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n");
713 if (param != I8042_RET_CTL_TEST) {
714 printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n",
715 param, I8042_RET_CTL_TEST);
723 * i8042_controller init initializes the i8042 controller, and,
724 * most importantly, sets it into non-xlated mode if that's
728 static int i8042_controller_init(void)
733 * Test the i8042. We need to know if it thinks it's working correctly
734 * before doing anything else.
737 if (i8042_flush() == I8042_BUFFER_SIZE) {
738 printk(KERN_ERR "i8042.c: No controller found.\n");
742 if (i8042_ctl_test())
746 * Save the CTR for restoral on unload / reboot.
749 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_RCTR)) {
750 printk(KERN_ERR "i8042.c: Can't read CTR while initializing i8042.\n");
754 i8042_initial_ctr = i8042_ctr;
757 * Disable the keyboard interface and interrupt.
760 i8042_ctr |= I8042_CTR_KBDDIS;
761 i8042_ctr &= ~I8042_CTR_KBDINT;
767 spin_lock_irqsave(&i8042_lock, flags);
768 if (~i8042_read_status() & I8042_STR_KEYLOCK) {
770 i8042_ctr |= I8042_CTR_IGNKEYLOCK;
772 printk(KERN_WARNING "i8042.c: Warning: Keylock active.\n");
774 spin_unlock_irqrestore(&i8042_lock, flags);
777 * If the chip is configured into nontranslated mode by the BIOS, don't
778 * bother enabling translating and be happy.
781 if (~i8042_ctr & I8042_CTR_XLATE)
785 * Set nontranslated mode for the kbd interface if requested by an option.
786 * After this the kbd interface becomes a simple serial in/out, like the aux
787 * interface is. We don't do this by default, since it can confuse notebook
792 i8042_ctr &= ~I8042_CTR_XLATE;
798 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
799 printk(KERN_ERR "i8042.c: Can't write CTR while initializing i8042.\n");
808 * Reset the controller.
810 static void i8042_controller_reset(void)
813 * Reset the controller if requested.
819 * Disable MUX mode if present.
822 if (i8042_mux_present)
823 i8042_set_mux_mode(0, NULL);
826 * Restore the original control register setting.
829 i8042_ctr = i8042_initial_ctr;
831 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
832 printk(KERN_WARNING "i8042.c: Can't restore CTR.\n");
837 * Here we try to reset everything back to a state in which the BIOS will be
838 * able to talk to the hardware when rebooting.
841 static void i8042_controller_cleanup(void)
848 * Reset anything that is connected to the ports.
851 for (i = 0; i < I8042_NUM_PORTS; i++)
852 if (i8042_ports[i].exists)
853 serio_cleanup(i8042_ports[i].serio);
855 i8042_controller_reset();
860 * i8042_panic_blink() will flash the keyboard LEDs and is called when
861 * kernel panics. Flashing LEDs is useful for users running X who may
862 * not see the console and will help distingushing panics from "real"
865 * Note that DELAY has a limit of 10ms so we will not get stuck here
866 * waiting for KBC to free up even if KBD interrupt is off
869 #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0)
871 static long i8042_panic_blink(long count)
874 static long last_blink;
878 * We expect frequency to be about 1/2s. KDB uses about 1s.
879 * Make sure they are different.
881 if (!i8042_blink_frequency)
883 if (count - last_blink < i8042_blink_frequency)
887 while (i8042_read_status() & I8042_STR_IBF)
889 i8042_write_data(0xed); /* set leds */
891 while (i8042_read_status() & I8042_STR_IBF)
894 i8042_write_data(led);
903 * Here we try to restore the original BIOS settings
906 static int i8042_suspend(struct device *dev, pm_message_t state, u32 level)
908 if (level == SUSPEND_DISABLE) {
909 del_timer_sync(&i8042_timer);
910 i8042_controller_reset();
918 * Here we try to reset everything back to a state in which suspended
921 static int i8042_resume(struct device *dev, u32 level)
925 if (level != RESUME_ENABLE)
928 if (i8042_ctl_test())
931 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
932 printk(KERN_ERR "i8042: Can't write CTR\n");
936 if (i8042_mux_present)
937 if (i8042_set_mux_mode(1, NULL) || i8042_enable_mux_ports())
938 printk(KERN_WARNING "i8042: failed to resume active multiplexor, mouse won't work.\n");
941 * Activate all ports.
944 for (i = 0; i < I8042_NUM_PORTS; i++)
945 i8042_activate_port(&i8042_ports[i]);
948 * Restart timer (for polling "stuck" data)
950 mod_timer(&i8042_timer, jiffies + I8042_POLL_PERIOD);
952 panic_blink = i8042_panic_blink;
959 * We need to reset the 8042 back to original mode on system shutdown,
960 * because otherwise BIOSes will be confused.
963 static void i8042_shutdown(struct device *dev)
965 i8042_controller_cleanup();
968 static struct device_driver i8042_driver = {
970 .bus = &platform_bus_type,
971 .suspend = i8042_suspend,
972 .resume = i8042_resume,
973 .shutdown = i8042_shutdown,
976 static void __init i8042_create_kbd_port(void)
979 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO];
981 serio = kmalloc(sizeof(struct serio), GFP_KERNEL);
983 memset(serio, 0, sizeof(struct serio));
984 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL;
985 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write;
986 serio->open = i8042_open;
987 serio->close = i8042_close;
988 serio->start = i8042_start;
989 serio->stop = i8042_stop;
990 serio->port_data = port;
991 serio->dev.parent = &i8042_platform_device->dev;
992 strlcpy(serio->name, "i8042 Kbd Port", sizeof(serio->name));
993 strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys));
996 i8042_port_register(port);
1000 static void __init i8042_create_aux_port(void)
1002 struct serio *serio;
1003 struct i8042_port *port = &i8042_ports[I8042_AUX_PORT_NO];
1005 serio = kmalloc(sizeof(struct serio), GFP_KERNEL);
1007 memset(serio, 0, sizeof(struct serio));
1008 serio->id.type = SERIO_8042;
1009 serio->write = i8042_aux_write;
1010 serio->open = i8042_open;
1011 serio->close = i8042_close;
1012 serio->start = i8042_start;
1013 serio->stop = i8042_stop;
1014 serio->port_data = port;
1015 serio->dev.parent = &i8042_platform_device->dev;
1016 strlcpy(serio->name, "i8042 Aux Port", sizeof(serio->name));
1017 strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys));
1019 port->serio = serio;
1020 i8042_port_register(port);
1024 static void __init i8042_create_mux_port(int index)
1026 struct serio *serio;
1027 struct i8042_port *port = &i8042_ports[I8042_MUX_PORT_NO + index];
1029 serio = kmalloc(sizeof(struct serio), GFP_KERNEL);
1031 memset(serio, 0, sizeof(struct serio));
1032 serio->id.type = SERIO_8042;
1033 serio->write = i8042_aux_write;
1034 serio->open = i8042_open;
1035 serio->close = i8042_close;
1036 serio->start = i8042_start;
1037 serio->stop = i8042_stop;
1038 serio->port_data = port;
1039 serio->dev.parent = &i8042_platform_device->dev;
1040 snprintf(serio->name, sizeof(serio->name), "i8042 Aux-%d Port", index);
1041 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, index + 1);
1043 *port = i8042_ports[I8042_AUX_PORT_NO];
1045 snprintf(port->name, sizeof(port->name), "AUX%d", index);
1047 port->serio = serio;
1048 i8042_port_register(port);
1052 static int __init i8042_init(void)
1059 init_timer(&i8042_timer);
1060 i8042_timer.function = i8042_timer_func;
1062 if (i8042_platform_init())
1065 i8042_ports[I8042_AUX_PORT_NO].irq = I8042_AUX_IRQ;
1066 i8042_ports[I8042_KBD_PORT_NO].irq = I8042_KBD_IRQ;
1068 if (i8042_controller_init()) {
1069 i8042_platform_exit();
1073 err = driver_register(&i8042_driver);
1075 i8042_platform_exit();
1079 i8042_platform_device = platform_device_register_simple("i8042", -1, NULL, 0);
1080 if (IS_ERR(i8042_platform_device)) {
1081 driver_unregister(&i8042_driver);
1082 i8042_platform_exit();
1083 return PTR_ERR(i8042_platform_device);
1086 if (!i8042_noaux && !i8042_check_aux()) {
1087 if (!i8042_nomux && !i8042_check_mux())
1088 for (i = 0; i < I8042_NUM_MUX_PORTS; i++)
1089 i8042_create_mux_port(i);
1091 i8042_create_aux_port();
1094 i8042_create_kbd_port();
1096 mod_timer(&i8042_timer, jiffies + I8042_POLL_PERIOD);
1101 static void __exit i8042_exit(void)
1105 i8042_controller_cleanup();
1107 for (i = 0; i < I8042_NUM_PORTS; i++)
1108 if (i8042_ports[i].exists)
1109 serio_unregister_port(i8042_ports[i].serio);
1111 del_timer_sync(&i8042_timer);
1113 platform_device_unregister(i8042_platform_device);
1114 driver_unregister(&i8042_driver);
1116 i8042_platform_exit();
1121 module_init(i8042_init);
1122 module_exit(i8042_exit);