err.no Git - linux-2.6/blob - drivers/infiniband/hw/mthca/mthca_qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Cisco Systems. All rights reserved.
   4  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  *
  35  * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
  36  */
  37
  38 #include <linux/string.h>
  39 #include <linux/slab.h>
  40
  41 #include <asm/io.h>
  42
  43 #include <rdma/ib_verbs.h>
  44 #include <rdma/ib_cache.h>
  45 #include <rdma/ib_pack.h>
  46
  47 #include "mthca_dev.h"
  48 #include "mthca_cmd.h"
  49 #include "mthca_memfree.h"
  50 #include "mthca_wqe.h"
  51
  52 enum {
  53         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
  54         MTHCA_ACK_REQ_FREQ       = 10,
  55         MTHCA_FLIGHT_LIMIT       = 9,
  56         MTHCA_UD_HEADER_SIZE     = 72, /* largest UD header possible */
  57         MTHCA_INLINE_HEADER_SIZE = 4,  /* data segment overhead for inline */
  58         MTHCA_INLINE_CHUNK_SIZE  = 16  /* inline data segment chunk */
  59 };
  60
  61 enum {
  62         MTHCA_QP_STATE_RST  = 0,
  63         MTHCA_QP_STATE_INIT = 1,
  64         MTHCA_QP_STATE_RTR  = 2,
  65         MTHCA_QP_STATE_RTS  = 3,
  66         MTHCA_QP_STATE_SQE  = 4,
  67         MTHCA_QP_STATE_SQD  = 5,
  68         MTHCA_QP_STATE_ERR  = 6,
  69         MTHCA_QP_STATE_DRAINING = 7
  70 };
  71
  72 enum {
  73         MTHCA_QP_ST_RC  = 0x0,
  74         MTHCA_QP_ST_UC  = 0x1,
  75         MTHCA_QP_ST_RD  = 0x2,
  76         MTHCA_QP_ST_UD  = 0x3,
  77         MTHCA_QP_ST_MLX = 0x7
  78 };
  79
  80 enum {
  81         MTHCA_QP_PM_MIGRATED = 0x3,
  82         MTHCA_QP_PM_ARMED    = 0x0,
  83         MTHCA_QP_PM_REARM    = 0x1
  84 };
  85
  86 enum {
  87         /* qp_context flags */
  88         MTHCA_QP_BIT_DE  = 1 <<  8,
  89         /* params1 */
  90         MTHCA_QP_BIT_SRE = 1 << 15,
  91         MTHCA_QP_BIT_SWE = 1 << 14,
  92         MTHCA_QP_BIT_SAE = 1 << 13,
  93         MTHCA_QP_BIT_SIC = 1 <<  4,
  94         MTHCA_QP_BIT_SSC = 1 <<  3,
  95         /* params2 */
  96         MTHCA_QP_BIT_RRE = 1 << 15,
  97         MTHCA_QP_BIT_RWE = 1 << 14,
  98         MTHCA_QP_BIT_RAE = 1 << 13,
  99         MTHCA_QP_BIT_RIC = 1 <<  4,
 100         MTHCA_QP_BIT_RSC = 1 <<  3
 101 };
 102
 103 enum {
 104         MTHCA_SEND_DOORBELL_FENCE = 1 << 5
 105 };
 106
 107 struct mthca_qp_path {
 108         __be32 port_pkey;
 109         u8     rnr_retry;
 110         u8     g_mylmc;
 111         __be16 rlid;
 112         u8     ackto;
 113         u8     mgid_index;
 114         u8     static_rate;
 115         u8     hop_limit;
 116         __be32 sl_tclass_flowlabel;
 117         u8     rgid[16];
 118 } __attribute__((packed));
 119
 120 struct mthca_qp_context {
 121         __be32 flags;
 122         __be32 tavor_sched_queue; /* Reserved on Arbel */
 123         u8     mtu_msgmax;
 124         u8     rq_size_stride;  /* Reserved on Tavor */
 125         u8     sq_size_stride;  /* Reserved on Tavor */
 126         u8     rlkey_arbel_sched_queue; /* Reserved on Tavor */
 127         __be32 usr_page;
 128         __be32 local_qpn;
 129         __be32 remote_qpn;
 130         u32    reserved1[2];
 131         struct mthca_qp_path pri_path;
 132         struct mthca_qp_path alt_path;
 133         __be32 rdd;
 134         __be32 pd;
 135         __be32 wqe_base;
 136         __be32 wqe_lkey;
 137         __be32 params1;
 138         __be32 reserved2;
 139         __be32 next_send_psn;
 140         __be32 cqn_snd;
 141         __be32 snd_wqe_base_l;  /* Next send WQE on Tavor */
 142         __be32 snd_db_index;    /* (debugging only entries) */
 143         __be32 last_acked_psn;
 144         __be32 ssn;
 145         __be32 params2;
 146         __be32 rnr_nextrecvpsn;
 147         __be32 ra_buff_indx;
 148         __be32 cqn_rcv;
 149         __be32 rcv_wqe_base_l;  /* Next recv WQE on Tavor */
 150         __be32 rcv_db_index;    /* (debugging only entries) */
 151         __be32 qkey;
 152         __be32 srqn;
 153         __be32 rmsn;
 154         __be16 rq_wqe_counter;  /* reserved on Tavor */
 155         __be16 sq_wqe_counter;  /* reserved on Tavor */
 156         u32    reserved3[18];
 157 } __attribute__((packed));
 158
 159 struct mthca_qp_param {
 160         __be32 opt_param_mask;
 161         u32    reserved1;
 162         struct mthca_qp_context context;
 163         u32    reserved2[62];
 164 } __attribute__((packed));
 165
 166 enum {
 167         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
 168         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
 169         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
 170         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
 171         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
 172         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
 173         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
 174         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
 175         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
 176         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
 177         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
 178         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
 179         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
 180         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
 181         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
 182         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
 183         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
 184 };
 185
 186 static const u8 mthca_opcode[] = {
 187         [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
 188         [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
 189         [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
 190         [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
 191         [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
 192         [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
 193         [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
 194 };
 195
 196 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
 197 {
 198         return qp->qpn >= dev->qp_table.sqp_start &&
 199                 qp->qpn <= dev->qp_table.sqp_start + 3;
 200 }
 201
 202 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
 203 {
 204         return qp->qpn >= dev->qp_table.sqp_start &&
 205                 qp->qpn <= dev->qp_table.sqp_start + 1;
 206 }
 207
 208 static void *get_recv_wqe(struct mthca_qp *qp, int n)
 209 {
 210         if (qp->is_direct)
 211                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
 212         else
 213                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
 214                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
 215 }
 216
 217 static void *get_send_wqe(struct mthca_qp *qp, int n)
 218 {
 219         if (qp->is_direct)
 220                 return qp->queue.direct.buf + qp->send_wqe_offset +
 221                         (n << qp->sq.wqe_shift);
 222         else
 223                 return qp->queue.page_list[(qp->send_wqe_offset +
 224                                             (n << qp->sq.wqe_shift)) >>
 225                                            PAGE_SHIFT].buf +
 226                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
 227                          (PAGE_SIZE - 1));
 228 }
 229
 230 static void mthca_wq_reset(struct mthca_wq *wq)
 231 {
 232         wq->next_ind  = 0;
 233         wq->last_comp = wq->max - 1;
 234         wq->head      = 0;
 235         wq->tail      = 0;
 236 }
 237
 238 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
 239                     enum ib_event_type event_type)
 240 {
 241         struct mthca_qp *qp;
 242         struct ib_event event;
 243
 244         spin_lock(&dev->qp_table.lock);
 245         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
 246         if (qp)
 247                 ++qp->refcount;
 248         spin_unlock(&dev->qp_table.lock);
 249
 250         if (!qp) {
 251                 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
 252                 return;
 253         }
 254
 255         if (event_type == IB_EVENT_PATH_MIG)
 256                 qp->port = qp->alt_port;
 257
 258         event.device      = &dev->ib_dev;
 259         event.event       = event_type;
 260         event.element.qp  = &qp->ibqp;
 261         if (qp->ibqp.event_handler)
 262                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
 263
 264         spin_lock(&dev->qp_table.lock);
 265         if (!--qp->refcount)
 266                 wake_up(&qp->wait);
 267         spin_unlock(&dev->qp_table.lock);
 268 }
 269
 270 static int to_mthca_state(enum ib_qp_state ib_state)
 271 {
 272         switch (ib_state) {
 273         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
 274         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
 275         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
 276         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
 277         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
 278         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
 279         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
 280         default:                return -1;
 281         }
 282 }
 283
 284 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
 285
 286 static int to_mthca_st(int transport)
 287 {
 288         switch (transport) {
 289         case RC:  return MTHCA_QP_ST_RC;
 290         case UC:  return MTHCA_QP_ST_UC;
 291         case UD:  return MTHCA_QP_ST_UD;
 292         case RD:  return MTHCA_QP_ST_RD;
 293         case MLX: return MTHCA_QP_ST_MLX;
 294         default:  return -1;
 295         }
 296 }
 297
 298 static void store_attrs(struct mthca_sqp *sqp, const struct ib_qp_attr *attr,
 299                         int attr_mask)
 300 {
 301         if (attr_mask & IB_QP_PKEY_INDEX)
 302                 sqp->pkey_index = attr->pkey_index;
 303         if (attr_mask & IB_QP_QKEY)
 304                 sqp->qkey = attr->qkey;
 305         if (attr_mask & IB_QP_SQ_PSN)
 306                 sqp->send_psn = attr->sq_psn;
 307 }
 308
 309 static void init_port(struct mthca_dev *dev, int port)
 310 {
 311         int err;
 312         u8 status;
 313         struct mthca_init_ib_param param;
 314
 315         memset(&param, 0, sizeof param);
 316
 317         param.port_width = dev->limits.port_width_cap;
 318         param.vl_cap     = dev->limits.vl_cap;
 319         param.mtu_cap    = dev->limits.mtu_cap;
 320         param.gid_cap    = dev->limits.gid_table_len;
 321         param.pkey_cap   = dev->limits.pkey_table_len;
 322
 323         err = mthca_INIT_IB(dev, &param, port, &status);
 324         if (err)
 325                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
 326         if (status)
 327                 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
 328 }
 329
 330 static __be32 get_hw_access_flags(struct mthca_qp *qp, const struct ib_qp_attr *attr,
 331                                   int attr_mask)
 332 {
 333         u8 dest_rd_atomic;
 334         u32 access_flags;
 335         u32 hw_access_flags = 0;
 336
 337         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 338                 dest_rd_atomic = attr->max_dest_rd_atomic;
 339         else
 340                 dest_rd_atomic = qp->resp_depth;
 341
 342         if (attr_mask & IB_QP_ACCESS_FLAGS)
 343                 access_flags = attr->qp_access_flags;
 344         else
 345                 access_flags = qp->atomic_rd_en;
 346
 347         if (!dest_rd_atomic)
 348                 access_flags &= IB_ACCESS_REMOTE_WRITE;
 349
 350         if (access_flags & IB_ACCESS_REMOTE_READ)
 351                 hw_access_flags |= MTHCA_QP_BIT_RRE;
 352         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
 353                 hw_access_flags |= MTHCA_QP_BIT_RAE;
 354         if (access_flags & IB_ACCESS_REMOTE_WRITE)
 355                 hw_access_flags |= MTHCA_QP_BIT_RWE;
 356
 357         return cpu_to_be32(hw_access_flags);
 358 }
 359
 360 static inline enum ib_qp_state to_ib_qp_state(int mthca_state)
 361 {
 362         switch (mthca_state) {
 363         case MTHCA_QP_STATE_RST:      return IB_QPS_RESET;
 364         case MTHCA_QP_STATE_INIT:     return IB_QPS_INIT;
 365         case MTHCA_QP_STATE_RTR:      return IB_QPS_RTR;
 366         case MTHCA_QP_STATE_RTS:      return IB_QPS_RTS;
 367         case MTHCA_QP_STATE_DRAINING:
 368         case MTHCA_QP_STATE_SQD:      return IB_QPS_SQD;
 369         case MTHCA_QP_STATE_SQE:      return IB_QPS_SQE;
 370         case MTHCA_QP_STATE_ERR:      return IB_QPS_ERR;
 371         default:                      return -1;
 372         }
 373 }
 374
 375 static inline enum ib_mig_state to_ib_mig_state(int mthca_mig_state)
 376 {
 377         switch (mthca_mig_state) {
 378         case 0:  return IB_MIG_ARMED;
 379         case 1:  return IB_MIG_REARM;
 380         case 3:  return IB_MIG_MIGRATED;
 381         default: return -1;
 382         }
 383 }
 384
 385 static int to_ib_qp_access_flags(int mthca_flags)
 386 {
 387         int ib_flags = 0;
 388
 389         if (mthca_flags & MTHCA_QP_BIT_RRE)
 390                 ib_flags |= IB_ACCESS_REMOTE_READ;
 391         if (mthca_flags & MTHCA_QP_BIT_RWE)
 392                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
 393         if (mthca_flags & MTHCA_QP_BIT_RAE)
 394                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
 395
 396         return ib_flags;
 397 }
 398
 399 static void to_ib_ah_attr(struct mthca_dev *dev, struct ib_ah_attr *ib_ah_attr,
 400                                 struct mthca_qp_path *path)
 401 {
 402         memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
 403         ib_ah_attr->port_num      = (be32_to_cpu(path->port_pkey) >> 24) & 0x3;
 404
 405         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->limits.num_ports)
 406                 return;
 407
 408         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
 409         ib_ah_attr->sl            = be32_to_cpu(path->sl_tclass_flowlabel) >> 28;
 410         ib_ah_attr->src_path_bits = path->g_mylmc & 0x7f;
 411         ib_ah_attr->static_rate   = mthca_rate_to_ib(dev,
 412                                                      path->static_rate & 0xf,
 413                                                      ib_ah_attr->port_num);
 414         ib_ah_attr->ah_flags      = (path->g_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
 415         if (ib_ah_attr->ah_flags) {
 416                 ib_ah_attr->grh.sgid_index = path->mgid_index & (dev->limits.gid_table_len - 1);
 417                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
 418                 ib_ah_attr->grh.traffic_class =
 419                         (be32_to_cpu(path->sl_tclass_flowlabel) >> 20) & 0xff;
 420                 ib_ah_attr->grh.flow_label =
 421                         be32_to_cpu(path->sl_tclass_flowlabel) & 0xfffff;
 422                 memcpy(ib_ah_attr->grh.dgid.raw,
 423                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
 424         }
 425 }
 426
 427 int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
 428                    struct ib_qp_init_attr *qp_init_attr)
 429 {
 430         struct mthca_dev *dev = to_mdev(ibqp->device);
 431         struct mthca_qp *qp = to_mqp(ibqp);
 432         int err = 0;
 433         struct mthca_mailbox *mailbox = NULL;
 434         struct mthca_qp_param *qp_param;
 435         struct mthca_qp_context *context;
 436         int mthca_state;
 437         u8 status;
 438
 439         if (qp->state == IB_QPS_RESET) {
 440                 qp_attr->qp_state = IB_QPS_RESET;
 441                 goto done;
 442         }
 443
 444         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 445         if (IS_ERR(mailbox))
 446                 return PTR_ERR(mailbox);
 447
 448         err = mthca_QUERY_QP(dev, qp->qpn, 0, mailbox, &status);
 449         if (err)
 450                 goto out;
 451         if (status) {
 452                 mthca_warn(dev, "QUERY_QP returned status %02x\n", status);
 453                 err = -EINVAL;
 454                 goto out;
 455         }
 456
 457         qp_param    = mailbox->buf;
 458         context     = &qp_param->context;
 459         mthca_state = be32_to_cpu(context->flags) >> 28;
 460
 461         qp_attr->qp_state            = to_ib_qp_state(mthca_state);
 462         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
 463         qp_attr->path_mig_state      =
 464                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
 465         qp_attr->qkey                = be32_to_cpu(context->qkey);
 466         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
 467         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
 468         qp_attr->dest_qp_num         = be32_to_cpu(context->remote_qpn) & 0xffffff;
 469         qp_attr->qp_access_flags     =
 470                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
 471
 472         if (qp->transport == RC || qp->transport == UC) {
 473                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
 474                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
 475                 qp_attr->alt_pkey_index =
 476                         be32_to_cpu(context->alt_path.port_pkey) & 0x7f;
 477                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
 478         }
 479
 480         qp_attr->pkey_index = be32_to_cpu(context->pri_path.port_pkey) & 0x7f;
 481         qp_attr->port_num   =
 482                 (be32_to_cpu(context->pri_path.port_pkey) >> 24) & 0x3;
 483
 484         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
 485         qp_attr->sq_draining = mthca_state == MTHCA_QP_STATE_DRAINING;
 486
 487         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
 488
 489         qp_attr->max_dest_rd_atomic =
 490                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
 491         qp_attr->min_rnr_timer      =
 492                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
 493         qp_attr->timeout            = context->pri_path.ackto >> 3;
 494         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
 495         qp_attr->rnr_retry          = context->pri_path.rnr_retry >> 5;
 496         qp_attr->alt_timeout        = context->alt_path.ackto >> 3;
 497
 498 done:
 499         qp_attr->cur_qp_state        = qp_attr->qp_state;
 500         qp_attr->cap.max_send_wr     = qp->sq.max;
 501         qp_attr->cap.max_recv_wr     = qp->rq.max;
 502         qp_attr->cap.max_send_sge    = qp->sq.max_gs;
 503         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
 504         qp_attr->cap.max_inline_data = qp->max_inline_data;
 505
 506         qp_init_attr->cap            = qp_attr->cap;
 507
 508 out:
 509         mthca_free_mailbox(dev, mailbox);
 510         return err;
 511 }
 512
 513 static int mthca_path_set(struct mthca_dev *dev, const struct ib_ah_attr *ah,
 514                           struct mthca_qp_path *path, u8 port)
 515 {
 516         path->g_mylmc     = ah->src_path_bits & 0x7f;
 517         path->rlid        = cpu_to_be16(ah->dlid);
 518         path->static_rate = mthca_get_rate(dev, ah->static_rate, port);
 519
 520         if (ah->ah_flags & IB_AH_GRH) {
 521                 if (ah->grh.sgid_index >= dev->limits.gid_table_len) {
 522                         mthca_dbg(dev, "sgid_index (%u) too large. max is %d\n",
 523                                   ah->grh.sgid_index, dev->limits.gid_table_len-1);
 524                         return -1;
 525                 }
 526
 527                 path->g_mylmc   |= 1 << 7;
 528                 path->mgid_index = ah->grh.sgid_index;
 529                 path->hop_limit  = ah->grh.hop_limit;
 530                 path->sl_tclass_flowlabel =
 531                         cpu_to_be32((ah->sl << 28)                |
 532                                     (ah->grh.traffic_class << 20) |
 533                                     (ah->grh.flow_label));
 534                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
 535         } else
 536                 path->sl_tclass_flowlabel = cpu_to_be32(ah->sl << 28);
 537
 538         return 0;
 539 }
 540
 541 static int __mthca_modify_qp(struct ib_qp *ibqp,
 542                              const struct ib_qp_attr *attr, int attr_mask,
 543                              enum ib_qp_state cur_state, enum ib_qp_state new_state)
 544 {
 545         struct mthca_dev *dev = to_mdev(ibqp->device);
 546         struct mthca_qp *qp = to_mqp(ibqp);
 547         struct mthca_mailbox *mailbox;
 548         struct mthca_qp_param *qp_param;
 549         struct mthca_qp_context *qp_context;
 550         u32 sqd_event = 0;
 551         u8 status;
 552         int err = -EINVAL;
 553
 554         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 555         if (IS_ERR(mailbox)) {
 556                 err = PTR_ERR(mailbox);
 557                 goto out;
 558         }
 559         qp_param = mailbox->buf;
 560         qp_context = &qp_param->context;
 561         memset(qp_param, 0, sizeof *qp_param);
 562
 563         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
 564                                              (to_mthca_st(qp->transport) << 16));
 565         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
 566         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 567                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 568         else {
 569                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
 570                 switch (attr->path_mig_state) {
 571                 case IB_MIG_MIGRATED:
 572                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 573                         break;
 574                 case IB_MIG_REARM:
 575                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
 576                         break;
 577                 case IB_MIG_ARMED:
 578                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
 579                         break;
 580                 }
 581         }
 582
 583         /* leave tavor_sched_queue as 0 */
 584
 585         if (qp->transport == MLX || qp->transport == UD)
 586                 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
 587         else if (attr_mask & IB_QP_PATH_MTU) {
 588                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_2048) {
 589                         mthca_dbg(dev, "path MTU (%u) is invalid\n",
 590                                   attr->path_mtu);
 591                         goto out_mailbox;
 592                 }
 593                 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 594         }
 595
 596         if (mthca_is_memfree(dev)) {
 597                 if (qp->rq.max)
 598                         qp_context->rq_size_stride = ilog2(qp->rq.max) << 3;
 599                 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
 600
 601                 if (qp->sq.max)
 602                         qp_context->sq_size_stride = ilog2(qp->sq.max) << 3;
 603                 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
 604         }
 605
 606         /* leave arbel_sched_queue as 0 */
 607
 608         if (qp->ibqp.uobject)
 609                 qp_context->usr_page =
 610                         cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
 611         else
 612                 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
 613         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
 614         if (attr_mask & IB_QP_DEST_QPN) {
 615                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 616         }
 617
 618         if (qp->transport == MLX)
 619                 qp_context->pri_path.port_pkey |=
 620                         cpu_to_be32(qp->port << 24);
 621         else {
 622                 if (attr_mask & IB_QP_PORT) {
 623                         qp_context->pri_path.port_pkey |=
 624                                 cpu_to_be32(attr->port_num << 24);
 625                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
 626                 }
 627         }
 628
 629         if (attr_mask & IB_QP_PKEY_INDEX) {
 630                 qp_context->pri_path.port_pkey |=
 631                         cpu_to_be32(attr->pkey_index);
 632                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
 633         }
 634
 635         if (attr_mask & IB_QP_RNR_RETRY) {
 636                 qp_context->alt_path.rnr_retry = qp_context->pri_path.rnr_retry =
 637                         attr->rnr_retry << 5;
 638                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY |
 639                                                         MTHCA_QP_OPTPAR_ALT_RNR_RETRY);
 640         }
 641
 642         if (attr_mask & IB_QP_AV) {
 643                 if (mthca_path_set(dev, &attr->ah_attr, &qp_context->pri_path,
 644                                    attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
 645                         goto out_mailbox;
 646
 647                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
 648         }
 649
 650         if (ibqp->qp_type == IB_QPT_RC &&
 651             cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
 652                 u8 sched_queue = ibqp->uobject ? 0x2 : 0x1;
 653
 654                 if (mthca_is_memfree(dev))
 655                         qp_context->rlkey_arbel_sched_queue |= sched_queue;
 656                 else
 657                         qp_context->tavor_sched_queue |= cpu_to_be32(sched_queue);
 658
 659                 qp_param->opt_param_mask |=
 660                         cpu_to_be32(MTHCA_QP_OPTPAR_SCHED_QUEUE);
 661         }
 662
 663         if (attr_mask & IB_QP_TIMEOUT) {
 664                 qp_context->pri_path.ackto = attr->timeout << 3;
 665                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
 666         }
 667
 668         if (attr_mask & IB_QP_ALT_PATH) {
 669                 if (attr->alt_pkey_index >= dev->limits.pkey_table_len) {
 670                         mthca_dbg(dev, "Alternate P_Key index (%u) too large. max is %d\n",
 671                                   attr->alt_pkey_index, dev->limits.pkey_table_len-1);
 672                         goto out_mailbox;
 673                 }
 674
 675                 if (attr->alt_port_num == 0 || attr->alt_port_num > dev->limits.num_ports) {
 676                         mthca_dbg(dev, "Alternate port number (%u) is invalid\n",
 677                                 attr->alt_port_num);
 678                         goto out_mailbox;
 679                 }
 680
 681                 if (mthca_path_set(dev, &attr->alt_ah_attr, &qp_context->alt_path,
 682                                    attr->alt_ah_attr.port_num))
 683                         goto out_mailbox;
 684
 685                 qp_context->alt_path.port_pkey |= cpu_to_be32(attr->alt_pkey_index |
 686                                                               attr->alt_port_num << 24);
 687                 qp_context->alt_path.ackto = attr->alt_timeout << 3;
 688                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH);
 689         }
 690
 691         /* leave rdd as 0 */
 692         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
 693         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
 694         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
 695         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
 696                                              (MTHCA_FLIGHT_LIMIT << 24) |
 697                                              MTHCA_QP_BIT_SWE);
 698         if (qp->sq_policy == IB_SIGNAL_ALL_WR)
 699                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
 700         if (attr_mask & IB_QP_RETRY_CNT) {
 701                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 702                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
 703         }
 704
 705         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 706                 if (attr->max_rd_atomic) {
 707                         qp_context->params1 |=
 708                                 cpu_to_be32(MTHCA_QP_BIT_SRE |
 709                                             MTHCA_QP_BIT_SAE);
 710                         qp_context->params1 |=
 711                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
 712                 }
 713                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
 714         }
 715
 716         if (attr_mask & IB_QP_SQ_PSN)
 717                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
 718         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
 719
 720         if (mthca_is_memfree(dev)) {
 721                 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
 722                 qp_context->snd_db_index   = cpu_to_be32(qp->sq.db_index);
 723         }
 724
 725         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 726                 if (attr->max_dest_rd_atomic)
 727                         qp_context->params2 |=
 728                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
 729
 730                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
 731         }
 732
 733         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
 734                 qp_context->params2      |= get_hw_access_flags(qp, attr, attr_mask);
 735                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 736                                                         MTHCA_QP_OPTPAR_RRE |
 737                                                         MTHCA_QP_OPTPAR_RAE);
 738         }
 739
 740         qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
 741
 742         if (ibqp->srq)
 743                 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
 744
 745         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 746                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 747                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
 748         }
 749         if (attr_mask & IB_QP_RQ_PSN)
 750                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 751
 752         qp_context->ra_buff_indx =
 753                 cpu_to_be32(dev->qp_table.rdb_base +
 754                             ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
 755                              dev->qp_table.rdb_shift));
 756
 757         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
 758
 759         if (mthca_is_memfree(dev))
 760                 qp_context->rcv_db_index   = cpu_to_be32(qp->rq.db_index);
 761
 762         if (attr_mask & IB_QP_QKEY) {
 763                 qp_context->qkey = cpu_to_be32(attr->qkey);
 764                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
 765         }
 766
 767         if (ibqp->srq)
 768                 qp_context->srqn = cpu_to_be32(1 << 24 |
 769                                                to_msrq(ibqp->srq)->srqn);
 770
 771         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
 772             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY               &&
 773             attr->en_sqd_async_notify)
 774                 sqd_event = 1 << 31;
 775
 776         err = mthca_MODIFY_QP(dev, cur_state, new_state, qp->qpn, 0,
 777                               mailbox, sqd_event, &status);
 778         if (err)
 779                 goto out_mailbox;
 780         if (status) {
 781                 mthca_warn(dev, "modify QP %d->%d returned status %02x.\n",
 782                            cur_state, new_state, status);
 783                 err = -EINVAL;
 784                 goto out_mailbox;
 785         }
 786
 787         qp->state = new_state;
 788         if (attr_mask & IB_QP_ACCESS_FLAGS)
 789                 qp->atomic_rd_en = attr->qp_access_flags;
 790         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 791                 qp->resp_depth = attr->max_dest_rd_atomic;
 792         if (attr_mask & IB_QP_PORT)
 793                 qp->port = attr->port_num;
 794         if (attr_mask & IB_QP_ALT_PATH)
 795                 qp->alt_port = attr->alt_port_num;
 796
 797         if (is_sqp(dev, qp))
 798                 store_attrs(to_msqp(qp), attr, attr_mask);
 799
 800         /*
 801          * If we moved QP0 to RTR, bring the IB link up; if we moved
 802          * QP0 to RESET or ERROR, bring the link back down.
 803          */
 804         if (is_qp0(dev, qp)) {
 805                 if (cur_state != IB_QPS_RTR &&
 806                     new_state == IB_QPS_RTR)
 807                         init_port(dev, qp->port);
 808
 809                 if (cur_state != IB_QPS_RESET &&
 810                     cur_state != IB_QPS_ERR &&
 811                     (new_state == IB_QPS_RESET ||
 812                      new_state == IB_QPS_ERR))
 813                         mthca_CLOSE_IB(dev, qp->port, &status);
 814         }
 815
 816         /*
 817          * If we moved a kernel QP to RESET, clean up all old CQ
 818          * entries and reinitialize the QP.
 819          */
 820         if (new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
 821                 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
 822                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 823                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
 824                         mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn, NULL);
 825
 826                 mthca_wq_reset(&qp->sq);
 827                 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
 828
 829                 mthca_wq_reset(&qp->rq);
 830                 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
 831
 832                 if (mthca_is_memfree(dev)) {
 833                         *qp->sq.db = 0;
 834                         *qp->rq.db = 0;
 835                 }
 836         }
 837
 838 out_mailbox:
 839         mthca_free_mailbox(dev, mailbox);
 840 out:
 841         return err;
 842 }
 843
 844 static const struct ib_qp_attr dummy_init_attr = { .port_num = 1 };
 845 static const int dummy_init_attr_mask[] = {
 846         [IB_QPT_UD]  = (IB_QP_PKEY_INDEX                |
 847                         IB_QP_PORT                      |
 848                         IB_QP_QKEY),
 849         [IB_QPT_UC]  = (IB_QP_PKEY_INDEX                |
 850                         IB_QP_PORT                      |
 851                         IB_QP_ACCESS_FLAGS),
 852         [IB_QPT_RC]  = (IB_QP_PKEY_INDEX                |
 853                         IB_QP_PORT                      |
 854                         IB_QP_ACCESS_FLAGS),
 855         [IB_QPT_SMI] = (IB_QP_PKEY_INDEX                |
 856                         IB_QP_QKEY),
 857         [IB_QPT_GSI] = (IB_QP_PKEY_INDEX                |
 858                         IB_QP_QKEY),
 859 };
 860
 861 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
 862                     struct ib_udata *udata)
 863 {
 864         struct mthca_dev *dev = to_mdev(ibqp->device);
 865         struct mthca_qp *qp = to_mqp(ibqp);
 866         enum ib_qp_state cur_state, new_state;
 867         int err = -EINVAL;
 868
 869         mutex_lock(&qp->mutex);
 870         if (attr_mask & IB_QP_CUR_STATE) {
 871                 cur_state = attr->cur_qp_state;
 872         } else {
 873                 spin_lock_irq(&qp->sq.lock);
 874                 spin_lock(&qp->rq.lock);
 875                 cur_state = qp->state;
 876                 spin_unlock(&qp->rq.lock);
 877                 spin_unlock_irq(&qp->sq.lock);
 878         }
 879
 880         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
 881
 882         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) {
 883                 mthca_dbg(dev, "Bad QP transition (transport %d) "
 884                           "%d->%d with attr 0x%08x\n",
 885                           qp->transport, cur_state, new_state,
 886                           attr_mask);
 887                 goto out;
 888         }
 889
 890         if ((attr_mask & IB_QP_PKEY_INDEX) &&
 891              attr->pkey_index >= dev->limits.pkey_table_len) {
 892                 mthca_dbg(dev, "P_Key index (%u) too large. max is %d\n",
 893                           attr->pkey_index, dev->limits.pkey_table_len-1);
 894                 goto out;
 895         }
 896
 897         if ((attr_mask & IB_QP_PORT) &&
 898             (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) {
 899                 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num);
 900                 goto out;
 901         }
 902
 903         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
 904             attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
 905                 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
 906                           attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
 907                 goto out;
 908         }
 909
 910         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
 911             attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
 912                 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
 913                           attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
 914                 goto out;
 915         }
 916
 917         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
 918                 err = 0;
 919                 goto out;
 920         }
 921
 922         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_ERR) {
 923                 err = __mthca_modify_qp(ibqp, &dummy_init_attr,
 924                                         dummy_init_attr_mask[ibqp->qp_type],
 925                                         IB_QPS_RESET, IB_QPS_INIT);
 926                 if (err)
 927                         goto out;
 928                 cur_state = IB_QPS_INIT;
 929         }
 930
 931         err = __mthca_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
 932
 933 out:
 934         mutex_unlock(&qp->mutex);
 935         return err;
 936 }
 937
 938 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz)
 939 {
 940         /*
 941          * Calculate the maximum size of WQE s/g segments, excluding
 942          * the next segment and other non-data segments.
 943          */
 944         int max_data_size = desc_sz - sizeof (struct mthca_next_seg);
 945
 946         switch (qp->transport) {
 947         case MLX:
 948                 max_data_size -= 2 * sizeof (struct mthca_data_seg);
 949                 break;
 950
 951         case UD:
 952                 if (mthca_is_memfree(dev))
 953                         max_data_size -= sizeof (struct mthca_arbel_ud_seg);
 954                 else
 955                         max_data_size -= sizeof (struct mthca_tavor_ud_seg);
 956                 break;
 957
 958         default:
 959                 max_data_size -= sizeof (struct mthca_raddr_seg);
 960                 break;
 961         }
 962
 963         return max_data_size;
 964 }
 965
 966 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size)
 967 {
 968         /* We don't support inline data for kernel QPs (yet). */
 969         return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0;
 970 }
 971
 972 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
 973                                  struct mthca_pd *pd,
 974                                  struct mthca_qp *qp)
 975 {
 976         int max_data_size = mthca_max_data_size(dev, qp,
 977                                                 min(dev->limits.max_desc_sz,
 978                                                     1 << qp->sq.wqe_shift));
 979
 980         qp->max_inline_data = mthca_max_inline_data(pd, max_data_size);
 981
 982         qp->sq.max_gs = min_t(int, dev->limits.max_sg,
 983                               max_data_size / sizeof (struct mthca_data_seg));
 984         qp->rq.max_gs = min_t(int, dev->limits.max_sg,
 985                                (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
 986                                 sizeof (struct mthca_next_seg)) /
 987                                sizeof (struct mthca_data_seg));
 988 }
 989
 990 /*
 991  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
 992  * rq.max_gs and sq.max_gs must all be assigned.
 993  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
 994  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
 995  * queue)
 996  */
 997 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
 998                                struct mthca_pd *pd,
 999                                struct mthca_qp *qp)
1000 {
1001         int size;
1002         int err = -ENOMEM;
1003
1004         size = sizeof (struct mthca_next_seg) +
1005                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
1006
1007         if (size > dev->limits.max_desc_sz)
1008                 return -EINVAL;
1009
1010         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
1011              qp->rq.wqe_shift++)
1012                 ; /* nothing */
1013
1014         size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
1015         switch (qp->transport) {
1016         case MLX:
1017                 size += 2 * sizeof (struct mthca_data_seg);
1018                 break;
1019
1020         case UD:
1021                 size += mthca_is_memfree(dev) ?
1022                         sizeof (struct mthca_arbel_ud_seg) :
1023                         sizeof (struct mthca_tavor_ud_seg);
1024                 break;
1025
1026         case UC:
1027                 size += sizeof (struct mthca_raddr_seg);
1028                 break;
1029
1030         case RC:
1031                 size += sizeof (struct mthca_raddr_seg);
1032                 /*
1033                  * An atomic op will require an atomic segment, a
1034                  * remote address segment and one scatter entry.
1035                  */
1036                 size = max_t(int, size,
1037                              sizeof (struct mthca_atomic_seg) +
1038                              sizeof (struct mthca_raddr_seg) +
1039                              sizeof (struct mthca_data_seg));
1040                 break;
1041
1042         default:
1043                 break;
1044         }
1045
1046         /* Make sure that we have enough space for a bind request */
1047         size = max_t(int, size, sizeof (struct mthca_bind_seg));
1048
1049         size += sizeof (struct mthca_next_seg);
1050
1051         if (size > dev->limits.max_desc_sz)
1052                 return -EINVAL;
1053
1054         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
1055              qp->sq.wqe_shift++)
1056                 ; /* nothing */
1057
1058         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
1059                                     1 << qp->sq.wqe_shift);
1060
1061         /*
1062          * If this is a userspace QP, we don't actually have to
1063          * allocate anything.  All we need is to calculate the WQE
1064          * sizes and the send_wqe_offset, so we're done now.
1065          */
1066         if (pd->ibpd.uobject)
1067                 return 0;
1068
1069         size = PAGE_ALIGN(qp->send_wqe_offset +
1070                           (qp->sq.max << qp->sq.wqe_shift));
1071
1072         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
1073                            GFP_KERNEL);
1074         if (!qp->wrid)
1075                 goto err_out;
1076
1077         err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1078                               &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1079         if (err)
1080                 goto err_out;
1081
1082         return 0;
1083
1084 err_out:
1085         kfree(qp->wrid);
1086         return err;
1087 }
1088
1089 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1090                                struct mthca_qp *qp)
1091 {
1092         mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1093                                        (qp->sq.max << qp->sq.wqe_shift)),
1094                        &qp->queue, qp->is_direct, &qp->mr);
1095         kfree(qp->wrid);
1096 }
1097
1098 static int mthca_map_memfree(struct mthca_dev *dev,
1099                              struct mthca_qp *qp)
1100 {
1101         int ret;
1102
1103         if (mthca_is_memfree(dev)) {
1104                 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1105                 if (ret)
1106                         return ret;
1107
1108                 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1109                 if (ret)
1110                         goto err_qpc;
1111
1112                 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1113                                       qp->qpn << dev->qp_table.rdb_shift);
1114                 if (ret)
1115                         goto err_eqpc;
1116
1117         }
1118
1119         return 0;
1120
1121 err_eqpc:
1122         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1123
1124 err_qpc:
1125         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1126
1127         return ret;
1128 }
1129
1130 static void mthca_unmap_memfree(struct mthca_dev *dev,
1131                                 struct mthca_qp *qp)
1132 {
1133         mthca_table_put(dev, dev->qp_table.rdb_table,
1134                         qp->qpn << dev->qp_table.rdb_shift);
1135         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1136         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1137 }
1138
1139 static int mthca_alloc_memfree(struct mthca_dev *dev,
1140                                struct mthca_qp *qp)
1141 {
1142         if (mthca_is_memfree(dev)) {
1143                 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1144                                                  qp->qpn, &qp->rq.db);
1145                 if (qp->rq.db_index < 0)
1146                         return -ENOMEM;
1147
1148                 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1149                                                  qp->qpn, &qp->sq.db);
1150                 if (qp->sq.db_index < 0) {
1151                         mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1152                         return -ENOMEM;
1153                 }
1154         }
1155
1156         return 0;
1157 }
1158
1159 static void mthca_free_memfree(struct mthca_dev *dev,
1160                                struct mthca_qp *qp)
1161 {
1162         if (mthca_is_memfree(dev)) {
1163                 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1164                 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1165         }
1166 }
1167
1168 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1169                                  struct mthca_pd *pd,
1170                                  struct mthca_cq *send_cq,
1171                                  struct mthca_cq *recv_cq,
1172                                  enum ib_sig_type send_policy,
1173                                  struct mthca_qp *qp)
1174 {
1175         int ret;
1176         int i;
1177
1178         qp->refcount = 1;
1179         init_waitqueue_head(&qp->wait);
1180         mutex_init(&qp->mutex);
1181         qp->state        = IB_QPS_RESET;
1182         qp->atomic_rd_en = 0;
1183         qp->resp_depth   = 0;
1184         qp->sq_policy    = send_policy;
1185         mthca_wq_reset(&qp->sq);
1186         mthca_wq_reset(&qp->rq);
1187
1188         spin_lock_init(&qp->sq.lock);
1189         spin_lock_init(&qp->rq.lock);
1190
1191         ret = mthca_map_memfree(dev, qp);
1192         if (ret)
1193                 return ret;
1194
1195         ret = mthca_alloc_wqe_buf(dev, pd, qp);
1196         if (ret) {
1197                 mthca_unmap_memfree(dev, qp);
1198                 return ret;
1199         }
1200
1201         mthca_adjust_qp_caps(dev, pd, qp);
1202
1203         /*
1204          * If this is a userspace QP, we're done now.  The doorbells
1205          * will be allocated and buffers will be initialized in
1206          * userspace.
1207          */
1208         if (pd->ibpd.uobject)
1209                 return 0;
1210
1211         ret = mthca_alloc_memfree(dev, qp);
1212         if (ret) {
1213                 mthca_free_wqe_buf(dev, qp);
1214                 mthca_unmap_memfree(dev, qp);
1215                 return ret;
1216         }
1217
1218         if (mthca_is_memfree(dev)) {
1219                 struct mthca_next_seg *next;
1220                 struct mthca_data_seg *scatter;
1221                 int size = (sizeof (struct mthca_next_seg) +
1222                             qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1223
1224                 for (i = 0; i < qp->rq.max; ++i) {
1225                         next = get_recv_wqe(qp, i);
1226                         next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1227                                                    qp->rq.wqe_shift);
1228                         next->ee_nds = cpu_to_be32(size);
1229
1230                         for (scatter = (void *) (next + 1);
1231                              (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1232                              ++scatter)
1233                                 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1234                 }
1235
1236                 for (i = 0; i < qp->sq.max; ++i) {
1237                         next = get_send_wqe(qp, i);
1238                         next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1239                                                     qp->sq.wqe_shift) +
1240                                                    qp->send_wqe_offset);
1241                 }
1242         }
1243
1244         qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1245         qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1246
1247         return 0;
1248 }
1249
1250 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1251                              struct mthca_pd *pd, struct mthca_qp *qp)
1252 {
1253         int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz);
1254
1255         /* Sanity check QP size before proceeding */
1256         if (cap->max_send_wr     > dev->limits.max_wqes ||
1257             cap->max_recv_wr     > dev->limits.max_wqes ||
1258             cap->max_send_sge    > dev->limits.max_sg   ||
1259             cap->max_recv_sge    > dev->limits.max_sg   ||
1260             cap->max_inline_data > mthca_max_inline_data(pd, max_data_size))
1261                 return -EINVAL;
1262
1263         /*
1264          * For MLX transport we need 2 extra S/G entries:
1265          * one for the header and one for the checksum at the end
1266          */
1267         if (qp->transport == MLX && cap->max_recv_sge + 2 > dev->limits.max_sg)
1268                 return -EINVAL;
1269
1270         if (mthca_is_memfree(dev)) {
1271                 qp->rq.max = cap->max_recv_wr ?
1272                         roundup_pow_of_two(cap->max_recv_wr) : 0;
1273                 qp->sq.max = cap->max_send_wr ?
1274                         roundup_pow_of_two(cap->max_send_wr) : 0;
1275         } else {
1276                 qp->rq.max = cap->max_recv_wr;
1277                 qp->sq.max = cap->max_send_wr;
1278         }
1279
1280         qp->rq.max_gs = cap->max_recv_sge;
1281         qp->sq.max_gs = max_t(int, cap->max_send_sge,
1282                               ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1283                                     MTHCA_INLINE_CHUNK_SIZE) /
1284                               sizeof (struct mthca_data_seg));
1285
1286         return 0;
1287 }
1288
1289 int mthca_alloc_qp(struct mthca_dev *dev,
1290                    struct mthca_pd *pd,
1291                    struct mthca_cq *send_cq,
1292                    struct mthca_cq *recv_cq,
1293                    enum ib_qp_type type,
1294                    enum ib_sig_type send_policy,
1295                    struct ib_qp_cap *cap,
1296                    struct mthca_qp *qp)
1297 {
1298         int err;
1299
1300         switch (type) {
1301         case IB_QPT_RC: qp->transport = RC; break;
1302         case IB_QPT_UC: qp->transport = UC; break;
1303         case IB_QPT_UD: qp->transport = UD; break;
1304         default: return -EINVAL;
1305         }
1306
1307         err = mthca_set_qp_size(dev, cap, pd, qp);
1308         if (err)
1309                 return err;
1310
1311         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1312         if (qp->qpn == -1)
1313                 return -ENOMEM;
1314
1315         /* initialize port to zero for error-catching. */
1316         qp->port = 0;
1317
1318         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1319                                     send_policy, qp);
1320         if (err) {
1321                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1322                 return err;
1323         }
1324
1325         spin_lock_irq(&dev->qp_table.lock);
1326         mthca_array_set(&dev->qp_table.qp,
1327                         qp->qpn & (dev->limits.num_qps - 1), qp);
1328         spin_unlock_irq(&dev->qp_table.lock);
1329
1330         return 0;
1331 }
1332
1333 static void mthca_lock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1334 {
1335         if (send_cq == recv_cq)
1336                 spin_lock_irq(&send_cq->lock);
1337         else if (send_cq->cqn < recv_cq->cqn) {
1338                 spin_lock_irq(&send_cq->lock);
1339                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1340         } else {
1341                 spin_lock_irq(&recv_cq->lock);
1342                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1343         }
1344 }
1345
1346 static void mthca_unlock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1347 {
1348         if (send_cq == recv_cq)
1349                 spin_unlock_irq(&send_cq->lock);
1350         else if (send_cq->cqn < recv_cq->cqn) {
1351                 spin_unlock(&recv_cq->lock);
1352                 spin_unlock_irq(&send_cq->lock);
1353         } else {
1354                 spin_unlock(&send_cq->lock);
1355                 spin_unlock_irq(&recv_cq->lock);
1356         }
1357 }
1358
1359 int mthca_alloc_sqp(struct mthca_dev *dev,
1360                     struct mthca_pd *pd,
1361                     struct mthca_cq *send_cq,
1362                     struct mthca_cq *recv_cq,
1363                     enum ib_sig_type send_policy,
1364                     struct ib_qp_cap *cap,
1365                     int qpn,
1366                     int port,
1367                     struct mthca_sqp *sqp)
1368 {
1369         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1370         int err;
1371
1372         sqp->qp.transport = MLX;
1373         err = mthca_set_qp_size(dev, cap, pd, &sqp->qp);
1374         if (err)
1375                 return err;
1376
1377         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1378         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1379                                              &sqp->header_dma, GFP_KERNEL);
1380         if (!sqp->header_buf)
1381                 return -ENOMEM;
1382
1383         spin_lock_irq(&dev->qp_table.lock);
1384         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1385                 err = -EBUSY;
1386         else
1387                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1388         spin_unlock_irq(&dev->qp_table.lock);
1389
1390         if (err)
1391                 goto err_out;
1392
1393         sqp->qp.port      = port;
1394         sqp->qp.qpn       = mqpn;
1395         sqp->qp.transport = MLX;
1396
1397         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1398                                     send_policy, &sqp->qp);
1399         if (err)
1400                 goto err_out_free;
1401
1402         atomic_inc(&pd->sqp_count);
1403
1404         return 0;
1405
1406  err_out_free:
1407         /*
1408          * Lock CQs here, so that CQ polling code can do QP lookup
1409          * without taking a lock.
1410          */
1411         mthca_lock_cqs(send_cq, recv_cq);
1412
1413         spin_lock(&dev->qp_table.lock);
1414         mthca_array_clear(&dev->qp_table.qp, mqpn);
1415         spin_unlock(&dev->qp_table.lock);
1416
1417         mthca_unlock_cqs(send_cq, recv_cq);
1418
1419  err_out:
1420         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1421                           sqp->header_buf, sqp->header_dma);
1422
1423         return err;
1424 }
1425
1426 static inline int get_qp_refcount(struct mthca_dev *dev, struct mthca_qp *qp)
1427 {
1428         int c;
1429
1430         spin_lock_irq(&dev->qp_table.lock);
1431         c = qp->refcount;
1432         spin_unlock_irq(&dev->qp_table.lock);
1433
1434         return c;
1435 }
1436
1437 void mthca_free_qp(struct mthca_dev *dev,
1438                    struct mthca_qp *qp)
1439 {
1440         u8 status;
1441         struct mthca_cq *send_cq;
1442         struct mthca_cq *recv_cq;
1443
1444         send_cq = to_mcq(qp->ibqp.send_cq);
1445         recv_cq = to_mcq(qp->ibqp.recv_cq);
1446
1447         /*
1448          * Lock CQs here, so that CQ polling code can do QP lookup
1449          * without taking a lock.
1450          */
1451         mthca_lock_cqs(send_cq, recv_cq);
1452
1453         spin_lock(&dev->qp_table.lock);
1454         mthca_array_clear(&dev->qp_table.qp,
1455                           qp->qpn & (dev->limits.num_qps - 1));
1456         --qp->refcount;
1457         spin_unlock(&dev->qp_table.lock);
1458
1459         mthca_unlock_cqs(send_cq, recv_cq);
1460
1461         wait_event(qp->wait, !get_qp_refcount(dev, qp));
1462
1463         if (qp->state != IB_QPS_RESET)
1464                 mthca_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, 0,
1465                                 NULL, 0, &status);
1466
1467         /*
1468          * If this is a userspace QP, the buffers, MR, CQs and so on
1469          * will be cleaned up in userspace, so all we have to do is
1470          * unref the mem-free tables and free the QPN in our table.
1471          */
1472         if (!qp->ibqp.uobject) {
1473                 mthca_cq_clean(dev, recv_cq, qp->qpn,
1474                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1475                 if (send_cq != recv_cq)
1476                         mthca_cq_clean(dev, send_cq, qp->qpn, NULL);
1477
1478                 mthca_free_memfree(dev, qp);
1479                 mthca_free_wqe_buf(dev, qp);
1480         }
1481
1482         mthca_unmap_memfree(dev, qp);
1483
1484         if (is_sqp(dev, qp)) {
1485                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1486                 dma_free_coherent(&dev->pdev->dev,
1487                                   to_msqp(qp)->header_buf_size,
1488                                   to_msqp(qp)->header_buf,
1489                                   to_msqp(qp)->header_dma);
1490         } else
1491                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1492 }
1493
1494 /* Create UD header for an MLX send and build a data segment for it */
1495 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1496                             int ind, struct ib_send_wr *wr,
1497                             struct mthca_mlx_seg *mlx,
1498                             struct mthca_data_seg *data)
1499 {
1500         int header_size;
1501         int err;
1502         u16 pkey;
1503
1504         ib_ud_header_init(256, /* assume a MAD */
1505                           mthca_ah_grh_present(to_mah(wr->wr.ud.ah)),
1506                           &sqp->ud_header);
1507
1508         err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1509         if (err)
1510                 return err;
1511         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1512         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1513                                   (sqp->ud_header.lrh.destination_lid ==
1514                                    IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1515                                   (sqp->ud_header.lrh.service_level << 8));
1516         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1517         mlx->vcrc = 0;
1518
1519         switch (wr->opcode) {
1520         case IB_WR_SEND:
1521                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1522                 sqp->ud_header.immediate_present = 0;
1523                 break;
1524         case IB_WR_SEND_WITH_IMM:
1525                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1526                 sqp->ud_header.immediate_present = 1;
1527                 sqp->ud_header.immediate_data = wr->imm_data;
1528                 break;
1529         default:
1530                 return -EINVAL;
1531         }
1532
1533         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1534         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1535                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1536         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1537         if (!sqp->qp.ibqp.qp_num)
1538                 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1539                                    sqp->pkey_index, &pkey);
1540         else
1541                 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1542                                    wr->wr.ud.pkey_index, &pkey);
1543         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1544         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1545         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1546         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1547                                                sqp->qkey : wr->wr.ud.remote_qkey);
1548         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1549
1550         header_size = ib_ud_header_pack(&sqp->ud_header,
1551                                         sqp->header_buf +
1552                                         ind * MTHCA_UD_HEADER_SIZE);
1553
1554         data->byte_count = cpu_to_be32(header_size);
1555         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1556         data->addr       = cpu_to_be64(sqp->header_dma +
1557                                        ind * MTHCA_UD_HEADER_SIZE);
1558
1559         return 0;
1560 }
1561
1562 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1563                                     struct ib_cq *ib_cq)
1564 {
1565         unsigned cur;
1566         struct mthca_cq *cq;
1567
1568         cur = wq->head - wq->tail;
1569         if (likely(cur + nreq < wq->max))
1570                 return 0;
1571
1572         cq = to_mcq(ib_cq);
1573         spin_lock(&cq->lock);
1574         cur = wq->head - wq->tail;
1575         spin_unlock(&cq->lock);
1576
1577         return cur + nreq >= wq->max;
1578 }
1579
1580 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1581                           struct ib_send_wr **bad_wr)
1582 {
1583         struct mthca_dev *dev = to_mdev(ibqp->device);
1584         struct mthca_qp *qp = to_mqp(ibqp);
1585         void *wqe;
1586         void *prev_wqe;
1587         unsigned long flags;
1588         int err = 0;
1589         int nreq;
1590         int i;
1591         int size;
1592         int size0 = 0;
1593         u32 f0;
1594         int ind;
1595         u8 op0 = 0;
1596
1597         spin_lock_irqsave(&qp->sq.lock, flags);
1598
1599         /* XXX check that state is OK to post send */
1600
1601         ind = qp->sq.next_ind;
1602
1603         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1604                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1605                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1606                                         " %d max, %d nreq)\n", qp->qpn,
1607                                         qp->sq.head, qp->sq.tail,
1608                                         qp->sq.max, nreq);
1609                         err = -ENOMEM;
1610                         *bad_wr = wr;
1611                         goto out;
1612                 }
1613
1614                 wqe = get_send_wqe(qp, ind);
1615                 prev_wqe = qp->sq.last;
1616                 qp->sq.last = wqe;
1617
1618                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1619                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1620                 ((struct mthca_next_seg *) wqe)->flags =
1621                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1622                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1623                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1624                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1625                         cpu_to_be32(1);
1626                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1627                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1628                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1629
1630                 wqe += sizeof (struct mthca_next_seg);
1631                 size = sizeof (struct mthca_next_seg) / 16;
1632
1633                 switch (qp->transport) {
1634                 case RC:
1635                         switch (wr->opcode) {
1636                         case IB_WR_ATOMIC_CMP_AND_SWP:
1637                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1638                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1639                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1640                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1641                                         cpu_to_be32(wr->wr.atomic.rkey);
1642                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1643
1644                                 wqe += sizeof (struct mthca_raddr_seg);
1645
1646                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1647                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1648                                                 cpu_to_be64(wr->wr.atomic.swap);
1649                                         ((struct mthca_atomic_seg *) wqe)->compare =
1650                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1651                                 } else {
1652                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1653                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1654                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1655                                 }
1656
1657                                 wqe += sizeof (struct mthca_atomic_seg);
1658                                 size += (sizeof (struct mthca_raddr_seg) +
1659                                          sizeof (struct mthca_atomic_seg)) / 16;
1660                                 break;
1661
1662                         case IB_WR_RDMA_WRITE:
1663                         case IB_WR_RDMA_WRITE_WITH_IMM:
1664                         case IB_WR_RDMA_READ:
1665                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1666                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1667                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1668                                         cpu_to_be32(wr->wr.rdma.rkey);
1669                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1670                                 wqe += sizeof (struct mthca_raddr_seg);
1671                                 size += sizeof (struct mthca_raddr_seg) / 16;
1672                                 break;
1673
1674                         default:
1675                                 /* No extra segments required for sends */
1676                                 break;
1677                         }
1678
1679                         break;
1680
1681                 case UC:
1682                         switch (wr->opcode) {
1683                         case IB_WR_RDMA_WRITE:
1684                         case IB_WR_RDMA_WRITE_WITH_IMM:
1685                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1686                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1687                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1688                                         cpu_to_be32(wr->wr.rdma.rkey);
1689                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1690                                 wqe += sizeof (struct mthca_raddr_seg);
1691                                 size += sizeof (struct mthca_raddr_seg) / 16;
1692                                 break;
1693
1694                         default:
1695                                 /* No extra segments required for sends */
1696                                 break;
1697                         }
1698
1699                         break;
1700
1701                 case UD:
1702                         ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1703                                 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1704                         ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1705                                 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1706                         ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1707                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1708                         ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1709                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1710
1711                         wqe += sizeof (struct mthca_tavor_ud_seg);
1712                         size += sizeof (struct mthca_tavor_ud_seg) / 16;
1713                         break;
1714
1715                 case MLX:
1716                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1717                                                wqe - sizeof (struct mthca_next_seg),
1718                                                wqe);
1719                         if (err) {
1720                                 *bad_wr = wr;
1721                                 goto out;
1722                         }
1723                         wqe += sizeof (struct mthca_data_seg);
1724                         size += sizeof (struct mthca_data_seg) / 16;
1725                         break;
1726                 }
1727
1728                 if (wr->num_sge > qp->sq.max_gs) {
1729                         mthca_err(dev, "too many gathers\n");
1730                         err = -EINVAL;
1731                         *bad_wr = wr;
1732                         goto out;
1733                 }
1734
1735                 for (i = 0; i < wr->num_sge; ++i) {
1736                         ((struct mthca_data_seg *) wqe)->byte_count =
1737                                 cpu_to_be32(wr->sg_list[i].length);
1738                         ((struct mthca_data_seg *) wqe)->lkey =
1739                                 cpu_to_be32(wr->sg_list[i].lkey);
1740                         ((struct mthca_data_seg *) wqe)->addr =
1741                                 cpu_to_be64(wr->sg_list[i].addr);
1742                         wqe += sizeof (struct mthca_data_seg);
1743                         size += sizeof (struct mthca_data_seg) / 16;
1744                 }
1745
1746                 /* Add one more inline data segment for ICRC */
1747                 if (qp->transport == MLX) {
1748                         ((struct mthca_data_seg *) wqe)->byte_count =
1749                                 cpu_to_be32((1 << 31) | 4);
1750                         ((u32 *) wqe)[1] = 0;
1751                         wqe += sizeof (struct mthca_data_seg);
1752                         size += sizeof (struct mthca_data_seg) / 16;
1753                 }
1754
1755                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1756
1757                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1758                         mthca_err(dev, "opcode invalid\n");
1759                         err = -EINVAL;
1760                         *bad_wr = wr;
1761                         goto out;
1762                 }
1763
1764                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1765                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
1766                                      qp->send_wqe_offset) |
1767                                     mthca_opcode[wr->opcode]);
1768                 wmb();
1769                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1770                         cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size |
1771                                     ((wr->send_flags & IB_SEND_FENCE) ?
1772                                     MTHCA_NEXT_FENCE : 0));
1773
1774                 if (!size0) {
1775                         size0 = size;
1776                         op0   = mthca_opcode[wr->opcode];
1777                         f0    = wr->send_flags & IB_SEND_FENCE ?
1778                                 MTHCA_SEND_DOORBELL_FENCE : 0;
1779                 }
1780
1781                 ++ind;
1782                 if (unlikely(ind >= qp->sq.max))
1783                         ind -= qp->sq.max;
1784         }
1785
1786 out:
1787         if (likely(nreq)) {
1788                 __be32 doorbell[2];
1789
1790                 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1791                                            qp->send_wqe_offset) | f0 | op0);
1792                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1793
1794                 wmb();
1795
1796                 mthca_write64(doorbell,
1797                               dev->kar + MTHCA_SEND_DOORBELL,
1798                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1799                 /*
1800                  * Make sure doorbells don't leak out of SQ spinlock
1801                  * and reach the HCA out of order:
1802                  */
1803                 mmiowb();
1804         }
1805
1806         qp->sq.next_ind = ind;
1807         qp->sq.head    += nreq;
1808
1809         spin_unlock_irqrestore(&qp->sq.lock, flags);
1810         return err;
1811 }
1812
1813 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1814                              struct ib_recv_wr **bad_wr)
1815 {
1816         struct mthca_dev *dev = to_mdev(ibqp->device);
1817         struct mthca_qp *qp = to_mqp(ibqp);
1818         __be32 doorbell[2];
1819         unsigned long flags;
1820         int err = 0;
1821         int nreq;
1822         int i;
1823         int size;
1824         int size0 = 0;
1825         int ind;
1826         void *wqe;
1827         void *prev_wqe;
1828
1829         spin_lock_irqsave(&qp->rq.lock, flags);
1830
1831         /* XXX check that state is OK to post receive */
1832
1833         ind = qp->rq.next_ind;
1834
1835         for (nreq = 0; wr; wr = wr->next) {
1836                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1837                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1838                                         " %d max, %d nreq)\n", qp->qpn,
1839                                         qp->rq.head, qp->rq.tail,
1840                                         qp->rq.max, nreq);
1841                         err = -ENOMEM;
1842                         *bad_wr = wr;
1843                         goto out;
1844                 }
1845
1846                 wqe = get_recv_wqe(qp, ind);
1847                 prev_wqe = qp->rq.last;
1848                 qp->rq.last = wqe;
1849
1850                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1851                 ((struct mthca_next_seg *) wqe)->ee_nds =
1852                         cpu_to_be32(MTHCA_NEXT_DBD);
1853                 ((struct mthca_next_seg *) wqe)->flags = 0;
1854
1855                 wqe += sizeof (struct mthca_next_seg);
1856                 size = sizeof (struct mthca_next_seg) / 16;
1857
1858                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1859                         err = -EINVAL;
1860                         *bad_wr = wr;
1861                         goto out;
1862                 }
1863
1864                 for (i = 0; i < wr->num_sge; ++i) {
1865                         ((struct mthca_data_seg *) wqe)->byte_count =
1866                                 cpu_to_be32(wr->sg_list[i].length);
1867                         ((struct mthca_data_seg *) wqe)->lkey =
1868                                 cpu_to_be32(wr->sg_list[i].lkey);
1869                         ((struct mthca_data_seg *) wqe)->addr =
1870                                 cpu_to_be64(wr->sg_list[i].addr);
1871                         wqe += sizeof (struct mthca_data_seg);
1872                         size += sizeof (struct mthca_data_seg) / 16;
1873                 }
1874
1875                 qp->wrid[ind] = wr->wr_id;
1876
1877                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1878                         cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1879                 wmb();
1880                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1881                         cpu_to_be32(MTHCA_NEXT_DBD | size);
1882
1883                 if (!size0)
1884                         size0 = size;
1885
1886                 ++ind;
1887                 if (unlikely(ind >= qp->rq.max))
1888                         ind -= qp->rq.max;
1889
1890                 ++nreq;
1891                 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1892                         nreq = 0;
1893
1894                         doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1895                         doorbell[1] = cpu_to_be32(qp->qpn << 8);
1896
1897                         wmb();
1898
1899                         mthca_write64(doorbell,
1900                                       dev->kar + MTHCA_RECEIVE_DOORBELL,
1901                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1902
1903                         qp->rq.next_ind = ind;
1904                         qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1905                         size0 = 0;
1906                 }
1907         }
1908
1909 out:
1910         if (likely(nreq)) {
1911                 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1912                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1913
1914                 wmb();
1915
1916                 mthca_write64(doorbell,
1917                               dev->kar + MTHCA_RECEIVE_DOORBELL,
1918                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1919         }
1920
1921         qp->rq.next_ind = ind;
1922         qp->rq.head    += nreq;
1923
1924         /*
1925          * Make sure doorbells don't leak out of RQ spinlock and reach
1926          * the HCA out of order:
1927          */
1928         mmiowb();
1929
1930         spin_unlock_irqrestore(&qp->rq.lock, flags);
1931         return err;
1932 }
1933
1934 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1935                           struct ib_send_wr **bad_wr)
1936 {
1937         struct mthca_dev *dev = to_mdev(ibqp->device);
1938         struct mthca_qp *qp = to_mqp(ibqp);
1939         __be32 doorbell[2];
1940         void *wqe;
1941         void *prev_wqe;
1942         unsigned long flags;
1943         int err = 0;
1944         int nreq;
1945         int i;
1946         int size;
1947         int size0 = 0;
1948         u32 f0;
1949         int ind;
1950         u8 op0 = 0;
1951
1952         spin_lock_irqsave(&qp->sq.lock, flags);
1953
1954         /* XXX check that state is OK to post send */
1955
1956         ind = qp->sq.head & (qp->sq.max - 1);
1957
1958         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1959                 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1960                         nreq = 0;
1961
1962                         doorbell[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1963                                                   ((qp->sq.head & 0xffff) << 8) |
1964                                                   f0 | op0);
1965                         doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1966
1967                         qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1968                         size0 = 0;
1969
1970                         /*
1971                          * Make sure that descriptors are written before
1972                          * doorbell record.
1973                          */
1974                         wmb();
1975                         *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1976
1977                         /*
1978                          * Make sure doorbell record is written before we
1979                          * write MMIO send doorbell.
1980                          */
1981                         wmb();
1982                         mthca_write64(doorbell,
1983                                       dev->kar + MTHCA_SEND_DOORBELL,
1984                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1985                 }
1986
1987                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1988                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1989                                         " %d max, %d nreq)\n", qp->qpn,
1990                                         qp->sq.head, qp->sq.tail,
1991                                         qp->sq.max, nreq);
1992                         err = -ENOMEM;
1993                         *bad_wr = wr;
1994                         goto out;
1995                 }
1996
1997                 wqe = get_send_wqe(qp, ind);
1998                 prev_wqe = qp->sq.last;
1999                 qp->sq.last = wqe;
2000
2001                 ((struct mthca_next_seg *) wqe)->flags =
2002                         ((wr->send_flags & IB_SEND_SIGNALED) ?
2003                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
2004                         ((wr->send_flags & IB_SEND_SOLICITED) ?
2005                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
2006                         cpu_to_be32(1);
2007                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
2008                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
2009                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
2010
2011                 wqe += sizeof (struct mthca_next_seg);
2012                 size = sizeof (struct mthca_next_seg) / 16;
2013
2014                 switch (qp->transport) {
2015                 case RC:
2016                         switch (wr->opcode) {
2017                         case IB_WR_ATOMIC_CMP_AND_SWP:
2018                         case IB_WR_ATOMIC_FETCH_AND_ADD:
2019                                 ((struct mthca_raddr_seg *) wqe)->raddr =
2020                                         cpu_to_be64(wr->wr.atomic.remote_addr);
2021                                 ((struct mthca_raddr_seg *) wqe)->rkey =
2022                                         cpu_to_be32(wr->wr.atomic.rkey);
2023                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
2024
2025                                 wqe += sizeof (struct mthca_raddr_seg);
2026
2027                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2028                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
2029                                                 cpu_to_be64(wr->wr.atomic.swap);
2030                                         ((struct mthca_atomic_seg *) wqe)->compare =
2031                                                 cpu_to_be64(wr->wr.atomic.compare_add);
2032                                 } else {
2033                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
2034                                                 cpu_to_be64(wr->wr.atomic.compare_add);
2035                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
2036                                 }
2037
2038                                 wqe += sizeof (struct mthca_atomic_seg);
2039                                 size += (sizeof (struct mthca_raddr_seg) +
2040                                          sizeof (struct mthca_atomic_seg)) / 16;
2041                                 break;
2042
2043                         case IB_WR_RDMA_READ:
2044                         case IB_WR_RDMA_WRITE:
2045                         case IB_WR_RDMA_WRITE_WITH_IMM:
2046                                 ((struct mthca_raddr_seg *) wqe)->raddr =
2047                                         cpu_to_be64(wr->wr.rdma.remote_addr);
2048                                 ((struct mthca_raddr_seg *) wqe)->rkey =
2049                                         cpu_to_be32(wr->wr.rdma.rkey);
2050                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
2051                                 wqe += sizeof (struct mthca_raddr_seg);
2052                                 size += sizeof (struct mthca_raddr_seg) / 16;
2053                                 break;
2054
2055                         default:
2056                                 /* No extra segments required for sends */
2057                                 break;
2058                         }
2059
2060                         break;
2061
2062                 case UC:
2063                         switch (wr->opcode) {
2064                         case IB_WR_RDMA_WRITE:
2065                         case IB_WR_RDMA_WRITE_WITH_IMM:
2066                                 ((struct mthca_raddr_seg *) wqe)->raddr =
2067                                         cpu_to_be64(wr->wr.rdma.remote_addr);
2068                                 ((struct mthca_raddr_seg *) wqe)->rkey =
2069                                         cpu_to_be32(wr->wr.rdma.rkey);
2070                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
2071                                 wqe += sizeof (struct mthca_raddr_seg);
2072                                 size += sizeof (struct mthca_raddr_seg) / 16;
2073                                 break;
2074
2075                         default:
2076                                 /* No extra segments required for sends */
2077                                 break;
2078                         }
2079
2080                         break;
2081
2082                 case UD:
2083                         memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
2084                                to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
2085                         ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
2086                                 cpu_to_be32(wr->wr.ud.remote_qpn);
2087                         ((struct mthca_arbel_ud_seg *) wqe)->qkey =
2088                                 cpu_to_be32(wr->wr.ud.remote_qkey);
2089
2090                         wqe += sizeof (struct mthca_arbel_ud_seg);
2091                         size += sizeof (struct mthca_arbel_ud_seg) / 16;
2092                         break;
2093
2094                 case MLX:
2095                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
2096                                                wqe - sizeof (struct mthca_next_seg),
2097                                                wqe);
2098                         if (err) {
2099                                 *bad_wr = wr;
2100                                 goto out;
2101                         }
2102                         wqe += sizeof (struct mthca_data_seg);
2103                         size += sizeof (struct mthca_data_seg) / 16;
2104                         break;
2105                 }
2106
2107                 if (wr->num_sge > qp->sq.max_gs) {
2108                         mthca_err(dev, "too many gathers\n");
2109                         err = -EINVAL;
2110                         *bad_wr = wr;
2111                         goto out;
2112                 }
2113
2114                 for (i = 0; i < wr->num_sge; ++i) {
2115                         ((struct mthca_data_seg *) wqe)->byte_count =
2116                                 cpu_to_be32(wr->sg_list[i].length);
2117                         ((struct mthca_data_seg *) wqe)->lkey =
2118                                 cpu_to_be32(wr->sg_list[i].lkey);
2119                         ((struct mthca_data_seg *) wqe)->addr =
2120                                 cpu_to_be64(wr->sg_list[i].addr);
2121                         wqe += sizeof (struct mthca_data_seg);
2122                         size += sizeof (struct mthca_data_seg) / 16;
2123                 }
2124
2125                 /* Add one more inline data segment for ICRC */
2126                 if (qp->transport == MLX) {
2127                         ((struct mthca_data_seg *) wqe)->byte_count =
2128                                 cpu_to_be32((1 << 31) | 4);
2129                         ((u32 *) wqe)[1] = 0;
2130                         wqe += sizeof (struct mthca_data_seg);
2131                         size += sizeof (struct mthca_data_seg) / 16;
2132                 }
2133
2134                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2135
2136                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2137                         mthca_err(dev, "opcode invalid\n");
2138                         err = -EINVAL;
2139                         *bad_wr = wr;
2140                         goto out;
2141                 }
2142
2143                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2144                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
2145                                      qp->send_wqe_offset) |
2146                                     mthca_opcode[wr->opcode]);
2147                 wmb();
2148                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2149                         cpu_to_be32(MTHCA_NEXT_DBD | size |
2150                                     ((wr->send_flags & IB_SEND_FENCE) ?
2151                                      MTHCA_NEXT_FENCE : 0));
2152
2153                 if (!size0) {
2154                         size0 = size;
2155                         op0   = mthca_opcode[wr->opcode];
2156                         f0    = wr->send_flags & IB_SEND_FENCE ?
2157                                 MTHCA_SEND_DOORBELL_FENCE : 0;
2158                 }
2159
2160                 ++ind;
2161                 if (unlikely(ind >= qp->sq.max))
2162                         ind -= qp->sq.max;
2163         }
2164
2165 out:
2166         if (likely(nreq)) {
2167                 doorbell[0] = cpu_to_be32((nreq << 24)                  |
2168                                           ((qp->sq.head & 0xffff) << 8) |
2169                                           f0 | op0);
2170                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
2171
2172                 qp->sq.head += nreq;
2173
2174                 /*
2175                  * Make sure that descriptors are written before
2176                  * doorbell record.
2177                  */
2178                 wmb();
2179                 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2180
2181                 /*
2182                  * Make sure doorbell record is written before we
2183                  * write MMIO send doorbell.
2184                  */
2185                 wmb();
2186                 mthca_write64(doorbell,
2187                               dev->kar + MTHCA_SEND_DOORBELL,
2188                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2189         }
2190
2191         /*
2192          * Make sure doorbells don't leak out of SQ spinlock and reach
2193          * the HCA out of order:
2194          */
2195         mmiowb();
2196
2197         spin_unlock_irqrestore(&qp->sq.lock, flags);
2198         return err;
2199 }
2200
2201 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2202                              struct ib_recv_wr **bad_wr)
2203 {
2204         struct mthca_dev *dev = to_mdev(ibqp->device);
2205         struct mthca_qp *qp = to_mqp(ibqp);
2206         unsigned long flags;
2207         int err = 0;
2208         int nreq;
2209         int ind;
2210         int i;
2211         void *wqe;
2212
2213         spin_lock_irqsave(&qp->rq.lock, flags);
2214
2215         /* XXX check that state is OK to post receive */
2216
2217         ind = qp->rq.head & (qp->rq.max - 1);
2218
2219         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2220                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2221                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2222                                         " %d max, %d nreq)\n", qp->qpn,
2223                                         qp->rq.head, qp->rq.tail,
2224                                         qp->rq.max, nreq);
2225                         err = -ENOMEM;
2226                         *bad_wr = wr;
2227                         goto out;
2228                 }
2229
2230                 wqe = get_recv_wqe(qp, ind);
2231
2232                 ((struct mthca_next_seg *) wqe)->flags = 0;
2233
2234                 wqe += sizeof (struct mthca_next_seg);
2235
2236                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2237                         err = -EINVAL;
2238                         *bad_wr = wr;
2239                         goto out;
2240                 }
2241
2242                 for (i = 0; i < wr->num_sge; ++i) {
2243                         ((struct mthca_data_seg *) wqe)->byte_count =
2244                                 cpu_to_be32(wr->sg_list[i].length);
2245                         ((struct mthca_data_seg *) wqe)->lkey =
2246                                 cpu_to_be32(wr->sg_list[i].lkey);
2247                         ((struct mthca_data_seg *) wqe)->addr =
2248                                 cpu_to_be64(wr->sg_list[i].addr);
2249                         wqe += sizeof (struct mthca_data_seg);
2250                 }
2251
2252                 if (i < qp->rq.max_gs) {
2253                         ((struct mthca_data_seg *) wqe)->byte_count = 0;
2254                         ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
2255                         ((struct mthca_data_seg *) wqe)->addr = 0;
2256                 }
2257
2258                 qp->wrid[ind] = wr->wr_id;
2259
2260                 ++ind;
2261                 if (unlikely(ind >= qp->rq.max))
2262                         ind -= qp->rq.max;
2263         }
2264 out:
2265         if (likely(nreq)) {
2266                 qp->rq.head += nreq;
2267
2268                 /*
2269                  * Make sure that descriptors are written before
2270                  * doorbell record.
2271                  */
2272                 wmb();
2273                 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2274         }
2275
2276         spin_unlock_irqrestore(&qp->rq.lock, flags);
2277         return err;
2278 }
2279
2280 void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2281                         int index, int *dbd, __be32 *new_wqe)
2282 {
2283         struct mthca_next_seg *next;
2284
2285         /*
2286          * For SRQs, all WQEs generate a CQE, so we're always at the
2287          * end of the doorbell chain.
2288          */
2289         if (qp->ibqp.srq) {
2290                 *new_wqe = 0;
2291                 return;
2292         }
2293
2294         if (is_send)
2295                 next = get_send_wqe(qp, index);
2296         else
2297                 next = get_recv_wqe(qp, index);
2298
2299         *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2300         if (next->ee_nds & cpu_to_be32(0x3f))
2301                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2302                         (next->ee_nds & cpu_to_be32(0x3f));
2303         else
2304                 *new_wqe = 0;
2305 }
2306
2307 int mthca_init_qp_table(struct mthca_dev *dev)
2308 {
2309         int err;
2310         u8 status;
2311         int i;
2312
2313         spin_lock_init(&dev->qp_table.lock);
2314
2315         /*
2316          * We reserve 2 extra QPs per port for the special QPs.  The
2317          * special QP for port 1 has to be even, so round up.
2318          */
2319         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2320         err = mthca_alloc_init(&dev->qp_table.alloc,
2321                                dev->limits.num_qps,
2322                                (1 << 24) - 1,
2323                                dev->qp_table.sqp_start +
2324                                MTHCA_MAX_PORTS * 2);
2325         if (err)
2326                 return err;
2327
2328         err = mthca_array_init(&dev->qp_table.qp,
2329                                dev->limits.num_qps);
2330         if (err) {
2331                 mthca_alloc_cleanup(&dev->qp_table.alloc);
2332                 return err;
2333         }
2334
2335         for (i = 0; i < 2; ++i) {
2336                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2337                                             dev->qp_table.sqp_start + i * 2,
2338                                             &status);
2339                 if (err)
2340                         goto err_out;
2341                 if (status) {
2342                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
2343                                    "status %02x, aborting.\n",
2344                                    status);
2345                         err = -EINVAL;
2346                         goto err_out;
2347                 }
2348         }
2349         return 0;
2350
2351  err_out:
2352         for (i = 0; i < 2; ++i)
2353                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2354
2355         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2356         mthca_alloc_cleanup(&dev->qp_table.alloc);
2357
2358         return err;
2359 }
2360
2361 void mthca_cleanup_qp_table(struct mthca_dev *dev)
2362 {
2363         int i;
2364         u8 status;
2365
2366         for (i = 0; i < 2; ++i)
2367                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2368
2369         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2370         mthca_alloc_cleanup(&dev->qp_table.alloc);
2371 }