2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #ifndef _IPATH_REGISTERS_H
35 #define _IPATH_REGISTERS_H
38 * This file should only be included by kernel source, and by the diags. It
39 * defines the registers, and their contents, for InfiniPath chips.
43 * These are the InfiniPath register and buffer bit definitions,
44 * that are visible to software, and needed only by the kernel
45 * and diag code. A few, that are visible to protocol and user
46 * code are in ipath_common.h. Some bits are specific
47 * to a given chip implementation, and have been moved to the
48 * chip-specific source file
51 /* kr_revision bits */
52 #define INFINIPATH_R_CHIPREVMINOR_MASK 0xFF
53 #define INFINIPATH_R_CHIPREVMINOR_SHIFT 0
54 #define INFINIPATH_R_CHIPREVMAJOR_MASK 0xFF
55 #define INFINIPATH_R_CHIPREVMAJOR_SHIFT 8
56 #define INFINIPATH_R_ARCH_MASK 0xFF
57 #define INFINIPATH_R_ARCH_SHIFT 16
58 #define INFINIPATH_R_SOFTWARE_MASK 0xFF
59 #define INFINIPATH_R_SOFTWARE_SHIFT 24
60 #define INFINIPATH_R_BOARDID_MASK 0xFF
61 #define INFINIPATH_R_BOARDID_SHIFT 32
64 #define INFINIPATH_C_FREEZEMODE 0x00000002
65 #define INFINIPATH_C_LINKENABLE 0x00000004
67 /* kr_sendctrl bits */
68 #define INFINIPATH_S_DISARMPIOBUF_SHIFT 16
70 #define IPATH_S_ABORT 0
71 #define IPATH_S_PIOINTBUFAVAIL 1
72 #define IPATH_S_PIOBUFAVAILUPD 2
73 #define IPATH_S_PIOENABLE 3
74 #define IPATH_S_DISARM 31
76 #define INFINIPATH_S_ABORT (1U << IPATH_S_ABORT)
77 #define INFINIPATH_S_PIOINTBUFAVAIL (1U << IPATH_S_PIOINTBUFAVAIL)
78 #define INFINIPATH_S_PIOBUFAVAILUPD (1U << IPATH_S_PIOBUFAVAILUPD)
79 #define INFINIPATH_S_PIOENABLE (1U << IPATH_S_PIOENABLE)
80 #define INFINIPATH_S_DISARM (1U << IPATH_S_DISARM)
83 #define INFINIPATH_R_PORTENABLE_SHIFT 0
84 #define INFINIPATH_R_QPMAP_ENABLE (1ULL << 38)
86 /* kr_intstatus, kr_intclear, kr_intmask bits */
87 #define INFINIPATH_I_RCVURG_SHIFT 0
88 #define INFINIPATH_I_RCVAVAIL_SHIFT 12
89 #define INFINIPATH_I_ERROR 0x80000000
90 #define INFINIPATH_I_SPIOSENT 0x40000000
91 #define INFINIPATH_I_SPIOBUFAVAIL 0x20000000
92 #define INFINIPATH_I_GPIO 0x10000000
94 /* kr_errorstatus, kr_errorclear, kr_errormask bits */
95 #define INFINIPATH_E_RFORMATERR 0x0000000000000001ULL
96 #define INFINIPATH_E_RVCRC 0x0000000000000002ULL
97 #define INFINIPATH_E_RICRC 0x0000000000000004ULL
98 #define INFINIPATH_E_RMINPKTLEN 0x0000000000000008ULL
99 #define INFINIPATH_E_RMAXPKTLEN 0x0000000000000010ULL
100 #define INFINIPATH_E_RLONGPKTLEN 0x0000000000000020ULL
101 #define INFINIPATH_E_RSHORTPKTLEN 0x0000000000000040ULL
102 #define INFINIPATH_E_RUNEXPCHAR 0x0000000000000080ULL
103 #define INFINIPATH_E_RUNSUPVL 0x0000000000000100ULL
104 #define INFINIPATH_E_REBP 0x0000000000000200ULL
105 #define INFINIPATH_E_RIBFLOW 0x0000000000000400ULL
106 #define INFINIPATH_E_RBADVERSION 0x0000000000000800ULL
107 #define INFINIPATH_E_RRCVEGRFULL 0x0000000000001000ULL
108 #define INFINIPATH_E_RRCVHDRFULL 0x0000000000002000ULL
109 #define INFINIPATH_E_RBADTID 0x0000000000004000ULL
110 #define INFINIPATH_E_RHDRLEN 0x0000000000008000ULL
111 #define INFINIPATH_E_RHDR 0x0000000000010000ULL
112 #define INFINIPATH_E_RIBLOSTLINK 0x0000000000020000ULL
113 #define INFINIPATH_E_SMINPKTLEN 0x0000000020000000ULL
114 #define INFINIPATH_E_SMAXPKTLEN 0x0000000040000000ULL
115 #define INFINIPATH_E_SUNDERRUN 0x0000000080000000ULL
116 #define INFINIPATH_E_SPKTLEN 0x0000000100000000ULL
117 #define INFINIPATH_E_SDROPPEDSMPPKT 0x0000000200000000ULL
118 #define INFINIPATH_E_SDROPPEDDATAPKT 0x0000000400000000ULL
119 #define INFINIPATH_E_SPIOARMLAUNCH 0x0000000800000000ULL
120 #define INFINIPATH_E_SUNEXPERRPKTNUM 0x0000001000000000ULL
121 #define INFINIPATH_E_SUNSUPVL 0x0000002000000000ULL
122 #define INFINIPATH_E_IBSTATUSCHANGED 0x0001000000000000ULL
123 #define INFINIPATH_E_INVALIDADDR 0x0002000000000000ULL
124 #define INFINIPATH_E_RESET 0x0004000000000000ULL
125 #define INFINIPATH_E_HARDWARE 0x0008000000000000ULL
128 * this is used to print "common" packet errors only when the
129 * __IPATH_ERRPKTDBG bit is set in ipath_debug.
131 #define INFINIPATH_E_PKTERRS ( INFINIPATH_E_SPKTLEN \
132 | INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_RVCRC \
133 | INFINIPATH_E_RICRC | INFINIPATH_E_RSHORTPKTLEN \
134 | INFINIPATH_E_REBP )
136 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
137 /* TXEMEMPARITYERR bit 0: PIObuf, 1: PIOpbc, 2: launchfifo
138 * RXEMEMPARITYERR bit 0: rcvbuf, 1: lookupq, 2: expTID, 3: eagerTID
139 * bit 4: flag buffer, 5: datainfo, 6: header info */
140 #define INFINIPATH_HWE_TXEMEMPARITYERR_MASK 0xFULL
141 #define INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT 40
142 #define INFINIPATH_HWE_RXEMEMPARITYERR_MASK 0x7FULL
143 #define INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT 44
144 #define INFINIPATH_HWE_IBCBUSTOSPCPARITYERR 0x4000000000000000ULL
145 #define INFINIPATH_HWE_IBCBUSFRSPCPARITYERR 0x8000000000000000ULL
146 /* txe mem parity errors (shift by INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) */
147 #define INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF 0x1ULL
148 #define INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC 0x2ULL
149 #define INFINIPATH_HWE_TXEMEMPARITYERR_PIOLAUNCHFIFO 0x4ULL
150 /* rxe mem parity errors (shift by INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) */
151 #define INFINIPATH_HWE_RXEMEMPARITYERR_RCVBUF 0x01ULL
152 #define INFINIPATH_HWE_RXEMEMPARITYERR_LOOKUPQ 0x02ULL
153 #define INFINIPATH_HWE_RXEMEMPARITYERR_EXPTID 0x04ULL
154 #define INFINIPATH_HWE_RXEMEMPARITYERR_EAGERTID 0x08ULL
155 #define INFINIPATH_HWE_RXEMEMPARITYERR_FLAGBUF 0x10ULL
156 #define INFINIPATH_HWE_RXEMEMPARITYERR_DATAINFO 0x20ULL
157 #define INFINIPATH_HWE_RXEMEMPARITYERR_HDRINFO 0x40ULL
158 /* waldo specific -- find the rest in ipath_6110.c */
159 #define INFINIPATH_HWE_RXDSYNCMEMPARITYERR 0x0000000400000000ULL
160 /* monty specific -- find the rest in ipath_6120.c */
161 #define INFINIPATH_HWE_MEMBISTFAILED 0x0040000000000000ULL
163 /* kr_hwdiagctrl bits */
164 #define INFINIPATH_DC_FORCETXEMEMPARITYERR_MASK 0xFULL
165 #define INFINIPATH_DC_FORCETXEMEMPARITYERR_SHIFT 40
166 #define INFINIPATH_DC_FORCERXEMEMPARITYERR_MASK 0x7FULL
167 #define INFINIPATH_DC_FORCERXEMEMPARITYERR_SHIFT 44
168 #define INFINIPATH_DC_FORCERXDSYNCMEMPARITYERR 0x0000000400000000ULL
169 #define INFINIPATH_DC_COUNTERDISABLE 0x1000000000000000ULL
170 #define INFINIPATH_DC_COUNTERWREN 0x2000000000000000ULL
171 #define INFINIPATH_DC_FORCEIBCBUSTOSPCPARITYERR 0x4000000000000000ULL
172 #define INFINIPATH_DC_FORCEIBCBUSFRSPCPARITYERR 0x8000000000000000ULL
174 /* kr_ibcctrl bits */
175 #define INFINIPATH_IBCC_FLOWCTRLPERIOD_MASK 0xFFULL
176 #define INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT 0
177 #define INFINIPATH_IBCC_FLOWCTRLWATERMARK_MASK 0xFFULL
178 #define INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT 8
179 #define INFINIPATH_IBCC_LINKINITCMD_MASK 0x3ULL
180 #define INFINIPATH_IBCC_LINKINITCMD_DISABLE 1
181 /* cycle through TS1/TS2 till OK */
182 #define INFINIPATH_IBCC_LINKINITCMD_POLL 2
183 /* wait for TS1, then go on */
184 #define INFINIPATH_IBCC_LINKINITCMD_SLEEP 3
185 #define INFINIPATH_IBCC_LINKINITCMD_SHIFT 16
186 #define INFINIPATH_IBCC_LINKCMD_MASK 0x3ULL
187 #define INFINIPATH_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */
188 #define INFINIPATH_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
189 #define INFINIPATH_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
190 #define INFINIPATH_IBCC_LINKCMD_SHIFT 18
191 #define INFINIPATH_IBCC_MAXPKTLEN_MASK 0x7FFULL
192 #define INFINIPATH_IBCC_MAXPKTLEN_SHIFT 20
193 #define INFINIPATH_IBCC_PHYERRTHRESHOLD_MASK 0xFULL
194 #define INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT 32
195 #define INFINIPATH_IBCC_OVERRUNTHRESHOLD_MASK 0xFULL
196 #define INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT 36
197 #define INFINIPATH_IBCC_CREDITSCALE_MASK 0x7ULL
198 #define INFINIPATH_IBCC_CREDITSCALE_SHIFT 40
199 #define INFINIPATH_IBCC_LOOPBACK 0x8000000000000000ULL
200 #define INFINIPATH_IBCC_LINKDOWNDEFAULTSTATE 0x4000000000000000ULL
202 /* kr_ibcstatus bits */
203 #define INFINIPATH_IBCS_LINKTRAININGSTATE_MASK 0xF
204 #define INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT 0
205 #define INFINIPATH_IBCS_LINKSTATE_MASK 0x7
206 #define INFINIPATH_IBCS_LINKSTATE_SHIFT 4
207 #define INFINIPATH_IBCS_TXREADY 0x40000000
208 #define INFINIPATH_IBCS_TXCREDITOK 0x80000000
209 /* link training states (shift by
210 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) */
211 #define INFINIPATH_IBCS_LT_STATE_DISABLED 0x00
212 #define INFINIPATH_IBCS_LT_STATE_LINKUP 0x01
213 #define INFINIPATH_IBCS_LT_STATE_POLLACTIVE 0x02
214 #define INFINIPATH_IBCS_LT_STATE_POLLQUIET 0x03
215 #define INFINIPATH_IBCS_LT_STATE_SLEEPDELAY 0x04
216 #define INFINIPATH_IBCS_LT_STATE_SLEEPQUIET 0x05
217 #define INFINIPATH_IBCS_LT_STATE_CFGDEBOUNCE 0x08
218 #define INFINIPATH_IBCS_LT_STATE_CFGRCVFCFG 0x09
219 #define INFINIPATH_IBCS_LT_STATE_CFGWAITRMT 0x0a
220 #define INFINIPATH_IBCS_LT_STATE_CFGIDLE 0x0b
221 #define INFINIPATH_IBCS_LT_STATE_RECOVERRETRAIN 0x0c
222 #define INFINIPATH_IBCS_LT_STATE_RECOVERWAITRMT 0x0e
223 #define INFINIPATH_IBCS_LT_STATE_RECOVERIDLE 0x0f
224 /* link state machine states (shift by INFINIPATH_IBCS_LINKSTATE_SHIFT) */
225 #define INFINIPATH_IBCS_L_STATE_DOWN 0x0
226 #define INFINIPATH_IBCS_L_STATE_INIT 0x1
227 #define INFINIPATH_IBCS_L_STATE_ARM 0x2
228 #define INFINIPATH_IBCS_L_STATE_ACTIVE 0x3
229 #define INFINIPATH_IBCS_L_STATE_ACT_DEFER 0x4
231 /* combination link status states that we use with some frequency */
232 #define IPATH_IBSTATE_MASK ((INFINIPATH_IBCS_LINKTRAININGSTATE_MASK \
233 << INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) | \
234 (INFINIPATH_IBCS_LINKSTATE_MASK \
235 <<INFINIPATH_IBCS_LINKSTATE_SHIFT))
236 #define IPATH_IBSTATE_INIT ((INFINIPATH_IBCS_L_STATE_INIT \
237 << INFINIPATH_IBCS_LINKSTATE_SHIFT) | \
238 (INFINIPATH_IBCS_LT_STATE_LINKUP \
239 <<INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT))
240 #define IPATH_IBSTATE_ARM ((INFINIPATH_IBCS_L_STATE_ARM \
241 << INFINIPATH_IBCS_LINKSTATE_SHIFT) | \
242 (INFINIPATH_IBCS_LT_STATE_LINKUP \
243 <<INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT))
244 #define IPATH_IBSTATE_ACTIVE ((INFINIPATH_IBCS_L_STATE_ACTIVE \
245 << INFINIPATH_IBCS_LINKSTATE_SHIFT) | \
246 (INFINIPATH_IBCS_LT_STATE_LINKUP \
247 <<INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT))
249 /* kr_extstatus bits */
250 #define INFINIPATH_EXTS_SERDESPLLLOCK 0x1
251 #define INFINIPATH_EXTS_GPIOIN_MASK 0xFFFFULL
252 #define INFINIPATH_EXTS_GPIOIN_SHIFT 48
254 /* kr_extctrl bits */
255 #define INFINIPATH_EXTC_GPIOINVERT_MASK 0xFFFFULL
256 #define INFINIPATH_EXTC_GPIOINVERT_SHIFT 32
257 #define INFINIPATH_EXTC_GPIOOE_MASK 0xFFFFULL
258 #define INFINIPATH_EXTC_GPIOOE_SHIFT 48
259 #define INFINIPATH_EXTC_SERDESENABLE 0x80000000ULL
260 #define INFINIPATH_EXTC_SERDESCONNECT 0x40000000ULL
261 #define INFINIPATH_EXTC_SERDESENTRUNKING 0x20000000ULL
262 #define INFINIPATH_EXTC_SERDESDISRXFIFO 0x10000000ULL
263 #define INFINIPATH_EXTC_SERDESENPLPBK1 0x08000000ULL
264 #define INFINIPATH_EXTC_SERDESENPLPBK2 0x04000000ULL
265 #define INFINIPATH_EXTC_SERDESENENCDEC 0x02000000ULL
266 #define INFINIPATH_EXTC_LED1SECPORT_ON 0x00000020ULL
267 #define INFINIPATH_EXTC_LED2SECPORT_ON 0x00000010ULL
268 #define INFINIPATH_EXTC_LED1PRIPORT_ON 0x00000008ULL
269 #define INFINIPATH_EXTC_LED2PRIPORT_ON 0x00000004ULL
270 #define INFINIPATH_EXTC_LEDGBLOK_ON 0x00000002ULL
271 #define INFINIPATH_EXTC_LEDGBLERR_OFF 0x00000001ULL
273 /* kr_partitionkey bits */
274 #define INFINIPATH_PKEY_SIZE 16
275 #define INFINIPATH_PKEY_MASK 0xFFFF
276 #define INFINIPATH_PKEY_DEFAULT_PKEY 0xFFFF
278 /* kr_serdesconfig0 bits */
279 #define INFINIPATH_SERDC0_RESET_MASK 0xfULL /* overal reset bits */
280 #define INFINIPATH_SERDC0_RESET_PLL 0x10000000ULL /* pll reset */
281 /* tx idle enables (per lane) */
282 #define INFINIPATH_SERDC0_TXIDLE 0xF000ULL
283 /* rx detect enables (per lane) */
284 #define INFINIPATH_SERDC0_RXDETECT_EN 0xF0000ULL
285 /* L1 Power down; use with RXDETECT, Otherwise not used on IB side */
286 #define INFINIPATH_SERDC0_L1PWR_DN 0xF0ULL
288 /* kr_xgxsconfig bits */
289 #define INFINIPATH_XGXS_RX_POL_SHIFT 19
290 #define INFINIPATH_XGXS_RX_POL_MASK 0xfULL
294 * IPATH_PIO_MAXIBHDR is the max IB header size allowed for in our
295 * PIO send buffers. This is well beyond anything currently
296 * defined in the InfiniBand spec.
298 #define IPATH_PIO_MAXIBHDR 128
300 typedef u64 ipath_err_t;
302 /* The following change with the type of device, so
303 * need to be part of the ipath_devdata struct, or
304 * we could have problems plugging in devices of
305 * different types (e.g. one HT, one PCIE)
306 * in one system, to be managed by one driver.
307 * On the other hand, this file is may also be included
308 * by other code, so leave the declarations here
309 * temporarily. Minor footprint issue if common-model
310 * linker used, none if C89+ linker used.
313 /* mask of defined bits for various registers */
314 extern u64 infinipath_i_bitsextant;
315 extern ipath_err_t infinipath_e_bitsextant, infinipath_hwe_bitsextant;
317 /* masks that are different in various chips, or only exist in some chips */
318 extern u32 infinipath_i_rcvavail_mask, infinipath_i_rcvurg_mask;
321 * These are the infinipath general register numbers (not offsets).
322 * The kernel registers are used directly, those beyond the kernel
323 * registers are calculated from one of the base registers. The use of
324 * an integer type doesn't allow type-checking as thorough as, say,
325 * an enum but allows for better hiding of chip differences.
327 typedef const u16 ipath_kreg, /* infinipath general registers */
328 ipath_creg, /* infinipath counter registers */
329 ipath_sreg; /* kernel-only, infinipath send registers */
332 * These are the chip registers common to all infinipath chips, and
333 * used both by the kernel and the diagnostics or other user code.
334 * They are all implemented such that 64 bit accesses work.
335 * Some implement no more than 32 bits. Because 64 bit reads
336 * require 2 HT cmds on opteron, we access those with 32 bit
337 * reads for efficiency (they are written as 64 bits, since
338 * the extra 32 bits are nearly free on writes, and it slightly reduces
339 * complexity). The rest are all accessed as 64 bits.
342 /* These are the 32 bit group */
343 ipath_kreg kr_control;
344 ipath_kreg kr_counterregbase;
345 ipath_kreg kr_intmask;
346 ipath_kreg kr_intstatus;
347 ipath_kreg kr_pagealign;
348 ipath_kreg kr_portcnt;
349 ipath_kreg kr_rcvtidbase;
350 ipath_kreg kr_rcvtidcnt;
351 ipath_kreg kr_rcvegrbase;
352 ipath_kreg kr_rcvegrcnt;
353 ipath_kreg kr_scratch;
354 ipath_kreg kr_sendctrl;
355 ipath_kreg kr_sendpiobufbase;
356 ipath_kreg kr_sendpiobufcnt;
357 ipath_kreg kr_sendpiosize;
358 ipath_kreg kr_sendregbase;
359 ipath_kreg kr_userregbase;
360 /* These are the 64 bit group */
361 ipath_kreg kr_debugport;
362 ipath_kreg kr_debugportselect;
363 ipath_kreg kr_errorclear;
364 ipath_kreg kr_errormask;
365 ipath_kreg kr_errorstatus;
366 ipath_kreg kr_extctrl;
367 ipath_kreg kr_extstatus;
368 ipath_kreg kr_gpio_clear;
369 ipath_kreg kr_gpio_mask;
370 ipath_kreg kr_gpio_out;
371 ipath_kreg kr_gpio_status;
372 ipath_kreg kr_hwdiagctrl;
373 ipath_kreg kr_hwerrclear;
374 ipath_kreg kr_hwerrmask;
375 ipath_kreg kr_hwerrstatus;
376 ipath_kreg kr_ibcctrl;
377 ipath_kreg kr_ibcstatus;
378 ipath_kreg kr_intblocked;
379 ipath_kreg kr_intclear;
380 ipath_kreg kr_interruptconfig;
382 ipath_kreg kr_partitionkey;
383 ipath_kreg kr_rcvbthqp;
384 ipath_kreg kr_rcvbufbase;
385 ipath_kreg kr_rcvbufsize;
386 ipath_kreg kr_rcvctrl;
387 ipath_kreg kr_rcvhdrcnt;
388 ipath_kreg kr_rcvhdrentsize;
389 ipath_kreg kr_rcvhdrsize;
390 ipath_kreg kr_rcvintmembase;
391 ipath_kreg kr_rcvintmemsize;
392 ipath_kreg kr_revision;
393 ipath_kreg kr_sendbuffererror;
394 ipath_kreg kr_sendpioavailaddr;
395 ipath_kreg kr_serdesconfig0;
396 ipath_kreg kr_serdesconfig1;
397 ipath_kreg kr_serdesstatus;
398 ipath_kreg kr_txintmembase;
399 ipath_kreg kr_txintmemsize;
400 ipath_kreg kr_xgxsconfig;
401 ipath_kreg kr_ibpllcfg;
402 /* use these two (and the following N ports) only with
403 * ipath_k*_kreg64_port(); not *kreg64() */
404 ipath_kreg kr_rcvhdraddr;
405 ipath_kreg kr_rcvhdrtailaddr;
407 /* remaining registers are not present on all types of infinipath
409 ipath_kreg kr_rcvpktledcnt;
410 ipath_kreg kr_pcierbuftestreg0;
411 ipath_kreg kr_pcierbuftestreg1;
412 ipath_kreg kr_pcieq0serdesconfig0;
413 ipath_kreg kr_pcieq0serdesconfig1;
414 ipath_kreg kr_pcieq0serdesstatus;
415 ipath_kreg kr_pcieq1serdesconfig0;
416 ipath_kreg kr_pcieq1serdesconfig1;
417 ipath_kreg kr_pcieq1serdesstatus;
421 ipath_creg cr_badformatcnt;
422 ipath_creg cr_erricrccnt;
423 ipath_creg cr_errlinkcnt;
424 ipath_creg cr_errlpcrccnt;
425 ipath_creg cr_errpkey;
426 ipath_creg cr_errrcvflowctrlcnt;
427 ipath_creg cr_err_rlencnt;
428 ipath_creg cr_errslencnt;
429 ipath_creg cr_errtidfull;
430 ipath_creg cr_errtidvalid;
431 ipath_creg cr_errvcrccnt;
432 ipath_creg cr_ibstatuschange;
433 ipath_creg cr_intcnt;
434 ipath_creg cr_invalidrlencnt;
435 ipath_creg cr_invalidslencnt;
436 ipath_creg cr_lbflowstallcnt;
437 ipath_creg cr_iblinkdowncnt;
438 ipath_creg cr_iblinkerrrecovcnt;
439 ipath_creg cr_ibsymbolerrcnt;
440 ipath_creg cr_pktrcvcnt;
441 ipath_creg cr_pktrcvflowctrlcnt;
442 ipath_creg cr_pktsendcnt;
443 ipath_creg cr_pktsendflowcnt;
444 ipath_creg cr_portovflcnt;
445 ipath_creg cr_rcvebpcnt;
446 ipath_creg cr_rcvovflcnt;
447 ipath_creg cr_rxdroppktcnt;
448 ipath_creg cr_senddropped;
449 ipath_creg cr_sendstallcnt;
450 ipath_creg cr_sendunderruncnt;
451 ipath_creg cr_unsupvlcnt;
452 ipath_creg cr_wordrcvcnt;
453 ipath_creg cr_wordsendcnt;
454 ipath_creg cr_vl15droppedpktcnt;
455 ipath_creg cr_rxotherlocalphyerrcnt;
456 ipath_creg cr_excessbufferovflcnt;
457 ipath_creg cr_locallinkintegrityerrcnt;
458 ipath_creg cr_rxvlerrcnt;
459 ipath_creg cr_rxdlidfltrcnt;
460 ipath_creg cr_psstat;
461 ipath_creg cr_psstart;
462 ipath_creg cr_psinterval;
463 ipath_creg cr_psrcvdatacount;
464 ipath_creg cr_psrcvpktscount;
465 ipath_creg cr_psxmitdatacount;
466 ipath_creg cr_psxmitpktscount;
467 ipath_creg cr_psxmitwaitcount;
470 #endif /* _IPATH_REGISTERS_H */