2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/spinlock.h>
35 #include <linux/idr.h>
36 #include <linux/pci.h>
38 #include <linux/delay.h>
39 #include <linux/netdevice.h>
40 #include <linux/vmalloc.h>
42 #include "ipath_kernel.h"
43 #include "ipath_verbs.h"
45 static void ipath_update_pio_bufs(struct ipath_devdata *);
47 const char *ipath_get_unit_name(int unit)
49 static char iname[16];
50 snprintf(iname, sizeof iname, "infinipath%u", unit);
54 #define DRIVER_LOAD_MSG "QLogic " IPATH_DRV_NAME " loaded: "
55 #define PFX IPATH_DRV_NAME ": "
58 * The size has to be longer than this string, so we can append
59 * board/chip information to it in the init code.
61 const char ib_ipath_version[] = IPATH_IDSTR "\n";
63 static struct idr unit_table;
64 DEFINE_SPINLOCK(ipath_devs_lock);
65 LIST_HEAD(ipath_dev_list);
67 wait_queue_head_t ipath_state_wait;
69 unsigned ipath_debug = __IPATH_INFO;
71 module_param_named(debug, ipath_debug, uint, S_IWUSR | S_IRUGO);
72 MODULE_PARM_DESC(debug, "mask for debug prints");
73 EXPORT_SYMBOL_GPL(ipath_debug);
75 unsigned ipath_mtu4096 = 1; /* max 4KB IB mtu by default, if supported */
76 module_param_named(mtu4096, ipath_mtu4096, uint, S_IRUGO);
77 MODULE_PARM_DESC(mtu4096, "enable MTU of 4096 bytes, if supported");
79 static unsigned ipath_hol_timeout_ms = 13000;
80 module_param_named(hol_timeout_ms, ipath_hol_timeout_ms, uint, S_IRUGO);
81 MODULE_PARM_DESC(hol_timeout_ms,
82 "duration of user app suspension after link failure");
84 unsigned ipath_linkrecovery = 1;
85 module_param_named(linkrecovery, ipath_linkrecovery, uint, S_IWUSR | S_IRUGO);
86 MODULE_PARM_DESC(linkrecovery, "enable workaround for link recovery issue");
88 MODULE_LICENSE("GPL");
89 MODULE_AUTHOR("QLogic <support@qlogic.com>");
90 MODULE_DESCRIPTION("QLogic InfiniPath driver");
93 * Table to translate the LINKTRAININGSTATE portion of
94 * IBCStatus to a human-readable form.
96 const char *ipath_ibcstatus_str[] = {
103 "LState6", /* unused */
104 "LState7", /* unused */
110 "CfgTxRevLane", /* unused before IBA7220 */
113 /* below were added for IBA7220 */
117 "CfgWaitCfgEnhanced",
122 "LTState18", "LTState19", "LTState1A", "LTState1B",
123 "LTState1C", "LTState1D", "LTState1E", "LTState1F"
126 static void __devexit ipath_remove_one(struct pci_dev *);
127 static int __devinit ipath_init_one(struct pci_dev *,
128 const struct pci_device_id *);
130 /* Only needed for registration, nothing else needs this info */
131 #define PCI_VENDOR_ID_PATHSCALE 0x1fc1
132 #define PCI_DEVICE_ID_INFINIPATH_HT 0xd
133 #define PCI_DEVICE_ID_INFINIPATH_PE800 0x10
135 /* Number of seconds before our card status check... */
136 #define STATUS_TIMEOUT 60
138 static const struct pci_device_id ipath_pci_tbl[] = {
139 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_HT) },
140 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_PE800) },
144 MODULE_DEVICE_TABLE(pci, ipath_pci_tbl);
146 static struct pci_driver ipath_driver = {
147 .name = IPATH_DRV_NAME,
148 .probe = ipath_init_one,
149 .remove = __devexit_p(ipath_remove_one),
150 .id_table = ipath_pci_tbl,
152 .groups = ipath_driver_attr_groups,
156 static inline void read_bars(struct ipath_devdata *dd, struct pci_dev *dev,
157 u32 *bar0, u32 *bar1)
161 ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
163 ipath_dev_err(dd, "failed to read bar0 before enable: "
166 ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, bar1);
168 ipath_dev_err(dd, "failed to read bar1 before enable: "
171 ipath_dbg("Read bar0 %x bar1 %x\n", *bar0, *bar1);
174 static void ipath_free_devdata(struct pci_dev *pdev,
175 struct ipath_devdata *dd)
179 pci_set_drvdata(pdev, NULL);
181 if (dd->ipath_unit != -1) {
182 spin_lock_irqsave(&ipath_devs_lock, flags);
183 idr_remove(&unit_table, dd->ipath_unit);
184 list_del(&dd->ipath_list);
185 spin_unlock_irqrestore(&ipath_devs_lock, flags);
190 static struct ipath_devdata *ipath_alloc_devdata(struct pci_dev *pdev)
193 struct ipath_devdata *dd;
196 if (!idr_pre_get(&unit_table, GFP_KERNEL)) {
197 dd = ERR_PTR(-ENOMEM);
201 dd = vmalloc(sizeof(*dd));
203 dd = ERR_PTR(-ENOMEM);
206 memset(dd, 0, sizeof(*dd));
209 spin_lock_irqsave(&ipath_devs_lock, flags);
211 ret = idr_get_new(&unit_table, dd, &dd->ipath_unit);
213 printk(KERN_ERR IPATH_DRV_NAME
214 ": Could not allocate unit ID: error %d\n", -ret);
215 ipath_free_devdata(pdev, dd);
221 pci_set_drvdata(pdev, dd);
223 list_add(&dd->ipath_list, &ipath_dev_list);
226 spin_unlock_irqrestore(&ipath_devs_lock, flags);
232 static inline struct ipath_devdata *__ipath_lookup(int unit)
234 return idr_find(&unit_table, unit);
237 struct ipath_devdata *ipath_lookup(int unit)
239 struct ipath_devdata *dd;
242 spin_lock_irqsave(&ipath_devs_lock, flags);
243 dd = __ipath_lookup(unit);
244 spin_unlock_irqrestore(&ipath_devs_lock, flags);
249 int ipath_count_units(int *npresentp, int *nupp, int *maxportsp)
251 int nunits, npresent, nup;
252 struct ipath_devdata *dd;
256 nunits = npresent = nup = maxports = 0;
258 spin_lock_irqsave(&ipath_devs_lock, flags);
260 list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
262 if ((dd->ipath_flags & IPATH_PRESENT) && dd->ipath_kregbase)
265 !(dd->ipath_flags & (IPATH_DISABLED | IPATH_LINKDOWN
268 if (dd->ipath_cfgports > maxports)
269 maxports = dd->ipath_cfgports;
272 spin_unlock_irqrestore(&ipath_devs_lock, flags);
275 *npresentp = npresent;
279 *maxportsp = maxports;
285 * These next two routines are placeholders in case we don't have per-arch
286 * code for controlling write combining. If explicit control of write
287 * combining is not available, performance will probably be awful.
290 int __attribute__((weak)) ipath_enable_wc(struct ipath_devdata *dd)
295 void __attribute__((weak)) ipath_disable_wc(struct ipath_devdata *dd)
300 * Perform a PIO buffer bandwidth write test, to verify proper system
301 * configuration. Even when all the setup calls work, occasionally
302 * BIOS or other issues can prevent write combining from working, or
303 * can cause other bandwidth problems to the chip.
305 * This test simply writes the same buffer over and over again, and
306 * measures close to the peak bandwidth to the chip (not testing
307 * data bandwidth to the wire). On chips that use an address-based
308 * trigger to send packets to the wire, this is easy. On chips that
309 * use a count to trigger, we want to make sure that the packet doesn't
310 * go out on the wire, or trigger flow control checks.
312 static void ipath_verify_pioperf(struct ipath_devdata *dd)
314 u32 pbnum, cnt, lcnt;
319 piobuf = ipath_getpiobuf(dd, 0, &pbnum);
321 dev_info(&dd->pcidev->dev,
322 "No PIObufs for checking perf, skipping\n");
327 * Enough to give us a reasonable test, less than piobuf size, and
328 * likely multiple of store buffer length.
334 dev_info(&dd->pcidev->dev,
335 "Couldn't get memory for checking PIO perf,"
340 preempt_disable(); /* we want reasonably accurate elapsed time */
341 msecs = 1 + jiffies_to_msecs(jiffies);
342 for (lcnt = 0; lcnt < 10000U; lcnt++) {
343 /* wait until we cross msec boundary */
344 if (jiffies_to_msecs(jiffies) >= msecs)
349 ipath_disable_armlaunch(dd);
352 * length 0, no dwords actually sent, and mark as VL15
353 * on chips where that may matter (due to IB flowcontrol)
355 if ((dd->ipath_flags & IPATH_HAS_PBC_CNT))
356 writeq(1UL << 63, piobuf);
362 * this is only roughly accurate, since even with preempt we
363 * still take interrupts that could take a while. Running for
364 * >= 5 msec seems to get us "close enough" to accurate values
366 msecs = jiffies_to_msecs(jiffies);
367 for (emsecs = lcnt = 0; emsecs <= 5UL; lcnt++) {
368 __iowrite32_copy(piobuf + 64, addr, cnt >> 2);
369 emsecs = jiffies_to_msecs(jiffies) - msecs;
372 /* 1 GiB/sec, slightly over IB SDR line rate */
373 if (lcnt < (emsecs * 1024U))
375 "Performance problem: bandwidth to PIO buffers is "
377 lcnt / (u32) emsecs);
379 ipath_dbg("PIO buffer bandwidth %u MiB/sec is OK\n",
380 lcnt / (u32) emsecs);
387 /* disarm piobuf, so it's available again */
388 ipath_disarm_piobufs(dd, pbnum, 1);
389 ipath_enable_armlaunch(dd);
392 static int __devinit ipath_init_one(struct pci_dev *pdev,
393 const struct pci_device_id *ent)
396 struct ipath_devdata *dd;
397 unsigned long long addr;
398 u32 bar0 = 0, bar1 = 0;
401 dd = ipath_alloc_devdata(pdev);
404 printk(KERN_ERR IPATH_DRV_NAME
405 ": Could not allocate devdata: error %d\n", -ret);
409 ipath_cdbg(VERBOSE, "initializing unit #%u\n", dd->ipath_unit);
411 ret = pci_enable_device(pdev);
413 /* This can happen iff:
415 * We did a chip reset, and then failed to reprogram the
416 * BAR, or the chip reset due to an internal error. We then
417 * unloaded the driver and reloaded it.
419 * Both reset cases set the BAR back to initial state. For
420 * the latter case, the AER sticky error bit at offset 0x718
421 * should be set, but the Linux kernel doesn't yet know
422 * about that, it appears. If the original BAR was retained
423 * in the kernel data structures, this may be OK.
425 ipath_dev_err(dd, "enable unit %d failed: error %d\n",
426 dd->ipath_unit, -ret);
429 addr = pci_resource_start(pdev, 0);
430 len = pci_resource_len(pdev, 0);
431 ipath_cdbg(VERBOSE, "regbase (0) %llx len %d irq %d, vend %x/%x "
432 "driver_data %lx\n", addr, len, pdev->irq, ent->vendor,
433 ent->device, ent->driver_data);
435 read_bars(dd, pdev, &bar0, &bar1);
437 if (!bar1 && !(bar0 & ~0xf)) {
439 dev_info(&pdev->dev, "BAR is 0 (probable RESET), "
440 "rewriting as %llx\n", addr);
441 ret = pci_write_config_dword(
442 pdev, PCI_BASE_ADDRESS_0, addr);
444 ipath_dev_err(dd, "rewrite of BAR0 "
445 "failed: err %d\n", -ret);
448 ret = pci_write_config_dword(
449 pdev, PCI_BASE_ADDRESS_1, addr >> 32);
451 ipath_dev_err(dd, "rewrite of BAR1 "
452 "failed: err %d\n", -ret);
456 ipath_dev_err(dd, "BAR is 0 (probable RESET), "
457 "not usable until reboot\n");
463 ret = pci_request_regions(pdev, IPATH_DRV_NAME);
465 dev_info(&pdev->dev, "pci_request_regions unit %u fails: "
466 "err %d\n", dd->ipath_unit, -ret);
470 ret = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
473 * if the 64 bit setup fails, try 32 bit. Some systems
474 * do not setup 64 bit maps on systems with 2GB or less
477 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
480 "Unable to set DMA mask for unit %u: %d\n",
481 dd->ipath_unit, ret);
485 ipath_dbg("No 64bit DMA mask, used 32 bit mask\n");
486 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
489 "Unable to set DMA consistent mask "
491 dd->ipath_unit, ret);
496 ret = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
499 "Unable to set DMA consistent mask "
501 dd->ipath_unit, ret);
504 pci_set_master(pdev);
507 * Save BARs to rewrite after device reset. Save all 64 bits of
510 dd->ipath_pcibar0 = addr;
511 dd->ipath_pcibar1 = addr >> 32;
512 dd->ipath_deviceid = ent->device; /* save for later use */
513 dd->ipath_vendorid = ent->vendor;
515 /* setup the chip-specific functions, as early as possible. */
516 switch (ent->device) {
517 case PCI_DEVICE_ID_INFINIPATH_HT:
519 ipath_init_iba6110_funcs(dd);
522 ipath_dev_err(dd, "QLogic HT device 0x%x cannot work if "
523 "CONFIG_HT_IRQ is not enabled\n", ent->device);
526 case PCI_DEVICE_ID_INFINIPATH_PE800:
527 #ifdef CONFIG_PCI_MSI
528 ipath_init_iba6120_funcs(dd);
531 ipath_dev_err(dd, "QLogic PCIE device 0x%x cannot work if "
532 "CONFIG_PCI_MSI is not enabled\n", ent->device);
536 ipath_dev_err(dd, "Found unknown QLogic deviceid 0x%x, "
537 "failing\n", ent->device);
541 for (j = 0; j < 6; j++) {
542 if (!pdev->resource[j].start)
544 ipath_cdbg(VERBOSE, "BAR %d start %llx, end %llx, len %llx\n",
545 j, (unsigned long long)pdev->resource[j].start,
546 (unsigned long long)pdev->resource[j].end,
547 (unsigned long long)pci_resource_len(pdev, j));
551 ipath_dev_err(dd, "No valid address in BAR 0!\n");
556 ret = pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
558 ipath_dev_err(dd, "Failed to read PCI revision ID unit "
559 "%u: err %d\n", dd->ipath_unit, -ret);
560 goto bail_regions; /* shouldn't ever happen */
562 dd->ipath_pcirev = rev;
564 #if defined(__powerpc__)
565 /* There isn't a generic way to specify writethrough mappings */
566 dd->ipath_kregbase = __ioremap(addr, len,
567 (_PAGE_NO_CACHE|_PAGE_WRITETHRU));
569 dd->ipath_kregbase = ioremap_nocache(addr, len);
572 if (!dd->ipath_kregbase) {
573 ipath_dbg("Unable to map io addr %llx to kvirt, failing\n",
578 dd->ipath_kregend = (u64 __iomem *)
579 ((void __iomem *)dd->ipath_kregbase + len);
580 dd->ipath_physaddr = addr; /* used for io_remap, etc. */
582 ipath_cdbg(VERBOSE, "mapped io addr %llx to kregbase %p\n",
583 addr, dd->ipath_kregbase);
585 if (dd->ipath_f_bus(dd, pdev))
586 ipath_dev_err(dd, "Failed to setup config space; "
587 "continuing anyway\n");
590 * set up our interrupt handler; IRQF_SHARED probably not needed,
591 * since MSI interrupts shouldn't be shared but won't hurt for now.
592 * check 0 irq after we return from chip-specific bus setup, since
593 * that can affect this due to setup
596 ipath_dev_err(dd, "irq is 0, BIOS error? Interrupts won't "
599 ret = request_irq(dd->ipath_irq, ipath_intr, IRQF_SHARED,
602 ipath_dev_err(dd, "Couldn't setup irq handler, "
603 "irq=%d: %d\n", dd->ipath_irq, ret);
608 ret = ipath_init_chip(dd, 0); /* do the chip-specific init */
612 ret = ipath_enable_wc(dd);
615 ipath_dev_err(dd, "Write combining not enabled "
616 "(err %d): performance may be poor\n",
621 ipath_verify_pioperf(dd);
623 ipath_device_create_group(&pdev->dev, dd);
624 ipathfs_add_device(dd);
627 ipath_register_ib_device(dd);
633 free_irq(pdev->irq, dd);
636 iounmap((volatile void __iomem *) dd->ipath_kregbase);
639 pci_release_regions(pdev);
642 pci_disable_device(pdev);
645 ipath_free_devdata(pdev, dd);
651 static void __devexit cleanup_device(struct ipath_devdata *dd)
655 if (*dd->ipath_statusp & IPATH_STATUS_CHIP_PRESENT) {
656 /* can't do anything more with chip; needs re-init */
657 *dd->ipath_statusp &= ~IPATH_STATUS_CHIP_PRESENT;
658 if (dd->ipath_kregbase) {
660 * if we haven't already cleaned up before these are
661 * to ensure any register reads/writes "fail" until
664 dd->ipath_kregbase = NULL;
665 dd->ipath_uregbase = 0;
666 dd->ipath_sregbase = 0;
667 dd->ipath_cregbase = 0;
668 dd->ipath_kregsize = 0;
670 ipath_disable_wc(dd);
673 if (dd->ipath_spectriggerhit)
674 dev_info(&dd->pcidev->dev, "%lu special trigger hits\n",
675 dd->ipath_spectriggerhit);
677 if (dd->ipath_pioavailregs_dma) {
678 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
679 (void *) dd->ipath_pioavailregs_dma,
680 dd->ipath_pioavailregs_phys);
681 dd->ipath_pioavailregs_dma = NULL;
683 if (dd->ipath_dummy_hdrq) {
684 dma_free_coherent(&dd->pcidev->dev,
685 dd->ipath_pd[0]->port_rcvhdrq_size,
686 dd->ipath_dummy_hdrq, dd->ipath_dummy_hdrq_phys);
687 dd->ipath_dummy_hdrq = NULL;
690 if (dd->ipath_pageshadow) {
691 struct page **tmpp = dd->ipath_pageshadow;
692 dma_addr_t *tmpd = dd->ipath_physshadow;
695 ipath_cdbg(VERBOSE, "Unlocking any expTID pages still "
697 for (port = 0; port < dd->ipath_cfgports; port++) {
698 int port_tidbase = port * dd->ipath_rcvtidcnt;
699 int maxtid = port_tidbase + dd->ipath_rcvtidcnt;
700 for (i = port_tidbase; i < maxtid; i++) {
703 pci_unmap_page(dd->pcidev, tmpd[i],
704 PAGE_SIZE, PCI_DMA_FROMDEVICE);
705 ipath_release_user_pages(&tmpp[i], 1);
711 ipath_stats.sps_pageunlocks += cnt;
712 ipath_cdbg(VERBOSE, "There were still %u expTID "
713 "entries locked\n", cnt);
715 if (ipath_stats.sps_pagelocks ||
716 ipath_stats.sps_pageunlocks)
717 ipath_cdbg(VERBOSE, "%llu pages locked, %llu "
718 "unlocked via ipath_m{un}lock\n",
720 ipath_stats.sps_pagelocks,
722 ipath_stats.sps_pageunlocks);
724 ipath_cdbg(VERBOSE, "Free shadow page tid array at %p\n",
725 dd->ipath_pageshadow);
726 tmpp = dd->ipath_pageshadow;
727 dd->ipath_pageshadow = NULL;
730 dd->ipath_egrtidbase = NULL;
734 * free any resources still in use (usually just kernel ports)
735 * at unload; we do for portcnt, not cfgports, because cfgports
736 * could have changed while we were loaded.
738 for (port = 0; port < dd->ipath_portcnt; port++) {
739 struct ipath_portdata *pd = dd->ipath_pd[port];
740 dd->ipath_pd[port] = NULL;
741 ipath_free_pddata(dd, pd);
745 * debuggability, in case some cleanup path tries to use it
751 static void __devexit ipath_remove_one(struct pci_dev *pdev)
753 struct ipath_devdata *dd = pci_get_drvdata(pdev);
755 ipath_cdbg(VERBOSE, "removing, pdev=%p, dd=%p\n", pdev, dd);
758 * disable the IB link early, to be sure no new packets arrive, which
759 * complicates the shutdown process
761 ipath_shutdown_device(dd);
763 flush_scheduled_work();
766 ipath_unregister_ib_device(dd->verbs_dev);
768 ipath_diag_remove(dd);
769 ipath_user_remove(dd);
770 ipathfs_remove_device(dd);
771 ipath_device_remove_group(&pdev->dev, dd);
773 ipath_cdbg(VERBOSE, "Releasing pci memory regions, dd %p, "
774 "unit %u\n", dd, (u32) dd->ipath_unit);
779 * turn off rcv, send, and interrupts for all ports, all drivers
780 * should also hard reset the chip here?
781 * free up port 0 (kernel) rcvhdr, egr bufs, and eventually tid bufs
782 * for all versions of the driver, if they were allocated
785 ipath_cdbg(VERBOSE, "unit %u free irq %d\n",
786 dd->ipath_unit, dd->ipath_irq);
787 dd->ipath_f_free_irq(dd);
789 ipath_dbg("irq is 0, not doing free_irq "
790 "for unit %u\n", dd->ipath_unit);
792 * we check for NULL here, because it's outside
793 * the kregbase check, and we need to call it
794 * after the free_irq. Thus it's possible that
795 * the function pointers were never initialized.
797 if (dd->ipath_f_cleanup)
798 /* clean up chip-specific stuff */
799 dd->ipath_f_cleanup(dd);
801 ipath_cdbg(VERBOSE, "Unmapping kregbase %p\n", dd->ipath_kregbase);
802 iounmap((volatile void __iomem *) dd->ipath_kregbase);
803 pci_release_regions(pdev);
804 ipath_cdbg(VERBOSE, "calling pci_disable_device\n");
805 pci_disable_device(pdev);
807 ipath_free_devdata(pdev, dd);
810 /* general driver use */
811 DEFINE_MUTEX(ipath_mutex);
813 static DEFINE_SPINLOCK(ipath_pioavail_lock);
816 * ipath_disarm_piobufs - cancel a range of PIO buffers
817 * @dd: the infinipath device
818 * @first: the first PIO buffer to cancel
819 * @cnt: the number of PIO buffers to cancel
821 * cancel a range of PIO buffers, used when they might be armed, but
822 * not triggered. Used at init to ensure buffer state, and also user
823 * process close, in case it died while writing to a PIO buffer
826 void ipath_disarm_piobufs(struct ipath_devdata *dd, unsigned first,
829 unsigned i, last = first + cnt;
832 ipath_cdbg(PKT, "disarm %u PIObufs first=%u\n", cnt, first);
833 for (i = first; i < last; i++) {
834 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
836 * The disarm-related bits are write-only, so it
837 * is ok to OR them in with our copy of sendctrl
838 * while we hold the lock.
840 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
841 dd->ipath_sendctrl | INFINIPATH_S_DISARM |
842 (i << INFINIPATH_S_DISARMPIOBUF_SHIFT));
843 /* can't disarm bufs back-to-back per iba7220 spec */
844 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
845 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
847 /* on some older chips, update may not happen after cancel */
848 ipath_force_pio_avail_update(dd);
852 * ipath_wait_linkstate - wait for an IB link state change to occur
853 * @dd: the infinipath device
854 * @state: the state to wait for
855 * @msecs: the number of milliseconds to wait
857 * wait up to msecs milliseconds for IB link state change to occur for
858 * now, take the easy polling route. Currently used only by
859 * ipath_set_linkstate. Returns 0 if state reached, otherwise
860 * -ETIMEDOUT state can have multiple states set, for any of several
863 int ipath_wait_linkstate(struct ipath_devdata *dd, u32 state, int msecs)
865 dd->ipath_state_wanted = state;
866 wait_event_interruptible_timeout(ipath_state_wait,
867 (dd->ipath_flags & state),
868 msecs_to_jiffies(msecs));
869 dd->ipath_state_wanted = 0;
871 if (!(dd->ipath_flags & state)) {
873 ipath_cdbg(VERBOSE, "Didn't reach linkstate %s within %u"
875 /* test INIT ahead of DOWN, both can be set */
876 (state & IPATH_LINKINIT) ? "INIT" :
877 ((state & IPATH_LINKDOWN) ? "DOWN" :
878 ((state & IPATH_LINKARMED) ? "ARM" : "ACTIVE")),
880 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
881 ipath_cdbg(VERBOSE, "ibcc=%llx ibcstatus=%llx (%s)\n",
882 (unsigned long long) ipath_read_kreg64(
883 dd, dd->ipath_kregs->kr_ibcctrl),
884 (unsigned long long) val,
885 ipath_ibcstatus_str[val & dd->ibcs_lts_mask]);
887 return (dd->ipath_flags & state) ? 0 : -ETIMEDOUT;
891 * Decode the error status into strings, deciding whether to always
892 * print * it or not depending on "normal packet errors" vs everything
893 * else. Return 1 if "real" errors, otherwise 0 if only packet
894 * errors, so caller can decide what to print with the string.
896 int ipath_decode_err(char *buf, size_t blen, ipath_err_t err)
900 if (err & INFINIPATH_E_PKTERRS) {
901 if (!(err & ~INFINIPATH_E_PKTERRS))
902 iserr = 0; // if only packet errors.
903 if (ipath_debug & __IPATH_ERRPKTDBG) {
904 if (err & INFINIPATH_E_REBP)
905 strlcat(buf, "EBP ", blen);
906 if (err & INFINIPATH_E_RVCRC)
907 strlcat(buf, "VCRC ", blen);
908 if (err & INFINIPATH_E_RICRC) {
909 strlcat(buf, "CRC ", blen);
910 // clear for check below, so only once
911 err &= INFINIPATH_E_RICRC;
913 if (err & INFINIPATH_E_RSHORTPKTLEN)
914 strlcat(buf, "rshortpktlen ", blen);
915 if (err & INFINIPATH_E_SDROPPEDDATAPKT)
916 strlcat(buf, "sdroppeddatapkt ", blen);
917 if (err & INFINIPATH_E_SPKTLEN)
918 strlcat(buf, "spktlen ", blen);
920 if ((err & INFINIPATH_E_RICRC) &&
921 !(err&(INFINIPATH_E_RVCRC|INFINIPATH_E_REBP)))
922 strlcat(buf, "CRC ", blen);
926 if (err & INFINIPATH_E_RHDRLEN)
927 strlcat(buf, "rhdrlen ", blen);
928 if (err & INFINIPATH_E_RBADTID)
929 strlcat(buf, "rbadtid ", blen);
930 if (err & INFINIPATH_E_RBADVERSION)
931 strlcat(buf, "rbadversion ", blen);
932 if (err & INFINIPATH_E_RHDR)
933 strlcat(buf, "rhdr ", blen);
934 if (err & INFINIPATH_E_SENDSPECIALTRIGGER)
935 strlcat(buf, "sendspecialtrigger ", blen);
936 if (err & INFINIPATH_E_RLONGPKTLEN)
937 strlcat(buf, "rlongpktlen ", blen);
938 if (err & INFINIPATH_E_RMAXPKTLEN)
939 strlcat(buf, "rmaxpktlen ", blen);
940 if (err & INFINIPATH_E_RMINPKTLEN)
941 strlcat(buf, "rminpktlen ", blen);
942 if (err & INFINIPATH_E_SMINPKTLEN)
943 strlcat(buf, "sminpktlen ", blen);
944 if (err & INFINIPATH_E_RFORMATERR)
945 strlcat(buf, "rformaterr ", blen);
946 if (err & INFINIPATH_E_RUNSUPVL)
947 strlcat(buf, "runsupvl ", blen);
948 if (err & INFINIPATH_E_RUNEXPCHAR)
949 strlcat(buf, "runexpchar ", blen);
950 if (err & INFINIPATH_E_RIBFLOW)
951 strlcat(buf, "ribflow ", blen);
952 if (err & INFINIPATH_E_SUNDERRUN)
953 strlcat(buf, "sunderrun ", blen);
954 if (err & INFINIPATH_E_SPIOARMLAUNCH)
955 strlcat(buf, "spioarmlaunch ", blen);
956 if (err & INFINIPATH_E_SUNEXPERRPKTNUM)
957 strlcat(buf, "sunexperrpktnum ", blen);
958 if (err & INFINIPATH_E_SDROPPEDSMPPKT)
959 strlcat(buf, "sdroppedsmppkt ", blen);
960 if (err & INFINIPATH_E_SMAXPKTLEN)
961 strlcat(buf, "smaxpktlen ", blen);
962 if (err & INFINIPATH_E_SUNSUPVL)
963 strlcat(buf, "sunsupVL ", blen);
964 if (err & INFINIPATH_E_INVALIDADDR)
965 strlcat(buf, "invalidaddr ", blen);
966 if (err & INFINIPATH_E_RRCVEGRFULL)
967 strlcat(buf, "rcvegrfull ", blen);
968 if (err & INFINIPATH_E_RRCVHDRFULL)
969 strlcat(buf, "rcvhdrfull ", blen);
970 if (err & INFINIPATH_E_IBSTATUSCHANGED)
971 strlcat(buf, "ibcstatuschg ", blen);
972 if (err & INFINIPATH_E_RIBLOSTLINK)
973 strlcat(buf, "riblostlink ", blen);
974 if (err & INFINIPATH_E_HARDWARE)
975 strlcat(buf, "hardware ", blen);
976 if (err & INFINIPATH_E_RESET)
977 strlcat(buf, "reset ", blen);
978 if (err & INFINIPATH_E_INVALIDEEPCMD)
979 strlcat(buf, "invalideepromcmd ", blen);
985 * get_rhf_errstring - decode RHF errors
986 * @err: the err number
987 * @msg: the output buffer
988 * @len: the length of the output buffer
990 * only used one place now, may want more later
992 static void get_rhf_errstring(u32 err, char *msg, size_t len)
994 /* if no errors, and so don't need to check what's first */
997 if (err & INFINIPATH_RHF_H_ICRCERR)
998 strlcat(msg, "icrcerr ", len);
999 if (err & INFINIPATH_RHF_H_VCRCERR)
1000 strlcat(msg, "vcrcerr ", len);
1001 if (err & INFINIPATH_RHF_H_PARITYERR)
1002 strlcat(msg, "parityerr ", len);
1003 if (err & INFINIPATH_RHF_H_LENERR)
1004 strlcat(msg, "lenerr ", len);
1005 if (err & INFINIPATH_RHF_H_MTUERR)
1006 strlcat(msg, "mtuerr ", len);
1007 if (err & INFINIPATH_RHF_H_IHDRERR)
1008 /* infinipath hdr checksum error */
1009 strlcat(msg, "ipathhdrerr ", len);
1010 if (err & INFINIPATH_RHF_H_TIDERR)
1011 strlcat(msg, "tiderr ", len);
1012 if (err & INFINIPATH_RHF_H_MKERR)
1013 /* bad port, offset, etc. */
1014 strlcat(msg, "invalid ipathhdr ", len);
1015 if (err & INFINIPATH_RHF_H_IBERR)
1016 strlcat(msg, "iberr ", len);
1017 if (err & INFINIPATH_RHF_L_SWA)
1018 strlcat(msg, "swA ", len);
1019 if (err & INFINIPATH_RHF_L_SWB)
1020 strlcat(msg, "swB ", len);
1024 * ipath_get_egrbuf - get an eager buffer
1025 * @dd: the infinipath device
1026 * @bufnum: the eager buffer to get
1028 * must only be called if ipath_pd[port] is known to be allocated
1030 static inline void *ipath_get_egrbuf(struct ipath_devdata *dd, u32 bufnum)
1032 return dd->ipath_port0_skbinfo ?
1033 (void *) dd->ipath_port0_skbinfo[bufnum].skb->data : NULL;
1037 * ipath_alloc_skb - allocate an skb and buffer with possible constraints
1038 * @dd: the infinipath device
1039 * @gfp_mask: the sk_buff SFP mask
1041 struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd,
1044 struct sk_buff *skb;
1048 * Only fully supported way to handle this is to allocate lots
1049 * extra, align as needed, and then do skb_reserve(). That wastes
1050 * a lot of memory... I'll have to hack this into infinipath_copy
1055 * We need 2 extra bytes for ipath_ether data sent in the
1056 * key header. In order to keep everything dword aligned,
1057 * we'll reserve 4 bytes.
1059 len = dd->ipath_ibmaxlen + 4;
1061 if (dd->ipath_flags & IPATH_4BYTE_TID) {
1062 /* We need a 2KB multiple alignment, and there is no way
1063 * to do it except to allocate extra and then skb_reserve
1064 * enough to bring it up to the right alignment.
1069 skb = __dev_alloc_skb(len, gfp_mask);
1071 ipath_dev_err(dd, "Failed to allocate skbuff, length %u\n",
1076 skb_reserve(skb, 4);
1078 if (dd->ipath_flags & IPATH_4BYTE_TID) {
1079 u32 una = (unsigned long)skb->data & 2047;
1081 skb_reserve(skb, 2048 - una);
1088 static void ipath_rcv_hdrerr(struct ipath_devdata *dd,
1093 struct ipath_message_header *hdr)
1097 get_rhf_errstring(eflags, emsg, sizeof emsg);
1098 ipath_cdbg(PKT, "RHFerrs %x hdrqtail=%x typ=%u "
1099 "tlen=%x opcode=%x egridx=%x: %s\n",
1101 ipath_hdrget_rcv_type(rhf_addr),
1102 ipath_hdrget_length_in_bytes(rhf_addr),
1103 be32_to_cpu(hdr->bth[0]) >> 24,
1106 /* Count local link integrity errors. */
1107 if (eflags & (INFINIPATH_RHF_H_ICRCERR | INFINIPATH_RHF_H_VCRCERR)) {
1108 u8 n = (dd->ipath_ibcctrl >>
1109 INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT) &
1110 INFINIPATH_IBCC_PHYERRTHRESHOLD_MASK;
1112 if (++dd->ipath_lli_counter > n) {
1113 dd->ipath_lli_counter = 0;
1114 dd->ipath_lli_errors++;
1120 * ipath_kreceive - receive a packet
1121 * @pd: the infinipath port
1123 * called from interrupt handler for errors or receive interrupt
1125 void ipath_kreceive(struct ipath_portdata *pd)
1127 struct ipath_devdata *dd = pd->port_dd;
1130 const u32 rsize = dd->ipath_rcvhdrentsize; /* words */
1131 const u32 maxcnt = dd->ipath_rcvhdrcnt * rsize; /* words */
1132 u32 etail = -1, l, hdrqtail;
1133 struct ipath_message_header *hdr;
1134 u32 eflags, i, etype, tlen, pkttot = 0, updegr = 0, reloop = 0;
1135 static u64 totcalls; /* stats, may eventually remove */
1139 rhf_addr = (__le32 *) pd->port_rcvhdrq + l + dd->ipath_rhf_offset;
1140 if (dd->ipath_flags & IPATH_NODMA_RTAIL) {
1141 u32 seq = ipath_hdrget_seq(rhf_addr);
1143 if (seq != pd->port_seq_cnt)
1147 hdrqtail = ipath_get_rcvhdrtail(pd);
1154 for (last = 0, i = 1; !last; i++) {
1155 hdr = dd->ipath_f_get_msgheader(dd, rhf_addr);
1156 eflags = ipath_hdrget_err_flags(rhf_addr);
1157 etype = ipath_hdrget_rcv_type(rhf_addr);
1159 tlen = ipath_hdrget_length_in_bytes(rhf_addr);
1161 if ((dd->ipath_flags & IPATH_NODMA_RTAIL) ?
1162 ipath_hdrget_use_egr_buf(rhf_addr) :
1163 (etype != RCVHQ_RCV_TYPE_EXPECTED)) {
1165 * It turns out that the chip uses an eager buffer
1166 * for all non-expected packets, whether it "needs"
1167 * one or not. So always get the index, but don't
1168 * set ebuf (so we try to copy data) unless the
1169 * length requires it.
1171 etail = ipath_hdrget_index(rhf_addr);
1173 if (tlen > sizeof(*hdr) ||
1174 etype == RCVHQ_RCV_TYPE_NON_KD)
1175 ebuf = ipath_get_egrbuf(dd, etail);
1179 * both tiderr and ipathhdrerr are set for all plain IB
1180 * packets; only ipathhdrerr should be set.
1183 if (etype != RCVHQ_RCV_TYPE_NON_KD &&
1184 etype != RCVHQ_RCV_TYPE_ERROR &&
1185 ipath_hdrget_ipath_ver(hdr->iph.ver_port_tid_offset) !=
1187 ipath_cdbg(PKT, "Bad InfiniPath protocol version "
1190 if (unlikely(eflags))
1191 ipath_rcv_hdrerr(dd, eflags, l, etail, rhf_addr, hdr);
1192 else if (etype == RCVHQ_RCV_TYPE_NON_KD) {
1193 ipath_ib_rcv(dd->verbs_dev, (u32 *)hdr, ebuf, tlen);
1194 if (dd->ipath_lli_counter)
1195 dd->ipath_lli_counter--;
1196 } else if (etype == RCVHQ_RCV_TYPE_EAGER) {
1197 u8 opcode = be32_to_cpu(hdr->bth[0]) >> 24;
1198 u32 qp = be32_to_cpu(hdr->bth[1]) & 0xffffff;
1199 ipath_cdbg(PKT, "typ %x, opcode %x (eager, "
1200 "qp=%x), len %x; ignored\n",
1201 etype, opcode, qp, tlen);
1203 else if (etype == RCVHQ_RCV_TYPE_EXPECTED)
1204 ipath_dbg("Bug: Expected TID, opcode %x; ignored\n",
1205 be32_to_cpu(hdr->bth[0]) >> 24);
1208 * error packet, type of error unknown.
1209 * Probably type 3, but we don't know, so don't
1210 * even try to print the opcode, etc.
1211 * Usually caused by a "bad packet", that has no
1212 * BTH, when the LRH says it should.
1214 ipath_cdbg(ERRPKT, "Error Pkt, but no eflags! egrbuf"
1215 " %x, len %x hdrq+%x rhf: %Lx\n",
1217 le64_to_cpu(*(__le64 *) rhf_addr));
1218 if (ipath_debug & __IPATH_ERRPKTDBG) {
1219 u32 j, *d, dw = rsize-2;
1220 if (rsize > (tlen>>2))
1223 printk(KERN_DEBUG "EPkt rcvhdr(%x dw):\n",
1225 for (j = 0; j < dw; j++)
1226 printk(KERN_DEBUG "%8x%s", d[j],
1227 (j%8) == 7 ? "\n" : " ");
1228 printk(KERN_DEBUG ".\n");
1234 rhf_addr = (__le32 *) pd->port_rcvhdrq +
1235 l + dd->ipath_rhf_offset;
1236 if (dd->ipath_flags & IPATH_NODMA_RTAIL) {
1237 u32 seq = ipath_hdrget_seq(rhf_addr);
1239 if (++pd->port_seq_cnt > 13)
1240 pd->port_seq_cnt = 1;
1241 if (seq != pd->port_seq_cnt)
1243 } else if (l == hdrqtail)
1246 * update head regs on last packet, and every 16 packets.
1247 * Reduce bus traffic, while still trying to prevent
1248 * rcvhdrq overflows, for when the queue is nearly full
1250 if (last || !(i & 0xf)) {
1253 /* request IBA6120 and 7220 interrupt only on last */
1255 lval |= dd->ipath_rhdrhead_intr_off;
1256 ipath_write_ureg(dd, ur_rcvhdrhead, lval,
1259 ipath_write_ureg(dd, ur_rcvegrindexhead,
1260 etail, pd->port_port);
1266 if (!dd->ipath_rhdrhead_intr_off && !reloop &&
1267 !(dd->ipath_flags & IPATH_NODMA_RTAIL)) {
1268 /* IBA6110 workaround; we can have a race clearing chip
1269 * interrupt with another interrupt about to be delivered,
1270 * and can clear it before it is delivered on the GPIO
1271 * workaround. By doing the extra check here for the
1272 * in-memory tail register updating while we were doing
1273 * earlier packets, we "almost" guarantee we have covered
1276 u32 hqtail = ipath_get_rcvhdrtail(pd);
1277 if (hqtail != hdrqtail) {
1279 reloop = 1; /* loop 1 extra time at most */
1288 if (pkttot > ipath_stats.sps_maxpkts_call)
1289 ipath_stats.sps_maxpkts_call = pkttot;
1290 ipath_stats.sps_port0pkts += pkttot;
1291 ipath_stats.sps_avgpkts_call =
1292 ipath_stats.sps_port0pkts / ++totcalls;
1298 * ipath_update_pio_bufs - update shadow copy of the PIO availability map
1299 * @dd: the infinipath device
1301 * called whenever our local copy indicates we have run out of send buffers
1302 * NOTE: This can be called from interrupt context by some code
1303 * and from non-interrupt context by ipath_getpiobuf().
1306 static void ipath_update_pio_bufs(struct ipath_devdata *dd)
1308 unsigned long flags;
1310 const unsigned piobregs = (unsigned)dd->ipath_pioavregs;
1312 /* If the generation (check) bits have changed, then we update the
1313 * busy bit for the corresponding PIO buffer. This algorithm will
1314 * modify positions to the value they already have in some cases
1315 * (i.e., no change), but it's faster than changing only the bits
1316 * that have changed.
1318 * We would like to do this atomicly, to avoid spinlocks in the
1319 * critical send path, but that's not really possible, given the
1320 * type of changes, and that this routine could be called on
1321 * multiple cpu's simultaneously, so we lock in this routine only,
1322 * to avoid conflicting updates; all we change is the shadow, and
1323 * it's a single 64 bit memory location, so by definition the update
1324 * is atomic in terms of what other cpu's can see in testing the
1325 * bits. The spin_lock overhead isn't too bad, since it only
1326 * happens when all buffers are in use, so only cpu overhead, not
1327 * latency or bandwidth is affected.
1329 if (!dd->ipath_pioavailregs_dma) {
1330 ipath_dbg("Update shadow pioavail, but regs_dma NULL!\n");
1333 if (ipath_debug & __IPATH_VERBDBG) {
1334 /* only if packet debug and verbose */
1335 volatile __le64 *dma = dd->ipath_pioavailregs_dma;
1336 unsigned long *shadow = dd->ipath_pioavailshadow;
1338 ipath_cdbg(PKT, "Refill avail, dma0=%llx shad0=%lx, "
1339 "d1=%llx s1=%lx, d2=%llx s2=%lx, d3=%llx "
1341 (unsigned long long) le64_to_cpu(dma[0]),
1343 (unsigned long long) le64_to_cpu(dma[1]),
1345 (unsigned long long) le64_to_cpu(dma[2]),
1347 (unsigned long long) le64_to_cpu(dma[3]),
1351 PKT, "2nd group, dma4=%llx shad4=%lx, "
1352 "d5=%llx s5=%lx, d6=%llx s6=%lx, "
1354 (unsigned long long) le64_to_cpu(dma[4]),
1356 (unsigned long long) le64_to_cpu(dma[5]),
1358 (unsigned long long) le64_to_cpu(dma[6]),
1360 (unsigned long long) le64_to_cpu(dma[7]),
1363 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1364 for (i = 0; i < piobregs; i++) {
1365 u64 pchbusy, pchg, piov, pnew;
1367 * Chip Errata: bug 6641; even and odd qwords>3 are swapped
1369 if (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS))
1370 piov = le64_to_cpu(dd->ipath_pioavailregs_dma[i ^ 1]);
1372 piov = le64_to_cpu(dd->ipath_pioavailregs_dma[i]);
1373 pchg = dd->ipath_pioavailkernel[i] &
1374 ~(dd->ipath_pioavailshadow[i] ^ piov);
1375 pchbusy = pchg << INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT;
1376 if (pchg && (pchbusy & dd->ipath_pioavailshadow[i])) {
1377 pnew = dd->ipath_pioavailshadow[i] & ~pchbusy;
1378 pnew |= piov & pchbusy;
1379 dd->ipath_pioavailshadow[i] = pnew;
1382 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1386 * ipath_setrcvhdrsize - set the receive header size
1387 * @dd: the infinipath device
1388 * @rhdrsize: the receive header size
1390 * called from user init code, and also layered driver init
1392 int ipath_setrcvhdrsize(struct ipath_devdata *dd, unsigned rhdrsize)
1396 if (dd->ipath_flags & IPATH_RCVHDRSZ_SET) {
1397 if (dd->ipath_rcvhdrsize != rhdrsize) {
1398 dev_info(&dd->pcidev->dev,
1399 "Error: can't set protocol header "
1400 "size %u, already %u\n",
1401 rhdrsize, dd->ipath_rcvhdrsize);
1404 ipath_cdbg(VERBOSE, "Reuse same protocol header "
1405 "size %u\n", dd->ipath_rcvhdrsize);
1406 } else if (rhdrsize > (dd->ipath_rcvhdrentsize -
1407 (sizeof(u64) / sizeof(u32)))) {
1408 ipath_dbg("Error: can't set protocol header size %u "
1409 "(> max %u)\n", rhdrsize,
1410 dd->ipath_rcvhdrentsize -
1411 (u32) (sizeof(u64) / sizeof(u32)));
1414 dd->ipath_flags |= IPATH_RCVHDRSZ_SET;
1415 dd->ipath_rcvhdrsize = rhdrsize;
1416 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
1417 dd->ipath_rcvhdrsize);
1418 ipath_cdbg(VERBOSE, "Set protocol header size to %u\n",
1419 dd->ipath_rcvhdrsize);
1425 * debugging code and stats updates if no pio buffers available.
1427 static noinline void no_pio_bufs(struct ipath_devdata *dd)
1429 unsigned long *shadow = dd->ipath_pioavailshadow;
1430 __le64 *dma = (__le64 *)dd->ipath_pioavailregs_dma;
1432 dd->ipath_upd_pio_shadow = 1;
1435 * not atomic, but if we lose a stat count in a while, that's OK
1437 ipath_stats.sps_nopiobufs++;
1438 if (!(++dd->ipath_consec_nopiobuf % 100000)) {
1439 ipath_dbg("%u pio sends with no bufavail; dmacopy: "
1440 "%llx %llx %llx %llx; shadow: %lx %lx %lx %lx\n",
1441 dd->ipath_consec_nopiobuf,
1442 (unsigned long long) le64_to_cpu(dma[0]),
1443 (unsigned long long) le64_to_cpu(dma[1]),
1444 (unsigned long long) le64_to_cpu(dma[2]),
1445 (unsigned long long) le64_to_cpu(dma[3]),
1446 shadow[0], shadow[1], shadow[2], shadow[3]);
1448 * 4 buffers per byte, 4 registers above, cover rest
1451 if ((dd->ipath_piobcnt2k + dd->ipath_piobcnt4k) >
1452 (sizeof(shadow[0]) * 4 * 4))
1453 ipath_dbg("2nd group: dmacopy: %llx %llx "
1454 "%llx %llx; shadow: %lx %lx %lx %lx\n",
1455 (unsigned long long)le64_to_cpu(dma[4]),
1456 (unsigned long long)le64_to_cpu(dma[5]),
1457 (unsigned long long)le64_to_cpu(dma[6]),
1458 (unsigned long long)le64_to_cpu(dma[7]),
1459 shadow[4], shadow[5], shadow[6],
1465 * common code for normal driver pio buffer allocation, and reserved
1468 * do appropriate marking as busy, etc.
1469 * returns buffer number if one found (>=0), negative number is error.
1471 static u32 __iomem *ipath_getpiobuf_range(struct ipath_devdata *dd,
1472 u32 *pbufnum, u32 first, u32 last, u32 firsti)
1474 int i, j, updated = 0;
1476 unsigned long flags;
1477 unsigned long *shadow = dd->ipath_pioavailshadow;
1480 piobcnt = last - first;
1481 if (dd->ipath_upd_pio_shadow) {
1483 * Minor optimization. If we had no buffers on last call,
1484 * start out by doing the update; continue and do scan even
1485 * if no buffers were updated, to be paranoid
1487 ipath_update_pio_bufs(dd);
1494 * while test_and_set_bit() is atomic, we do that and then the
1495 * change_bit(), and the pair is not. See if this is the cause
1496 * of the remaining armlaunch errors.
1498 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1499 for (j = 0; j < piobcnt; j++, i++) {
1502 if (__test_and_set_bit((2 * i) + 1, shadow))
1504 /* flip generation bit */
1505 __change_bit(2 * i, shadow);
1508 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1513 * first time through; shadow exhausted, but may be
1514 * buffers available, try an update and then rescan.
1516 ipath_update_pio_bufs(dd);
1520 } else if (updated == 1 && piobcnt <=
1521 ((dd->ipath_sendctrl
1522 >> INFINIPATH_S_UPDTHRESH_SHIFT) &
1523 INFINIPATH_S_UPDTHRESH_MASK)) {
1525 * for chips supporting and using the update
1526 * threshold we need to force an update of the
1527 * in-memory copy if the count is less than the
1528 * thershold, then check one more time.
1530 ipath_force_pio_avail_update(dd);
1531 ipath_update_pio_bufs(dd);
1540 if (i < dd->ipath_piobcnt2k)
1541 buf = (u32 __iomem *) (dd->ipath_pio2kbase +
1542 i * dd->ipath_palign);
1544 buf = (u32 __iomem *)
1545 (dd->ipath_pio4kbase +
1546 (i - dd->ipath_piobcnt2k) * dd->ipath_4kalign);
1555 * ipath_getpiobuf - find an available pio buffer
1556 * @dd: the infinipath device
1557 * @plen: the size of the PIO buffer needed in 32-bit words
1558 * @pbufnum: the buffer number is placed here
1560 u32 __iomem *ipath_getpiobuf(struct ipath_devdata *dd, u32 plen, u32 *pbufnum)
1566 if (plen + 1 >= IPATH_SMALLBUF_DWORDS) {
1567 first = dd->ipath_piobcnt2k;
1568 lasti = dd->ipath_lastpioindexl;
1571 lasti = dd->ipath_lastpioindex;
1573 nbufs = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
1574 buf = ipath_getpiobuf_range(dd, &pnum, first, nbufs, lasti);
1578 * Set next starting place. It's just an optimization,
1579 * it doesn't matter who wins on this, so no locking
1581 if (plen + 1 >= IPATH_SMALLBUF_DWORDS)
1582 dd->ipath_lastpioindexl = pnum + 1;
1584 dd->ipath_lastpioindex = pnum + 1;
1585 if (dd->ipath_upd_pio_shadow)
1586 dd->ipath_upd_pio_shadow = 0;
1587 if (dd->ipath_consec_nopiobuf)
1588 dd->ipath_consec_nopiobuf = 0;
1589 ipath_cdbg(VERBOSE, "Return piobuf%u %uk @ %p\n",
1590 pnum, (pnum < dd->ipath_piobcnt2k) ? 2 : 4, buf);
1599 * ipath_chg_pioavailkernel - change which send buffers are available for kernel
1600 * @dd: the infinipath device
1601 * @start: the starting send buffer number
1602 * @len: the number of send buffers
1603 * @avail: true if the buffers are available for kernel use, false otherwise
1605 void ipath_chg_pioavailkernel(struct ipath_devdata *dd, unsigned start,
1606 unsigned len, int avail)
1608 unsigned long flags;
1611 /* There are two bits per send buffer (busy and generation) */
1616 /* Set or clear the generation bits. */
1617 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1618 while (start < end) {
1620 __clear_bit(start + INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT,
1621 dd->ipath_pioavailshadow);
1622 __set_bit(start, dd->ipath_pioavailkernel);
1624 __set_bit(start + INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT,
1625 dd->ipath_pioavailshadow);
1626 __clear_bit(start, dd->ipath_pioavailkernel);
1630 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1634 * ipath_create_rcvhdrq - create a receive header queue
1635 * @dd: the infinipath device
1636 * @pd: the port data
1638 * this must be contiguous memory (from an i/o perspective), and must be
1639 * DMA'able (which means for some systems, it will go through an IOMMU,
1640 * or be forced into a low address range).
1642 int ipath_create_rcvhdrq(struct ipath_devdata *dd,
1643 struct ipath_portdata *pd)
1647 if (!pd->port_rcvhdrq) {
1648 dma_addr_t phys_hdrqtail;
1649 gfp_t gfp_flags = GFP_USER | __GFP_COMP;
1650 int amt = ALIGN(dd->ipath_rcvhdrcnt * dd->ipath_rcvhdrentsize *
1651 sizeof(u32), PAGE_SIZE);
1653 pd->port_rcvhdrq = dma_alloc_coherent(
1654 &dd->pcidev->dev, amt, &pd->port_rcvhdrq_phys,
1657 if (!pd->port_rcvhdrq) {
1658 ipath_dev_err(dd, "attempt to allocate %d bytes "
1659 "for port %u rcvhdrq failed\n",
1660 amt, pd->port_port);
1665 if (!(dd->ipath_flags & IPATH_NODMA_RTAIL)) {
1666 pd->port_rcvhdrtail_kvaddr = dma_alloc_coherent(
1667 &dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail,
1669 if (!pd->port_rcvhdrtail_kvaddr) {
1670 ipath_dev_err(dd, "attempt to allocate 1 page "
1671 "for port %u rcvhdrqtailaddr "
1672 "failed\n", pd->port_port);
1674 dma_free_coherent(&dd->pcidev->dev, amt,
1676 pd->port_rcvhdrq_phys);
1677 pd->port_rcvhdrq = NULL;
1680 pd->port_rcvhdrqtailaddr_phys = phys_hdrqtail;
1681 ipath_cdbg(VERBOSE, "port %d hdrtailaddr, %llx "
1682 "physical\n", pd->port_port,
1683 (unsigned long long) phys_hdrqtail);
1686 pd->port_rcvhdrq_size = amt;
1688 ipath_cdbg(VERBOSE, "%d pages at %p (phys %lx) size=%lu "
1689 "for port %u rcvhdr Q\n",
1690 amt >> PAGE_SHIFT, pd->port_rcvhdrq,
1691 (unsigned long) pd->port_rcvhdrq_phys,
1692 (unsigned long) pd->port_rcvhdrq_size,
1696 ipath_cdbg(VERBOSE, "reuse port %d rcvhdrq @%p %llx phys; "
1697 "hdrtailaddr@%p %llx physical\n",
1698 pd->port_port, pd->port_rcvhdrq,
1699 (unsigned long long) pd->port_rcvhdrq_phys,
1700 pd->port_rcvhdrtail_kvaddr, (unsigned long long)
1701 pd->port_rcvhdrqtailaddr_phys);
1703 /* clear for security and sanity on each use */
1704 memset(pd->port_rcvhdrq, 0, pd->port_rcvhdrq_size);
1705 if (pd->port_rcvhdrtail_kvaddr)
1706 memset(pd->port_rcvhdrtail_kvaddr, 0, PAGE_SIZE);
1709 * tell chip each time we init it, even if we are re-using previous
1710 * memory (we zero the register at process close)
1712 ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdrtailaddr,
1713 pd->port_port, pd->port_rcvhdrqtailaddr_phys);
1714 ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdraddr,
1715 pd->port_port, pd->port_rcvhdrq_phys);
1723 * Flush all sends that might be in the ready to send state, as well as any
1724 * that are in the process of being sent. Used whenever we need to be
1725 * sure the send side is idle. Cleans up all buffer state by canceling
1726 * all pio buffers, and issuing an abort, which cleans up anything in the
1727 * launch fifo. The cancel is superfluous on some chip versions, but
1728 * it's safer to always do it.
1729 * PIOAvail bits are updated by the chip as if normal send had happened.
1731 void ipath_cancel_sends(struct ipath_devdata *dd, int restore_sendctrl)
1733 if (dd->ipath_flags & IPATH_IB_AUTONEG_INPROG) {
1734 ipath_cdbg(VERBOSE, "Ignore while in autonegotiation\n");
1737 ipath_dbg("Cancelling all in-progress send buffers\n");
1739 /* skip armlaunch errs for a while */
1740 dd->ipath_lastcancel = jiffies + HZ / 2;
1743 * the abort bit is auto-clearing. We read scratch to be sure
1744 * that cancels and the abort have taken effect in the chip.
1746 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1747 INFINIPATH_S_ABORT);
1748 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1749 ipath_disarm_piobufs(dd, 0,
1750 (unsigned)(dd->ipath_piobcnt2k + dd->ipath_piobcnt4k));
1751 if (restore_sendctrl) /* else done by caller later */
1752 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1753 dd->ipath_sendctrl);
1755 /* and again, be sure all have hit the chip */
1756 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1761 * Force an update of in-memory copy of the pioavail registers, when
1762 * needed for any of a variety of reasons. We read the scratch register
1763 * to make it highly likely that the update will have happened by the
1764 * time we return. If already off (as in cancel_sends above), this
1765 * routine is a nop, on the assumption that the caller will "do the
1768 void ipath_force_pio_avail_update(struct ipath_devdata *dd)
1770 unsigned long flags;
1772 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1773 if (dd->ipath_sendctrl & INFINIPATH_S_PIOBUFAVAILUPD) {
1774 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1775 dd->ipath_sendctrl & ~INFINIPATH_S_PIOBUFAVAILUPD);
1776 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1777 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1778 dd->ipath_sendctrl);
1779 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1781 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1784 static void ipath_set_ib_lstate(struct ipath_devdata *dd, int linkcmd,
1788 static const char *what[4] = {
1790 [INFINIPATH_IBCC_LINKCMD_DOWN] = "DOWN",
1791 [INFINIPATH_IBCC_LINKCMD_ARMED] = "ARMED",
1792 [INFINIPATH_IBCC_LINKCMD_ACTIVE] = "ACTIVE"
1795 if (linitcmd == INFINIPATH_IBCC_LINKINITCMD_DISABLE) {
1797 * If we are told to disable, note that so link-recovery
1798 * code does not attempt to bring us back up.
1801 dd->ipath_flags |= IPATH_IB_LINK_DISABLED;
1803 } else if (linitcmd) {
1805 * Any other linkinitcmd will lead to LINKDOWN and then
1806 * to INIT (if all is well), so clear flag to let
1807 * link-recovery code attempt to bring us back up.
1810 dd->ipath_flags &= ~IPATH_IB_LINK_DISABLED;
1814 mod_wd = (linkcmd << dd->ibcc_lc_shift) |
1815 (linitcmd << INFINIPATH_IBCC_LINKINITCMD_SHIFT);
1817 "Moving unit %u to %s (initcmd=0x%x), current ltstate is %s\n",
1818 dd->ipath_unit, what[linkcmd], linitcmd,
1819 ipath_ibcstatus_str[ipath_ib_linktrstate(dd,
1820 ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus))]);
1822 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
1823 dd->ipath_ibcctrl | mod_wd);
1824 /* read from chip so write is flushed */
1825 (void) ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
1828 int ipath_set_linkstate(struct ipath_devdata *dd, u8 newstate)
1834 case IPATH_IB_LINKDOWN_ONLY:
1835 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN, 0);
1840 case IPATH_IB_LINKDOWN:
1841 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN,
1842 INFINIPATH_IBCC_LINKINITCMD_POLL);
1847 case IPATH_IB_LINKDOWN_SLEEP:
1848 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN,
1849 INFINIPATH_IBCC_LINKINITCMD_SLEEP);
1854 case IPATH_IB_LINKDOWN_DISABLE:
1855 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN,
1856 INFINIPATH_IBCC_LINKINITCMD_DISABLE);
1861 case IPATH_IB_LINKARM:
1862 if (dd->ipath_flags & IPATH_LINKARMED) {
1866 if (!(dd->ipath_flags &
1867 (IPATH_LINKINIT | IPATH_LINKACTIVE))) {
1871 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ARMED, 0);
1874 * Since the port can transition to ACTIVE by receiving
1875 * a non VL 15 packet, wait for either state.
1877 lstate = IPATH_LINKARMED | IPATH_LINKACTIVE;
1880 case IPATH_IB_LINKACTIVE:
1881 if (dd->ipath_flags & IPATH_LINKACTIVE) {
1885 if (!(dd->ipath_flags & IPATH_LINKARMED)) {
1889 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ACTIVE, 0);
1890 lstate = IPATH_LINKACTIVE;
1893 case IPATH_IB_LINK_LOOPBACK:
1894 dev_info(&dd->pcidev->dev, "Enabling IB local loopback\n");
1895 dd->ipath_ibcctrl |= INFINIPATH_IBCC_LOOPBACK;
1896 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
1899 /* turn heartbeat off, as it causes loopback to fail */
1900 dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
1901 IPATH_IB_HRTBT_OFF);
1906 case IPATH_IB_LINK_EXTERNAL:
1907 dev_info(&dd->pcidev->dev,
1908 "Disabling IB local loopback (normal)\n");
1909 dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
1911 dd->ipath_ibcctrl &= ~INFINIPATH_IBCC_LOOPBACK;
1912 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
1919 * Heartbeat can be explicitly enabled by the user via
1920 * "hrtbt_enable" "file", and if disabled, trying to enable here
1921 * will have no effect. Implicit changes (heartbeat off when
1922 * loopback on, and vice versa) are included to ease testing.
1924 case IPATH_IB_LINK_HRTBT:
1925 ret = dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
1929 case IPATH_IB_LINK_NO_HRTBT:
1930 ret = dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
1931 IPATH_IB_HRTBT_OFF);
1935 ipath_dbg("Invalid linkstate 0x%x requested\n", newstate);
1939 ret = ipath_wait_linkstate(dd, lstate, 2000);
1946 * ipath_set_mtu - set the MTU
1947 * @dd: the infinipath device
1950 * we can handle "any" incoming size, the issue here is whether we
1951 * need to restrict our outgoing size. For now, we don't do any
1952 * sanity checking on this, and we don't deal with what happens to
1953 * programs that are already running when the size changes.
1954 * NOTE: changing the MTU will usually cause the IBC to go back to
1955 * link initialize (IPATH_IBSTATE_INIT) state...
1957 int ipath_set_mtu(struct ipath_devdata *dd, u16 arg)
1964 * mtu is IB data payload max. It's the largest power of 2 less
1965 * than piosize (or even larger, since it only really controls the
1966 * largest we can receive; we can send the max of the mtu and
1967 * piosize). We check that it's one of the valid IB sizes.
1969 if (arg != 256 && arg != 512 && arg != 1024 && arg != 2048 &&
1970 (arg != 4096 || !ipath_mtu4096)) {
1971 ipath_dbg("Trying to set invalid mtu %u, failing\n", arg);
1975 if (dd->ipath_ibmtu == arg) {
1976 ret = 0; /* same as current */
1980 piosize = dd->ipath_ibmaxlen;
1981 dd->ipath_ibmtu = arg;
1983 if (arg >= (piosize - IPATH_PIO_MAXIBHDR)) {
1984 /* Only if it's not the initial value (or reset to it) */
1985 if (piosize != dd->ipath_init_ibmaxlen) {
1986 if (arg > piosize && arg <= dd->ipath_init_ibmaxlen)
1987 piosize = dd->ipath_init_ibmaxlen;
1988 dd->ipath_ibmaxlen = piosize;
1991 } else if ((arg + IPATH_PIO_MAXIBHDR) != dd->ipath_ibmaxlen) {
1992 piosize = arg + IPATH_PIO_MAXIBHDR;
1993 ipath_cdbg(VERBOSE, "ibmaxlen was 0x%x, setting to 0x%x "
1994 "(mtu 0x%x)\n", dd->ipath_ibmaxlen, piosize,
1996 dd->ipath_ibmaxlen = piosize;
2001 u64 ibc = dd->ipath_ibcctrl, ibdw;
2003 * update our housekeeping variables, and set IBC max
2004 * size, same as init code; max IBC is max we allow in
2005 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
2007 dd->ipath_ibmaxlen = piosize - 2 * sizeof(u32);
2008 ibdw = (dd->ipath_ibmaxlen >> 2) + 1;
2009 ibc &= ~(INFINIPATH_IBCC_MAXPKTLEN_MASK <<
2010 dd->ibcc_mpl_shift);
2011 ibc |= ibdw << dd->ibcc_mpl_shift;
2012 dd->ipath_ibcctrl = ibc;
2013 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
2015 dd->ipath_f_tidtemplate(dd);
2024 int ipath_set_lid(struct ipath_devdata *dd, u32 lid, u8 lmc)
2026 dd->ipath_lid = lid;
2027 dd->ipath_lmc = lmc;
2029 dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_LIDLMC, lid |
2030 (~((1U << lmc) - 1)) << 16);
2032 dev_info(&dd->pcidev->dev, "We got a lid: 0x%x\n", lid);
2039 * ipath_write_kreg_port - write a device's per-port 64-bit kernel register
2040 * @dd: the infinipath device
2041 * @regno: the register number to write
2042 * @port: the port containing the register
2043 * @value: the value to write
2045 * Registers that vary with the chip implementation constants (port)
2048 void ipath_write_kreg_port(const struct ipath_devdata *dd, ipath_kreg regno,
2049 unsigned port, u64 value)
2053 if (port < dd->ipath_portcnt &&
2054 (regno == dd->ipath_kregs->kr_rcvhdraddr ||
2055 regno == dd->ipath_kregs->kr_rcvhdrtailaddr))
2056 where = regno + port;
2060 ipath_write_kreg(dd, where, value);
2064 * Following deal with the "obviously simple" task of overriding the state
2065 * of the LEDS, which normally indicate link physical and logical status.
2066 * The complications arise in dealing with different hardware mappings
2067 * and the board-dependent routine being called from interrupts.
2068 * and then there's the requirement to _flash_ them.
2070 #define LED_OVER_FREQ_SHIFT 8
2071 #define LED_OVER_FREQ_MASK (0xFF<<LED_OVER_FREQ_SHIFT)
2072 /* Below is "non-zero" to force override, but both actual LEDs are off */
2073 #define LED_OVER_BOTH_OFF (8)
2075 static void ipath_run_led_override(unsigned long opaque)
2077 struct ipath_devdata *dd = (struct ipath_devdata *)opaque;
2080 u64 lstate, ltstate, val;
2082 if (!(dd->ipath_flags & IPATH_INITTED))
2085 pidx = dd->ipath_led_override_phase++ & 1;
2086 dd->ipath_led_override = dd->ipath_led_override_vals[pidx];
2087 timeoff = dd->ipath_led_override_timeoff;
2090 * below potentially restores the LED values per current status,
2091 * should also possibly setup the traffic-blink register,
2092 * but leave that to per-chip functions.
2094 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
2095 ltstate = (val >> INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) &
2097 lstate = (val >> dd->ibcs_ls_shift) & INFINIPATH_IBCS_LINKSTATE_MASK;
2099 dd->ipath_f_setextled(dd, lstate, ltstate);
2100 mod_timer(&dd->ipath_led_override_timer, jiffies + timeoff);
2103 void ipath_set_led_override(struct ipath_devdata *dd, unsigned int val)
2107 if (!(dd->ipath_flags & IPATH_INITTED))
2110 /* First check if we are blinking. If not, use 1HZ polling */
2112 freq = (val & LED_OVER_FREQ_MASK) >> LED_OVER_FREQ_SHIFT;
2115 /* For blink, set each phase from one nybble of val */
2116 dd->ipath_led_override_vals[0] = val & 0xF;
2117 dd->ipath_led_override_vals[1] = (val >> 4) & 0xF;
2118 timeoff = (HZ << 4)/freq;
2120 /* Non-blink set both phases the same. */
2121 dd->ipath_led_override_vals[0] = val & 0xF;
2122 dd->ipath_led_override_vals[1] = val & 0xF;
2124 dd->ipath_led_override_timeoff = timeoff;
2127 * If the timer has not already been started, do so. Use a "quick"
2128 * timeout so the function will be called soon, to look at our request.
2130 if (atomic_inc_return(&dd->ipath_led_override_timer_active) == 1) {
2131 /* Need to start timer */
2132 init_timer(&dd->ipath_led_override_timer);
2133 dd->ipath_led_override_timer.function =
2134 ipath_run_led_override;
2135 dd->ipath_led_override_timer.data = (unsigned long) dd;
2136 dd->ipath_led_override_timer.expires = jiffies + 1;
2137 add_timer(&dd->ipath_led_override_timer);
2139 atomic_dec(&dd->ipath_led_override_timer_active);
2143 * ipath_shutdown_device - shut down a device
2144 * @dd: the infinipath device
2146 * This is called to make the device quiet when we are about to
2147 * unload the driver, and also when the device is administratively
2148 * disabled. It does not free any data structures.
2149 * Everything it does has to be setup again by ipath_init_chip(dd,1)
2151 void ipath_shutdown_device(struct ipath_devdata *dd)
2153 unsigned long flags;
2155 ipath_dbg("Shutting down the device\n");
2157 ipath_hol_up(dd); /* make sure user processes aren't suspended */
2159 dd->ipath_flags |= IPATH_LINKUNK;
2160 dd->ipath_flags &= ~(IPATH_INITTED | IPATH_LINKDOWN |
2161 IPATH_LINKINIT | IPATH_LINKARMED |
2163 *dd->ipath_statusp &= ~(IPATH_STATUS_IB_CONF |
2164 IPATH_STATUS_IB_READY);
2166 /* mask interrupts, but not errors */
2167 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
2169 dd->ipath_rcvctrl = 0;
2170 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
2174 * gracefully stop all sends allowing any in progress to trickle out
2177 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
2178 dd->ipath_sendctrl = 0;
2179 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
2181 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
2182 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
2185 * enough for anything that's going to trickle out to have actually
2190 ipath_set_ib_lstate(dd, 0, INFINIPATH_IBCC_LINKINITCMD_DISABLE);
2191 ipath_cancel_sends(dd, 0);
2193 signal_ib_event(dd, IB_EVENT_PORT_ERR);
2196 dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
2197 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
2198 dd->ipath_control | INFINIPATH_C_FREEZEMODE);
2201 * clear SerdesEnable and turn the leds off; do this here because
2202 * we are unloading, so don't count on interrupts to move along
2203 * Turn the LEDs off explictly for the same reason.
2205 dd->ipath_f_quiet_serdes(dd);
2207 /* stop all the timers that might still be running */
2208 del_timer_sync(&dd->ipath_hol_timer);
2209 if (dd->ipath_stats_timer_active) {
2210 del_timer_sync(&dd->ipath_stats_timer);
2211 dd->ipath_stats_timer_active = 0;
2213 if (dd->ipath_intrchk_timer.data) {
2214 del_timer_sync(&dd->ipath_intrchk_timer);
2215 dd->ipath_intrchk_timer.data = 0;
2219 * clear all interrupts and errors, so that the next time the driver
2220 * is loaded or device is enabled, we know that whatever is set
2221 * happened while we were unloaded
2223 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
2224 ~0ULL & ~INFINIPATH_HWE_MEMBISTFAILED);
2225 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
2226 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
2228 ipath_cdbg(VERBOSE, "Flush time and errors to EEPROM\n");
2229 ipath_update_eeprom_log(dd);
2233 * ipath_free_pddata - free a port's allocated data
2234 * @dd: the infinipath device
2235 * @pd: the portdata structure
2237 * free up any allocated data for a port
2238 * This should not touch anything that would affect a simultaneous
2239 * re-allocation of port data, because it is called after ipath_mutex
2240 * is released (and can be called from reinit as well).
2241 * It should never change any chip state, or global driver state.
2242 * (The only exception to global state is freeing the port0 port0_skbs.)
2244 void ipath_free_pddata(struct ipath_devdata *dd, struct ipath_portdata *pd)
2249 if (pd->port_rcvhdrq) {
2250 ipath_cdbg(VERBOSE, "free closed port %d rcvhdrq @ %p "
2251 "(size=%lu)\n", pd->port_port, pd->port_rcvhdrq,
2252 (unsigned long) pd->port_rcvhdrq_size);
2253 dma_free_coherent(&dd->pcidev->dev, pd->port_rcvhdrq_size,
2254 pd->port_rcvhdrq, pd->port_rcvhdrq_phys);
2255 pd->port_rcvhdrq = NULL;
2256 if (pd->port_rcvhdrtail_kvaddr) {
2257 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
2258 pd->port_rcvhdrtail_kvaddr,
2259 pd->port_rcvhdrqtailaddr_phys);
2260 pd->port_rcvhdrtail_kvaddr = NULL;
2263 if (pd->port_port && pd->port_rcvegrbuf) {
2266 for (e = 0; e < pd->port_rcvegrbuf_chunks; e++) {
2267 void *base = pd->port_rcvegrbuf[e];
2268 size_t size = pd->port_rcvegrbuf_size;
2270 ipath_cdbg(VERBOSE, "egrbuf free(%p, %lu), "
2271 "chunk %u/%u\n", base,
2272 (unsigned long) size,
2273 e, pd->port_rcvegrbuf_chunks);
2274 dma_free_coherent(&dd->pcidev->dev, size,
2275 base, pd->port_rcvegrbuf_phys[e]);
2277 kfree(pd->port_rcvegrbuf);
2278 pd->port_rcvegrbuf = NULL;
2279 kfree(pd->port_rcvegrbuf_phys);
2280 pd->port_rcvegrbuf_phys = NULL;
2281 pd->port_rcvegrbuf_chunks = 0;
2282 } else if (pd->port_port == 0 && dd->ipath_port0_skbinfo) {
2284 struct ipath_skbinfo *skbinfo = dd->ipath_port0_skbinfo;
2286 dd->ipath_port0_skbinfo = NULL;
2287 ipath_cdbg(VERBOSE, "free closed port %d "
2288 "ipath_port0_skbinfo @ %p\n", pd->port_port,
2290 for (e = 0; e < dd->ipath_p0_rcvegrcnt; e++)
2291 if (skbinfo[e].skb) {
2292 pci_unmap_single(dd->pcidev, skbinfo[e].phys,
2294 PCI_DMA_FROMDEVICE);
2295 dev_kfree_skb(skbinfo[e].skb);
2299 kfree(pd->port_tid_pg_list);
2300 vfree(pd->subport_uregbase);
2301 vfree(pd->subport_rcvegrbuf);
2302 vfree(pd->subport_rcvhdr_base);
2306 static int __init infinipath_init(void)
2310 if (ipath_debug & __IPATH_DBG)
2311 printk(KERN_INFO DRIVER_LOAD_MSG "%s", ib_ipath_version);
2314 * These must be called before the driver is registered with
2315 * the PCI subsystem.
2317 idr_init(&unit_table);
2318 if (!idr_pre_get(&unit_table, GFP_KERNEL)) {
2319 printk(KERN_ERR IPATH_DRV_NAME ": idr_pre_get() failed\n");
2324 ret = pci_register_driver(&ipath_driver);
2326 printk(KERN_ERR IPATH_DRV_NAME
2327 ": Unable to register driver: error %d\n", -ret);
2331 ret = ipath_init_ipathfs();
2333 printk(KERN_ERR IPATH_DRV_NAME ": Unable to create "
2334 "ipathfs: error %d\n", -ret);
2341 pci_unregister_driver(&ipath_driver);
2344 idr_destroy(&unit_table);
2350 static void __exit infinipath_cleanup(void)
2352 ipath_exit_ipathfs();
2354 ipath_cdbg(VERBOSE, "Unregistering pci driver\n");
2355 pci_unregister_driver(&ipath_driver);
2357 idr_destroy(&unit_table);
2361 * ipath_reset_device - reset the chip if possible
2362 * @unit: the device to reset
2364 * Whether or not reset is successful, we attempt to re-initialize the chip
2365 * (that is, much like a driver unload/reload). We clear the INITTED flag
2366 * so that the various entry points will fail until we reinitialize. For
2367 * now, we only allow this if no user ports are open that use chip resources
2369 int ipath_reset_device(int unit)
2372 struct ipath_devdata *dd = ipath_lookup(unit);
2379 if (atomic_read(&dd->ipath_led_override_timer_active)) {
2380 /* Need to stop LED timer, _then_ shut off LEDs */
2381 del_timer_sync(&dd->ipath_led_override_timer);
2382 atomic_set(&dd->ipath_led_override_timer_active, 0);
2385 /* Shut off LEDs after we are sure timer is not running */
2386 dd->ipath_led_override = LED_OVER_BOTH_OFF;
2387 dd->ipath_f_setextled(dd, 0, 0);
2389 dev_info(&dd->pcidev->dev, "Reset on unit %u requested\n", unit);
2391 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) {
2392 dev_info(&dd->pcidev->dev, "Invalid unit number %u or "
2393 "not initialized or not present\n", unit);
2399 for (i = 1; i < dd->ipath_cfgports; i++) {
2400 if (dd->ipath_pd[i] && dd->ipath_pd[i]->port_cnt) {
2401 ipath_dbg("unit %u port %d is in use "
2402 "(PID %u cmd %s), can't reset\n",
2404 dd->ipath_pd[i]->port_pid,
2405 dd->ipath_pd[i]->port_comm);
2411 dd->ipath_flags &= ~IPATH_INITTED;
2412 ret = dd->ipath_f_reset(dd);
2414 ipath_dbg("reset was not successful\n");
2415 ipath_dbg("Trying to reinitialize unit %u after reset attempt\n",
2417 ret = ipath_init_chip(dd, 1);
2419 ipath_dev_err(dd, "Reinitialize unit %u after "
2420 "reset failed with %d\n", unit, ret);
2422 dev_info(&dd->pcidev->dev, "Reinitialized unit %u after "
2423 "resetting\n", unit);
2430 * send a signal to all the processes that have the driver open
2431 * through the normal interfaces (i.e., everything other than diags
2432 * interface). Returns number of signalled processes.
2434 static int ipath_signal_procs(struct ipath_devdata *dd, int sig)
2436 int i, sub, any = 0;
2441 for (i = 1; i < dd->ipath_cfgports; i++) {
2442 if (!dd->ipath_pd[i] || !dd->ipath_pd[i]->port_cnt ||
2443 !dd->ipath_pd[i]->port_pid)
2445 pid = dd->ipath_pd[i]->port_pid;
2446 dev_info(&dd->pcidev->dev, "context %d in use "
2447 "(PID %u), sending signal %d\n",
2449 kill_proc(pid, sig, 1);
2451 for (sub = 0; sub < INFINIPATH_MAX_SUBPORT; sub++) {
2452 pid = dd->ipath_pd[i]->port_subpid[sub];
2455 dev_info(&dd->pcidev->dev, "sub-context "
2456 "%d:%d in use (PID %u), sending "
2457 "signal %d\n", i, sub, pid, sig);
2458 kill_proc(pid, sig, 1);
2465 static void ipath_hol_signal_down(struct ipath_devdata *dd)
2467 if (ipath_signal_procs(dd, SIGSTOP))
2468 ipath_dbg("Stopped some processes\n");
2469 ipath_cancel_sends(dd, 1);
2473 static void ipath_hol_signal_up(struct ipath_devdata *dd)
2475 if (ipath_signal_procs(dd, SIGCONT))
2476 ipath_dbg("Continued some processes\n");
2480 * link is down, stop any users processes, and flush pending sends
2481 * to prevent HoL blocking, then start the HoL timer that
2482 * periodically continues, then stop procs, so they can detect
2483 * link down if they want, and do something about it.
2484 * Timer may already be running, so use __mod_timer, not add_timer.
2486 void ipath_hol_down(struct ipath_devdata *dd)
2488 dd->ipath_hol_state = IPATH_HOL_DOWN;
2489 ipath_hol_signal_down(dd);
2490 dd->ipath_hol_next = IPATH_HOL_DOWNCONT;
2491 dd->ipath_hol_timer.expires = jiffies +
2492 msecs_to_jiffies(ipath_hol_timeout_ms);
2493 __mod_timer(&dd->ipath_hol_timer, dd->ipath_hol_timer.expires);
2497 * link is up, continue any user processes, and ensure timer
2498 * is a nop, if running. Let timer keep running, if set; it
2499 * will nop when it sees the link is up
2501 void ipath_hol_up(struct ipath_devdata *dd)
2503 ipath_hol_signal_up(dd);
2504 dd->ipath_hol_state = IPATH_HOL_UP;
2508 * toggle the running/not running state of user proceses
2509 * to prevent HoL blocking on chip resources, but still allow
2510 * user processes to do link down special case handling.
2511 * Should only be called via the timer
2513 void ipath_hol_event(unsigned long opaque)
2515 struct ipath_devdata *dd = (struct ipath_devdata *)opaque;
2517 if (dd->ipath_hol_next == IPATH_HOL_DOWNSTOP
2518 && dd->ipath_hol_state != IPATH_HOL_UP) {
2519 dd->ipath_hol_next = IPATH_HOL_DOWNCONT;
2520 ipath_dbg("Stopping processes\n");
2521 ipath_hol_signal_down(dd);
2522 } else { /* may do "extra" if also in ipath_hol_up() */
2523 dd->ipath_hol_next = IPATH_HOL_DOWNSTOP;
2524 ipath_dbg("Continuing processes\n");
2525 ipath_hol_signal_up(dd);
2527 if (dd->ipath_hol_state == IPATH_HOL_UP)
2528 ipath_dbg("link's up, don't resched timer\n");
2530 dd->ipath_hol_timer.expires = jiffies +
2531 msecs_to_jiffies(ipath_hol_timeout_ms);
2532 __mod_timer(&dd->ipath_hol_timer,
2533 dd->ipath_hol_timer.expires);
2537 int ipath_set_rx_pol_inv(struct ipath_devdata *dd, u8 new_pol_inv)
2541 if (new_pol_inv > INFINIPATH_XGXS_RX_POL_MASK)
2543 if (dd->ipath_rx_pol_inv != new_pol_inv) {
2544 dd->ipath_rx_pol_inv = new_pol_inv;
2545 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
2546 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
2547 INFINIPATH_XGXS_RX_POL_SHIFT);
2548 val |= ((u64)dd->ipath_rx_pol_inv) <<
2549 INFINIPATH_XGXS_RX_POL_SHIFT;
2550 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
2556 * Disable and enable the armlaunch error. Used for PIO bandwidth testing on
2557 * the 7220, which is count-based, rather than trigger-based. Safe for the
2558 * driver check, since it's at init. Not completely safe when used for
2559 * user-mode checking, since some error checking can be lost, but not
2560 * particularly risky, and only has problematic side-effects in the face of
2561 * very buggy user code. There is no reference counting, but that's also
2562 * fine, given the intended use.
2564 void ipath_enable_armlaunch(struct ipath_devdata *dd)
2566 dd->ipath_lasterror &= ~INFINIPATH_E_SPIOARMLAUNCH;
2567 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
2568 INFINIPATH_E_SPIOARMLAUNCH);
2569 dd->ipath_errormask |= INFINIPATH_E_SPIOARMLAUNCH;
2570 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
2571 dd->ipath_errormask);
2574 void ipath_disable_armlaunch(struct ipath_devdata *dd)
2576 /* so don't re-enable if already set */
2577 dd->ipath_maskederrs &= ~INFINIPATH_E_SPIOARMLAUNCH;
2578 dd->ipath_errormask &= ~INFINIPATH_E_SPIOARMLAUNCH;
2579 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
2580 dd->ipath_errormask);
2583 module_init(infinipath_init);
2584 module_exit(infinipath_cleanup);