2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/spinlock.h>
35 #include <linux/idr.h>
36 #include <linux/pci.h>
38 #include <linux/delay.h>
39 #include <linux/netdevice.h>
40 #include <linux/vmalloc.h>
42 #include "ipath_kernel.h"
43 #include "ipath_verbs.h"
45 static void ipath_update_pio_bufs(struct ipath_devdata *);
47 const char *ipath_get_unit_name(int unit)
49 static char iname[16];
50 snprintf(iname, sizeof iname, "infinipath%u", unit);
54 #define DRIVER_LOAD_MSG "QLogic " IPATH_DRV_NAME " loaded: "
55 #define PFX IPATH_DRV_NAME ": "
58 * The size has to be longer than this string, so we can append
59 * board/chip information to it in the init code.
61 const char ib_ipath_version[] = IPATH_IDSTR "\n";
63 static struct idr unit_table;
64 DEFINE_SPINLOCK(ipath_devs_lock);
65 LIST_HEAD(ipath_dev_list);
67 wait_queue_head_t ipath_state_wait;
69 unsigned ipath_debug = __IPATH_INFO;
71 module_param_named(debug, ipath_debug, uint, S_IWUSR | S_IRUGO);
72 MODULE_PARM_DESC(debug, "mask for debug prints");
73 EXPORT_SYMBOL_GPL(ipath_debug);
75 unsigned ipath_mtu4096 = 1; /* max 4KB IB mtu by default, if supported */
76 module_param_named(mtu4096, ipath_mtu4096, uint, S_IRUGO);
77 MODULE_PARM_DESC(mtu4096, "enable MTU of 4096 bytes, if supported");
79 static unsigned ipath_hol_timeout_ms = 13000;
80 module_param_named(hol_timeout_ms, ipath_hol_timeout_ms, uint, S_IRUGO);
81 MODULE_PARM_DESC(hol_timeout_ms,
82 "duration of user app suspension after link failure");
84 unsigned ipath_linkrecovery = 1;
85 module_param_named(linkrecovery, ipath_linkrecovery, uint, S_IWUSR | S_IRUGO);
86 MODULE_PARM_DESC(linkrecovery, "enable workaround for link recovery issue");
88 MODULE_LICENSE("GPL");
89 MODULE_AUTHOR("QLogic <support@qlogic.com>");
90 MODULE_DESCRIPTION("QLogic InfiniPath driver");
92 const char *ipath_ibcstatus_str[] = {
99 "LState6", /* unused */
100 "LState7", /* unused */
106 "LState0xD", /* unused */
111 static void __devexit ipath_remove_one(struct pci_dev *);
112 static int __devinit ipath_init_one(struct pci_dev *,
113 const struct pci_device_id *);
115 /* Only needed for registration, nothing else needs this info */
116 #define PCI_VENDOR_ID_PATHSCALE 0x1fc1
117 #define PCI_DEVICE_ID_INFINIPATH_HT 0xd
118 #define PCI_DEVICE_ID_INFINIPATH_PE800 0x10
120 /* Number of seconds before our card status check... */
121 #define STATUS_TIMEOUT 60
123 static const struct pci_device_id ipath_pci_tbl[] = {
124 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_HT) },
125 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_PE800) },
129 MODULE_DEVICE_TABLE(pci, ipath_pci_tbl);
131 static struct pci_driver ipath_driver = {
132 .name = IPATH_DRV_NAME,
133 .probe = ipath_init_one,
134 .remove = __devexit_p(ipath_remove_one),
135 .id_table = ipath_pci_tbl,
137 .groups = ipath_driver_attr_groups,
141 static void ipath_check_status(struct work_struct *work)
143 struct ipath_devdata *dd = container_of(work, struct ipath_devdata,
147 * If we don't have any interrupts, let the user know and
148 * don't bother checking again.
150 if (dd->ipath_int_counter == 0)
151 dev_err(&dd->pcidev->dev, "No interrupts detected.\n");
154 static inline void read_bars(struct ipath_devdata *dd, struct pci_dev *dev,
155 u32 *bar0, u32 *bar1)
159 ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
161 ipath_dev_err(dd, "failed to read bar0 before enable: "
164 ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, bar1);
166 ipath_dev_err(dd, "failed to read bar1 before enable: "
169 ipath_dbg("Read bar0 %x bar1 %x\n", *bar0, *bar1);
172 static void ipath_free_devdata(struct pci_dev *pdev,
173 struct ipath_devdata *dd)
177 pci_set_drvdata(pdev, NULL);
179 if (dd->ipath_unit != -1) {
180 spin_lock_irqsave(&ipath_devs_lock, flags);
181 idr_remove(&unit_table, dd->ipath_unit);
182 list_del(&dd->ipath_list);
183 spin_unlock_irqrestore(&ipath_devs_lock, flags);
188 static struct ipath_devdata *ipath_alloc_devdata(struct pci_dev *pdev)
191 struct ipath_devdata *dd;
194 if (!idr_pre_get(&unit_table, GFP_KERNEL)) {
195 dd = ERR_PTR(-ENOMEM);
199 dd = vmalloc(sizeof(*dd));
201 dd = ERR_PTR(-ENOMEM);
204 memset(dd, 0, sizeof(*dd));
207 spin_lock_irqsave(&ipath_devs_lock, flags);
209 ret = idr_get_new(&unit_table, dd, &dd->ipath_unit);
211 printk(KERN_ERR IPATH_DRV_NAME
212 ": Could not allocate unit ID: error %d\n", -ret);
213 ipath_free_devdata(pdev, dd);
219 pci_set_drvdata(pdev, dd);
221 INIT_DELAYED_WORK(&dd->status_work, ipath_check_status);
223 list_add(&dd->ipath_list, &ipath_dev_list);
226 spin_unlock_irqrestore(&ipath_devs_lock, flags);
232 static inline struct ipath_devdata *__ipath_lookup(int unit)
234 return idr_find(&unit_table, unit);
237 struct ipath_devdata *ipath_lookup(int unit)
239 struct ipath_devdata *dd;
242 spin_lock_irqsave(&ipath_devs_lock, flags);
243 dd = __ipath_lookup(unit);
244 spin_unlock_irqrestore(&ipath_devs_lock, flags);
249 int ipath_count_units(int *npresentp, int *nupp, int *maxportsp)
251 int nunits, npresent, nup;
252 struct ipath_devdata *dd;
256 nunits = npresent = nup = maxports = 0;
258 spin_lock_irqsave(&ipath_devs_lock, flags);
260 list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
262 if ((dd->ipath_flags & IPATH_PRESENT) && dd->ipath_kregbase)
265 !(dd->ipath_flags & (IPATH_DISABLED | IPATH_LINKDOWN
268 if (dd->ipath_cfgports > maxports)
269 maxports = dd->ipath_cfgports;
272 spin_unlock_irqrestore(&ipath_devs_lock, flags);
275 *npresentp = npresent;
279 *maxportsp = maxports;
285 * These next two routines are placeholders in case we don't have per-arch
286 * code for controlling write combining. If explicit control of write
287 * combining is not available, performance will probably be awful.
290 int __attribute__((weak)) ipath_enable_wc(struct ipath_devdata *dd)
295 void __attribute__((weak)) ipath_disable_wc(struct ipath_devdata *dd)
300 * Perform a PIO buffer bandwidth write test, to verify proper system
301 * configuration. Even when all the setup calls work, occasionally
302 * BIOS or other issues can prevent write combining from working, or
303 * can cause other bandwidth problems to the chip.
305 * This test simply writes the same buffer over and over again, and
306 * measures close to the peak bandwidth to the chip (not testing
307 * data bandwidth to the wire). On chips that use an address-based
308 * trigger to send packets to the wire, this is easy. On chips that
309 * use a count to trigger, we want to make sure that the packet doesn't
310 * go out on the wire, or trigger flow control checks.
312 static void ipath_verify_pioperf(struct ipath_devdata *dd)
314 u32 pbnum, cnt, lcnt;
319 piobuf = ipath_getpiobuf(dd, 0, &pbnum);
321 dev_info(&dd->pcidev->dev,
322 "No PIObufs for checking perf, skipping\n");
327 * Enough to give us a reasonable test, less than piobuf size, and
328 * likely multiple of store buffer length.
334 dev_info(&dd->pcidev->dev,
335 "Couldn't get memory for checking PIO perf,"
340 preempt_disable(); /* we want reasonably accurate elapsed time */
341 msecs = 1 + jiffies_to_msecs(jiffies);
342 for (lcnt = 0; lcnt < 10000U; lcnt++) {
343 /* wait until we cross msec boundary */
344 if (jiffies_to_msecs(jiffies) >= msecs)
349 ipath_disable_armlaunch(dd);
351 writeq(0, piobuf); /* length 0, no dwords actually sent */
355 * this is only roughly accurate, since even with preempt we
356 * still take interrupts that could take a while. Running for
357 * >= 5 msec seems to get us "close enough" to accurate values
359 msecs = jiffies_to_msecs(jiffies);
360 for (emsecs = lcnt = 0; emsecs <= 5UL; lcnt++) {
361 __iowrite32_copy(piobuf + 64, addr, cnt >> 2);
362 emsecs = jiffies_to_msecs(jiffies) - msecs;
365 /* 1 GiB/sec, slightly over IB SDR line rate */
366 if (lcnt < (emsecs * 1024U))
368 "Performance problem: bandwidth to PIO buffers is "
370 lcnt / (u32) emsecs);
372 ipath_dbg("PIO buffer bandwidth %u MiB/sec is OK\n",
373 lcnt / (u32) emsecs);
380 /* disarm piobuf, so it's available again */
381 ipath_disarm_piobufs(dd, pbnum, 1);
382 ipath_enable_armlaunch(dd);
385 static int __devinit ipath_init_one(struct pci_dev *pdev,
386 const struct pci_device_id *ent)
389 struct ipath_devdata *dd;
390 unsigned long long addr;
391 u32 bar0 = 0, bar1 = 0;
393 dd = ipath_alloc_devdata(pdev);
396 printk(KERN_ERR IPATH_DRV_NAME
397 ": Could not allocate devdata: error %d\n", -ret);
401 ipath_cdbg(VERBOSE, "initializing unit #%u\n", dd->ipath_unit);
403 ret = pci_enable_device(pdev);
405 /* This can happen iff:
407 * We did a chip reset, and then failed to reprogram the
408 * BAR, or the chip reset due to an internal error. We then
409 * unloaded the driver and reloaded it.
411 * Both reset cases set the BAR back to initial state. For
412 * the latter case, the AER sticky error bit at offset 0x718
413 * should be set, but the Linux kernel doesn't yet know
414 * about that, it appears. If the original BAR was retained
415 * in the kernel data structures, this may be OK.
417 ipath_dev_err(dd, "enable unit %d failed: error %d\n",
418 dd->ipath_unit, -ret);
421 addr = pci_resource_start(pdev, 0);
422 len = pci_resource_len(pdev, 0);
423 ipath_cdbg(VERBOSE, "regbase (0) %llx len %d pdev->irq %d, vend %x/%x "
424 "driver_data %lx\n", addr, len, pdev->irq, ent->vendor,
425 ent->device, ent->driver_data);
427 read_bars(dd, pdev, &bar0, &bar1);
429 if (!bar1 && !(bar0 & ~0xf)) {
431 dev_info(&pdev->dev, "BAR is 0 (probable RESET), "
432 "rewriting as %llx\n", addr);
433 ret = pci_write_config_dword(
434 pdev, PCI_BASE_ADDRESS_0, addr);
436 ipath_dev_err(dd, "rewrite of BAR0 "
437 "failed: err %d\n", -ret);
440 ret = pci_write_config_dword(
441 pdev, PCI_BASE_ADDRESS_1, addr >> 32);
443 ipath_dev_err(dd, "rewrite of BAR1 "
444 "failed: err %d\n", -ret);
448 ipath_dev_err(dd, "BAR is 0 (probable RESET), "
449 "not usable until reboot\n");
455 ret = pci_request_regions(pdev, IPATH_DRV_NAME);
457 dev_info(&pdev->dev, "pci_request_regions unit %u fails: "
458 "err %d\n", dd->ipath_unit, -ret);
462 ret = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
465 * if the 64 bit setup fails, try 32 bit. Some systems
466 * do not setup 64 bit maps on systems with 2GB or less
469 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
472 "Unable to set DMA mask for unit %u: %d\n",
473 dd->ipath_unit, ret);
477 ipath_dbg("No 64bit DMA mask, used 32 bit mask\n");
478 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
481 "Unable to set DMA consistent mask "
483 dd->ipath_unit, ret);
488 ret = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
491 "Unable to set DMA consistent mask "
493 dd->ipath_unit, ret);
496 pci_set_master(pdev);
499 * Save BARs to rewrite after device reset. Save all 64 bits of
502 dd->ipath_pcibar0 = addr;
503 dd->ipath_pcibar1 = addr >> 32;
504 dd->ipath_deviceid = ent->device; /* save for later use */
505 dd->ipath_vendorid = ent->vendor;
507 /* setup the chip-specific functions, as early as possible. */
508 switch (ent->device) {
509 case PCI_DEVICE_ID_INFINIPATH_HT:
511 ipath_init_iba6110_funcs(dd);
514 ipath_dev_err(dd, "QLogic HT device 0x%x cannot work if "
515 "CONFIG_HT_IRQ is not enabled\n", ent->device);
518 case PCI_DEVICE_ID_INFINIPATH_PE800:
519 #ifdef CONFIG_PCI_MSI
520 ipath_init_iba6120_funcs(dd);
523 ipath_dev_err(dd, "QLogic PCIE device 0x%x cannot work if "
524 "CONFIG_PCI_MSI is not enabled\n", ent->device);
528 ipath_dev_err(dd, "Found unknown QLogic deviceid 0x%x, "
529 "failing\n", ent->device);
533 for (j = 0; j < 6; j++) {
534 if (!pdev->resource[j].start)
536 ipath_cdbg(VERBOSE, "BAR %d start %llx, end %llx, len %llx\n",
537 j, (unsigned long long)pdev->resource[j].start,
538 (unsigned long long)pdev->resource[j].end,
539 (unsigned long long)pci_resource_len(pdev, j));
543 ipath_dev_err(dd, "No valid address in BAR 0!\n");
548 dd->ipath_pcirev = pdev->revision;
550 #if defined(__powerpc__)
551 /* There isn't a generic way to specify writethrough mappings */
552 dd->ipath_kregbase = __ioremap(addr, len,
553 (_PAGE_NO_CACHE|_PAGE_WRITETHRU));
555 dd->ipath_kregbase = ioremap_nocache(addr, len);
558 if (!dd->ipath_kregbase) {
559 ipath_dbg("Unable to map io addr %llx to kvirt, failing\n",
564 dd->ipath_kregend = (u64 __iomem *)
565 ((void __iomem *)dd->ipath_kregbase + len);
566 dd->ipath_physaddr = addr; /* used for io_remap, etc. */
568 ipath_cdbg(VERBOSE, "mapped io addr %llx to kregbase %p\n",
569 addr, dd->ipath_kregbase);
572 * clear ipath_flags here instead of in ipath_init_chip as it is set
573 * by ipath_setup_htconfig.
576 dd->ipath_lli_counter = 0;
577 dd->ipath_lli_errors = 0;
579 if (dd->ipath_f_bus(dd, pdev))
580 ipath_dev_err(dd, "Failed to setup config space; "
581 "continuing anyway\n");
584 * set up our interrupt handler; IRQF_SHARED probably not needed,
585 * since MSI interrupts shouldn't be shared but won't hurt for now.
586 * check 0 irq after we return from chip-specific bus setup, since
587 * that can affect this due to setup
590 ipath_dev_err(dd, "irq is 0, BIOS error? Interrupts won't "
593 ret = request_irq(dd->ipath_irq, ipath_intr, IRQF_SHARED,
596 ipath_dev_err(dd, "Couldn't setup irq handler, "
597 "irq=%d: %d\n", dd->ipath_irq, ret);
602 ret = ipath_init_chip(dd, 0); /* do the chip-specific init */
606 ret = ipath_enable_wc(dd);
609 ipath_dev_err(dd, "Write combining not enabled "
610 "(err %d): performance may be poor\n",
615 ipath_verify_pioperf(dd);
617 ipath_device_create_group(&pdev->dev, dd);
618 ipathfs_add_device(dd);
621 ipath_register_ib_device(dd);
623 /* Check that card status in STATUS_TIMEOUT seconds. */
624 schedule_delayed_work(&dd->status_work, HZ * STATUS_TIMEOUT);
630 free_irq(pdev->irq, dd);
633 iounmap((volatile void __iomem *) dd->ipath_kregbase);
636 pci_release_regions(pdev);
639 pci_disable_device(pdev);
642 ipath_free_devdata(pdev, dd);
648 static void __devexit cleanup_device(struct ipath_devdata *dd)
652 if (*dd->ipath_statusp & IPATH_STATUS_CHIP_PRESENT) {
653 /* can't do anything more with chip; needs re-init */
654 *dd->ipath_statusp &= ~IPATH_STATUS_CHIP_PRESENT;
655 if (dd->ipath_kregbase) {
657 * if we haven't already cleaned up before these are
658 * to ensure any register reads/writes "fail" until
661 dd->ipath_kregbase = NULL;
662 dd->ipath_uregbase = 0;
663 dd->ipath_sregbase = 0;
664 dd->ipath_cregbase = 0;
665 dd->ipath_kregsize = 0;
667 ipath_disable_wc(dd);
670 if (dd->ipath_pioavailregs_dma) {
671 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
672 (void *) dd->ipath_pioavailregs_dma,
673 dd->ipath_pioavailregs_phys);
674 dd->ipath_pioavailregs_dma = NULL;
676 if (dd->ipath_dummy_hdrq) {
677 dma_free_coherent(&dd->pcidev->dev,
678 dd->ipath_pd[0]->port_rcvhdrq_size,
679 dd->ipath_dummy_hdrq, dd->ipath_dummy_hdrq_phys);
680 dd->ipath_dummy_hdrq = NULL;
683 if (dd->ipath_pageshadow) {
684 struct page **tmpp = dd->ipath_pageshadow;
685 dma_addr_t *tmpd = dd->ipath_physshadow;
688 ipath_cdbg(VERBOSE, "Unlocking any expTID pages still "
690 for (port = 0; port < dd->ipath_cfgports; port++) {
691 int port_tidbase = port * dd->ipath_rcvtidcnt;
692 int maxtid = port_tidbase + dd->ipath_rcvtidcnt;
693 for (i = port_tidbase; i < maxtid; i++) {
696 pci_unmap_page(dd->pcidev, tmpd[i],
697 PAGE_SIZE, PCI_DMA_FROMDEVICE);
698 ipath_release_user_pages(&tmpp[i], 1);
704 ipath_stats.sps_pageunlocks += cnt;
705 ipath_cdbg(VERBOSE, "There were still %u expTID "
706 "entries locked\n", cnt);
708 if (ipath_stats.sps_pagelocks ||
709 ipath_stats.sps_pageunlocks)
710 ipath_cdbg(VERBOSE, "%llu pages locked, %llu "
711 "unlocked via ipath_m{un}lock\n",
713 ipath_stats.sps_pagelocks,
715 ipath_stats.sps_pageunlocks);
717 ipath_cdbg(VERBOSE, "Free shadow page tid array at %p\n",
718 dd->ipath_pageshadow);
719 tmpp = dd->ipath_pageshadow;
720 dd->ipath_pageshadow = NULL;
723 dd->ipath_egrtidbase = NULL;
727 * free any resources still in use (usually just kernel ports)
728 * at unload; we do for portcnt, not cfgports, because cfgports
729 * could have changed while we were loaded.
731 for (port = 0; port < dd->ipath_portcnt; port++) {
732 struct ipath_portdata *pd = dd->ipath_pd[port];
733 dd->ipath_pd[port] = NULL;
734 ipath_free_pddata(dd, pd);
738 * debuggability, in case some cleanup path tries to use it
744 static void __devexit ipath_remove_one(struct pci_dev *pdev)
746 struct ipath_devdata *dd = pci_get_drvdata(pdev);
748 ipath_cdbg(VERBOSE, "removing, pdev=%p, dd=%p\n", pdev, dd);
751 * disable the IB link early, to be sure no new packets arrive, which
752 * complicates the shutdown process
754 ipath_shutdown_device(dd);
756 cancel_delayed_work(&dd->status_work);
757 flush_scheduled_work();
760 ipath_unregister_ib_device(dd->verbs_dev);
762 ipath_diag_remove(dd);
763 ipath_user_remove(dd);
764 ipathfs_remove_device(dd);
765 ipath_device_remove_group(&pdev->dev, dd);
767 ipath_cdbg(VERBOSE, "Releasing pci memory regions, dd %p, "
768 "unit %u\n", dd, (u32) dd->ipath_unit);
773 * turn off rcv, send, and interrupts for all ports, all drivers
774 * should also hard reset the chip here?
775 * free up port 0 (kernel) rcvhdr, egr bufs, and eventually tid bufs
776 * for all versions of the driver, if they were allocated
779 ipath_cdbg(VERBOSE, "unit %u free irq %d\n",
780 dd->ipath_unit, dd->ipath_irq);
781 dd->ipath_f_free_irq(dd);
783 ipath_dbg("irq is 0, not doing free_irq "
784 "for unit %u\n", dd->ipath_unit);
786 * we check for NULL here, because it's outside
787 * the kregbase check, and we need to call it
788 * after the free_irq. Thus it's possible that
789 * the function pointers were never initialized.
791 if (dd->ipath_f_cleanup)
792 /* clean up chip-specific stuff */
793 dd->ipath_f_cleanup(dd);
795 ipath_cdbg(VERBOSE, "Unmapping kregbase %p\n", dd->ipath_kregbase);
796 iounmap((volatile void __iomem *) dd->ipath_kregbase);
797 pci_release_regions(pdev);
798 ipath_cdbg(VERBOSE, "calling pci_disable_device\n");
799 pci_disable_device(pdev);
801 ipath_free_devdata(pdev, dd);
804 /* general driver use */
805 DEFINE_MUTEX(ipath_mutex);
807 static DEFINE_SPINLOCK(ipath_pioavail_lock);
810 * ipath_disarm_piobufs - cancel a range of PIO buffers
811 * @dd: the infinipath device
812 * @first: the first PIO buffer to cancel
813 * @cnt: the number of PIO buffers to cancel
815 * cancel a range of PIO buffers, used when they might be armed, but
816 * not triggered. Used at init to ensure buffer state, and also user
817 * process close, in case it died while writing to a PIO buffer
820 void ipath_disarm_piobufs(struct ipath_devdata *dd, unsigned first,
823 unsigned i, last = first + cnt;
826 ipath_cdbg(PKT, "disarm %u PIObufs first=%u\n", cnt, first);
827 for (i = first; i < last; i++) {
828 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
830 * The disarm-related bits are write-only, so it
831 * is ok to OR them in with our copy of sendctrl
832 * while we hold the lock.
834 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
835 dd->ipath_sendctrl | INFINIPATH_S_DISARM |
836 (i << INFINIPATH_S_DISARMPIOBUF_SHIFT));
837 /* can't disarm bufs back-to-back per iba7220 spec */
838 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
839 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
841 /* on some older chips, update may not happen after cancel */
842 ipath_force_pio_avail_update(dd);
846 * ipath_wait_linkstate - wait for an IB link state change to occur
847 * @dd: the infinipath device
848 * @state: the state to wait for
849 * @msecs: the number of milliseconds to wait
851 * wait up to msecs milliseconds for IB link state change to occur for
852 * now, take the easy polling route. Currently used only by
853 * ipath_set_linkstate. Returns 0 if state reached, otherwise
854 * -ETIMEDOUT state can have multiple states set, for any of several
857 int ipath_wait_linkstate(struct ipath_devdata *dd, u32 state, int msecs)
859 dd->ipath_state_wanted = state;
860 wait_event_interruptible_timeout(ipath_state_wait,
861 (dd->ipath_flags & state),
862 msecs_to_jiffies(msecs));
863 dd->ipath_state_wanted = 0;
865 if (!(dd->ipath_flags & state)) {
867 ipath_cdbg(VERBOSE, "Didn't reach linkstate %s within %u"
869 /* test INIT ahead of DOWN, both can be set */
870 (state & IPATH_LINKINIT) ? "INIT" :
871 ((state & IPATH_LINKDOWN) ? "DOWN" :
872 ((state & IPATH_LINKARMED) ? "ARM" : "ACTIVE")),
874 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
875 ipath_cdbg(VERBOSE, "ibcc=%llx ibcstatus=%llx (%s)\n",
876 (unsigned long long) ipath_read_kreg64(
877 dd, dd->ipath_kregs->kr_ibcctrl),
878 (unsigned long long) val,
879 ipath_ibcstatus_str[val & 0xf]);
881 return (dd->ipath_flags & state) ? 0 : -ETIMEDOUT;
885 * Decode the error status into strings, deciding whether to always
886 * print * it or not depending on "normal packet errors" vs everything
887 * else. Return 1 if "real" errors, otherwise 0 if only packet
888 * errors, so caller can decide what to print with the string.
890 int ipath_decode_err(char *buf, size_t blen, ipath_err_t err)
894 if (err & INFINIPATH_E_PKTERRS) {
895 if (!(err & ~INFINIPATH_E_PKTERRS))
896 iserr = 0; // if only packet errors.
897 if (ipath_debug & __IPATH_ERRPKTDBG) {
898 if (err & INFINIPATH_E_REBP)
899 strlcat(buf, "EBP ", blen);
900 if (err & INFINIPATH_E_RVCRC)
901 strlcat(buf, "VCRC ", blen);
902 if (err & INFINIPATH_E_RICRC) {
903 strlcat(buf, "CRC ", blen);
904 // clear for check below, so only once
905 err &= INFINIPATH_E_RICRC;
907 if (err & INFINIPATH_E_RSHORTPKTLEN)
908 strlcat(buf, "rshortpktlen ", blen);
909 if (err & INFINIPATH_E_SDROPPEDDATAPKT)
910 strlcat(buf, "sdroppeddatapkt ", blen);
911 if (err & INFINIPATH_E_SPKTLEN)
912 strlcat(buf, "spktlen ", blen);
914 if ((err & INFINIPATH_E_RICRC) &&
915 !(err&(INFINIPATH_E_RVCRC|INFINIPATH_E_REBP)))
916 strlcat(buf, "CRC ", blen);
920 if (err & INFINIPATH_E_RHDRLEN)
921 strlcat(buf, "rhdrlen ", blen);
922 if (err & INFINIPATH_E_RBADTID)
923 strlcat(buf, "rbadtid ", blen);
924 if (err & INFINIPATH_E_RBADVERSION)
925 strlcat(buf, "rbadversion ", blen);
926 if (err & INFINIPATH_E_RHDR)
927 strlcat(buf, "rhdr ", blen);
928 if (err & INFINIPATH_E_RLONGPKTLEN)
929 strlcat(buf, "rlongpktlen ", blen);
930 if (err & INFINIPATH_E_RMAXPKTLEN)
931 strlcat(buf, "rmaxpktlen ", blen);
932 if (err & INFINIPATH_E_RMINPKTLEN)
933 strlcat(buf, "rminpktlen ", blen);
934 if (err & INFINIPATH_E_SMINPKTLEN)
935 strlcat(buf, "sminpktlen ", blen);
936 if (err & INFINIPATH_E_RFORMATERR)
937 strlcat(buf, "rformaterr ", blen);
938 if (err & INFINIPATH_E_RUNSUPVL)
939 strlcat(buf, "runsupvl ", blen);
940 if (err & INFINIPATH_E_RUNEXPCHAR)
941 strlcat(buf, "runexpchar ", blen);
942 if (err & INFINIPATH_E_RIBFLOW)
943 strlcat(buf, "ribflow ", blen);
944 if (err & INFINIPATH_E_SUNDERRUN)
945 strlcat(buf, "sunderrun ", blen);
946 if (err & INFINIPATH_E_SPIOARMLAUNCH)
947 strlcat(buf, "spioarmlaunch ", blen);
948 if (err & INFINIPATH_E_SUNEXPERRPKTNUM)
949 strlcat(buf, "sunexperrpktnum ", blen);
950 if (err & INFINIPATH_E_SDROPPEDSMPPKT)
951 strlcat(buf, "sdroppedsmppkt ", blen);
952 if (err & INFINIPATH_E_SMAXPKTLEN)
953 strlcat(buf, "smaxpktlen ", blen);
954 if (err & INFINIPATH_E_SUNSUPVL)
955 strlcat(buf, "sunsupVL ", blen);
956 if (err & INFINIPATH_E_INVALIDADDR)
957 strlcat(buf, "invalidaddr ", blen);
958 if (err & INFINIPATH_E_RRCVEGRFULL)
959 strlcat(buf, "rcvegrfull ", blen);
960 if (err & INFINIPATH_E_RRCVHDRFULL)
961 strlcat(buf, "rcvhdrfull ", blen);
962 if (err & INFINIPATH_E_IBSTATUSCHANGED)
963 strlcat(buf, "ibcstatuschg ", blen);
964 if (err & INFINIPATH_E_RIBLOSTLINK)
965 strlcat(buf, "riblostlink ", blen);
966 if (err & INFINIPATH_E_HARDWARE)
967 strlcat(buf, "hardware ", blen);
968 if (err & INFINIPATH_E_RESET)
969 strlcat(buf, "reset ", blen);
975 * get_rhf_errstring - decode RHF errors
976 * @err: the err number
977 * @msg: the output buffer
978 * @len: the length of the output buffer
980 * only used one place now, may want more later
982 static void get_rhf_errstring(u32 err, char *msg, size_t len)
984 /* if no errors, and so don't need to check what's first */
987 if (err & INFINIPATH_RHF_H_ICRCERR)
988 strlcat(msg, "icrcerr ", len);
989 if (err & INFINIPATH_RHF_H_VCRCERR)
990 strlcat(msg, "vcrcerr ", len);
991 if (err & INFINIPATH_RHF_H_PARITYERR)
992 strlcat(msg, "parityerr ", len);
993 if (err & INFINIPATH_RHF_H_LENERR)
994 strlcat(msg, "lenerr ", len);
995 if (err & INFINIPATH_RHF_H_MTUERR)
996 strlcat(msg, "mtuerr ", len);
997 if (err & INFINIPATH_RHF_H_IHDRERR)
998 /* infinipath hdr checksum error */
999 strlcat(msg, "ipathhdrerr ", len);
1000 if (err & INFINIPATH_RHF_H_TIDERR)
1001 strlcat(msg, "tiderr ", len);
1002 if (err & INFINIPATH_RHF_H_MKERR)
1003 /* bad port, offset, etc. */
1004 strlcat(msg, "invalid ipathhdr ", len);
1005 if (err & INFINIPATH_RHF_H_IBERR)
1006 strlcat(msg, "iberr ", len);
1007 if (err & INFINIPATH_RHF_L_SWA)
1008 strlcat(msg, "swA ", len);
1009 if (err & INFINIPATH_RHF_L_SWB)
1010 strlcat(msg, "swB ", len);
1014 * ipath_get_egrbuf - get an eager buffer
1015 * @dd: the infinipath device
1016 * @bufnum: the eager buffer to get
1018 * must only be called if ipath_pd[port] is known to be allocated
1020 static inline void *ipath_get_egrbuf(struct ipath_devdata *dd, u32 bufnum)
1022 return dd->ipath_port0_skbinfo ?
1023 (void *) dd->ipath_port0_skbinfo[bufnum].skb->data : NULL;
1027 * ipath_alloc_skb - allocate an skb and buffer with possible constraints
1028 * @dd: the infinipath device
1029 * @gfp_mask: the sk_buff SFP mask
1031 struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd,
1034 struct sk_buff *skb;
1038 * Only fully supported way to handle this is to allocate lots
1039 * extra, align as needed, and then do skb_reserve(). That wastes
1040 * a lot of memory... I'll have to hack this into infinipath_copy
1045 * We need 2 extra bytes for ipath_ether data sent in the
1046 * key header. In order to keep everything dword aligned,
1047 * we'll reserve 4 bytes.
1049 len = dd->ipath_ibmaxlen + 4;
1051 if (dd->ipath_flags & IPATH_4BYTE_TID) {
1052 /* We need a 2KB multiple alignment, and there is no way
1053 * to do it except to allocate extra and then skb_reserve
1054 * enough to bring it up to the right alignment.
1059 skb = __dev_alloc_skb(len, gfp_mask);
1061 ipath_dev_err(dd, "Failed to allocate skbuff, length %u\n",
1066 skb_reserve(skb, 4);
1068 if (dd->ipath_flags & IPATH_4BYTE_TID) {
1069 u32 una = (unsigned long)skb->data & 2047;
1071 skb_reserve(skb, 2048 - una);
1078 static void ipath_rcv_hdrerr(struct ipath_devdata *dd,
1083 struct ipath_message_header *hdr)
1087 get_rhf_errstring(eflags, emsg, sizeof emsg);
1088 ipath_cdbg(PKT, "RHFerrs %x hdrqtail=%x typ=%u "
1089 "tlen=%x opcode=%x egridx=%x: %s\n",
1091 ipath_hdrget_rcv_type(rhf_addr),
1092 ipath_hdrget_length_in_bytes(rhf_addr),
1093 be32_to_cpu(hdr->bth[0]) >> 24,
1096 /* Count local link integrity errors. */
1097 if (eflags & (INFINIPATH_RHF_H_ICRCERR | INFINIPATH_RHF_H_VCRCERR)) {
1098 u8 n = (dd->ipath_ibcctrl >>
1099 INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT) &
1100 INFINIPATH_IBCC_PHYERRTHRESHOLD_MASK;
1102 if (++dd->ipath_lli_counter > n) {
1103 dd->ipath_lli_counter = 0;
1104 dd->ipath_lli_errors++;
1110 * ipath_kreceive - receive a packet
1111 * @pd: the infinipath port
1113 * called from interrupt handler for errors or receive interrupt
1115 void ipath_kreceive(struct ipath_portdata *pd)
1117 struct ipath_devdata *dd = pd->port_dd;
1120 const u32 rsize = dd->ipath_rcvhdrentsize; /* words */
1121 const u32 maxcnt = dd->ipath_rcvhdrcnt * rsize; /* words */
1122 u32 etail = -1, l, hdrqtail;
1123 struct ipath_message_header *hdr;
1124 u32 eflags, i, etype, tlen, pkttot = 0, updegr = 0, reloop = 0;
1125 static u64 totcalls; /* stats, may eventually remove */
1129 rhf_addr = (__le32 *) pd->port_rcvhdrq + l + dd->ipath_rhf_offset;
1130 if (dd->ipath_flags & IPATH_NODMA_RTAIL) {
1131 u32 seq = ipath_hdrget_seq(rhf_addr);
1133 if (seq != pd->port_seq_cnt)
1137 hdrqtail = ipath_get_rcvhdrtail(pd);
1144 for (last = 0, i = 1; !last; i++) {
1145 hdr = dd->ipath_f_get_msgheader(dd, rhf_addr);
1146 eflags = ipath_hdrget_err_flags(rhf_addr);
1147 etype = ipath_hdrget_rcv_type(rhf_addr);
1149 tlen = ipath_hdrget_length_in_bytes(rhf_addr);
1151 if ((dd->ipath_flags & IPATH_NODMA_RTAIL) ?
1152 ipath_hdrget_use_egr_buf(rhf_addr) :
1153 (etype != RCVHQ_RCV_TYPE_EXPECTED)) {
1155 * It turns out that the chip uses an eager buffer
1156 * for all non-expected packets, whether it "needs"
1157 * one or not. So always get the index, but don't
1158 * set ebuf (so we try to copy data) unless the
1159 * length requires it.
1161 etail = ipath_hdrget_index(rhf_addr);
1163 if (tlen > sizeof(*hdr) ||
1164 etype == RCVHQ_RCV_TYPE_NON_KD)
1165 ebuf = ipath_get_egrbuf(dd, etail);
1169 * both tiderr and ipathhdrerr are set for all plain IB
1170 * packets; only ipathhdrerr should be set.
1173 if (etype != RCVHQ_RCV_TYPE_NON_KD &&
1174 etype != RCVHQ_RCV_TYPE_ERROR &&
1175 ipath_hdrget_ipath_ver(hdr->iph.ver_port_tid_offset) !=
1177 ipath_cdbg(PKT, "Bad InfiniPath protocol version "
1180 if (unlikely(eflags))
1181 ipath_rcv_hdrerr(dd, eflags, l, etail, rhf_addr, hdr);
1182 else if (etype == RCVHQ_RCV_TYPE_NON_KD) {
1183 ipath_ib_rcv(dd->verbs_dev, (u32 *)hdr, ebuf, tlen);
1184 if (dd->ipath_lli_counter)
1185 dd->ipath_lli_counter--;
1186 } else if (etype == RCVHQ_RCV_TYPE_EAGER) {
1187 u8 opcode = be32_to_cpu(hdr->bth[0]) >> 24;
1188 u32 qp = be32_to_cpu(hdr->bth[1]) & 0xffffff;
1189 ipath_cdbg(PKT, "typ %x, opcode %x (eager, "
1190 "qp=%x), len %x; ignored\n",
1191 etype, opcode, qp, tlen);
1193 else if (etype == RCVHQ_RCV_TYPE_EXPECTED)
1194 ipath_dbg("Bug: Expected TID, opcode %x; ignored\n",
1195 be32_to_cpu(hdr->bth[0]) >> 24);
1198 * error packet, type of error unknown.
1199 * Probably type 3, but we don't know, so don't
1200 * even try to print the opcode, etc.
1201 * Usually caused by a "bad packet", that has no
1202 * BTH, when the LRH says it should.
1204 ipath_cdbg(ERRPKT, "Error Pkt, but no eflags! egrbuf"
1205 " %x, len %x hdrq+%x rhf: %Lx\n",
1207 le64_to_cpu(*(__le64 *) rhf_addr));
1208 if (ipath_debug & __IPATH_ERRPKTDBG) {
1209 u32 j, *d, dw = rsize-2;
1210 if (rsize > (tlen>>2))
1213 printk(KERN_DEBUG "EPkt rcvhdr(%x dw):\n",
1215 for (j = 0; j < dw; j++)
1216 printk(KERN_DEBUG "%8x%s", d[j],
1217 (j%8) == 7 ? "\n" : " ");
1218 printk(KERN_DEBUG ".\n");
1224 rhf_addr = (__le32 *) pd->port_rcvhdrq +
1225 l + dd->ipath_rhf_offset;
1226 if (dd->ipath_flags & IPATH_NODMA_RTAIL) {
1227 u32 seq = ipath_hdrget_seq(rhf_addr);
1229 if (++pd->port_seq_cnt > 13)
1230 pd->port_seq_cnt = 1;
1231 if (seq != pd->port_seq_cnt)
1233 } else if (l == hdrqtail)
1236 * update head regs on last packet, and every 16 packets.
1237 * Reduce bus traffic, while still trying to prevent
1238 * rcvhdrq overflows, for when the queue is nearly full
1240 if (last || !(i & 0xf)) {
1243 /* request IBA6120 and 7220 interrupt only on last */
1245 lval |= dd->ipath_rhdrhead_intr_off;
1246 ipath_write_ureg(dd, ur_rcvhdrhead, lval,
1249 ipath_write_ureg(dd, ur_rcvegrindexhead,
1250 etail, pd->port_port);
1256 if (!dd->ipath_rhdrhead_intr_off && !reloop &&
1257 !(dd->ipath_flags & IPATH_NODMA_RTAIL)) {
1258 /* IBA6110 workaround; we can have a race clearing chip
1259 * interrupt with another interrupt about to be delivered,
1260 * and can clear it before it is delivered on the GPIO
1261 * workaround. By doing the extra check here for the
1262 * in-memory tail register updating while we were doing
1263 * earlier packets, we "almost" guarantee we have covered
1266 u32 hqtail = ipath_get_rcvhdrtail(pd);
1267 if (hqtail != hdrqtail) {
1269 reloop = 1; /* loop 1 extra time at most */
1278 if (pkttot > ipath_stats.sps_maxpkts_call)
1279 ipath_stats.sps_maxpkts_call = pkttot;
1280 ipath_stats.sps_port0pkts += pkttot;
1281 ipath_stats.sps_avgpkts_call =
1282 ipath_stats.sps_port0pkts / ++totcalls;
1288 * ipath_update_pio_bufs - update shadow copy of the PIO availability map
1289 * @dd: the infinipath device
1291 * called whenever our local copy indicates we have run out of send buffers
1292 * NOTE: This can be called from interrupt context by some code
1293 * and from non-interrupt context by ipath_getpiobuf().
1296 static void ipath_update_pio_bufs(struct ipath_devdata *dd)
1298 unsigned long flags;
1300 const unsigned piobregs = (unsigned)dd->ipath_pioavregs;
1302 /* If the generation (check) bits have changed, then we update the
1303 * busy bit for the corresponding PIO buffer. This algorithm will
1304 * modify positions to the value they already have in some cases
1305 * (i.e., no change), but it's faster than changing only the bits
1306 * that have changed.
1308 * We would like to do this atomicly, to avoid spinlocks in the
1309 * critical send path, but that's not really possible, given the
1310 * type of changes, and that this routine could be called on
1311 * multiple cpu's simultaneously, so we lock in this routine only,
1312 * to avoid conflicting updates; all we change is the shadow, and
1313 * it's a single 64 bit memory location, so by definition the update
1314 * is atomic in terms of what other cpu's can see in testing the
1315 * bits. The spin_lock overhead isn't too bad, since it only
1316 * happens when all buffers are in use, so only cpu overhead, not
1317 * latency or bandwidth is affected.
1319 if (!dd->ipath_pioavailregs_dma) {
1320 ipath_dbg("Update shadow pioavail, but regs_dma NULL!\n");
1323 if (ipath_debug & __IPATH_VERBDBG) {
1324 /* only if packet debug and verbose */
1325 volatile __le64 *dma = dd->ipath_pioavailregs_dma;
1326 unsigned long *shadow = dd->ipath_pioavailshadow;
1328 ipath_cdbg(PKT, "Refill avail, dma0=%llx shad0=%lx, "
1329 "d1=%llx s1=%lx, d2=%llx s2=%lx, d3=%llx "
1331 (unsigned long long) le64_to_cpu(dma[0]),
1333 (unsigned long long) le64_to_cpu(dma[1]),
1335 (unsigned long long) le64_to_cpu(dma[2]),
1337 (unsigned long long) le64_to_cpu(dma[3]),
1341 PKT, "2nd group, dma4=%llx shad4=%lx, "
1342 "d5=%llx s5=%lx, d6=%llx s6=%lx, "
1344 (unsigned long long) le64_to_cpu(dma[4]),
1346 (unsigned long long) le64_to_cpu(dma[5]),
1348 (unsigned long long) le64_to_cpu(dma[6]),
1350 (unsigned long long) le64_to_cpu(dma[7]),
1353 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1354 for (i = 0; i < piobregs; i++) {
1355 u64 pchbusy, pchg, piov, pnew;
1357 * Chip Errata: bug 6641; even and odd qwords>3 are swapped
1359 if (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS))
1360 piov = le64_to_cpu(dd->ipath_pioavailregs_dma[i ^ 1]);
1362 piov = le64_to_cpu(dd->ipath_pioavailregs_dma[i]);
1363 pchg = dd->ipath_pioavailkernel[i] &
1364 ~(dd->ipath_pioavailshadow[i] ^ piov);
1365 pchbusy = pchg << INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT;
1366 if (pchg && (pchbusy & dd->ipath_pioavailshadow[i])) {
1367 pnew = dd->ipath_pioavailshadow[i] & ~pchbusy;
1368 pnew |= piov & pchbusy;
1369 dd->ipath_pioavailshadow[i] = pnew;
1372 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1376 * ipath_setrcvhdrsize - set the receive header size
1377 * @dd: the infinipath device
1378 * @rhdrsize: the receive header size
1380 * called from user init code, and also layered driver init
1382 int ipath_setrcvhdrsize(struct ipath_devdata *dd, unsigned rhdrsize)
1386 if (dd->ipath_flags & IPATH_RCVHDRSZ_SET) {
1387 if (dd->ipath_rcvhdrsize != rhdrsize) {
1388 dev_info(&dd->pcidev->dev,
1389 "Error: can't set protocol header "
1390 "size %u, already %u\n",
1391 rhdrsize, dd->ipath_rcvhdrsize);
1394 ipath_cdbg(VERBOSE, "Reuse same protocol header "
1395 "size %u\n", dd->ipath_rcvhdrsize);
1396 } else if (rhdrsize > (dd->ipath_rcvhdrentsize -
1397 (sizeof(u64) / sizeof(u32)))) {
1398 ipath_dbg("Error: can't set protocol header size %u "
1399 "(> max %u)\n", rhdrsize,
1400 dd->ipath_rcvhdrentsize -
1401 (u32) (sizeof(u64) / sizeof(u32)));
1404 dd->ipath_flags |= IPATH_RCVHDRSZ_SET;
1405 dd->ipath_rcvhdrsize = rhdrsize;
1406 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
1407 dd->ipath_rcvhdrsize);
1408 ipath_cdbg(VERBOSE, "Set protocol header size to %u\n",
1409 dd->ipath_rcvhdrsize);
1415 * debugging code and stats updates if no pio buffers available.
1417 static noinline void no_pio_bufs(struct ipath_devdata *dd)
1419 unsigned long *shadow = dd->ipath_pioavailshadow;
1420 __le64 *dma = (__le64 *)dd->ipath_pioavailregs_dma;
1422 dd->ipath_upd_pio_shadow = 1;
1425 * not atomic, but if we lose a stat count in a while, that's OK
1427 ipath_stats.sps_nopiobufs++;
1428 if (!(++dd->ipath_consec_nopiobuf % 100000)) {
1429 ipath_dbg("%u pio sends with no bufavail; dmacopy: "
1430 "%llx %llx %llx %llx; shadow: %lx %lx %lx %lx\n",
1431 dd->ipath_consec_nopiobuf,
1432 (unsigned long long) le64_to_cpu(dma[0]),
1433 (unsigned long long) le64_to_cpu(dma[1]),
1434 (unsigned long long) le64_to_cpu(dma[2]),
1435 (unsigned long long) le64_to_cpu(dma[3]),
1436 shadow[0], shadow[1], shadow[2], shadow[3]);
1438 * 4 buffers per byte, 4 registers above, cover rest
1441 if ((dd->ipath_piobcnt2k + dd->ipath_piobcnt4k) >
1442 (sizeof(shadow[0]) * 4 * 4))
1443 ipath_dbg("2nd group: dmacopy: %llx %llx "
1444 "%llx %llx; shadow: %lx %lx %lx %lx\n",
1445 (unsigned long long)le64_to_cpu(dma[4]),
1446 (unsigned long long)le64_to_cpu(dma[5]),
1447 (unsigned long long)le64_to_cpu(dma[6]),
1448 (unsigned long long)le64_to_cpu(dma[7]),
1449 shadow[4], shadow[5], shadow[6],
1455 * common code for normal driver pio buffer allocation, and reserved
1458 * do appropriate marking as busy, etc.
1459 * returns buffer number if one found (>=0), negative number is error.
1461 static u32 __iomem *ipath_getpiobuf_range(struct ipath_devdata *dd,
1462 u32 *pbufnum, u32 first, u32 last, u32 firsti)
1464 int i, j, updated = 0;
1466 unsigned long flags;
1467 unsigned long *shadow = dd->ipath_pioavailshadow;
1470 piobcnt = last - first;
1471 if (dd->ipath_upd_pio_shadow) {
1473 * Minor optimization. If we had no buffers on last call,
1474 * start out by doing the update; continue and do scan even
1475 * if no buffers were updated, to be paranoid
1477 ipath_update_pio_bufs(dd);
1484 * while test_and_set_bit() is atomic, we do that and then the
1485 * change_bit(), and the pair is not. See if this is the cause
1486 * of the remaining armlaunch errors.
1488 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1489 for (j = 0; j < piobcnt; j++, i++) {
1492 if (__test_and_set_bit((2 * i) + 1, shadow))
1494 /* flip generation bit */
1495 __change_bit(2 * i, shadow);
1498 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1503 * first time through; shadow exhausted, but may be
1504 * buffers available, try an update and then rescan.
1506 ipath_update_pio_bufs(dd);
1510 } else if (updated == 1 && piobcnt <=
1511 ((dd->ipath_sendctrl
1512 >> INFINIPATH_S_UPDTHRESH_SHIFT) &
1513 INFINIPATH_S_UPDTHRESH_MASK)) {
1515 * for chips supporting and using the update
1516 * threshold we need to force an update of the
1517 * in-memory copy if the count is less than the
1518 * thershold, then check one more time.
1520 ipath_force_pio_avail_update(dd);
1521 ipath_update_pio_bufs(dd);
1530 if (i < dd->ipath_piobcnt2k)
1531 buf = (u32 __iomem *) (dd->ipath_pio2kbase +
1532 i * dd->ipath_palign);
1534 buf = (u32 __iomem *)
1535 (dd->ipath_pio4kbase +
1536 (i - dd->ipath_piobcnt2k) * dd->ipath_4kalign);
1545 * ipath_getpiobuf - find an available pio buffer
1546 * @dd: the infinipath device
1547 * @plen: the size of the PIO buffer needed in 32-bit words
1548 * @pbufnum: the buffer number is placed here
1550 u32 __iomem *ipath_getpiobuf(struct ipath_devdata *dd, u32 plen, u32 *pbufnum)
1556 if (plen + 1 >= IPATH_SMALLBUF_DWORDS) {
1557 first = dd->ipath_piobcnt2k;
1558 lasti = dd->ipath_lastpioindexl;
1561 lasti = dd->ipath_lastpioindex;
1563 nbufs = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
1564 buf = ipath_getpiobuf_range(dd, &pnum, first, nbufs, lasti);
1568 * Set next starting place. It's just an optimization,
1569 * it doesn't matter who wins on this, so no locking
1571 if (plen + 1 >= IPATH_SMALLBUF_DWORDS)
1572 dd->ipath_lastpioindexl = pnum + 1;
1574 dd->ipath_lastpioindex = pnum + 1;
1575 if (dd->ipath_upd_pio_shadow)
1576 dd->ipath_upd_pio_shadow = 0;
1577 if (dd->ipath_consec_nopiobuf)
1578 dd->ipath_consec_nopiobuf = 0;
1579 ipath_cdbg(VERBOSE, "Return piobuf%u %uk @ %p\n",
1580 pnum, (pnum < dd->ipath_piobcnt2k) ? 2 : 4, buf);
1589 * ipath_chg_pioavailkernel - change which send buffers are available for kernel
1590 * @dd: the infinipath device
1591 * @start: the starting send buffer number
1592 * @len: the number of send buffers
1593 * @avail: true if the buffers are available for kernel use, false otherwise
1595 void ipath_chg_pioavailkernel(struct ipath_devdata *dd, unsigned start,
1596 unsigned len, int avail)
1598 unsigned long flags;
1601 /* There are two bits per send buffer (busy and generation) */
1606 /* Set or clear the generation bits. */
1607 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1608 while (start < end) {
1610 __clear_bit(start + INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT,
1611 dd->ipath_pioavailshadow);
1612 __set_bit(start, dd->ipath_pioavailkernel);
1614 __set_bit(start + INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT,
1615 dd->ipath_pioavailshadow);
1616 __clear_bit(start, dd->ipath_pioavailkernel);
1620 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1624 * ipath_create_rcvhdrq - create a receive header queue
1625 * @dd: the infinipath device
1626 * @pd: the port data
1628 * this must be contiguous memory (from an i/o perspective), and must be
1629 * DMA'able (which means for some systems, it will go through an IOMMU,
1630 * or be forced into a low address range).
1632 int ipath_create_rcvhdrq(struct ipath_devdata *dd,
1633 struct ipath_portdata *pd)
1637 if (!pd->port_rcvhdrq) {
1638 dma_addr_t phys_hdrqtail;
1639 gfp_t gfp_flags = GFP_USER | __GFP_COMP;
1640 int amt = ALIGN(dd->ipath_rcvhdrcnt * dd->ipath_rcvhdrentsize *
1641 sizeof(u32), PAGE_SIZE);
1643 pd->port_rcvhdrq = dma_alloc_coherent(
1644 &dd->pcidev->dev, amt, &pd->port_rcvhdrq_phys,
1647 if (!pd->port_rcvhdrq) {
1648 ipath_dev_err(dd, "attempt to allocate %d bytes "
1649 "for port %u rcvhdrq failed\n",
1650 amt, pd->port_port);
1655 if (!(dd->ipath_flags & IPATH_NODMA_RTAIL)) {
1656 pd->port_rcvhdrtail_kvaddr = dma_alloc_coherent(
1657 &dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail,
1659 if (!pd->port_rcvhdrtail_kvaddr) {
1660 ipath_dev_err(dd, "attempt to allocate 1 page "
1661 "for port %u rcvhdrqtailaddr "
1662 "failed\n", pd->port_port);
1664 dma_free_coherent(&dd->pcidev->dev, amt,
1666 pd->port_rcvhdrq_phys);
1667 pd->port_rcvhdrq = NULL;
1670 pd->port_rcvhdrqtailaddr_phys = phys_hdrqtail;
1671 ipath_cdbg(VERBOSE, "port %d hdrtailaddr, %llx "
1672 "physical\n", pd->port_port,
1673 (unsigned long long) phys_hdrqtail);
1676 pd->port_rcvhdrq_size = amt;
1678 ipath_cdbg(VERBOSE, "%d pages at %p (phys %lx) size=%lu "
1679 "for port %u rcvhdr Q\n",
1680 amt >> PAGE_SHIFT, pd->port_rcvhdrq,
1681 (unsigned long) pd->port_rcvhdrq_phys,
1682 (unsigned long) pd->port_rcvhdrq_size,
1686 ipath_cdbg(VERBOSE, "reuse port %d rcvhdrq @%p %llx phys; "
1687 "hdrtailaddr@%p %llx physical\n",
1688 pd->port_port, pd->port_rcvhdrq,
1689 (unsigned long long) pd->port_rcvhdrq_phys,
1690 pd->port_rcvhdrtail_kvaddr, (unsigned long long)
1691 pd->port_rcvhdrqtailaddr_phys);
1693 /* clear for security and sanity on each use */
1694 memset(pd->port_rcvhdrq, 0, pd->port_rcvhdrq_size);
1695 if (pd->port_rcvhdrtail_kvaddr)
1696 memset(pd->port_rcvhdrtail_kvaddr, 0, PAGE_SIZE);
1699 * tell chip each time we init it, even if we are re-using previous
1700 * memory (we zero the register at process close)
1702 ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdrtailaddr,
1703 pd->port_port, pd->port_rcvhdrqtailaddr_phys);
1704 ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdraddr,
1705 pd->port_port, pd->port_rcvhdrq_phys);
1713 * Flush all sends that might be in the ready to send state, as well as any
1714 * that are in the process of being sent. Used whenever we need to be
1715 * sure the send side is idle. Cleans up all buffer state by canceling
1716 * all pio buffers, and issuing an abort, which cleans up anything in the
1717 * launch fifo. The cancel is superfluous on some chip versions, but
1718 * it's safer to always do it.
1719 * PIOAvail bits are updated by the chip as if normal send had happened.
1721 void ipath_cancel_sends(struct ipath_devdata *dd, int restore_sendctrl)
1723 ipath_dbg("Cancelling all in-progress send buffers\n");
1725 /* skip armlaunch errs for a while */
1726 dd->ipath_lastcancel = jiffies + HZ / 2;
1729 * the abort bit is auto-clearing. We read scratch to be sure
1730 * that cancels and the abort have taken effect in the chip.
1732 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1733 INFINIPATH_S_ABORT);
1734 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1735 ipath_disarm_piobufs(dd, 0,
1736 (unsigned)(dd->ipath_piobcnt2k + dd->ipath_piobcnt4k));
1737 if (restore_sendctrl) /* else done by caller later */
1738 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1739 dd->ipath_sendctrl);
1741 /* and again, be sure all have hit the chip */
1742 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1746 * Force an update of in-memory copy of the pioavail registers, when
1747 * needed for any of a variety of reasons. We read the scratch register
1748 * to make it highly likely that the update will have happened by the
1749 * time we return. If already off (as in cancel_sends above), this
1750 * routine is a nop, on the assumption that the caller will "do the
1753 void ipath_force_pio_avail_update(struct ipath_devdata *dd)
1755 unsigned long flags;
1757 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1758 if (dd->ipath_sendctrl & INFINIPATH_S_PIOBUFAVAILUPD) {
1759 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1760 dd->ipath_sendctrl & ~INFINIPATH_S_PIOBUFAVAILUPD);
1761 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1762 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1763 dd->ipath_sendctrl);
1764 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1766 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1769 static void ipath_set_ib_lstate(struct ipath_devdata *dd, int linkcmd,
1773 static const char *what[4] = {
1775 [INFINIPATH_IBCC_LINKCMD_DOWN] = "DOWN",
1776 [INFINIPATH_IBCC_LINKCMD_ARMED] = "ARMED",
1777 [INFINIPATH_IBCC_LINKCMD_ACTIVE] = "ACTIVE"
1780 if (linitcmd == INFINIPATH_IBCC_LINKINITCMD_DISABLE) {
1782 * If we are told to disable, note that so link-recovery
1783 * code does not attempt to bring us back up.
1786 dd->ipath_flags |= IPATH_IB_LINK_DISABLED;
1788 } else if (linitcmd) {
1790 * Any other linkinitcmd will lead to LINKDOWN and then
1791 * to INIT (if all is well), so clear flag to let
1792 * link-recovery code attempt to bring us back up.
1795 dd->ipath_flags &= ~IPATH_IB_LINK_DISABLED;
1799 mod_wd = (linkcmd << dd->ibcc_lc_shift) |
1800 (linitcmd << INFINIPATH_IBCC_LINKINITCMD_SHIFT);
1802 "Moving unit %u to %s (initcmd=0x%x), current ltstate is %s\n",
1803 dd->ipath_unit, what[linkcmd], linitcmd,
1804 ipath_ibcstatus_str[ipath_ib_linktrstate(dd,
1805 ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus))]);
1807 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
1808 dd->ipath_ibcctrl | mod_wd);
1809 /* read from chip so write is flushed */
1810 (void) ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
1813 int ipath_set_linkstate(struct ipath_devdata *dd, u8 newstate)
1819 case IPATH_IB_LINKDOWN_ONLY:
1820 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN, 0);
1825 case IPATH_IB_LINKDOWN:
1826 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN,
1827 INFINIPATH_IBCC_LINKINITCMD_POLL);
1832 case IPATH_IB_LINKDOWN_SLEEP:
1833 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN,
1834 INFINIPATH_IBCC_LINKINITCMD_SLEEP);
1839 case IPATH_IB_LINKDOWN_DISABLE:
1840 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN,
1841 INFINIPATH_IBCC_LINKINITCMD_DISABLE);
1846 case IPATH_IB_LINKARM:
1847 if (dd->ipath_flags & IPATH_LINKARMED) {
1851 if (!(dd->ipath_flags &
1852 (IPATH_LINKINIT | IPATH_LINKACTIVE))) {
1856 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ARMED, 0);
1859 * Since the port can transition to ACTIVE by receiving
1860 * a non VL 15 packet, wait for either state.
1862 lstate = IPATH_LINKARMED | IPATH_LINKACTIVE;
1865 case IPATH_IB_LINKACTIVE:
1866 if (dd->ipath_flags & IPATH_LINKACTIVE) {
1870 if (!(dd->ipath_flags & IPATH_LINKARMED)) {
1874 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ACTIVE, 0);
1875 lstate = IPATH_LINKACTIVE;
1878 case IPATH_IB_LINK_LOOPBACK:
1879 dev_info(&dd->pcidev->dev, "Enabling IB local loopback\n");
1880 dd->ipath_ibcctrl |= INFINIPATH_IBCC_LOOPBACK;
1881 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
1884 /* turn heartbeat off, as it causes loopback to fail */
1885 dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
1886 IPATH_IB_HRTBT_OFF);
1891 case IPATH_IB_LINK_EXTERNAL:
1892 dev_info(&dd->pcidev->dev,
1893 "Disabling IB local loopback (normal)\n");
1894 dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
1896 dd->ipath_ibcctrl &= ~INFINIPATH_IBCC_LOOPBACK;
1897 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
1904 * Heartbeat can be explicitly enabled by the user via
1905 * "hrtbt_enable" "file", and if disabled, trying to enable here
1906 * will have no effect. Implicit changes (heartbeat off when
1907 * loopback on, and vice versa) are included to ease testing.
1909 case IPATH_IB_LINK_HRTBT:
1910 ret = dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
1914 case IPATH_IB_LINK_NO_HRTBT:
1915 ret = dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
1916 IPATH_IB_HRTBT_OFF);
1920 ipath_dbg("Invalid linkstate 0x%x requested\n", newstate);
1924 ret = ipath_wait_linkstate(dd, lstate, 2000);
1931 * ipath_set_mtu - set the MTU
1932 * @dd: the infinipath device
1935 * we can handle "any" incoming size, the issue here is whether we
1936 * need to restrict our outgoing size. For now, we don't do any
1937 * sanity checking on this, and we don't deal with what happens to
1938 * programs that are already running when the size changes.
1939 * NOTE: changing the MTU will usually cause the IBC to go back to
1940 * link initialize (IPATH_IBSTATE_INIT) state...
1942 int ipath_set_mtu(struct ipath_devdata *dd, u16 arg)
1949 * mtu is IB data payload max. It's the largest power of 2 less
1950 * than piosize (or even larger, since it only really controls the
1951 * largest we can receive; we can send the max of the mtu and
1952 * piosize). We check that it's one of the valid IB sizes.
1954 if (arg != 256 && arg != 512 && arg != 1024 && arg != 2048 &&
1955 (arg != 4096 || !ipath_mtu4096)) {
1956 ipath_dbg("Trying to set invalid mtu %u, failing\n", arg);
1960 if (dd->ipath_ibmtu == arg) {
1961 ret = 0; /* same as current */
1965 piosize = dd->ipath_ibmaxlen;
1966 dd->ipath_ibmtu = arg;
1968 if (arg >= (piosize - IPATH_PIO_MAXIBHDR)) {
1969 /* Only if it's not the initial value (or reset to it) */
1970 if (piosize != dd->ipath_init_ibmaxlen) {
1971 if (arg > piosize && arg <= dd->ipath_init_ibmaxlen)
1972 piosize = dd->ipath_init_ibmaxlen;
1973 dd->ipath_ibmaxlen = piosize;
1976 } else if ((arg + IPATH_PIO_MAXIBHDR) != dd->ipath_ibmaxlen) {
1977 piosize = arg + IPATH_PIO_MAXIBHDR;
1978 ipath_cdbg(VERBOSE, "ibmaxlen was 0x%x, setting to 0x%x "
1979 "(mtu 0x%x)\n", dd->ipath_ibmaxlen, piosize,
1981 dd->ipath_ibmaxlen = piosize;
1986 u64 ibc = dd->ipath_ibcctrl, ibdw;
1988 * update our housekeeping variables, and set IBC max
1989 * size, same as init code; max IBC is max we allow in
1990 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
1992 dd->ipath_ibmaxlen = piosize - 2 * sizeof(u32);
1993 ibdw = (dd->ipath_ibmaxlen >> 2) + 1;
1994 ibc &= ~(INFINIPATH_IBCC_MAXPKTLEN_MASK <<
1995 dd->ibcc_mpl_shift);
1996 ibc |= ibdw << dd->ibcc_mpl_shift;
1997 dd->ipath_ibcctrl = ibc;
1998 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
2000 dd->ipath_f_tidtemplate(dd);
2009 int ipath_set_lid(struct ipath_devdata *dd, u32 arg, u8 lmc)
2011 dd->ipath_lid = arg;
2012 dd->ipath_lmc = lmc;
2019 * ipath_write_kreg_port - write a device's per-port 64-bit kernel register
2020 * @dd: the infinipath device
2021 * @regno: the register number to write
2022 * @port: the port containing the register
2023 * @value: the value to write
2025 * Registers that vary with the chip implementation constants (port)
2028 void ipath_write_kreg_port(const struct ipath_devdata *dd, ipath_kreg regno,
2029 unsigned port, u64 value)
2033 if (port < dd->ipath_portcnt &&
2034 (regno == dd->ipath_kregs->kr_rcvhdraddr ||
2035 regno == dd->ipath_kregs->kr_rcvhdrtailaddr))
2036 where = regno + port;
2040 ipath_write_kreg(dd, where, value);
2044 * Following deal with the "obviously simple" task of overriding the state
2045 * of the LEDS, which normally indicate link physical and logical status.
2046 * The complications arise in dealing with different hardware mappings
2047 * and the board-dependent routine being called from interrupts.
2048 * and then there's the requirement to _flash_ them.
2050 #define LED_OVER_FREQ_SHIFT 8
2051 #define LED_OVER_FREQ_MASK (0xFF<<LED_OVER_FREQ_SHIFT)
2052 /* Below is "non-zero" to force override, but both actual LEDs are off */
2053 #define LED_OVER_BOTH_OFF (8)
2055 static void ipath_run_led_override(unsigned long opaque)
2057 struct ipath_devdata *dd = (struct ipath_devdata *)opaque;
2060 u64 lstate, ltstate, val;
2062 if (!(dd->ipath_flags & IPATH_INITTED))
2065 pidx = dd->ipath_led_override_phase++ & 1;
2066 dd->ipath_led_override = dd->ipath_led_override_vals[pidx];
2067 timeoff = dd->ipath_led_override_timeoff;
2070 * below potentially restores the LED values per current status,
2071 * should also possibly setup the traffic-blink register,
2072 * but leave that to per-chip functions.
2074 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
2075 ltstate = (val >> INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) &
2077 lstate = (val >> dd->ibcs_ls_shift) & INFINIPATH_IBCS_LINKSTATE_MASK;
2079 dd->ipath_f_setextled(dd, lstate, ltstate);
2080 mod_timer(&dd->ipath_led_override_timer, jiffies + timeoff);
2083 void ipath_set_led_override(struct ipath_devdata *dd, unsigned int val)
2087 if (!(dd->ipath_flags & IPATH_INITTED))
2090 /* First check if we are blinking. If not, use 1HZ polling */
2092 freq = (val & LED_OVER_FREQ_MASK) >> LED_OVER_FREQ_SHIFT;
2095 /* For blink, set each phase from one nybble of val */
2096 dd->ipath_led_override_vals[0] = val & 0xF;
2097 dd->ipath_led_override_vals[1] = (val >> 4) & 0xF;
2098 timeoff = (HZ << 4)/freq;
2100 /* Non-blink set both phases the same. */
2101 dd->ipath_led_override_vals[0] = val & 0xF;
2102 dd->ipath_led_override_vals[1] = val & 0xF;
2104 dd->ipath_led_override_timeoff = timeoff;
2107 * If the timer has not already been started, do so. Use a "quick"
2108 * timeout so the function will be called soon, to look at our request.
2110 if (atomic_inc_return(&dd->ipath_led_override_timer_active) == 1) {
2111 /* Need to start timer */
2112 init_timer(&dd->ipath_led_override_timer);
2113 dd->ipath_led_override_timer.function =
2114 ipath_run_led_override;
2115 dd->ipath_led_override_timer.data = (unsigned long) dd;
2116 dd->ipath_led_override_timer.expires = jiffies + 1;
2117 add_timer(&dd->ipath_led_override_timer);
2119 atomic_dec(&dd->ipath_led_override_timer_active);
2123 * ipath_shutdown_device - shut down a device
2124 * @dd: the infinipath device
2126 * This is called to make the device quiet when we are about to
2127 * unload the driver, and also when the device is administratively
2128 * disabled. It does not free any data structures.
2129 * Everything it does has to be setup again by ipath_init_chip(dd,1)
2131 void ipath_shutdown_device(struct ipath_devdata *dd)
2133 unsigned long flags;
2135 ipath_dbg("Shutting down the device\n");
2137 ipath_hol_up(dd); /* make sure user processes aren't suspended */
2139 dd->ipath_flags |= IPATH_LINKUNK;
2140 dd->ipath_flags &= ~(IPATH_INITTED | IPATH_LINKDOWN |
2141 IPATH_LINKINIT | IPATH_LINKARMED |
2143 *dd->ipath_statusp &= ~(IPATH_STATUS_IB_CONF |
2144 IPATH_STATUS_IB_READY);
2146 /* mask interrupts, but not errors */
2147 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
2149 dd->ipath_rcvctrl = 0;
2150 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
2154 * gracefully stop all sends allowing any in progress to trickle out
2157 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
2158 dd->ipath_sendctrl = 0;
2159 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
2161 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
2162 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
2165 * enough for anything that's going to trickle out to have actually
2170 ipath_set_ib_lstate(dd, 0, INFINIPATH_IBCC_LINKINITCMD_DISABLE);
2171 ipath_cancel_sends(dd, 0);
2173 signal_ib_event(dd, IB_EVENT_PORT_ERR);
2176 dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
2177 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
2178 dd->ipath_control | INFINIPATH_C_FREEZEMODE);
2181 * clear SerdesEnable and turn the leds off; do this here because
2182 * we are unloading, so don't count on interrupts to move along
2183 * Turn the LEDs off explictly for the same reason.
2185 dd->ipath_f_quiet_serdes(dd);
2187 /* stop all the timers that might still be running */
2188 del_timer_sync(&dd->ipath_hol_timer);
2189 if (dd->ipath_stats_timer_active) {
2190 del_timer_sync(&dd->ipath_stats_timer);
2191 dd->ipath_stats_timer_active = 0;
2195 * clear all interrupts and errors, so that the next time the driver
2196 * is loaded or device is enabled, we know that whatever is set
2197 * happened while we were unloaded
2199 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
2200 ~0ULL & ~INFINIPATH_HWE_MEMBISTFAILED);
2201 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
2202 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
2204 ipath_cdbg(VERBOSE, "Flush time and errors to EEPROM\n");
2205 ipath_update_eeprom_log(dd);
2209 * ipath_free_pddata - free a port's allocated data
2210 * @dd: the infinipath device
2211 * @pd: the portdata structure
2213 * free up any allocated data for a port
2214 * This should not touch anything that would affect a simultaneous
2215 * re-allocation of port data, because it is called after ipath_mutex
2216 * is released (and can be called from reinit as well).
2217 * It should never change any chip state, or global driver state.
2218 * (The only exception to global state is freeing the port0 port0_skbs.)
2220 void ipath_free_pddata(struct ipath_devdata *dd, struct ipath_portdata *pd)
2225 if (pd->port_rcvhdrq) {
2226 ipath_cdbg(VERBOSE, "free closed port %d rcvhdrq @ %p "
2227 "(size=%lu)\n", pd->port_port, pd->port_rcvhdrq,
2228 (unsigned long) pd->port_rcvhdrq_size);
2229 dma_free_coherent(&dd->pcidev->dev, pd->port_rcvhdrq_size,
2230 pd->port_rcvhdrq, pd->port_rcvhdrq_phys);
2231 pd->port_rcvhdrq = NULL;
2232 if (pd->port_rcvhdrtail_kvaddr) {
2233 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
2234 pd->port_rcvhdrtail_kvaddr,
2235 pd->port_rcvhdrqtailaddr_phys);
2236 pd->port_rcvhdrtail_kvaddr = NULL;
2239 if (pd->port_port && pd->port_rcvegrbuf) {
2242 for (e = 0; e < pd->port_rcvegrbuf_chunks; e++) {
2243 void *base = pd->port_rcvegrbuf[e];
2244 size_t size = pd->port_rcvegrbuf_size;
2246 ipath_cdbg(VERBOSE, "egrbuf free(%p, %lu), "
2247 "chunk %u/%u\n", base,
2248 (unsigned long) size,
2249 e, pd->port_rcvegrbuf_chunks);
2250 dma_free_coherent(&dd->pcidev->dev, size,
2251 base, pd->port_rcvegrbuf_phys[e]);
2253 kfree(pd->port_rcvegrbuf);
2254 pd->port_rcvegrbuf = NULL;
2255 kfree(pd->port_rcvegrbuf_phys);
2256 pd->port_rcvegrbuf_phys = NULL;
2257 pd->port_rcvegrbuf_chunks = 0;
2258 } else if (pd->port_port == 0 && dd->ipath_port0_skbinfo) {
2260 struct ipath_skbinfo *skbinfo = dd->ipath_port0_skbinfo;
2262 dd->ipath_port0_skbinfo = NULL;
2263 ipath_cdbg(VERBOSE, "free closed port %d "
2264 "ipath_port0_skbinfo @ %p\n", pd->port_port,
2266 for (e = 0; e < dd->ipath_p0_rcvegrcnt; e++)
2267 if (skbinfo[e].skb) {
2268 pci_unmap_single(dd->pcidev, skbinfo[e].phys,
2270 PCI_DMA_FROMDEVICE);
2271 dev_kfree_skb(skbinfo[e].skb);
2275 kfree(pd->port_tid_pg_list);
2276 vfree(pd->subport_uregbase);
2277 vfree(pd->subport_rcvegrbuf);
2278 vfree(pd->subport_rcvhdr_base);
2282 static int __init infinipath_init(void)
2286 if (ipath_debug & __IPATH_DBG)
2287 printk(KERN_INFO DRIVER_LOAD_MSG "%s", ib_ipath_version);
2290 * These must be called before the driver is registered with
2291 * the PCI subsystem.
2293 idr_init(&unit_table);
2294 if (!idr_pre_get(&unit_table, GFP_KERNEL)) {
2299 ret = pci_register_driver(&ipath_driver);
2301 printk(KERN_ERR IPATH_DRV_NAME
2302 ": Unable to register driver: error %d\n", -ret);
2306 ret = ipath_init_ipathfs();
2308 printk(KERN_ERR IPATH_DRV_NAME ": Unable to create "
2309 "ipathfs: error %d\n", -ret);
2316 pci_unregister_driver(&ipath_driver);
2319 idr_destroy(&unit_table);
2325 static void __exit infinipath_cleanup(void)
2327 ipath_exit_ipathfs();
2329 ipath_cdbg(VERBOSE, "Unregistering pci driver\n");
2330 pci_unregister_driver(&ipath_driver);
2332 idr_destroy(&unit_table);
2336 * ipath_reset_device - reset the chip if possible
2337 * @unit: the device to reset
2339 * Whether or not reset is successful, we attempt to re-initialize the chip
2340 * (that is, much like a driver unload/reload). We clear the INITTED flag
2341 * so that the various entry points will fail until we reinitialize. For
2342 * now, we only allow this if no user ports are open that use chip resources
2344 int ipath_reset_device(int unit)
2347 struct ipath_devdata *dd = ipath_lookup(unit);
2354 if (atomic_read(&dd->ipath_led_override_timer_active)) {
2355 /* Need to stop LED timer, _then_ shut off LEDs */
2356 del_timer_sync(&dd->ipath_led_override_timer);
2357 atomic_set(&dd->ipath_led_override_timer_active, 0);
2360 /* Shut off LEDs after we are sure timer is not running */
2361 dd->ipath_led_override = LED_OVER_BOTH_OFF;
2362 dd->ipath_f_setextled(dd, 0, 0);
2364 dev_info(&dd->pcidev->dev, "Reset on unit %u requested\n", unit);
2366 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) {
2367 dev_info(&dd->pcidev->dev, "Invalid unit number %u or "
2368 "not initialized or not present\n", unit);
2374 for (i = 1; i < dd->ipath_cfgports; i++) {
2375 if (dd->ipath_pd[i] && dd->ipath_pd[i]->port_cnt) {
2376 ipath_dbg("unit %u port %d is in use "
2377 "(PID %u cmd %s), can't reset\n",
2379 dd->ipath_pd[i]->port_pid,
2380 dd->ipath_pd[i]->port_comm);
2386 dd->ipath_flags &= ~IPATH_INITTED;
2387 ret = dd->ipath_f_reset(dd);
2389 ipath_dbg("reset was not successful\n");
2390 ipath_dbg("Trying to reinitialize unit %u after reset attempt\n",
2392 ret = ipath_init_chip(dd, 1);
2394 ipath_dev_err(dd, "Reinitialize unit %u after "
2395 "reset failed with %d\n", unit, ret);
2397 dev_info(&dd->pcidev->dev, "Reinitialized unit %u after "
2398 "resetting\n", unit);
2405 * send a signal to all the processes that have the driver open
2406 * through the normal interfaces (i.e., everything other than diags
2407 * interface). Returns number of signalled processes.
2409 static int ipath_signal_procs(struct ipath_devdata *dd, int sig)
2411 int i, sub, any = 0;
2416 for (i = 1; i < dd->ipath_cfgports; i++) {
2417 if (!dd->ipath_pd[i] || !dd->ipath_pd[i]->port_cnt ||
2418 !dd->ipath_pd[i]->port_pid)
2420 pid = dd->ipath_pd[i]->port_pid;
2421 dev_info(&dd->pcidev->dev, "context %d in use "
2422 "(PID %u), sending signal %d\n",
2424 kill_proc(pid, sig, 1);
2426 for (sub = 0; sub < INFINIPATH_MAX_SUBPORT; sub++) {
2427 pid = dd->ipath_pd[i]->port_subpid[sub];
2430 dev_info(&dd->pcidev->dev, "sub-context "
2431 "%d:%d in use (PID %u), sending "
2432 "signal %d\n", i, sub, pid, sig);
2433 kill_proc(pid, sig, 1);
2440 static void ipath_hol_signal_down(struct ipath_devdata *dd)
2442 if (ipath_signal_procs(dd, SIGSTOP))
2443 ipath_dbg("Stopped some processes\n");
2444 ipath_cancel_sends(dd, 1);
2448 static void ipath_hol_signal_up(struct ipath_devdata *dd)
2450 if (ipath_signal_procs(dd, SIGCONT))
2451 ipath_dbg("Continued some processes\n");
2455 * link is down, stop any users processes, and flush pending sends
2456 * to prevent HoL blocking, then start the HoL timer that
2457 * periodically continues, then stop procs, so they can detect
2458 * link down if they want, and do something about it.
2459 * Timer may already be running, so use __mod_timer, not add_timer.
2461 void ipath_hol_down(struct ipath_devdata *dd)
2463 dd->ipath_hol_state = IPATH_HOL_DOWN;
2464 ipath_hol_signal_down(dd);
2465 dd->ipath_hol_next = IPATH_HOL_DOWNCONT;
2466 dd->ipath_hol_timer.expires = jiffies +
2467 msecs_to_jiffies(ipath_hol_timeout_ms);
2468 __mod_timer(&dd->ipath_hol_timer, dd->ipath_hol_timer.expires);
2472 * link is up, continue any user processes, and ensure timer
2473 * is a nop, if running. Let timer keep running, if set; it
2474 * will nop when it sees the link is up
2476 void ipath_hol_up(struct ipath_devdata *dd)
2478 ipath_hol_signal_up(dd);
2479 dd->ipath_hol_state = IPATH_HOL_UP;
2483 * toggle the running/not running state of user proceses
2484 * to prevent HoL blocking on chip resources, but still allow
2485 * user processes to do link down special case handling.
2486 * Should only be called via the timer
2488 void ipath_hol_event(unsigned long opaque)
2490 struct ipath_devdata *dd = (struct ipath_devdata *)opaque;
2492 if (dd->ipath_hol_next == IPATH_HOL_DOWNSTOP
2493 && dd->ipath_hol_state != IPATH_HOL_UP) {
2494 dd->ipath_hol_next = IPATH_HOL_DOWNCONT;
2495 ipath_dbg("Stopping processes\n");
2496 ipath_hol_signal_down(dd);
2497 } else { /* may do "extra" if also in ipath_hol_up() */
2498 dd->ipath_hol_next = IPATH_HOL_DOWNSTOP;
2499 ipath_dbg("Continuing processes\n");
2500 ipath_hol_signal_up(dd);
2502 if (dd->ipath_hol_state == IPATH_HOL_UP)
2503 ipath_dbg("link's up, don't resched timer\n");
2505 dd->ipath_hol_timer.expires = jiffies +
2506 msecs_to_jiffies(ipath_hol_timeout_ms);
2507 __mod_timer(&dd->ipath_hol_timer,
2508 dd->ipath_hol_timer.expires);
2512 int ipath_set_rx_pol_inv(struct ipath_devdata *dd, u8 new_pol_inv)
2516 if (new_pol_inv > INFINIPATH_XGXS_RX_POL_MASK)
2518 if (dd->ipath_rx_pol_inv != new_pol_inv) {
2519 dd->ipath_rx_pol_inv = new_pol_inv;
2520 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
2521 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
2522 INFINIPATH_XGXS_RX_POL_SHIFT);
2523 val |= ((u64)dd->ipath_rx_pol_inv) <<
2524 INFINIPATH_XGXS_RX_POL_SHIFT;
2525 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
2531 * Disable and enable the armlaunch error. Used for PIO bandwidth testing on
2532 * the 7220, which is count-based, rather than trigger-based. Safe for the
2533 * driver check, since it's at init. Not completely safe when used for
2534 * user-mode checking, since some error checking can be lost, but not
2535 * particularly risky, and only has problematic side-effects in the face of
2536 * very buggy user code. There is no reference counting, but that's also
2537 * fine, given the intended use.
2539 void ipath_enable_armlaunch(struct ipath_devdata *dd)
2541 dd->ipath_lasterror &= ~INFINIPATH_E_SPIOARMLAUNCH;
2542 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
2543 INFINIPATH_E_SPIOARMLAUNCH);
2544 dd->ipath_errormask |= INFINIPATH_E_SPIOARMLAUNCH;
2545 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
2546 dd->ipath_errormask);
2549 void ipath_disable_armlaunch(struct ipath_devdata *dd)
2551 /* so don't re-enable if already set */
2552 dd->ipath_maskederrs &= ~INFINIPATH_E_SPIOARMLAUNCH;
2553 dd->ipath_errormask &= ~INFINIPATH_E_SPIOARMLAUNCH;
2554 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
2555 dd->ipath_errormask);
2558 module_init(infinipath_init);
2559 module_exit(infinipath_cleanup);