2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/spinlock.h>
35 #include <linux/idr.h>
36 #include <linux/pci.h>
38 #include <linux/delay.h>
39 #include <linux/netdevice.h>
40 #include <linux/vmalloc.h>
42 #include "ipath_kernel.h"
43 #include "ipath_verbs.h"
45 static void ipath_update_pio_bufs(struct ipath_devdata *);
47 const char *ipath_get_unit_name(int unit)
49 static char iname[16];
50 snprintf(iname, sizeof iname, "infinipath%u", unit);
54 #define DRIVER_LOAD_MSG "QLogic " IPATH_DRV_NAME " loaded: "
55 #define PFX IPATH_DRV_NAME ": "
58 * The size has to be longer than this string, so we can append
59 * board/chip information to it in the init code.
61 const char ib_ipath_version[] = IPATH_IDSTR "\n";
63 static struct idr unit_table;
64 DEFINE_SPINLOCK(ipath_devs_lock);
65 LIST_HEAD(ipath_dev_list);
67 wait_queue_head_t ipath_state_wait;
69 unsigned ipath_debug = __IPATH_INFO;
71 module_param_named(debug, ipath_debug, uint, S_IWUSR | S_IRUGO);
72 MODULE_PARM_DESC(debug, "mask for debug prints");
73 EXPORT_SYMBOL_GPL(ipath_debug);
75 unsigned ipath_mtu4096 = 1; /* max 4KB IB mtu by default, if supported */
76 module_param_named(mtu4096, ipath_mtu4096, uint, S_IRUGO);
77 MODULE_PARM_DESC(mtu4096, "enable MTU of 4096 bytes, if supported");
79 static unsigned ipath_hol_timeout_ms = 13000;
80 module_param_named(hol_timeout_ms, ipath_hol_timeout_ms, uint, S_IRUGO);
81 MODULE_PARM_DESC(hol_timeout_ms,
82 "duration of user app suspension after link failure");
84 unsigned ipath_linkrecovery = 1;
85 module_param_named(linkrecovery, ipath_linkrecovery, uint, S_IWUSR | S_IRUGO);
86 MODULE_PARM_DESC(linkrecovery, "enable workaround for link recovery issue");
88 MODULE_LICENSE("GPL");
89 MODULE_AUTHOR("QLogic <support@qlogic.com>");
90 MODULE_DESCRIPTION("QLogic InfiniPath driver");
92 const char *ipath_ibcstatus_str[] = {
99 "LState6", /* unused */
100 "LState7", /* unused */
106 "LState0xD", /* unused */
111 static void __devexit ipath_remove_one(struct pci_dev *);
112 static int __devinit ipath_init_one(struct pci_dev *,
113 const struct pci_device_id *);
115 /* Only needed for registration, nothing else needs this info */
116 #define PCI_VENDOR_ID_PATHSCALE 0x1fc1
117 #define PCI_DEVICE_ID_INFINIPATH_HT 0xd
118 #define PCI_DEVICE_ID_INFINIPATH_PE800 0x10
120 /* Number of seconds before our card status check... */
121 #define STATUS_TIMEOUT 60
123 static const struct pci_device_id ipath_pci_tbl[] = {
124 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_HT) },
125 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_PE800) },
129 MODULE_DEVICE_TABLE(pci, ipath_pci_tbl);
131 static struct pci_driver ipath_driver = {
132 .name = IPATH_DRV_NAME,
133 .probe = ipath_init_one,
134 .remove = __devexit_p(ipath_remove_one),
135 .id_table = ipath_pci_tbl,
137 .groups = ipath_driver_attr_groups,
141 static inline void read_bars(struct ipath_devdata *dd, struct pci_dev *dev,
142 u32 *bar0, u32 *bar1)
146 ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
148 ipath_dev_err(dd, "failed to read bar0 before enable: "
151 ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, bar1);
153 ipath_dev_err(dd, "failed to read bar1 before enable: "
156 ipath_dbg("Read bar0 %x bar1 %x\n", *bar0, *bar1);
159 static void ipath_free_devdata(struct pci_dev *pdev,
160 struct ipath_devdata *dd)
164 pci_set_drvdata(pdev, NULL);
166 if (dd->ipath_unit != -1) {
167 spin_lock_irqsave(&ipath_devs_lock, flags);
168 idr_remove(&unit_table, dd->ipath_unit);
169 list_del(&dd->ipath_list);
170 spin_unlock_irqrestore(&ipath_devs_lock, flags);
175 static struct ipath_devdata *ipath_alloc_devdata(struct pci_dev *pdev)
178 struct ipath_devdata *dd;
181 if (!idr_pre_get(&unit_table, GFP_KERNEL)) {
182 dd = ERR_PTR(-ENOMEM);
186 dd = vmalloc(sizeof(*dd));
188 dd = ERR_PTR(-ENOMEM);
191 memset(dd, 0, sizeof(*dd));
194 spin_lock_irqsave(&ipath_devs_lock, flags);
196 ret = idr_get_new(&unit_table, dd, &dd->ipath_unit);
198 printk(KERN_ERR IPATH_DRV_NAME
199 ": Could not allocate unit ID: error %d\n", -ret);
200 ipath_free_devdata(pdev, dd);
206 pci_set_drvdata(pdev, dd);
208 list_add(&dd->ipath_list, &ipath_dev_list);
211 spin_unlock_irqrestore(&ipath_devs_lock, flags);
217 static inline struct ipath_devdata *__ipath_lookup(int unit)
219 return idr_find(&unit_table, unit);
222 struct ipath_devdata *ipath_lookup(int unit)
224 struct ipath_devdata *dd;
227 spin_lock_irqsave(&ipath_devs_lock, flags);
228 dd = __ipath_lookup(unit);
229 spin_unlock_irqrestore(&ipath_devs_lock, flags);
234 int ipath_count_units(int *npresentp, int *nupp, int *maxportsp)
236 int nunits, npresent, nup;
237 struct ipath_devdata *dd;
241 nunits = npresent = nup = maxports = 0;
243 spin_lock_irqsave(&ipath_devs_lock, flags);
245 list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
247 if ((dd->ipath_flags & IPATH_PRESENT) && dd->ipath_kregbase)
250 !(dd->ipath_flags & (IPATH_DISABLED | IPATH_LINKDOWN
253 if (dd->ipath_cfgports > maxports)
254 maxports = dd->ipath_cfgports;
257 spin_unlock_irqrestore(&ipath_devs_lock, flags);
260 *npresentp = npresent;
264 *maxportsp = maxports;
270 * These next two routines are placeholders in case we don't have per-arch
271 * code for controlling write combining. If explicit control of write
272 * combining is not available, performance will probably be awful.
275 int __attribute__((weak)) ipath_enable_wc(struct ipath_devdata *dd)
280 void __attribute__((weak)) ipath_disable_wc(struct ipath_devdata *dd)
285 * Perform a PIO buffer bandwidth write test, to verify proper system
286 * configuration. Even when all the setup calls work, occasionally
287 * BIOS or other issues can prevent write combining from working, or
288 * can cause other bandwidth problems to the chip.
290 * This test simply writes the same buffer over and over again, and
291 * measures close to the peak bandwidth to the chip (not testing
292 * data bandwidth to the wire). On chips that use an address-based
293 * trigger to send packets to the wire, this is easy. On chips that
294 * use a count to trigger, we want to make sure that the packet doesn't
295 * go out on the wire, or trigger flow control checks.
297 static void ipath_verify_pioperf(struct ipath_devdata *dd)
299 u32 pbnum, cnt, lcnt;
304 piobuf = ipath_getpiobuf(dd, 0, &pbnum);
306 dev_info(&dd->pcidev->dev,
307 "No PIObufs for checking perf, skipping\n");
312 * Enough to give us a reasonable test, less than piobuf size, and
313 * likely multiple of store buffer length.
319 dev_info(&dd->pcidev->dev,
320 "Couldn't get memory for checking PIO perf,"
325 preempt_disable(); /* we want reasonably accurate elapsed time */
326 msecs = 1 + jiffies_to_msecs(jiffies);
327 for (lcnt = 0; lcnt < 10000U; lcnt++) {
328 /* wait until we cross msec boundary */
329 if (jiffies_to_msecs(jiffies) >= msecs)
334 ipath_disable_armlaunch(dd);
336 writeq(0, piobuf); /* length 0, no dwords actually sent */
340 * this is only roughly accurate, since even with preempt we
341 * still take interrupts that could take a while. Running for
342 * >= 5 msec seems to get us "close enough" to accurate values
344 msecs = jiffies_to_msecs(jiffies);
345 for (emsecs = lcnt = 0; emsecs <= 5UL; lcnt++) {
346 __iowrite32_copy(piobuf + 64, addr, cnt >> 2);
347 emsecs = jiffies_to_msecs(jiffies) - msecs;
350 /* 1 GiB/sec, slightly over IB SDR line rate */
351 if (lcnt < (emsecs * 1024U))
353 "Performance problem: bandwidth to PIO buffers is "
355 lcnt / (u32) emsecs);
357 ipath_dbg("PIO buffer bandwidth %u MiB/sec is OK\n",
358 lcnt / (u32) emsecs);
365 /* disarm piobuf, so it's available again */
366 ipath_disarm_piobufs(dd, pbnum, 1);
367 ipath_enable_armlaunch(dd);
370 static int __devinit ipath_init_one(struct pci_dev *pdev,
371 const struct pci_device_id *ent)
374 struct ipath_devdata *dd;
375 unsigned long long addr;
376 u32 bar0 = 0, bar1 = 0;
378 dd = ipath_alloc_devdata(pdev);
381 printk(KERN_ERR IPATH_DRV_NAME
382 ": Could not allocate devdata: error %d\n", -ret);
386 ipath_cdbg(VERBOSE, "initializing unit #%u\n", dd->ipath_unit);
388 ret = pci_enable_device(pdev);
390 /* This can happen iff:
392 * We did a chip reset, and then failed to reprogram the
393 * BAR, or the chip reset due to an internal error. We then
394 * unloaded the driver and reloaded it.
396 * Both reset cases set the BAR back to initial state. For
397 * the latter case, the AER sticky error bit at offset 0x718
398 * should be set, but the Linux kernel doesn't yet know
399 * about that, it appears. If the original BAR was retained
400 * in the kernel data structures, this may be OK.
402 ipath_dev_err(dd, "enable unit %d failed: error %d\n",
403 dd->ipath_unit, -ret);
406 addr = pci_resource_start(pdev, 0);
407 len = pci_resource_len(pdev, 0);
408 ipath_cdbg(VERBOSE, "regbase (0) %llx len %d pdev->irq %d, vend %x/%x "
409 "driver_data %lx\n", addr, len, pdev->irq, ent->vendor,
410 ent->device, ent->driver_data);
412 read_bars(dd, pdev, &bar0, &bar1);
414 if (!bar1 && !(bar0 & ~0xf)) {
416 dev_info(&pdev->dev, "BAR is 0 (probable RESET), "
417 "rewriting as %llx\n", addr);
418 ret = pci_write_config_dword(
419 pdev, PCI_BASE_ADDRESS_0, addr);
421 ipath_dev_err(dd, "rewrite of BAR0 "
422 "failed: err %d\n", -ret);
425 ret = pci_write_config_dword(
426 pdev, PCI_BASE_ADDRESS_1, addr >> 32);
428 ipath_dev_err(dd, "rewrite of BAR1 "
429 "failed: err %d\n", -ret);
433 ipath_dev_err(dd, "BAR is 0 (probable RESET), "
434 "not usable until reboot\n");
440 ret = pci_request_regions(pdev, IPATH_DRV_NAME);
442 dev_info(&pdev->dev, "pci_request_regions unit %u fails: "
443 "err %d\n", dd->ipath_unit, -ret);
447 ret = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
450 * if the 64 bit setup fails, try 32 bit. Some systems
451 * do not setup 64 bit maps on systems with 2GB or less
454 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
457 "Unable to set DMA mask for unit %u: %d\n",
458 dd->ipath_unit, ret);
462 ipath_dbg("No 64bit DMA mask, used 32 bit mask\n");
463 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
466 "Unable to set DMA consistent mask "
468 dd->ipath_unit, ret);
473 ret = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
476 "Unable to set DMA consistent mask "
478 dd->ipath_unit, ret);
481 pci_set_master(pdev);
484 * Save BARs to rewrite after device reset. Save all 64 bits of
487 dd->ipath_pcibar0 = addr;
488 dd->ipath_pcibar1 = addr >> 32;
489 dd->ipath_deviceid = ent->device; /* save for later use */
490 dd->ipath_vendorid = ent->vendor;
492 /* setup the chip-specific functions, as early as possible. */
493 switch (ent->device) {
494 case PCI_DEVICE_ID_INFINIPATH_HT:
496 ipath_init_iba6110_funcs(dd);
499 ipath_dev_err(dd, "QLogic HT device 0x%x cannot work if "
500 "CONFIG_HT_IRQ is not enabled\n", ent->device);
503 case PCI_DEVICE_ID_INFINIPATH_PE800:
504 #ifdef CONFIG_PCI_MSI
505 ipath_init_iba6120_funcs(dd);
508 ipath_dev_err(dd, "QLogic PCIE device 0x%x cannot work if "
509 "CONFIG_PCI_MSI is not enabled\n", ent->device);
513 ipath_dev_err(dd, "Found unknown QLogic deviceid 0x%x, "
514 "failing\n", ent->device);
518 for (j = 0; j < 6; j++) {
519 if (!pdev->resource[j].start)
521 ipath_cdbg(VERBOSE, "BAR %d start %llx, end %llx, len %llx\n",
522 j, (unsigned long long)pdev->resource[j].start,
523 (unsigned long long)pdev->resource[j].end,
524 (unsigned long long)pci_resource_len(pdev, j));
528 ipath_dev_err(dd, "No valid address in BAR 0!\n");
533 dd->ipath_pcirev = pdev->revision;
535 #if defined(__powerpc__)
536 /* There isn't a generic way to specify writethrough mappings */
537 dd->ipath_kregbase = __ioremap(addr, len,
538 (_PAGE_NO_CACHE|_PAGE_WRITETHRU));
540 dd->ipath_kregbase = ioremap_nocache(addr, len);
543 if (!dd->ipath_kregbase) {
544 ipath_dbg("Unable to map io addr %llx to kvirt, failing\n",
549 dd->ipath_kregend = (u64 __iomem *)
550 ((void __iomem *)dd->ipath_kregbase + len);
551 dd->ipath_physaddr = addr; /* used for io_remap, etc. */
553 ipath_cdbg(VERBOSE, "mapped io addr %llx to kregbase %p\n",
554 addr, dd->ipath_kregbase);
557 * clear ipath_flags here instead of in ipath_init_chip as it is set
558 * by ipath_setup_htconfig.
561 dd->ipath_lli_counter = 0;
562 dd->ipath_lli_errors = 0;
564 if (dd->ipath_f_bus(dd, pdev))
565 ipath_dev_err(dd, "Failed to setup config space; "
566 "continuing anyway\n");
569 * set up our interrupt handler; IRQF_SHARED probably not needed,
570 * since MSI interrupts shouldn't be shared but won't hurt for now.
571 * check 0 irq after we return from chip-specific bus setup, since
572 * that can affect this due to setup
575 ipath_dev_err(dd, "irq is 0, BIOS error? Interrupts won't "
578 ret = request_irq(dd->ipath_irq, ipath_intr, IRQF_SHARED,
581 ipath_dev_err(dd, "Couldn't setup irq handler, "
582 "irq=%d: %d\n", dd->ipath_irq, ret);
587 ret = ipath_init_chip(dd, 0); /* do the chip-specific init */
591 ret = ipath_enable_wc(dd);
594 ipath_dev_err(dd, "Write combining not enabled "
595 "(err %d): performance may be poor\n",
600 ipath_verify_pioperf(dd);
602 ipath_device_create_group(&pdev->dev, dd);
603 ipathfs_add_device(dd);
606 ipath_register_ib_device(dd);
612 free_irq(pdev->irq, dd);
615 iounmap((volatile void __iomem *) dd->ipath_kregbase);
618 pci_release_regions(pdev);
621 pci_disable_device(pdev);
624 ipath_free_devdata(pdev, dd);
630 static void __devexit cleanup_device(struct ipath_devdata *dd)
634 if (*dd->ipath_statusp & IPATH_STATUS_CHIP_PRESENT) {
635 /* can't do anything more with chip; needs re-init */
636 *dd->ipath_statusp &= ~IPATH_STATUS_CHIP_PRESENT;
637 if (dd->ipath_kregbase) {
639 * if we haven't already cleaned up before these are
640 * to ensure any register reads/writes "fail" until
643 dd->ipath_kregbase = NULL;
644 dd->ipath_uregbase = 0;
645 dd->ipath_sregbase = 0;
646 dd->ipath_cregbase = 0;
647 dd->ipath_kregsize = 0;
649 ipath_disable_wc(dd);
652 if (dd->ipath_pioavailregs_dma) {
653 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
654 (void *) dd->ipath_pioavailregs_dma,
655 dd->ipath_pioavailregs_phys);
656 dd->ipath_pioavailregs_dma = NULL;
658 if (dd->ipath_dummy_hdrq) {
659 dma_free_coherent(&dd->pcidev->dev,
660 dd->ipath_pd[0]->port_rcvhdrq_size,
661 dd->ipath_dummy_hdrq, dd->ipath_dummy_hdrq_phys);
662 dd->ipath_dummy_hdrq = NULL;
665 if (dd->ipath_pageshadow) {
666 struct page **tmpp = dd->ipath_pageshadow;
667 dma_addr_t *tmpd = dd->ipath_physshadow;
670 ipath_cdbg(VERBOSE, "Unlocking any expTID pages still "
672 for (port = 0; port < dd->ipath_cfgports; port++) {
673 int port_tidbase = port * dd->ipath_rcvtidcnt;
674 int maxtid = port_tidbase + dd->ipath_rcvtidcnt;
675 for (i = port_tidbase; i < maxtid; i++) {
678 pci_unmap_page(dd->pcidev, tmpd[i],
679 PAGE_SIZE, PCI_DMA_FROMDEVICE);
680 ipath_release_user_pages(&tmpp[i], 1);
686 ipath_stats.sps_pageunlocks += cnt;
687 ipath_cdbg(VERBOSE, "There were still %u expTID "
688 "entries locked\n", cnt);
690 if (ipath_stats.sps_pagelocks ||
691 ipath_stats.sps_pageunlocks)
692 ipath_cdbg(VERBOSE, "%llu pages locked, %llu "
693 "unlocked via ipath_m{un}lock\n",
695 ipath_stats.sps_pagelocks,
697 ipath_stats.sps_pageunlocks);
699 ipath_cdbg(VERBOSE, "Free shadow page tid array at %p\n",
700 dd->ipath_pageshadow);
701 tmpp = dd->ipath_pageshadow;
702 dd->ipath_pageshadow = NULL;
705 dd->ipath_egrtidbase = NULL;
709 * free any resources still in use (usually just kernel ports)
710 * at unload; we do for portcnt, not cfgports, because cfgports
711 * could have changed while we were loaded.
713 for (port = 0; port < dd->ipath_portcnt; port++) {
714 struct ipath_portdata *pd = dd->ipath_pd[port];
715 dd->ipath_pd[port] = NULL;
716 ipath_free_pddata(dd, pd);
720 * debuggability, in case some cleanup path tries to use it
726 static void __devexit ipath_remove_one(struct pci_dev *pdev)
728 struct ipath_devdata *dd = pci_get_drvdata(pdev);
730 ipath_cdbg(VERBOSE, "removing, pdev=%p, dd=%p\n", pdev, dd);
733 * disable the IB link early, to be sure no new packets arrive, which
734 * complicates the shutdown process
736 ipath_shutdown_device(dd);
738 flush_scheduled_work();
741 ipath_unregister_ib_device(dd->verbs_dev);
743 ipath_diag_remove(dd);
744 ipath_user_remove(dd);
745 ipathfs_remove_device(dd);
746 ipath_device_remove_group(&pdev->dev, dd);
748 ipath_cdbg(VERBOSE, "Releasing pci memory regions, dd %p, "
749 "unit %u\n", dd, (u32) dd->ipath_unit);
754 * turn off rcv, send, and interrupts for all ports, all drivers
755 * should also hard reset the chip here?
756 * free up port 0 (kernel) rcvhdr, egr bufs, and eventually tid bufs
757 * for all versions of the driver, if they were allocated
760 ipath_cdbg(VERBOSE, "unit %u free irq %d\n",
761 dd->ipath_unit, dd->ipath_irq);
762 dd->ipath_f_free_irq(dd);
764 ipath_dbg("irq is 0, not doing free_irq "
765 "for unit %u\n", dd->ipath_unit);
767 * we check for NULL here, because it's outside
768 * the kregbase check, and we need to call it
769 * after the free_irq. Thus it's possible that
770 * the function pointers were never initialized.
772 if (dd->ipath_f_cleanup)
773 /* clean up chip-specific stuff */
774 dd->ipath_f_cleanup(dd);
776 ipath_cdbg(VERBOSE, "Unmapping kregbase %p\n", dd->ipath_kregbase);
777 iounmap((volatile void __iomem *) dd->ipath_kregbase);
778 pci_release_regions(pdev);
779 ipath_cdbg(VERBOSE, "calling pci_disable_device\n");
780 pci_disable_device(pdev);
782 ipath_free_devdata(pdev, dd);
785 /* general driver use */
786 DEFINE_MUTEX(ipath_mutex);
788 static DEFINE_SPINLOCK(ipath_pioavail_lock);
791 * ipath_disarm_piobufs - cancel a range of PIO buffers
792 * @dd: the infinipath device
793 * @first: the first PIO buffer to cancel
794 * @cnt: the number of PIO buffers to cancel
796 * cancel a range of PIO buffers, used when they might be armed, but
797 * not triggered. Used at init to ensure buffer state, and also user
798 * process close, in case it died while writing to a PIO buffer
801 void ipath_disarm_piobufs(struct ipath_devdata *dd, unsigned first,
804 unsigned i, last = first + cnt;
807 ipath_cdbg(PKT, "disarm %u PIObufs first=%u\n", cnt, first);
808 for (i = first; i < last; i++) {
809 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
811 * The disarm-related bits are write-only, so it
812 * is ok to OR them in with our copy of sendctrl
813 * while we hold the lock.
815 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
816 dd->ipath_sendctrl | INFINIPATH_S_DISARM |
817 (i << INFINIPATH_S_DISARMPIOBUF_SHIFT));
818 /* can't disarm bufs back-to-back per iba7220 spec */
819 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
820 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
822 /* on some older chips, update may not happen after cancel */
823 ipath_force_pio_avail_update(dd);
827 * ipath_wait_linkstate - wait for an IB link state change to occur
828 * @dd: the infinipath device
829 * @state: the state to wait for
830 * @msecs: the number of milliseconds to wait
832 * wait up to msecs milliseconds for IB link state change to occur for
833 * now, take the easy polling route. Currently used only by
834 * ipath_set_linkstate. Returns 0 if state reached, otherwise
835 * -ETIMEDOUT state can have multiple states set, for any of several
838 int ipath_wait_linkstate(struct ipath_devdata *dd, u32 state, int msecs)
840 dd->ipath_state_wanted = state;
841 wait_event_interruptible_timeout(ipath_state_wait,
842 (dd->ipath_flags & state),
843 msecs_to_jiffies(msecs));
844 dd->ipath_state_wanted = 0;
846 if (!(dd->ipath_flags & state)) {
848 ipath_cdbg(VERBOSE, "Didn't reach linkstate %s within %u"
850 /* test INIT ahead of DOWN, both can be set */
851 (state & IPATH_LINKINIT) ? "INIT" :
852 ((state & IPATH_LINKDOWN) ? "DOWN" :
853 ((state & IPATH_LINKARMED) ? "ARM" : "ACTIVE")),
855 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
856 ipath_cdbg(VERBOSE, "ibcc=%llx ibcstatus=%llx (%s)\n",
857 (unsigned long long) ipath_read_kreg64(
858 dd, dd->ipath_kregs->kr_ibcctrl),
859 (unsigned long long) val,
860 ipath_ibcstatus_str[val & 0xf]);
862 return (dd->ipath_flags & state) ? 0 : -ETIMEDOUT;
866 * Decode the error status into strings, deciding whether to always
867 * print * it or not depending on "normal packet errors" vs everything
868 * else. Return 1 if "real" errors, otherwise 0 if only packet
869 * errors, so caller can decide what to print with the string.
871 int ipath_decode_err(char *buf, size_t blen, ipath_err_t err)
875 if (err & INFINIPATH_E_PKTERRS) {
876 if (!(err & ~INFINIPATH_E_PKTERRS))
877 iserr = 0; // if only packet errors.
878 if (ipath_debug & __IPATH_ERRPKTDBG) {
879 if (err & INFINIPATH_E_REBP)
880 strlcat(buf, "EBP ", blen);
881 if (err & INFINIPATH_E_RVCRC)
882 strlcat(buf, "VCRC ", blen);
883 if (err & INFINIPATH_E_RICRC) {
884 strlcat(buf, "CRC ", blen);
885 // clear for check below, so only once
886 err &= INFINIPATH_E_RICRC;
888 if (err & INFINIPATH_E_RSHORTPKTLEN)
889 strlcat(buf, "rshortpktlen ", blen);
890 if (err & INFINIPATH_E_SDROPPEDDATAPKT)
891 strlcat(buf, "sdroppeddatapkt ", blen);
892 if (err & INFINIPATH_E_SPKTLEN)
893 strlcat(buf, "spktlen ", blen);
895 if ((err & INFINIPATH_E_RICRC) &&
896 !(err&(INFINIPATH_E_RVCRC|INFINIPATH_E_REBP)))
897 strlcat(buf, "CRC ", blen);
901 if (err & INFINIPATH_E_RHDRLEN)
902 strlcat(buf, "rhdrlen ", blen);
903 if (err & INFINIPATH_E_RBADTID)
904 strlcat(buf, "rbadtid ", blen);
905 if (err & INFINIPATH_E_RBADVERSION)
906 strlcat(buf, "rbadversion ", blen);
907 if (err & INFINIPATH_E_RHDR)
908 strlcat(buf, "rhdr ", blen);
909 if (err & INFINIPATH_E_RLONGPKTLEN)
910 strlcat(buf, "rlongpktlen ", blen);
911 if (err & INFINIPATH_E_RMAXPKTLEN)
912 strlcat(buf, "rmaxpktlen ", blen);
913 if (err & INFINIPATH_E_RMINPKTLEN)
914 strlcat(buf, "rminpktlen ", blen);
915 if (err & INFINIPATH_E_SMINPKTLEN)
916 strlcat(buf, "sminpktlen ", blen);
917 if (err & INFINIPATH_E_RFORMATERR)
918 strlcat(buf, "rformaterr ", blen);
919 if (err & INFINIPATH_E_RUNSUPVL)
920 strlcat(buf, "runsupvl ", blen);
921 if (err & INFINIPATH_E_RUNEXPCHAR)
922 strlcat(buf, "runexpchar ", blen);
923 if (err & INFINIPATH_E_RIBFLOW)
924 strlcat(buf, "ribflow ", blen);
925 if (err & INFINIPATH_E_SUNDERRUN)
926 strlcat(buf, "sunderrun ", blen);
927 if (err & INFINIPATH_E_SPIOARMLAUNCH)
928 strlcat(buf, "spioarmlaunch ", blen);
929 if (err & INFINIPATH_E_SUNEXPERRPKTNUM)
930 strlcat(buf, "sunexperrpktnum ", blen);
931 if (err & INFINIPATH_E_SDROPPEDSMPPKT)
932 strlcat(buf, "sdroppedsmppkt ", blen);
933 if (err & INFINIPATH_E_SMAXPKTLEN)
934 strlcat(buf, "smaxpktlen ", blen);
935 if (err & INFINIPATH_E_SUNSUPVL)
936 strlcat(buf, "sunsupVL ", blen);
937 if (err & INFINIPATH_E_INVALIDADDR)
938 strlcat(buf, "invalidaddr ", blen);
939 if (err & INFINIPATH_E_RRCVEGRFULL)
940 strlcat(buf, "rcvegrfull ", blen);
941 if (err & INFINIPATH_E_RRCVHDRFULL)
942 strlcat(buf, "rcvhdrfull ", blen);
943 if (err & INFINIPATH_E_IBSTATUSCHANGED)
944 strlcat(buf, "ibcstatuschg ", blen);
945 if (err & INFINIPATH_E_RIBLOSTLINK)
946 strlcat(buf, "riblostlink ", blen);
947 if (err & INFINIPATH_E_HARDWARE)
948 strlcat(buf, "hardware ", blen);
949 if (err & INFINIPATH_E_RESET)
950 strlcat(buf, "reset ", blen);
956 * get_rhf_errstring - decode RHF errors
957 * @err: the err number
958 * @msg: the output buffer
959 * @len: the length of the output buffer
961 * only used one place now, may want more later
963 static void get_rhf_errstring(u32 err, char *msg, size_t len)
965 /* if no errors, and so don't need to check what's first */
968 if (err & INFINIPATH_RHF_H_ICRCERR)
969 strlcat(msg, "icrcerr ", len);
970 if (err & INFINIPATH_RHF_H_VCRCERR)
971 strlcat(msg, "vcrcerr ", len);
972 if (err & INFINIPATH_RHF_H_PARITYERR)
973 strlcat(msg, "parityerr ", len);
974 if (err & INFINIPATH_RHF_H_LENERR)
975 strlcat(msg, "lenerr ", len);
976 if (err & INFINIPATH_RHF_H_MTUERR)
977 strlcat(msg, "mtuerr ", len);
978 if (err & INFINIPATH_RHF_H_IHDRERR)
979 /* infinipath hdr checksum error */
980 strlcat(msg, "ipathhdrerr ", len);
981 if (err & INFINIPATH_RHF_H_TIDERR)
982 strlcat(msg, "tiderr ", len);
983 if (err & INFINIPATH_RHF_H_MKERR)
984 /* bad port, offset, etc. */
985 strlcat(msg, "invalid ipathhdr ", len);
986 if (err & INFINIPATH_RHF_H_IBERR)
987 strlcat(msg, "iberr ", len);
988 if (err & INFINIPATH_RHF_L_SWA)
989 strlcat(msg, "swA ", len);
990 if (err & INFINIPATH_RHF_L_SWB)
991 strlcat(msg, "swB ", len);
995 * ipath_get_egrbuf - get an eager buffer
996 * @dd: the infinipath device
997 * @bufnum: the eager buffer to get
999 * must only be called if ipath_pd[port] is known to be allocated
1001 static inline void *ipath_get_egrbuf(struct ipath_devdata *dd, u32 bufnum)
1003 return dd->ipath_port0_skbinfo ?
1004 (void *) dd->ipath_port0_skbinfo[bufnum].skb->data : NULL;
1008 * ipath_alloc_skb - allocate an skb and buffer with possible constraints
1009 * @dd: the infinipath device
1010 * @gfp_mask: the sk_buff SFP mask
1012 struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd,
1015 struct sk_buff *skb;
1019 * Only fully supported way to handle this is to allocate lots
1020 * extra, align as needed, and then do skb_reserve(). That wastes
1021 * a lot of memory... I'll have to hack this into infinipath_copy
1026 * We need 2 extra bytes for ipath_ether data sent in the
1027 * key header. In order to keep everything dword aligned,
1028 * we'll reserve 4 bytes.
1030 len = dd->ipath_ibmaxlen + 4;
1032 if (dd->ipath_flags & IPATH_4BYTE_TID) {
1033 /* We need a 2KB multiple alignment, and there is no way
1034 * to do it except to allocate extra and then skb_reserve
1035 * enough to bring it up to the right alignment.
1040 skb = __dev_alloc_skb(len, gfp_mask);
1042 ipath_dev_err(dd, "Failed to allocate skbuff, length %u\n",
1047 skb_reserve(skb, 4);
1049 if (dd->ipath_flags & IPATH_4BYTE_TID) {
1050 u32 una = (unsigned long)skb->data & 2047;
1052 skb_reserve(skb, 2048 - una);
1059 static void ipath_rcv_hdrerr(struct ipath_devdata *dd,
1064 struct ipath_message_header *hdr)
1068 get_rhf_errstring(eflags, emsg, sizeof emsg);
1069 ipath_cdbg(PKT, "RHFerrs %x hdrqtail=%x typ=%u "
1070 "tlen=%x opcode=%x egridx=%x: %s\n",
1072 ipath_hdrget_rcv_type(rhf_addr),
1073 ipath_hdrget_length_in_bytes(rhf_addr),
1074 be32_to_cpu(hdr->bth[0]) >> 24,
1077 /* Count local link integrity errors. */
1078 if (eflags & (INFINIPATH_RHF_H_ICRCERR | INFINIPATH_RHF_H_VCRCERR)) {
1079 u8 n = (dd->ipath_ibcctrl >>
1080 INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT) &
1081 INFINIPATH_IBCC_PHYERRTHRESHOLD_MASK;
1083 if (++dd->ipath_lli_counter > n) {
1084 dd->ipath_lli_counter = 0;
1085 dd->ipath_lli_errors++;
1091 * ipath_kreceive - receive a packet
1092 * @pd: the infinipath port
1094 * called from interrupt handler for errors or receive interrupt
1096 void ipath_kreceive(struct ipath_portdata *pd)
1098 struct ipath_devdata *dd = pd->port_dd;
1101 const u32 rsize = dd->ipath_rcvhdrentsize; /* words */
1102 const u32 maxcnt = dd->ipath_rcvhdrcnt * rsize; /* words */
1103 u32 etail = -1, l, hdrqtail;
1104 struct ipath_message_header *hdr;
1105 u32 eflags, i, etype, tlen, pkttot = 0, updegr = 0, reloop = 0;
1106 static u64 totcalls; /* stats, may eventually remove */
1110 rhf_addr = (__le32 *) pd->port_rcvhdrq + l + dd->ipath_rhf_offset;
1111 if (dd->ipath_flags & IPATH_NODMA_RTAIL) {
1112 u32 seq = ipath_hdrget_seq(rhf_addr);
1114 if (seq != pd->port_seq_cnt)
1118 hdrqtail = ipath_get_rcvhdrtail(pd);
1125 for (last = 0, i = 1; !last; i++) {
1126 hdr = dd->ipath_f_get_msgheader(dd, rhf_addr);
1127 eflags = ipath_hdrget_err_flags(rhf_addr);
1128 etype = ipath_hdrget_rcv_type(rhf_addr);
1130 tlen = ipath_hdrget_length_in_bytes(rhf_addr);
1132 if ((dd->ipath_flags & IPATH_NODMA_RTAIL) ?
1133 ipath_hdrget_use_egr_buf(rhf_addr) :
1134 (etype != RCVHQ_RCV_TYPE_EXPECTED)) {
1136 * It turns out that the chip uses an eager buffer
1137 * for all non-expected packets, whether it "needs"
1138 * one or not. So always get the index, but don't
1139 * set ebuf (so we try to copy data) unless the
1140 * length requires it.
1142 etail = ipath_hdrget_index(rhf_addr);
1144 if (tlen > sizeof(*hdr) ||
1145 etype == RCVHQ_RCV_TYPE_NON_KD)
1146 ebuf = ipath_get_egrbuf(dd, etail);
1150 * both tiderr and ipathhdrerr are set for all plain IB
1151 * packets; only ipathhdrerr should be set.
1154 if (etype != RCVHQ_RCV_TYPE_NON_KD &&
1155 etype != RCVHQ_RCV_TYPE_ERROR &&
1156 ipath_hdrget_ipath_ver(hdr->iph.ver_port_tid_offset) !=
1158 ipath_cdbg(PKT, "Bad InfiniPath protocol version "
1161 if (unlikely(eflags))
1162 ipath_rcv_hdrerr(dd, eflags, l, etail, rhf_addr, hdr);
1163 else if (etype == RCVHQ_RCV_TYPE_NON_KD) {
1164 ipath_ib_rcv(dd->verbs_dev, (u32 *)hdr, ebuf, tlen);
1165 if (dd->ipath_lli_counter)
1166 dd->ipath_lli_counter--;
1167 } else if (etype == RCVHQ_RCV_TYPE_EAGER) {
1168 u8 opcode = be32_to_cpu(hdr->bth[0]) >> 24;
1169 u32 qp = be32_to_cpu(hdr->bth[1]) & 0xffffff;
1170 ipath_cdbg(PKT, "typ %x, opcode %x (eager, "
1171 "qp=%x), len %x; ignored\n",
1172 etype, opcode, qp, tlen);
1174 else if (etype == RCVHQ_RCV_TYPE_EXPECTED)
1175 ipath_dbg("Bug: Expected TID, opcode %x; ignored\n",
1176 be32_to_cpu(hdr->bth[0]) >> 24);
1179 * error packet, type of error unknown.
1180 * Probably type 3, but we don't know, so don't
1181 * even try to print the opcode, etc.
1182 * Usually caused by a "bad packet", that has no
1183 * BTH, when the LRH says it should.
1185 ipath_cdbg(ERRPKT, "Error Pkt, but no eflags! egrbuf"
1186 " %x, len %x hdrq+%x rhf: %Lx\n",
1188 le64_to_cpu(*(__le64 *) rhf_addr));
1189 if (ipath_debug & __IPATH_ERRPKTDBG) {
1190 u32 j, *d, dw = rsize-2;
1191 if (rsize > (tlen>>2))
1194 printk(KERN_DEBUG "EPkt rcvhdr(%x dw):\n",
1196 for (j = 0; j < dw; j++)
1197 printk(KERN_DEBUG "%8x%s", d[j],
1198 (j%8) == 7 ? "\n" : " ");
1199 printk(KERN_DEBUG ".\n");
1205 rhf_addr = (__le32 *) pd->port_rcvhdrq +
1206 l + dd->ipath_rhf_offset;
1207 if (dd->ipath_flags & IPATH_NODMA_RTAIL) {
1208 u32 seq = ipath_hdrget_seq(rhf_addr);
1210 if (++pd->port_seq_cnt > 13)
1211 pd->port_seq_cnt = 1;
1212 if (seq != pd->port_seq_cnt)
1214 } else if (l == hdrqtail)
1217 * update head regs on last packet, and every 16 packets.
1218 * Reduce bus traffic, while still trying to prevent
1219 * rcvhdrq overflows, for when the queue is nearly full
1221 if (last || !(i & 0xf)) {
1224 /* request IBA6120 and 7220 interrupt only on last */
1226 lval |= dd->ipath_rhdrhead_intr_off;
1227 ipath_write_ureg(dd, ur_rcvhdrhead, lval,
1230 ipath_write_ureg(dd, ur_rcvegrindexhead,
1231 etail, pd->port_port);
1237 if (!dd->ipath_rhdrhead_intr_off && !reloop &&
1238 !(dd->ipath_flags & IPATH_NODMA_RTAIL)) {
1239 /* IBA6110 workaround; we can have a race clearing chip
1240 * interrupt with another interrupt about to be delivered,
1241 * and can clear it before it is delivered on the GPIO
1242 * workaround. By doing the extra check here for the
1243 * in-memory tail register updating while we were doing
1244 * earlier packets, we "almost" guarantee we have covered
1247 u32 hqtail = ipath_get_rcvhdrtail(pd);
1248 if (hqtail != hdrqtail) {
1250 reloop = 1; /* loop 1 extra time at most */
1259 if (pkttot > ipath_stats.sps_maxpkts_call)
1260 ipath_stats.sps_maxpkts_call = pkttot;
1261 ipath_stats.sps_port0pkts += pkttot;
1262 ipath_stats.sps_avgpkts_call =
1263 ipath_stats.sps_port0pkts / ++totcalls;
1269 * ipath_update_pio_bufs - update shadow copy of the PIO availability map
1270 * @dd: the infinipath device
1272 * called whenever our local copy indicates we have run out of send buffers
1273 * NOTE: This can be called from interrupt context by some code
1274 * and from non-interrupt context by ipath_getpiobuf().
1277 static void ipath_update_pio_bufs(struct ipath_devdata *dd)
1279 unsigned long flags;
1281 const unsigned piobregs = (unsigned)dd->ipath_pioavregs;
1283 /* If the generation (check) bits have changed, then we update the
1284 * busy bit for the corresponding PIO buffer. This algorithm will
1285 * modify positions to the value they already have in some cases
1286 * (i.e., no change), but it's faster than changing only the bits
1287 * that have changed.
1289 * We would like to do this atomicly, to avoid spinlocks in the
1290 * critical send path, but that's not really possible, given the
1291 * type of changes, and that this routine could be called on
1292 * multiple cpu's simultaneously, so we lock in this routine only,
1293 * to avoid conflicting updates; all we change is the shadow, and
1294 * it's a single 64 bit memory location, so by definition the update
1295 * is atomic in terms of what other cpu's can see in testing the
1296 * bits. The spin_lock overhead isn't too bad, since it only
1297 * happens when all buffers are in use, so only cpu overhead, not
1298 * latency or bandwidth is affected.
1300 if (!dd->ipath_pioavailregs_dma) {
1301 ipath_dbg("Update shadow pioavail, but regs_dma NULL!\n");
1304 if (ipath_debug & __IPATH_VERBDBG) {
1305 /* only if packet debug and verbose */
1306 volatile __le64 *dma = dd->ipath_pioavailregs_dma;
1307 unsigned long *shadow = dd->ipath_pioavailshadow;
1309 ipath_cdbg(PKT, "Refill avail, dma0=%llx shad0=%lx, "
1310 "d1=%llx s1=%lx, d2=%llx s2=%lx, d3=%llx "
1312 (unsigned long long) le64_to_cpu(dma[0]),
1314 (unsigned long long) le64_to_cpu(dma[1]),
1316 (unsigned long long) le64_to_cpu(dma[2]),
1318 (unsigned long long) le64_to_cpu(dma[3]),
1322 PKT, "2nd group, dma4=%llx shad4=%lx, "
1323 "d5=%llx s5=%lx, d6=%llx s6=%lx, "
1325 (unsigned long long) le64_to_cpu(dma[4]),
1327 (unsigned long long) le64_to_cpu(dma[5]),
1329 (unsigned long long) le64_to_cpu(dma[6]),
1331 (unsigned long long) le64_to_cpu(dma[7]),
1334 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1335 for (i = 0; i < piobregs; i++) {
1336 u64 pchbusy, pchg, piov, pnew;
1338 * Chip Errata: bug 6641; even and odd qwords>3 are swapped
1340 if (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS))
1341 piov = le64_to_cpu(dd->ipath_pioavailregs_dma[i ^ 1]);
1343 piov = le64_to_cpu(dd->ipath_pioavailregs_dma[i]);
1344 pchg = dd->ipath_pioavailkernel[i] &
1345 ~(dd->ipath_pioavailshadow[i] ^ piov);
1346 pchbusy = pchg << INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT;
1347 if (pchg && (pchbusy & dd->ipath_pioavailshadow[i])) {
1348 pnew = dd->ipath_pioavailshadow[i] & ~pchbusy;
1349 pnew |= piov & pchbusy;
1350 dd->ipath_pioavailshadow[i] = pnew;
1353 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1357 * ipath_setrcvhdrsize - set the receive header size
1358 * @dd: the infinipath device
1359 * @rhdrsize: the receive header size
1361 * called from user init code, and also layered driver init
1363 int ipath_setrcvhdrsize(struct ipath_devdata *dd, unsigned rhdrsize)
1367 if (dd->ipath_flags & IPATH_RCVHDRSZ_SET) {
1368 if (dd->ipath_rcvhdrsize != rhdrsize) {
1369 dev_info(&dd->pcidev->dev,
1370 "Error: can't set protocol header "
1371 "size %u, already %u\n",
1372 rhdrsize, dd->ipath_rcvhdrsize);
1375 ipath_cdbg(VERBOSE, "Reuse same protocol header "
1376 "size %u\n", dd->ipath_rcvhdrsize);
1377 } else if (rhdrsize > (dd->ipath_rcvhdrentsize -
1378 (sizeof(u64) / sizeof(u32)))) {
1379 ipath_dbg("Error: can't set protocol header size %u "
1380 "(> max %u)\n", rhdrsize,
1381 dd->ipath_rcvhdrentsize -
1382 (u32) (sizeof(u64) / sizeof(u32)));
1385 dd->ipath_flags |= IPATH_RCVHDRSZ_SET;
1386 dd->ipath_rcvhdrsize = rhdrsize;
1387 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
1388 dd->ipath_rcvhdrsize);
1389 ipath_cdbg(VERBOSE, "Set protocol header size to %u\n",
1390 dd->ipath_rcvhdrsize);
1396 * debugging code and stats updates if no pio buffers available.
1398 static noinline void no_pio_bufs(struct ipath_devdata *dd)
1400 unsigned long *shadow = dd->ipath_pioavailshadow;
1401 __le64 *dma = (__le64 *)dd->ipath_pioavailregs_dma;
1403 dd->ipath_upd_pio_shadow = 1;
1406 * not atomic, but if we lose a stat count in a while, that's OK
1408 ipath_stats.sps_nopiobufs++;
1409 if (!(++dd->ipath_consec_nopiobuf % 100000)) {
1410 ipath_dbg("%u pio sends with no bufavail; dmacopy: "
1411 "%llx %llx %llx %llx; shadow: %lx %lx %lx %lx\n",
1412 dd->ipath_consec_nopiobuf,
1413 (unsigned long long) le64_to_cpu(dma[0]),
1414 (unsigned long long) le64_to_cpu(dma[1]),
1415 (unsigned long long) le64_to_cpu(dma[2]),
1416 (unsigned long long) le64_to_cpu(dma[3]),
1417 shadow[0], shadow[1], shadow[2], shadow[3]);
1419 * 4 buffers per byte, 4 registers above, cover rest
1422 if ((dd->ipath_piobcnt2k + dd->ipath_piobcnt4k) >
1423 (sizeof(shadow[0]) * 4 * 4))
1424 ipath_dbg("2nd group: dmacopy: %llx %llx "
1425 "%llx %llx; shadow: %lx %lx %lx %lx\n",
1426 (unsigned long long)le64_to_cpu(dma[4]),
1427 (unsigned long long)le64_to_cpu(dma[5]),
1428 (unsigned long long)le64_to_cpu(dma[6]),
1429 (unsigned long long)le64_to_cpu(dma[7]),
1430 shadow[4], shadow[5], shadow[6],
1436 * common code for normal driver pio buffer allocation, and reserved
1439 * do appropriate marking as busy, etc.
1440 * returns buffer number if one found (>=0), negative number is error.
1442 static u32 __iomem *ipath_getpiobuf_range(struct ipath_devdata *dd,
1443 u32 *pbufnum, u32 first, u32 last, u32 firsti)
1445 int i, j, updated = 0;
1447 unsigned long flags;
1448 unsigned long *shadow = dd->ipath_pioavailshadow;
1451 piobcnt = last - first;
1452 if (dd->ipath_upd_pio_shadow) {
1454 * Minor optimization. If we had no buffers on last call,
1455 * start out by doing the update; continue and do scan even
1456 * if no buffers were updated, to be paranoid
1458 ipath_update_pio_bufs(dd);
1465 * while test_and_set_bit() is atomic, we do that and then the
1466 * change_bit(), and the pair is not. See if this is the cause
1467 * of the remaining armlaunch errors.
1469 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1470 for (j = 0; j < piobcnt; j++, i++) {
1473 if (__test_and_set_bit((2 * i) + 1, shadow))
1475 /* flip generation bit */
1476 __change_bit(2 * i, shadow);
1479 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1484 * first time through; shadow exhausted, but may be
1485 * buffers available, try an update and then rescan.
1487 ipath_update_pio_bufs(dd);
1491 } else if (updated == 1 && piobcnt <=
1492 ((dd->ipath_sendctrl
1493 >> INFINIPATH_S_UPDTHRESH_SHIFT) &
1494 INFINIPATH_S_UPDTHRESH_MASK)) {
1496 * for chips supporting and using the update
1497 * threshold we need to force an update of the
1498 * in-memory copy if the count is less than the
1499 * thershold, then check one more time.
1501 ipath_force_pio_avail_update(dd);
1502 ipath_update_pio_bufs(dd);
1511 if (i < dd->ipath_piobcnt2k)
1512 buf = (u32 __iomem *) (dd->ipath_pio2kbase +
1513 i * dd->ipath_palign);
1515 buf = (u32 __iomem *)
1516 (dd->ipath_pio4kbase +
1517 (i - dd->ipath_piobcnt2k) * dd->ipath_4kalign);
1526 * ipath_getpiobuf - find an available pio buffer
1527 * @dd: the infinipath device
1528 * @plen: the size of the PIO buffer needed in 32-bit words
1529 * @pbufnum: the buffer number is placed here
1531 u32 __iomem *ipath_getpiobuf(struct ipath_devdata *dd, u32 plen, u32 *pbufnum)
1537 if (plen + 1 >= IPATH_SMALLBUF_DWORDS) {
1538 first = dd->ipath_piobcnt2k;
1539 lasti = dd->ipath_lastpioindexl;
1542 lasti = dd->ipath_lastpioindex;
1544 nbufs = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
1545 buf = ipath_getpiobuf_range(dd, &pnum, first, nbufs, lasti);
1549 * Set next starting place. It's just an optimization,
1550 * it doesn't matter who wins on this, so no locking
1552 if (plen + 1 >= IPATH_SMALLBUF_DWORDS)
1553 dd->ipath_lastpioindexl = pnum + 1;
1555 dd->ipath_lastpioindex = pnum + 1;
1556 if (dd->ipath_upd_pio_shadow)
1557 dd->ipath_upd_pio_shadow = 0;
1558 if (dd->ipath_consec_nopiobuf)
1559 dd->ipath_consec_nopiobuf = 0;
1560 ipath_cdbg(VERBOSE, "Return piobuf%u %uk @ %p\n",
1561 pnum, (pnum < dd->ipath_piobcnt2k) ? 2 : 4, buf);
1570 * ipath_chg_pioavailkernel - change which send buffers are available for kernel
1571 * @dd: the infinipath device
1572 * @start: the starting send buffer number
1573 * @len: the number of send buffers
1574 * @avail: true if the buffers are available for kernel use, false otherwise
1576 void ipath_chg_pioavailkernel(struct ipath_devdata *dd, unsigned start,
1577 unsigned len, int avail)
1579 unsigned long flags;
1582 /* There are two bits per send buffer (busy and generation) */
1587 /* Set or clear the generation bits. */
1588 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1589 while (start < end) {
1591 __clear_bit(start + INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT,
1592 dd->ipath_pioavailshadow);
1593 __set_bit(start, dd->ipath_pioavailkernel);
1595 __set_bit(start + INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT,
1596 dd->ipath_pioavailshadow);
1597 __clear_bit(start, dd->ipath_pioavailkernel);
1601 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1605 * ipath_create_rcvhdrq - create a receive header queue
1606 * @dd: the infinipath device
1607 * @pd: the port data
1609 * this must be contiguous memory (from an i/o perspective), and must be
1610 * DMA'able (which means for some systems, it will go through an IOMMU,
1611 * or be forced into a low address range).
1613 int ipath_create_rcvhdrq(struct ipath_devdata *dd,
1614 struct ipath_portdata *pd)
1618 if (!pd->port_rcvhdrq) {
1619 dma_addr_t phys_hdrqtail;
1620 gfp_t gfp_flags = GFP_USER | __GFP_COMP;
1621 int amt = ALIGN(dd->ipath_rcvhdrcnt * dd->ipath_rcvhdrentsize *
1622 sizeof(u32), PAGE_SIZE);
1624 pd->port_rcvhdrq = dma_alloc_coherent(
1625 &dd->pcidev->dev, amt, &pd->port_rcvhdrq_phys,
1628 if (!pd->port_rcvhdrq) {
1629 ipath_dev_err(dd, "attempt to allocate %d bytes "
1630 "for port %u rcvhdrq failed\n",
1631 amt, pd->port_port);
1636 if (!(dd->ipath_flags & IPATH_NODMA_RTAIL)) {
1637 pd->port_rcvhdrtail_kvaddr = dma_alloc_coherent(
1638 &dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail,
1640 if (!pd->port_rcvhdrtail_kvaddr) {
1641 ipath_dev_err(dd, "attempt to allocate 1 page "
1642 "for port %u rcvhdrqtailaddr "
1643 "failed\n", pd->port_port);
1645 dma_free_coherent(&dd->pcidev->dev, amt,
1647 pd->port_rcvhdrq_phys);
1648 pd->port_rcvhdrq = NULL;
1651 pd->port_rcvhdrqtailaddr_phys = phys_hdrqtail;
1652 ipath_cdbg(VERBOSE, "port %d hdrtailaddr, %llx "
1653 "physical\n", pd->port_port,
1654 (unsigned long long) phys_hdrqtail);
1657 pd->port_rcvhdrq_size = amt;
1659 ipath_cdbg(VERBOSE, "%d pages at %p (phys %lx) size=%lu "
1660 "for port %u rcvhdr Q\n",
1661 amt >> PAGE_SHIFT, pd->port_rcvhdrq,
1662 (unsigned long) pd->port_rcvhdrq_phys,
1663 (unsigned long) pd->port_rcvhdrq_size,
1667 ipath_cdbg(VERBOSE, "reuse port %d rcvhdrq @%p %llx phys; "
1668 "hdrtailaddr@%p %llx physical\n",
1669 pd->port_port, pd->port_rcvhdrq,
1670 (unsigned long long) pd->port_rcvhdrq_phys,
1671 pd->port_rcvhdrtail_kvaddr, (unsigned long long)
1672 pd->port_rcvhdrqtailaddr_phys);
1674 /* clear for security and sanity on each use */
1675 memset(pd->port_rcvhdrq, 0, pd->port_rcvhdrq_size);
1676 if (pd->port_rcvhdrtail_kvaddr)
1677 memset(pd->port_rcvhdrtail_kvaddr, 0, PAGE_SIZE);
1680 * tell chip each time we init it, even if we are re-using previous
1681 * memory (we zero the register at process close)
1683 ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdrtailaddr,
1684 pd->port_port, pd->port_rcvhdrqtailaddr_phys);
1685 ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdraddr,
1686 pd->port_port, pd->port_rcvhdrq_phys);
1694 * Flush all sends that might be in the ready to send state, as well as any
1695 * that are in the process of being sent. Used whenever we need to be
1696 * sure the send side is idle. Cleans up all buffer state by canceling
1697 * all pio buffers, and issuing an abort, which cleans up anything in the
1698 * launch fifo. The cancel is superfluous on some chip versions, but
1699 * it's safer to always do it.
1700 * PIOAvail bits are updated by the chip as if normal send had happened.
1702 void ipath_cancel_sends(struct ipath_devdata *dd, int restore_sendctrl)
1704 ipath_dbg("Cancelling all in-progress send buffers\n");
1706 /* skip armlaunch errs for a while */
1707 dd->ipath_lastcancel = jiffies + HZ / 2;
1710 * the abort bit is auto-clearing. We read scratch to be sure
1711 * that cancels and the abort have taken effect in the chip.
1713 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1714 INFINIPATH_S_ABORT);
1715 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1716 ipath_disarm_piobufs(dd, 0,
1717 (unsigned)(dd->ipath_piobcnt2k + dd->ipath_piobcnt4k));
1718 if (restore_sendctrl) /* else done by caller later */
1719 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1720 dd->ipath_sendctrl);
1722 /* and again, be sure all have hit the chip */
1723 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1727 * Force an update of in-memory copy of the pioavail registers, when
1728 * needed for any of a variety of reasons. We read the scratch register
1729 * to make it highly likely that the update will have happened by the
1730 * time we return. If already off (as in cancel_sends above), this
1731 * routine is a nop, on the assumption that the caller will "do the
1734 void ipath_force_pio_avail_update(struct ipath_devdata *dd)
1736 unsigned long flags;
1738 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1739 if (dd->ipath_sendctrl & INFINIPATH_S_PIOBUFAVAILUPD) {
1740 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1741 dd->ipath_sendctrl & ~INFINIPATH_S_PIOBUFAVAILUPD);
1742 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1743 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1744 dd->ipath_sendctrl);
1745 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1747 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1750 static void ipath_set_ib_lstate(struct ipath_devdata *dd, int linkcmd,
1754 static const char *what[4] = {
1756 [INFINIPATH_IBCC_LINKCMD_DOWN] = "DOWN",
1757 [INFINIPATH_IBCC_LINKCMD_ARMED] = "ARMED",
1758 [INFINIPATH_IBCC_LINKCMD_ACTIVE] = "ACTIVE"
1761 if (linitcmd == INFINIPATH_IBCC_LINKINITCMD_DISABLE) {
1763 * If we are told to disable, note that so link-recovery
1764 * code does not attempt to bring us back up.
1767 dd->ipath_flags |= IPATH_IB_LINK_DISABLED;
1769 } else if (linitcmd) {
1771 * Any other linkinitcmd will lead to LINKDOWN and then
1772 * to INIT (if all is well), so clear flag to let
1773 * link-recovery code attempt to bring us back up.
1776 dd->ipath_flags &= ~IPATH_IB_LINK_DISABLED;
1780 mod_wd = (linkcmd << dd->ibcc_lc_shift) |
1781 (linitcmd << INFINIPATH_IBCC_LINKINITCMD_SHIFT);
1783 "Moving unit %u to %s (initcmd=0x%x), current ltstate is %s\n",
1784 dd->ipath_unit, what[linkcmd], linitcmd,
1785 ipath_ibcstatus_str[ipath_ib_linktrstate(dd,
1786 ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus))]);
1788 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
1789 dd->ipath_ibcctrl | mod_wd);
1790 /* read from chip so write is flushed */
1791 (void) ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
1794 int ipath_set_linkstate(struct ipath_devdata *dd, u8 newstate)
1800 case IPATH_IB_LINKDOWN_ONLY:
1801 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN, 0);
1806 case IPATH_IB_LINKDOWN:
1807 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN,
1808 INFINIPATH_IBCC_LINKINITCMD_POLL);
1813 case IPATH_IB_LINKDOWN_SLEEP:
1814 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN,
1815 INFINIPATH_IBCC_LINKINITCMD_SLEEP);
1820 case IPATH_IB_LINKDOWN_DISABLE:
1821 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN,
1822 INFINIPATH_IBCC_LINKINITCMD_DISABLE);
1827 case IPATH_IB_LINKARM:
1828 if (dd->ipath_flags & IPATH_LINKARMED) {
1832 if (!(dd->ipath_flags &
1833 (IPATH_LINKINIT | IPATH_LINKACTIVE))) {
1837 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ARMED, 0);
1840 * Since the port can transition to ACTIVE by receiving
1841 * a non VL 15 packet, wait for either state.
1843 lstate = IPATH_LINKARMED | IPATH_LINKACTIVE;
1846 case IPATH_IB_LINKACTIVE:
1847 if (dd->ipath_flags & IPATH_LINKACTIVE) {
1851 if (!(dd->ipath_flags & IPATH_LINKARMED)) {
1855 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ACTIVE, 0);
1856 lstate = IPATH_LINKACTIVE;
1859 case IPATH_IB_LINK_LOOPBACK:
1860 dev_info(&dd->pcidev->dev, "Enabling IB local loopback\n");
1861 dd->ipath_ibcctrl |= INFINIPATH_IBCC_LOOPBACK;
1862 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
1865 /* turn heartbeat off, as it causes loopback to fail */
1866 dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
1867 IPATH_IB_HRTBT_OFF);
1872 case IPATH_IB_LINK_EXTERNAL:
1873 dev_info(&dd->pcidev->dev,
1874 "Disabling IB local loopback (normal)\n");
1875 dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
1877 dd->ipath_ibcctrl &= ~INFINIPATH_IBCC_LOOPBACK;
1878 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
1885 * Heartbeat can be explicitly enabled by the user via
1886 * "hrtbt_enable" "file", and if disabled, trying to enable here
1887 * will have no effect. Implicit changes (heartbeat off when
1888 * loopback on, and vice versa) are included to ease testing.
1890 case IPATH_IB_LINK_HRTBT:
1891 ret = dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
1895 case IPATH_IB_LINK_NO_HRTBT:
1896 ret = dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
1897 IPATH_IB_HRTBT_OFF);
1901 ipath_dbg("Invalid linkstate 0x%x requested\n", newstate);
1905 ret = ipath_wait_linkstate(dd, lstate, 2000);
1912 * ipath_set_mtu - set the MTU
1913 * @dd: the infinipath device
1916 * we can handle "any" incoming size, the issue here is whether we
1917 * need to restrict our outgoing size. For now, we don't do any
1918 * sanity checking on this, and we don't deal with what happens to
1919 * programs that are already running when the size changes.
1920 * NOTE: changing the MTU will usually cause the IBC to go back to
1921 * link initialize (IPATH_IBSTATE_INIT) state...
1923 int ipath_set_mtu(struct ipath_devdata *dd, u16 arg)
1930 * mtu is IB data payload max. It's the largest power of 2 less
1931 * than piosize (or even larger, since it only really controls the
1932 * largest we can receive; we can send the max of the mtu and
1933 * piosize). We check that it's one of the valid IB sizes.
1935 if (arg != 256 && arg != 512 && arg != 1024 && arg != 2048 &&
1936 (arg != 4096 || !ipath_mtu4096)) {
1937 ipath_dbg("Trying to set invalid mtu %u, failing\n", arg);
1941 if (dd->ipath_ibmtu == arg) {
1942 ret = 0; /* same as current */
1946 piosize = dd->ipath_ibmaxlen;
1947 dd->ipath_ibmtu = arg;
1949 if (arg >= (piosize - IPATH_PIO_MAXIBHDR)) {
1950 /* Only if it's not the initial value (or reset to it) */
1951 if (piosize != dd->ipath_init_ibmaxlen) {
1952 if (arg > piosize && arg <= dd->ipath_init_ibmaxlen)
1953 piosize = dd->ipath_init_ibmaxlen;
1954 dd->ipath_ibmaxlen = piosize;
1957 } else if ((arg + IPATH_PIO_MAXIBHDR) != dd->ipath_ibmaxlen) {
1958 piosize = arg + IPATH_PIO_MAXIBHDR;
1959 ipath_cdbg(VERBOSE, "ibmaxlen was 0x%x, setting to 0x%x "
1960 "(mtu 0x%x)\n", dd->ipath_ibmaxlen, piosize,
1962 dd->ipath_ibmaxlen = piosize;
1967 u64 ibc = dd->ipath_ibcctrl, ibdw;
1969 * update our housekeeping variables, and set IBC max
1970 * size, same as init code; max IBC is max we allow in
1971 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
1973 dd->ipath_ibmaxlen = piosize - 2 * sizeof(u32);
1974 ibdw = (dd->ipath_ibmaxlen >> 2) + 1;
1975 ibc &= ~(INFINIPATH_IBCC_MAXPKTLEN_MASK <<
1976 dd->ibcc_mpl_shift);
1977 ibc |= ibdw << dd->ibcc_mpl_shift;
1978 dd->ipath_ibcctrl = ibc;
1979 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
1981 dd->ipath_f_tidtemplate(dd);
1990 int ipath_set_lid(struct ipath_devdata *dd, u32 lid, u8 lmc)
1992 dd->ipath_lid = lid;
1993 dd->ipath_lmc = lmc;
1995 dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_LIDLMC, lid |
1996 (~((1U << lmc) - 1)) << 16);
1998 dev_info(&dd->pcidev->dev, "We got a lid: 0x%x\n", lid);
2005 * ipath_write_kreg_port - write a device's per-port 64-bit kernel register
2006 * @dd: the infinipath device
2007 * @regno: the register number to write
2008 * @port: the port containing the register
2009 * @value: the value to write
2011 * Registers that vary with the chip implementation constants (port)
2014 void ipath_write_kreg_port(const struct ipath_devdata *dd, ipath_kreg regno,
2015 unsigned port, u64 value)
2019 if (port < dd->ipath_portcnt &&
2020 (regno == dd->ipath_kregs->kr_rcvhdraddr ||
2021 regno == dd->ipath_kregs->kr_rcvhdrtailaddr))
2022 where = regno + port;
2026 ipath_write_kreg(dd, where, value);
2030 * Following deal with the "obviously simple" task of overriding the state
2031 * of the LEDS, which normally indicate link physical and logical status.
2032 * The complications arise in dealing with different hardware mappings
2033 * and the board-dependent routine being called from interrupts.
2034 * and then there's the requirement to _flash_ them.
2036 #define LED_OVER_FREQ_SHIFT 8
2037 #define LED_OVER_FREQ_MASK (0xFF<<LED_OVER_FREQ_SHIFT)
2038 /* Below is "non-zero" to force override, but both actual LEDs are off */
2039 #define LED_OVER_BOTH_OFF (8)
2041 static void ipath_run_led_override(unsigned long opaque)
2043 struct ipath_devdata *dd = (struct ipath_devdata *)opaque;
2046 u64 lstate, ltstate, val;
2048 if (!(dd->ipath_flags & IPATH_INITTED))
2051 pidx = dd->ipath_led_override_phase++ & 1;
2052 dd->ipath_led_override = dd->ipath_led_override_vals[pidx];
2053 timeoff = dd->ipath_led_override_timeoff;
2056 * below potentially restores the LED values per current status,
2057 * should also possibly setup the traffic-blink register,
2058 * but leave that to per-chip functions.
2060 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
2061 ltstate = (val >> INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) &
2063 lstate = (val >> dd->ibcs_ls_shift) & INFINIPATH_IBCS_LINKSTATE_MASK;
2065 dd->ipath_f_setextled(dd, lstate, ltstate);
2066 mod_timer(&dd->ipath_led_override_timer, jiffies + timeoff);
2069 void ipath_set_led_override(struct ipath_devdata *dd, unsigned int val)
2073 if (!(dd->ipath_flags & IPATH_INITTED))
2076 /* First check if we are blinking. If not, use 1HZ polling */
2078 freq = (val & LED_OVER_FREQ_MASK) >> LED_OVER_FREQ_SHIFT;
2081 /* For blink, set each phase from one nybble of val */
2082 dd->ipath_led_override_vals[0] = val & 0xF;
2083 dd->ipath_led_override_vals[1] = (val >> 4) & 0xF;
2084 timeoff = (HZ << 4)/freq;
2086 /* Non-blink set both phases the same. */
2087 dd->ipath_led_override_vals[0] = val & 0xF;
2088 dd->ipath_led_override_vals[1] = val & 0xF;
2090 dd->ipath_led_override_timeoff = timeoff;
2093 * If the timer has not already been started, do so. Use a "quick"
2094 * timeout so the function will be called soon, to look at our request.
2096 if (atomic_inc_return(&dd->ipath_led_override_timer_active) == 1) {
2097 /* Need to start timer */
2098 init_timer(&dd->ipath_led_override_timer);
2099 dd->ipath_led_override_timer.function =
2100 ipath_run_led_override;
2101 dd->ipath_led_override_timer.data = (unsigned long) dd;
2102 dd->ipath_led_override_timer.expires = jiffies + 1;
2103 add_timer(&dd->ipath_led_override_timer);
2105 atomic_dec(&dd->ipath_led_override_timer_active);
2109 * ipath_shutdown_device - shut down a device
2110 * @dd: the infinipath device
2112 * This is called to make the device quiet when we are about to
2113 * unload the driver, and also when the device is administratively
2114 * disabled. It does not free any data structures.
2115 * Everything it does has to be setup again by ipath_init_chip(dd,1)
2117 void ipath_shutdown_device(struct ipath_devdata *dd)
2119 unsigned long flags;
2121 ipath_dbg("Shutting down the device\n");
2123 ipath_hol_up(dd); /* make sure user processes aren't suspended */
2125 dd->ipath_flags |= IPATH_LINKUNK;
2126 dd->ipath_flags &= ~(IPATH_INITTED | IPATH_LINKDOWN |
2127 IPATH_LINKINIT | IPATH_LINKARMED |
2129 *dd->ipath_statusp &= ~(IPATH_STATUS_IB_CONF |
2130 IPATH_STATUS_IB_READY);
2132 /* mask interrupts, but not errors */
2133 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
2135 dd->ipath_rcvctrl = 0;
2136 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
2140 * gracefully stop all sends allowing any in progress to trickle out
2143 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
2144 dd->ipath_sendctrl = 0;
2145 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
2147 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
2148 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
2151 * enough for anything that's going to trickle out to have actually
2156 ipath_set_ib_lstate(dd, 0, INFINIPATH_IBCC_LINKINITCMD_DISABLE);
2157 ipath_cancel_sends(dd, 0);
2159 signal_ib_event(dd, IB_EVENT_PORT_ERR);
2162 dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
2163 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
2164 dd->ipath_control | INFINIPATH_C_FREEZEMODE);
2167 * clear SerdesEnable and turn the leds off; do this here because
2168 * we are unloading, so don't count on interrupts to move along
2169 * Turn the LEDs off explictly for the same reason.
2171 dd->ipath_f_quiet_serdes(dd);
2173 /* stop all the timers that might still be running */
2174 del_timer_sync(&dd->ipath_hol_timer);
2175 if (dd->ipath_stats_timer_active) {
2176 del_timer_sync(&dd->ipath_stats_timer);
2177 dd->ipath_stats_timer_active = 0;
2179 if (dd->ipath_intrchk_timer.data) {
2180 del_timer_sync(&dd->ipath_intrchk_timer);
2181 dd->ipath_intrchk_timer.data = 0;
2185 * clear all interrupts and errors, so that the next time the driver
2186 * is loaded or device is enabled, we know that whatever is set
2187 * happened while we were unloaded
2189 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
2190 ~0ULL & ~INFINIPATH_HWE_MEMBISTFAILED);
2191 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
2192 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
2194 ipath_cdbg(VERBOSE, "Flush time and errors to EEPROM\n");
2195 ipath_update_eeprom_log(dd);
2199 * ipath_free_pddata - free a port's allocated data
2200 * @dd: the infinipath device
2201 * @pd: the portdata structure
2203 * free up any allocated data for a port
2204 * This should not touch anything that would affect a simultaneous
2205 * re-allocation of port data, because it is called after ipath_mutex
2206 * is released (and can be called from reinit as well).
2207 * It should never change any chip state, or global driver state.
2208 * (The only exception to global state is freeing the port0 port0_skbs.)
2210 void ipath_free_pddata(struct ipath_devdata *dd, struct ipath_portdata *pd)
2215 if (pd->port_rcvhdrq) {
2216 ipath_cdbg(VERBOSE, "free closed port %d rcvhdrq @ %p "
2217 "(size=%lu)\n", pd->port_port, pd->port_rcvhdrq,
2218 (unsigned long) pd->port_rcvhdrq_size);
2219 dma_free_coherent(&dd->pcidev->dev, pd->port_rcvhdrq_size,
2220 pd->port_rcvhdrq, pd->port_rcvhdrq_phys);
2221 pd->port_rcvhdrq = NULL;
2222 if (pd->port_rcvhdrtail_kvaddr) {
2223 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
2224 pd->port_rcvhdrtail_kvaddr,
2225 pd->port_rcvhdrqtailaddr_phys);
2226 pd->port_rcvhdrtail_kvaddr = NULL;
2229 if (pd->port_port && pd->port_rcvegrbuf) {
2232 for (e = 0; e < pd->port_rcvegrbuf_chunks; e++) {
2233 void *base = pd->port_rcvegrbuf[e];
2234 size_t size = pd->port_rcvegrbuf_size;
2236 ipath_cdbg(VERBOSE, "egrbuf free(%p, %lu), "
2237 "chunk %u/%u\n", base,
2238 (unsigned long) size,
2239 e, pd->port_rcvegrbuf_chunks);
2240 dma_free_coherent(&dd->pcidev->dev, size,
2241 base, pd->port_rcvegrbuf_phys[e]);
2243 kfree(pd->port_rcvegrbuf);
2244 pd->port_rcvegrbuf = NULL;
2245 kfree(pd->port_rcvegrbuf_phys);
2246 pd->port_rcvegrbuf_phys = NULL;
2247 pd->port_rcvegrbuf_chunks = 0;
2248 } else if (pd->port_port == 0 && dd->ipath_port0_skbinfo) {
2250 struct ipath_skbinfo *skbinfo = dd->ipath_port0_skbinfo;
2252 dd->ipath_port0_skbinfo = NULL;
2253 ipath_cdbg(VERBOSE, "free closed port %d "
2254 "ipath_port0_skbinfo @ %p\n", pd->port_port,
2256 for (e = 0; e < dd->ipath_p0_rcvegrcnt; e++)
2257 if (skbinfo[e].skb) {
2258 pci_unmap_single(dd->pcidev, skbinfo[e].phys,
2260 PCI_DMA_FROMDEVICE);
2261 dev_kfree_skb(skbinfo[e].skb);
2265 kfree(pd->port_tid_pg_list);
2266 vfree(pd->subport_uregbase);
2267 vfree(pd->subport_rcvegrbuf);
2268 vfree(pd->subport_rcvhdr_base);
2272 static int __init infinipath_init(void)
2276 if (ipath_debug & __IPATH_DBG)
2277 printk(KERN_INFO DRIVER_LOAD_MSG "%s", ib_ipath_version);
2280 * These must be called before the driver is registered with
2281 * the PCI subsystem.
2283 idr_init(&unit_table);
2284 if (!idr_pre_get(&unit_table, GFP_KERNEL)) {
2289 ret = pci_register_driver(&ipath_driver);
2291 printk(KERN_ERR IPATH_DRV_NAME
2292 ": Unable to register driver: error %d\n", -ret);
2296 ret = ipath_init_ipathfs();
2298 printk(KERN_ERR IPATH_DRV_NAME ": Unable to create "
2299 "ipathfs: error %d\n", -ret);
2306 pci_unregister_driver(&ipath_driver);
2309 idr_destroy(&unit_table);
2315 static void __exit infinipath_cleanup(void)
2317 ipath_exit_ipathfs();
2319 ipath_cdbg(VERBOSE, "Unregistering pci driver\n");
2320 pci_unregister_driver(&ipath_driver);
2322 idr_destroy(&unit_table);
2326 * ipath_reset_device - reset the chip if possible
2327 * @unit: the device to reset
2329 * Whether or not reset is successful, we attempt to re-initialize the chip
2330 * (that is, much like a driver unload/reload). We clear the INITTED flag
2331 * so that the various entry points will fail until we reinitialize. For
2332 * now, we only allow this if no user ports are open that use chip resources
2334 int ipath_reset_device(int unit)
2337 struct ipath_devdata *dd = ipath_lookup(unit);
2344 if (atomic_read(&dd->ipath_led_override_timer_active)) {
2345 /* Need to stop LED timer, _then_ shut off LEDs */
2346 del_timer_sync(&dd->ipath_led_override_timer);
2347 atomic_set(&dd->ipath_led_override_timer_active, 0);
2350 /* Shut off LEDs after we are sure timer is not running */
2351 dd->ipath_led_override = LED_OVER_BOTH_OFF;
2352 dd->ipath_f_setextled(dd, 0, 0);
2354 dev_info(&dd->pcidev->dev, "Reset on unit %u requested\n", unit);
2356 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) {
2357 dev_info(&dd->pcidev->dev, "Invalid unit number %u or "
2358 "not initialized or not present\n", unit);
2364 for (i = 1; i < dd->ipath_cfgports; i++) {
2365 if (dd->ipath_pd[i] && dd->ipath_pd[i]->port_cnt) {
2366 ipath_dbg("unit %u port %d is in use "
2367 "(PID %u cmd %s), can't reset\n",
2369 dd->ipath_pd[i]->port_pid,
2370 dd->ipath_pd[i]->port_comm);
2376 dd->ipath_flags &= ~IPATH_INITTED;
2377 ret = dd->ipath_f_reset(dd);
2379 ipath_dbg("reset was not successful\n");
2380 ipath_dbg("Trying to reinitialize unit %u after reset attempt\n",
2382 ret = ipath_init_chip(dd, 1);
2384 ipath_dev_err(dd, "Reinitialize unit %u after "
2385 "reset failed with %d\n", unit, ret);
2387 dev_info(&dd->pcidev->dev, "Reinitialized unit %u after "
2388 "resetting\n", unit);
2395 * send a signal to all the processes that have the driver open
2396 * through the normal interfaces (i.e., everything other than diags
2397 * interface). Returns number of signalled processes.
2399 static int ipath_signal_procs(struct ipath_devdata *dd, int sig)
2401 int i, sub, any = 0;
2406 for (i = 1; i < dd->ipath_cfgports; i++) {
2407 if (!dd->ipath_pd[i] || !dd->ipath_pd[i]->port_cnt ||
2408 !dd->ipath_pd[i]->port_pid)
2410 pid = dd->ipath_pd[i]->port_pid;
2411 dev_info(&dd->pcidev->dev, "context %d in use "
2412 "(PID %u), sending signal %d\n",
2414 kill_proc(pid, sig, 1);
2416 for (sub = 0; sub < INFINIPATH_MAX_SUBPORT; sub++) {
2417 pid = dd->ipath_pd[i]->port_subpid[sub];
2420 dev_info(&dd->pcidev->dev, "sub-context "
2421 "%d:%d in use (PID %u), sending "
2422 "signal %d\n", i, sub, pid, sig);
2423 kill_proc(pid, sig, 1);
2430 static void ipath_hol_signal_down(struct ipath_devdata *dd)
2432 if (ipath_signal_procs(dd, SIGSTOP))
2433 ipath_dbg("Stopped some processes\n");
2434 ipath_cancel_sends(dd, 1);
2438 static void ipath_hol_signal_up(struct ipath_devdata *dd)
2440 if (ipath_signal_procs(dd, SIGCONT))
2441 ipath_dbg("Continued some processes\n");
2445 * link is down, stop any users processes, and flush pending sends
2446 * to prevent HoL blocking, then start the HoL timer that
2447 * periodically continues, then stop procs, so they can detect
2448 * link down if they want, and do something about it.
2449 * Timer may already be running, so use __mod_timer, not add_timer.
2451 void ipath_hol_down(struct ipath_devdata *dd)
2453 dd->ipath_hol_state = IPATH_HOL_DOWN;
2454 ipath_hol_signal_down(dd);
2455 dd->ipath_hol_next = IPATH_HOL_DOWNCONT;
2456 dd->ipath_hol_timer.expires = jiffies +
2457 msecs_to_jiffies(ipath_hol_timeout_ms);
2458 __mod_timer(&dd->ipath_hol_timer, dd->ipath_hol_timer.expires);
2462 * link is up, continue any user processes, and ensure timer
2463 * is a nop, if running. Let timer keep running, if set; it
2464 * will nop when it sees the link is up
2466 void ipath_hol_up(struct ipath_devdata *dd)
2468 ipath_hol_signal_up(dd);
2469 dd->ipath_hol_state = IPATH_HOL_UP;
2473 * toggle the running/not running state of user proceses
2474 * to prevent HoL blocking on chip resources, but still allow
2475 * user processes to do link down special case handling.
2476 * Should only be called via the timer
2478 void ipath_hol_event(unsigned long opaque)
2480 struct ipath_devdata *dd = (struct ipath_devdata *)opaque;
2482 if (dd->ipath_hol_next == IPATH_HOL_DOWNSTOP
2483 && dd->ipath_hol_state != IPATH_HOL_UP) {
2484 dd->ipath_hol_next = IPATH_HOL_DOWNCONT;
2485 ipath_dbg("Stopping processes\n");
2486 ipath_hol_signal_down(dd);
2487 } else { /* may do "extra" if also in ipath_hol_up() */
2488 dd->ipath_hol_next = IPATH_HOL_DOWNSTOP;
2489 ipath_dbg("Continuing processes\n");
2490 ipath_hol_signal_up(dd);
2492 if (dd->ipath_hol_state == IPATH_HOL_UP)
2493 ipath_dbg("link's up, don't resched timer\n");
2495 dd->ipath_hol_timer.expires = jiffies +
2496 msecs_to_jiffies(ipath_hol_timeout_ms);
2497 __mod_timer(&dd->ipath_hol_timer,
2498 dd->ipath_hol_timer.expires);
2502 int ipath_set_rx_pol_inv(struct ipath_devdata *dd, u8 new_pol_inv)
2506 if (new_pol_inv > INFINIPATH_XGXS_RX_POL_MASK)
2508 if (dd->ipath_rx_pol_inv != new_pol_inv) {
2509 dd->ipath_rx_pol_inv = new_pol_inv;
2510 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
2511 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
2512 INFINIPATH_XGXS_RX_POL_SHIFT);
2513 val |= ((u64)dd->ipath_rx_pol_inv) <<
2514 INFINIPATH_XGXS_RX_POL_SHIFT;
2515 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
2521 * Disable and enable the armlaunch error. Used for PIO bandwidth testing on
2522 * the 7220, which is count-based, rather than trigger-based. Safe for the
2523 * driver check, since it's at init. Not completely safe when used for
2524 * user-mode checking, since some error checking can be lost, but not
2525 * particularly risky, and only has problematic side-effects in the face of
2526 * very buggy user code. There is no reference counting, but that's also
2527 * fine, given the intended use.
2529 void ipath_enable_armlaunch(struct ipath_devdata *dd)
2531 dd->ipath_lasterror &= ~INFINIPATH_E_SPIOARMLAUNCH;
2532 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
2533 INFINIPATH_E_SPIOARMLAUNCH);
2534 dd->ipath_errormask |= INFINIPATH_E_SPIOARMLAUNCH;
2535 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
2536 dd->ipath_errormask);
2539 void ipath_disable_armlaunch(struct ipath_devdata *dd)
2541 /* so don't re-enable if already set */
2542 dd->ipath_maskederrs &= ~INFINIPATH_E_SPIOARMLAUNCH;
2543 dd->ipath_errormask &= ~INFINIPATH_E_SPIOARMLAUNCH;
2544 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
2545 dd->ipath_errormask);
2548 module_init(infinipath_init);
2549 module_exit(infinipath_cleanup);