err.no Git - linux-2.6/blob - drivers/infiniband/hw/cxgb3/iwch_qp.c

   1 /*
   2  * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #include "iwch_provider.h"
  33 #include "iwch.h"
  34 #include "iwch_cm.h"
  35 #include "cxio_hal.h"
  36
  37 #define NO_SUPPORT -1
  38
  39 static int iwch_build_rdma_send(union t3_wr *wqe, struct ib_send_wr *wr,
  40                                 u8 * flit_cnt)
  41 {
  42         int i;
  43         u32 plen;
  44
  45         switch (wr->opcode) {
  46         case IB_WR_SEND:
  47                 if (wr->send_flags & IB_SEND_SOLICITED)
  48                         wqe->send.rdmaop = T3_SEND_WITH_SE;
  49                 else
  50                         wqe->send.rdmaop = T3_SEND;
  51                 wqe->send.rem_stag = 0;
  52                 break;
  53         case IB_WR_SEND_WITH_INV:
  54                 if (wr->send_flags & IB_SEND_SOLICITED)
  55                         wqe->send.rdmaop = T3_SEND_WITH_SE_INV;
  56                 else
  57                         wqe->send.rdmaop = T3_SEND_WITH_INV;
  58                 wqe->send.rem_stag = cpu_to_be32(wr->ex.invalidate_rkey);
  59                 break;
  60         default:
  61                 return -EINVAL;
  62         }
  63         if (wr->num_sge > T3_MAX_SGE)
  64                 return -EINVAL;
  65         wqe->send.reserved[0] = 0;
  66         wqe->send.reserved[1] = 0;
  67         wqe->send.reserved[2] = 0;
  68         plen = 0;
  69         for (i = 0; i < wr->num_sge; i++) {
  70                 if ((plen + wr->sg_list[i].length) < plen)
  71                         return -EMSGSIZE;
  72
  73                 plen += wr->sg_list[i].length;
  74                 wqe->send.sgl[i].stag = cpu_to_be32(wr->sg_list[i].lkey);
  75                 wqe->send.sgl[i].len = cpu_to_be32(wr->sg_list[i].length);
  76                 wqe->send.sgl[i].to = cpu_to_be64(wr->sg_list[i].addr);
  77         }
  78         wqe->send.num_sgle = cpu_to_be32(wr->num_sge);
  79         *flit_cnt = 4 + ((wr->num_sge) << 1);
  80         wqe->send.plen = cpu_to_be32(plen);
  81         return 0;
  82 }
  83
  84 static int iwch_build_rdma_write(union t3_wr *wqe, struct ib_send_wr *wr,
  85                                  u8 *flit_cnt)
  86 {
  87         int i;
  88         u32 plen;
  89         if (wr->num_sge > T3_MAX_SGE)
  90                 return -EINVAL;
  91         wqe->write.rdmaop = T3_RDMA_WRITE;
  92         wqe->write.reserved[0] = 0;
  93         wqe->write.reserved[1] = 0;
  94         wqe->write.reserved[2] = 0;
  95         wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
  96         wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
  97
  98         if (wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) {
  99                 plen = 4;
 100                 wqe->write.sgl[0].stag = wr->ex.imm_data;
 101                 wqe->write.sgl[0].len = __constant_cpu_to_be32(0);
 102                 wqe->write.num_sgle = __constant_cpu_to_be32(0);
 103                 *flit_cnt = 6;
 104         } else {
 105                 plen = 0;
 106                 for (i = 0; i < wr->num_sge; i++) {
 107                         if ((plen + wr->sg_list[i].length) < plen) {
 108                                 return -EMSGSIZE;
 109                         }
 110                         plen += wr->sg_list[i].length;
 111                         wqe->write.sgl[i].stag =
 112                             cpu_to_be32(wr->sg_list[i].lkey);
 113                         wqe->write.sgl[i].len =
 114                             cpu_to_be32(wr->sg_list[i].length);
 115                         wqe->write.sgl[i].to =
 116                             cpu_to_be64(wr->sg_list[i].addr);
 117                 }
 118                 wqe->write.num_sgle = cpu_to_be32(wr->num_sge);
 119                 *flit_cnt = 5 + ((wr->num_sge) << 1);
 120         }
 121         wqe->write.plen = cpu_to_be32(plen);
 122         return 0;
 123 }
 124
 125 static int iwch_build_rdma_read(union t3_wr *wqe, struct ib_send_wr *wr,
 126                                 u8 *flit_cnt)
 127 {
 128         if (wr->num_sge > 1)
 129                 return -EINVAL;
 130         wqe->read.rdmaop = T3_READ_REQ;
 131         if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
 132                 wqe->read.local_inv = 1;
 133         else
 134                 wqe->read.local_inv = 0;
 135         wqe->read.reserved[0] = 0;
 136         wqe->read.reserved[1] = 0;
 137         wqe->read.rem_stag = cpu_to_be32(wr->wr.rdma.rkey);
 138         wqe->read.rem_to = cpu_to_be64(wr->wr.rdma.remote_addr);
 139         wqe->read.local_stag = cpu_to_be32(wr->sg_list[0].lkey);
 140         wqe->read.local_len = cpu_to_be32(wr->sg_list[0].length);
 141         wqe->read.local_to = cpu_to_be64(wr->sg_list[0].addr);
 142         *flit_cnt = sizeof(struct t3_rdma_read_wr) >> 3;
 143         return 0;
 144 }
 145
 146 static int iwch_build_fastreg(union t3_wr *wqe, struct ib_send_wr *wr,
 147                                 u8 *flit_cnt, int *wr_cnt, struct t3_wq *wq)
 148 {
 149         int i;
 150         __be64 *p;
 151
 152         if (wr->wr.fast_reg.page_list_len > T3_MAX_FASTREG_DEPTH)
 153                 return -EINVAL;
 154         *wr_cnt = 1;
 155         wqe->fastreg.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
 156         wqe->fastreg.len = cpu_to_be32(wr->wr.fast_reg.length);
 157         wqe->fastreg.va_base_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
 158         wqe->fastreg.va_base_lo_fbo =
 159                                 cpu_to_be32(wr->wr.fast_reg.iova_start & 0xffffffff);
 160         wqe->fastreg.page_type_perms = cpu_to_be32(
 161                 V_FR_PAGE_COUNT(wr->wr.fast_reg.page_list_len) |
 162                 V_FR_PAGE_SIZE(wr->wr.fast_reg.page_shift-12) |
 163                 V_FR_TYPE(TPT_VATO) |
 164                 V_FR_PERMS(iwch_ib_to_tpt_access(wr->wr.fast_reg.access_flags)));
 165         p = &wqe->fastreg.pbl_addrs[0];
 166         for (i = 0; i < wr->wr.fast_reg.page_list_len; i++, p++) {
 167
 168                 /* If we need a 2nd WR, then set it up */
 169                 if (i == T3_MAX_FASTREG_FRAG) {
 170                         *wr_cnt = 2;
 171                         wqe = (union t3_wr *)(wq->queue +
 172                                 Q_PTR2IDX((wq->wptr+1), wq->size_log2));
 173                         build_fw_riwrh((void *)wqe, T3_WR_FASTREG, 0,
 174                                Q_GENBIT(wq->wptr + 1, wq->size_log2),
 175                                0, 1 + wr->wr.fast_reg.page_list_len - T3_MAX_FASTREG_FRAG,
 176                                T3_EOP);
 177
 178                         p = &wqe->pbl_frag.pbl_addrs[0];
 179                 }
 180                 *p = cpu_to_be64((u64)wr->wr.fast_reg.page_list->page_list[i]);
 181         }
 182         *flit_cnt = 5 + wr->wr.fast_reg.page_list_len;
 183         if (*flit_cnt > 15)
 184                 *flit_cnt = 15;
 185         return 0;
 186 }
 187
 188 static int iwch_build_inv_stag(union t3_wr *wqe, struct ib_send_wr *wr,
 189                                 u8 *flit_cnt)
 190 {
 191         wqe->local_inv.stag = cpu_to_be32(wr->ex.invalidate_rkey);
 192         wqe->local_inv.reserved = 0;
 193         *flit_cnt = sizeof(struct t3_local_inv_wr) >> 3;
 194         return 0;
 195 }
 196
 197 /*
 198  * TBD: this is going to be moved to firmware. Missing pdid/qpid check for now.
 199  */
 200 static int iwch_sgl2pbl_map(struct iwch_dev *rhp, struct ib_sge *sg_list,
 201                             u32 num_sgle, u32 * pbl_addr, u8 * page_size)
 202 {
 203         int i;
 204         struct iwch_mr *mhp;
 205         u32 offset;
 206         for (i = 0; i < num_sgle; i++) {
 207
 208                 mhp = get_mhp(rhp, (sg_list[i].lkey) >> 8);
 209                 if (!mhp) {
 210                         PDBG("%s %d\n", __func__, __LINE__);
 211                         return -EIO;
 212                 }
 213                 if (!mhp->attr.state) {
 214                         PDBG("%s %d\n", __func__, __LINE__);
 215                         return -EIO;
 216                 }
 217                 if (mhp->attr.zbva) {
 218                         PDBG("%s %d\n", __func__, __LINE__);
 219                         return -EIO;
 220                 }
 221
 222                 if (sg_list[i].addr < mhp->attr.va_fbo) {
 223                         PDBG("%s %d\n", __func__, __LINE__);
 224                         return -EINVAL;
 225                 }
 226                 if (sg_list[i].addr + ((u64) sg_list[i].length) <
 227                     sg_list[i].addr) {
 228                         PDBG("%s %d\n", __func__, __LINE__);
 229                         return -EINVAL;
 230                 }
 231                 if (sg_list[i].addr + ((u64) sg_list[i].length) >
 232                     mhp->attr.va_fbo + ((u64) mhp->attr.len)) {
 233                         PDBG("%s %d\n", __func__, __LINE__);
 234                         return -EINVAL;
 235                 }
 236                 offset = sg_list[i].addr - mhp->attr.va_fbo;
 237                 offset += ((u32) mhp->attr.va_fbo) %
 238                           (1UL << (12 + mhp->attr.page_size));
 239                 pbl_addr[i] = ((mhp->attr.pbl_addr -
 240                                 rhp->rdev.rnic_info.pbl_base) >> 3) +
 241                               (offset >> (12 + mhp->attr.page_size));
 242                 page_size[i] = mhp->attr.page_size;
 243         }
 244         return 0;
 245 }
 246
 247 static int iwch_build_rdma_recv(struct iwch_dev *rhp, union t3_wr *wqe,
 248                                 struct ib_recv_wr *wr)
 249 {
 250         int i;
 251         if (wr->num_sge > T3_MAX_SGE)
 252                 return -EINVAL;
 253         wqe->recv.num_sgle = cpu_to_be32(wr->num_sge);
 254         for (i = 0; i < wr->num_sge; i++) {
 255                 wqe->recv.sgl[i].stag = cpu_to_be32(wr->sg_list[i].lkey);
 256                 wqe->recv.sgl[i].len = cpu_to_be32(wr->sg_list[i].length);
 257                 wqe->recv.sgl[i].to = cpu_to_be64(wr->sg_list[i].addr);
 258         }
 259         for (; i < T3_MAX_SGE; i++) {
 260                 wqe->recv.sgl[i].stag = 0;
 261                 wqe->recv.sgl[i].len = 0;
 262                 wqe->recv.sgl[i].to = 0;
 263         }
 264         return 0;
 265 }
 266
 267 int iwch_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 268                       struct ib_send_wr **bad_wr)
 269 {
 270         int err = 0;
 271         u8 uninitialized_var(t3_wr_flit_cnt);
 272         enum t3_wr_opcode t3_wr_opcode = 0;
 273         enum t3_wr_flags t3_wr_flags;
 274         struct iwch_qp *qhp;
 275         u32 idx;
 276         union t3_wr *wqe;
 277         u32 num_wrs;
 278         unsigned long flag;
 279         struct t3_swsq *sqp;
 280         int wr_cnt = 1;
 281
 282         qhp = to_iwch_qp(ibqp);
 283         spin_lock_irqsave(&qhp->lock, flag);
 284         if (qhp->attr.state > IWCH_QP_STATE_RTS) {
 285                 spin_unlock_irqrestore(&qhp->lock, flag);
 286                 return -EINVAL;
 287         }
 288         num_wrs = Q_FREECNT(qhp->wq.sq_rptr, qhp->wq.sq_wptr,
 289                   qhp->wq.sq_size_log2);
 290         if (num_wrs <= 0) {
 291                 spin_unlock_irqrestore(&qhp->lock, flag);
 292                 return -ENOMEM;
 293         }
 294         while (wr) {
 295                 if (num_wrs == 0) {
 296                         err = -ENOMEM;
 297                         *bad_wr = wr;
 298                         break;
 299                 }
 300                 idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2);
 301                 wqe = (union t3_wr *) (qhp->wq.queue + idx);
 302                 t3_wr_flags = 0;
 303                 if (wr->send_flags & IB_SEND_SOLICITED)
 304                         t3_wr_flags |= T3_SOLICITED_EVENT_FLAG;
 305                 if (wr->send_flags & IB_SEND_SIGNALED)
 306                         t3_wr_flags |= T3_COMPLETION_FLAG;
 307                 sqp = qhp->wq.sq +
 308                       Q_PTR2IDX(qhp->wq.sq_wptr, qhp->wq.sq_size_log2);
 309                 switch (wr->opcode) {
 310                 case IB_WR_SEND:
 311                 case IB_WR_SEND_WITH_INV:
 312                         if (wr->send_flags & IB_SEND_FENCE)
 313                                 t3_wr_flags |= T3_READ_FENCE_FLAG;
 314                         t3_wr_opcode = T3_WR_SEND;
 315                         err = iwch_build_rdma_send(wqe, wr, &t3_wr_flit_cnt);
 316                         break;
 317                 case IB_WR_RDMA_WRITE:
 318                 case IB_WR_RDMA_WRITE_WITH_IMM:
 319                         t3_wr_opcode = T3_WR_WRITE;
 320                         err = iwch_build_rdma_write(wqe, wr, &t3_wr_flit_cnt);
 321                         break;
 322                 case IB_WR_RDMA_READ:
 323                 case IB_WR_RDMA_READ_WITH_INV:
 324                         t3_wr_opcode = T3_WR_READ;
 325                         t3_wr_flags = 0; /* T3 reads are always signaled */
 326                         err = iwch_build_rdma_read(wqe, wr, &t3_wr_flit_cnt);
 327                         if (err)
 328                                 break;
 329                         sqp->read_len = wqe->read.local_len;
 330                         if (!qhp->wq.oldest_read)
 331                                 qhp->wq.oldest_read = sqp;
 332                         break;
 333                 case IB_WR_FAST_REG_MR:
 334                         t3_wr_opcode = T3_WR_FASTREG;
 335                         err = iwch_build_fastreg(wqe, wr, &t3_wr_flit_cnt,
 336                                                  &wr_cnt, &qhp->wq);
 337                         break;
 338                 case IB_WR_LOCAL_INV:
 339                         if (wr->send_flags & IB_SEND_FENCE)
 340                                 t3_wr_flags |= T3_LOCAL_FENCE_FLAG;
 341                         t3_wr_opcode = T3_WR_INV_STAG;
 342                         err = iwch_build_inv_stag(wqe, wr, &t3_wr_flit_cnt);
 343                         break;
 344                 default:
 345                         PDBG("%s post of type=%d TBD!\n", __func__,
 346                              wr->opcode);
 347                         err = -EINVAL;
 348                 }
 349                 if (err) {
 350                         *bad_wr = wr;
 351                         break;
 352                 }
 353                 wqe->send.wrid.id0.hi = qhp->wq.sq_wptr;
 354                 sqp->wr_id = wr->wr_id;
 355                 sqp->opcode = wr2opcode(t3_wr_opcode);
 356                 sqp->sq_wptr = qhp->wq.sq_wptr;
 357                 sqp->complete = 0;
 358                 sqp->signaled = (wr->send_flags & IB_SEND_SIGNALED);
 359
 360                 build_fw_riwrh((void *) wqe, t3_wr_opcode, t3_wr_flags,
 361                                Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2),
 362                                0, t3_wr_flit_cnt,
 363                                (wr_cnt == 1) ? T3_SOPEOP : T3_SOP);
 364                 PDBG("%s cookie 0x%llx wq idx 0x%x swsq idx %ld opcode %d\n",
 365                      __func__, (unsigned long long) wr->wr_id, idx,
 366                      Q_PTR2IDX(qhp->wq.sq_wptr, qhp->wq.sq_size_log2),
 367                      sqp->opcode);
 368                 wr = wr->next;
 369                 num_wrs--;
 370                 qhp->wq.wptr += wr_cnt;
 371                 ++(qhp->wq.sq_wptr);
 372         }
 373         spin_unlock_irqrestore(&qhp->lock, flag);
 374         ring_doorbell(qhp->wq.doorbell, qhp->wq.qpid);
 375         return err;
 376 }
 377
 378 int iwch_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 379                       struct ib_recv_wr **bad_wr)
 380 {
 381         int err = 0;
 382         struct iwch_qp *qhp;
 383         u32 idx;
 384         union t3_wr *wqe;
 385         u32 num_wrs;
 386         unsigned long flag;
 387
 388         qhp = to_iwch_qp(ibqp);
 389         spin_lock_irqsave(&qhp->lock, flag);
 390         if (qhp->attr.state > IWCH_QP_STATE_RTS) {
 391                 spin_unlock_irqrestore(&qhp->lock, flag);
 392                 return -EINVAL;
 393         }
 394         num_wrs = Q_FREECNT(qhp->wq.rq_rptr, qhp->wq.rq_wptr,
 395                             qhp->wq.rq_size_log2) - 1;
 396         if (!wr) {
 397                 spin_unlock_irqrestore(&qhp->lock, flag);
 398                 return -EINVAL;
 399         }
 400         while (wr) {
 401                 idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2);
 402                 wqe = (union t3_wr *) (qhp->wq.queue + idx);
 403                 if (num_wrs)
 404                         err = iwch_build_rdma_recv(qhp->rhp, wqe, wr);
 405                 else
 406                         err = -ENOMEM;
 407                 if (err) {
 408                         *bad_wr = wr;
 409                         break;
 410                 }
 411                 qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr, qhp->wq.rq_size_log2)] =
 412                         wr->wr_id;
 413                 build_fw_riwrh((void *) wqe, T3_WR_RCV, T3_COMPLETION_FLAG,
 414                                Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2),
 415                                0, sizeof(struct t3_receive_wr) >> 3, T3_SOPEOP);
 416                 PDBG("%s cookie 0x%llx idx 0x%x rq_wptr 0x%x rw_rptr 0x%x "
 417                      "wqe %p \n", __func__, (unsigned long long) wr->wr_id,
 418                      idx, qhp->wq.rq_wptr, qhp->wq.rq_rptr, wqe);
 419                 ++(qhp->wq.rq_wptr);
 420                 ++(qhp->wq.wptr);
 421                 wr = wr->next;
 422                 num_wrs--;
 423         }
 424         spin_unlock_irqrestore(&qhp->lock, flag);
 425         ring_doorbell(qhp->wq.doorbell, qhp->wq.qpid);
 426         return err;
 427 }
 428
 429 int iwch_bind_mw(struct ib_qp *qp,
 430                              struct ib_mw *mw,
 431                              struct ib_mw_bind *mw_bind)
 432 {
 433         struct iwch_dev *rhp;
 434         struct iwch_mw *mhp;
 435         struct iwch_qp *qhp;
 436         union t3_wr *wqe;
 437         u32 pbl_addr;
 438         u8 page_size;
 439         u32 num_wrs;
 440         unsigned long flag;
 441         struct ib_sge sgl;
 442         int err=0;
 443         enum t3_wr_flags t3_wr_flags;
 444         u32 idx;
 445         struct t3_swsq *sqp;
 446
 447         qhp = to_iwch_qp(qp);
 448         mhp = to_iwch_mw(mw);
 449         rhp = qhp->rhp;
 450
 451         spin_lock_irqsave(&qhp->lock, flag);
 452         if (qhp->attr.state > IWCH_QP_STATE_RTS) {
 453                 spin_unlock_irqrestore(&qhp->lock, flag);
 454                 return -EINVAL;
 455         }
 456         num_wrs = Q_FREECNT(qhp->wq.sq_rptr, qhp->wq.sq_wptr,
 457                             qhp->wq.sq_size_log2);
 458         if ((num_wrs) <= 0) {
 459                 spin_unlock_irqrestore(&qhp->lock, flag);
 460                 return -ENOMEM;
 461         }
 462         idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2);
 463         PDBG("%s: idx 0x%0x, mw 0x%p, mw_bind 0x%p\n", __func__, idx,
 464              mw, mw_bind);
 465         wqe = (union t3_wr *) (qhp->wq.queue + idx);
 466
 467         t3_wr_flags = 0;
 468         if (mw_bind->send_flags & IB_SEND_SIGNALED)
 469                 t3_wr_flags = T3_COMPLETION_FLAG;
 470
 471         sgl.addr = mw_bind->addr;
 472         sgl.lkey = mw_bind->mr->lkey;
 473         sgl.length = mw_bind->length;
 474         wqe->bind.reserved = 0;
 475         wqe->bind.type = TPT_VATO;
 476
 477         /* TBD: check perms */
 478         wqe->bind.perms = iwch_ib_to_tpt_access(mw_bind->mw_access_flags);
 479         wqe->bind.mr_stag = cpu_to_be32(mw_bind->mr->lkey);
 480         wqe->bind.mw_stag = cpu_to_be32(mw->rkey);
 481         wqe->bind.mw_len = cpu_to_be32(mw_bind->length);
 482         wqe->bind.mw_va = cpu_to_be64(mw_bind->addr);
 483         err = iwch_sgl2pbl_map(rhp, &sgl, 1, &pbl_addr, &page_size);
 484         if (err) {
 485                 spin_unlock_irqrestore(&qhp->lock, flag);
 486                 return err;
 487         }
 488         wqe->send.wrid.id0.hi = qhp->wq.sq_wptr;
 489         sqp = qhp->wq.sq + Q_PTR2IDX(qhp->wq.sq_wptr, qhp->wq.sq_size_log2);
 490         sqp->wr_id = mw_bind->wr_id;
 491         sqp->opcode = T3_BIND_MW;
 492         sqp->sq_wptr = qhp->wq.sq_wptr;
 493         sqp->complete = 0;
 494         sqp->signaled = (mw_bind->send_flags & IB_SEND_SIGNALED);
 495         wqe->bind.mr_pbl_addr = cpu_to_be32(pbl_addr);
 496         wqe->bind.mr_pagesz = page_size;
 497         build_fw_riwrh((void *)wqe, T3_WR_BIND, t3_wr_flags,
 498                        Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2), 0,
 499                        sizeof(struct t3_bind_mw_wr) >> 3, T3_SOPEOP);
 500         ++(qhp->wq.wptr);
 501         ++(qhp->wq.sq_wptr);
 502         spin_unlock_irqrestore(&qhp->lock, flag);
 503
 504         ring_doorbell(qhp->wq.doorbell, qhp->wq.qpid);
 505
 506         return err;
 507 }
 508
 509 static inline void build_term_codes(struct respQ_msg_t *rsp_msg,
 510                                     u8 *layer_type, u8 *ecode)
 511 {
 512         int status = TPT_ERR_INTERNAL_ERR;
 513         int tagged = 0;
 514         int opcode = -1;
 515         int rqtype = 0;
 516         int send_inv = 0;
 517
 518         if (rsp_msg) {
 519                 status = CQE_STATUS(rsp_msg->cqe);
 520                 opcode = CQE_OPCODE(rsp_msg->cqe);
 521                 rqtype = RQ_TYPE(rsp_msg->cqe);
 522                 send_inv = (opcode == T3_SEND_WITH_INV) ||
 523                            (opcode == T3_SEND_WITH_SE_INV);
 524                 tagged = (opcode == T3_RDMA_WRITE) ||
 525                          (rqtype && (opcode == T3_READ_RESP));
 526         }
 527
 528         switch (status) {
 529         case TPT_ERR_STAG:
 530                 if (send_inv) {
 531                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 532                         *ecode = RDMAP_CANT_INV_STAG;
 533                 } else {
 534                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 535                         *ecode = RDMAP_INV_STAG;
 536                 }
 537                 break;
 538         case TPT_ERR_PDID:
 539                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 540                 if ((opcode == T3_SEND_WITH_INV) ||
 541                     (opcode == T3_SEND_WITH_SE_INV))
 542                         *ecode = RDMAP_CANT_INV_STAG;
 543                 else
 544                         *ecode = RDMAP_STAG_NOT_ASSOC;
 545                 break;
 546         case TPT_ERR_QPID:
 547                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 548                 *ecode = RDMAP_STAG_NOT_ASSOC;
 549                 break;
 550         case TPT_ERR_ACCESS:
 551                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 552                 *ecode = RDMAP_ACC_VIOL;
 553                 break;
 554         case TPT_ERR_WRAP:
 555                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 556                 *ecode = RDMAP_TO_WRAP;
 557                 break;
 558         case TPT_ERR_BOUND:
 559                 if (tagged) {
 560                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 561                         *ecode = DDPT_BASE_BOUNDS;
 562                 } else {
 563                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 564                         *ecode = RDMAP_BASE_BOUNDS;
 565                 }
 566                 break;
 567         case TPT_ERR_INVALIDATE_SHARED_MR:
 568         case TPT_ERR_INVALIDATE_MR_WITH_MW_BOUND:
 569                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 570                 *ecode = RDMAP_CANT_INV_STAG;
 571                 break;
 572         case TPT_ERR_ECC:
 573         case TPT_ERR_ECC_PSTAG:
 574         case TPT_ERR_INTERNAL_ERR:
 575                 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
 576                 *ecode = 0;
 577                 break;
 578         case TPT_ERR_OUT_OF_RQE:
 579                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 580                 *ecode = DDPU_INV_MSN_NOBUF;
 581                 break;
 582         case TPT_ERR_PBL_ADDR_BOUND:
 583                 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 584                 *ecode = DDPT_BASE_BOUNDS;
 585                 break;
 586         case TPT_ERR_CRC:
 587                 *layer_type = LAYER_MPA|DDP_LLP;
 588                 *ecode = MPA_CRC_ERR;
 589                 break;
 590         case TPT_ERR_MARKER:
 591                 *layer_type = LAYER_MPA|DDP_LLP;
 592                 *ecode = MPA_MARKER_ERR;
 593                 break;
 594         case TPT_ERR_PDU_LEN_ERR:
 595                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 596                 *ecode = DDPU_MSG_TOOBIG;
 597                 break;
 598         case TPT_ERR_DDP_VERSION:
 599                 if (tagged) {
 600                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 601                         *ecode = DDPT_INV_VERS;
 602                 } else {
 603                         *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 604                         *ecode = DDPU_INV_VERS;
 605                 }
 606                 break;
 607         case TPT_ERR_RDMA_VERSION:
 608                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 609                 *ecode = RDMAP_INV_VERS;
 610                 break;
 611         case TPT_ERR_OPCODE:
 612                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 613                 *ecode = RDMAP_INV_OPCODE;
 614                 break;
 615         case TPT_ERR_DDP_QUEUE_NUM:
 616                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 617                 *ecode = DDPU_INV_QN;
 618                 break;
 619         case TPT_ERR_MSN:
 620         case TPT_ERR_MSN_GAP:
 621         case TPT_ERR_MSN_RANGE:
 622         case TPT_ERR_IRD_OVERFLOW:
 623                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 624                 *ecode = DDPU_INV_MSN_RANGE;
 625                 break;
 626         case TPT_ERR_TBIT:
 627                 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
 628                 *ecode = 0;
 629                 break;
 630         case TPT_ERR_MO:
 631                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 632                 *ecode = DDPU_INV_MO;
 633                 break;
 634         default:
 635                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
 636                 *ecode = 0;
 637                 break;
 638         }
 639 }
 640
 641 int iwch_post_zb_read(struct iwch_qp *qhp)
 642 {
 643         union t3_wr *wqe;
 644         struct sk_buff *skb;
 645         u8 flit_cnt = sizeof(struct t3_rdma_read_wr) >> 3;
 646
 647         PDBG("%s enter\n", __func__);
 648         skb = alloc_skb(40, GFP_KERNEL);
 649         if (!skb) {
 650                 printk(KERN_ERR "%s cannot send zb_read!!\n", __func__);
 651                 return -ENOMEM;
 652         }
 653         wqe = (union t3_wr *)skb_put(skb, sizeof(struct t3_rdma_read_wr));
 654         memset(wqe, 0, sizeof(struct t3_rdma_read_wr));
 655         wqe->read.rdmaop = T3_READ_REQ;
 656         wqe->read.reserved[0] = 0;
 657         wqe->read.reserved[1] = 0;
 658         wqe->read.reserved[2] = 0;
 659         wqe->read.rem_stag = cpu_to_be32(1);
 660         wqe->read.rem_to = cpu_to_be64(1);
 661         wqe->read.local_stag = cpu_to_be32(1);
 662         wqe->read.local_len = cpu_to_be32(0);
 663         wqe->read.local_to = cpu_to_be64(1);
 664         wqe->send.wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_READ));
 665         wqe->send.wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(qhp->ep->hwtid)|
 666                                                 V_FW_RIWR_LEN(flit_cnt));
 667         skb->priority = CPL_PRIORITY_DATA;
 668         return cxgb3_ofld_send(qhp->rhp->rdev.t3cdev_p, skb);
 669 }
 670
 671 /*
 672  * This posts a TERMINATE with layer=RDMA, type=catastrophic.
 673  */
 674 int iwch_post_terminate(struct iwch_qp *qhp, struct respQ_msg_t *rsp_msg)
 675 {
 676         union t3_wr *wqe;
 677         struct terminate_message *term;
 678         struct sk_buff *skb;
 679
 680         PDBG("%s %d\n", __func__, __LINE__);
 681         skb = alloc_skb(40, GFP_ATOMIC);
 682         if (!skb) {
 683                 printk(KERN_ERR "%s cannot send TERMINATE!\n", __func__);
 684                 return -ENOMEM;
 685         }
 686         wqe = (union t3_wr *)skb_put(skb, 40);
 687         memset(wqe, 0, 40);
 688         wqe->send.rdmaop = T3_TERMINATE;
 689
 690         /* immediate data length */
 691         wqe->send.plen = htonl(4);
 692
 693         /* immediate data starts here. */
 694         term = (struct terminate_message *)wqe->send.sgl;
 695         build_term_codes(rsp_msg, &term->layer_etype, &term->ecode);
 696         wqe->send.wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_SEND) |
 697                          V_FW_RIWR_FLAGS(T3_COMPLETION_FLAG | T3_NOTIFY_FLAG));
 698         wqe->send.wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(qhp->ep->hwtid));
 699         skb->priority = CPL_PRIORITY_DATA;
 700         return cxgb3_ofld_send(qhp->rhp->rdev.t3cdev_p, skb);
 701 }
 702
 703 /*
 704  * Assumes qhp lock is held.
 705  */
 706 static void __flush_qp(struct iwch_qp *qhp, unsigned long *flag)
 707 {
 708         struct iwch_cq *rchp, *schp;
 709         int count;
 710         int flushed;
 711
 712         rchp = get_chp(qhp->rhp, qhp->attr.rcq);
 713         schp = get_chp(qhp->rhp, qhp->attr.scq);
 714
 715         PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
 716         /* take a ref on the qhp since we must release the lock */
 717         atomic_inc(&qhp->refcnt);
 718         spin_unlock_irqrestore(&qhp->lock, *flag);
 719
 720         /* locking heirarchy: cq lock first, then qp lock. */
 721         spin_lock_irqsave(&rchp->lock, *flag);
 722         spin_lock(&qhp->lock);
 723         cxio_flush_hw_cq(&rchp->cq);
 724         cxio_count_rcqes(&rchp->cq, &qhp->wq, &count);
 725         flushed = cxio_flush_rq(&qhp->wq, &rchp->cq, count);
 726         spin_unlock(&qhp->lock);
 727         spin_unlock_irqrestore(&rchp->lock, *flag);
 728         if (flushed)
 729                 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
 730
 731         /* locking heirarchy: cq lock first, then qp lock. */
 732         spin_lock_irqsave(&schp->lock, *flag);
 733         spin_lock(&qhp->lock);
 734         cxio_flush_hw_cq(&schp->cq);
 735         cxio_count_scqes(&schp->cq, &qhp->wq, &count);
 736         flushed = cxio_flush_sq(&qhp->wq, &schp->cq, count);
 737         spin_unlock(&qhp->lock);
 738         spin_unlock_irqrestore(&schp->lock, *flag);
 739         if (flushed)
 740                 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
 741
 742         /* deref */
 743         if (atomic_dec_and_test(&qhp->refcnt))
 744                 wake_up(&qhp->wait);
 745
 746         spin_lock_irqsave(&qhp->lock, *flag);
 747 }
 748
 749 static void flush_qp(struct iwch_qp *qhp, unsigned long *flag)
 750 {
 751         if (qhp->ibqp.uobject)
 752                 cxio_set_wq_in_error(&qhp->wq);
 753         else
 754                 __flush_qp(qhp, flag);
 755 }
 756
 757
 758 /*
 759  * Return count of RECV WRs posted
 760  */
 761 u16 iwch_rqes_posted(struct iwch_qp *qhp)
 762 {
 763         union t3_wr *wqe = qhp->wq.queue;
 764         u16 count = 0;
 765         while ((count+1) != 0 && fw_riwrh_opcode((struct fw_riwrh *)wqe) == T3_WR_RCV) {
 766                 count++;
 767                 wqe++;
 768         }
 769         PDBG("%s qhp %p count %u\n", __func__, qhp, count);
 770         return count;
 771 }
 772
 773 static int rdma_init(struct iwch_dev *rhp, struct iwch_qp *qhp,
 774                                 enum iwch_qp_attr_mask mask,
 775                                 struct iwch_qp_attributes *attrs)
 776 {
 777         struct t3_rdma_init_attr init_attr;
 778         int ret;
 779
 780         init_attr.tid = qhp->ep->hwtid;
 781         init_attr.qpid = qhp->wq.qpid;
 782         init_attr.pdid = qhp->attr.pd;
 783         init_attr.scqid = qhp->attr.scq;
 784         init_attr.rcqid = qhp->attr.rcq;
 785         init_attr.rq_addr = qhp->wq.rq_addr;
 786         init_attr.rq_size = 1 << qhp->wq.rq_size_log2;
 787         init_attr.mpaattrs = uP_RI_MPA_IETF_ENABLE |
 788                 qhp->attr.mpa_attr.recv_marker_enabled |
 789                 (qhp->attr.mpa_attr.xmit_marker_enabled << 1) |
 790                 (qhp->attr.mpa_attr.crc_enabled << 2);
 791
 792         /*
 793          * XXX - The IWCM doesn't quite handle getting these
 794          * attrs set before going into RTS.  For now, just turn
 795          * them on always...
 796          */
 797 #if 0
 798         init_attr.qpcaps = qhp->attr.enableRdmaRead |
 799                 (qhp->attr.enableRdmaWrite << 1) |
 800                 (qhp->attr.enableBind << 2) |
 801                 (qhp->attr.enable_stag0_fastreg << 3) |
 802                 (qhp->attr.enable_stag0_fastreg << 4);
 803 #else
 804         init_attr.qpcaps = 0x1f;
 805 #endif
 806         init_attr.tcp_emss = qhp->ep->emss;
 807         init_attr.ord = qhp->attr.max_ord;
 808         init_attr.ird = qhp->attr.max_ird;
 809         init_attr.qp_dma_addr = qhp->wq.dma_addr;
 810         init_attr.qp_dma_size = (1UL << qhp->wq.size_log2);
 811         init_attr.rqe_count = iwch_rqes_posted(qhp);
 812         init_attr.flags = qhp->attr.mpa_attr.initiator ? MPA_INITIATOR : 0;
 813         init_attr.flags |= capable(CAP_NET_BIND_SERVICE) ? PRIV_QP : 0;
 814         if (peer2peer) {
 815                 init_attr.rtr_type = RTR_READ;
 816                 if (init_attr.ord == 0 && qhp->attr.mpa_attr.initiator)
 817                         init_attr.ord = 1;
 818                 if (init_attr.ird == 0 && !qhp->attr.mpa_attr.initiator)
 819                         init_attr.ird = 1;
 820         } else
 821                 init_attr.rtr_type = 0;
 822         init_attr.irs = qhp->ep->rcv_seq;
 823         PDBG("%s init_attr.rq_addr 0x%x init_attr.rq_size = %d "
 824              "flags 0x%x qpcaps 0x%x\n", __func__,
 825              init_attr.rq_addr, init_attr.rq_size,
 826              init_attr.flags, init_attr.qpcaps);
 827         ret = cxio_rdma_init(&rhp->rdev, &init_attr);
 828         PDBG("%s ret %d\n", __func__, ret);
 829         return ret;
 830 }
 831
 832 int iwch_modify_qp(struct iwch_dev *rhp, struct iwch_qp *qhp,
 833                                 enum iwch_qp_attr_mask mask,
 834                                 struct iwch_qp_attributes *attrs,
 835                                 int internal)
 836 {
 837         int ret = 0;
 838         struct iwch_qp_attributes newattr = qhp->attr;
 839         unsigned long flag;
 840         int disconnect = 0;
 841         int terminate = 0;
 842         int abort = 0;
 843         int free = 0;
 844         struct iwch_ep *ep = NULL;
 845
 846         PDBG("%s qhp %p qpid 0x%x ep %p state %d -> %d\n", __func__,
 847              qhp, qhp->wq.qpid, qhp->ep, qhp->attr.state,
 848              (mask & IWCH_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
 849
 850         spin_lock_irqsave(&qhp->lock, flag);
 851
 852         /* Process attr changes if in IDLE */
 853         if (mask & IWCH_QP_ATTR_VALID_MODIFY) {
 854                 if (qhp->attr.state != IWCH_QP_STATE_IDLE) {
 855                         ret = -EIO;
 856                         goto out;
 857                 }
 858                 if (mask & IWCH_QP_ATTR_ENABLE_RDMA_READ)
 859                         newattr.enable_rdma_read = attrs->enable_rdma_read;
 860                 if (mask & IWCH_QP_ATTR_ENABLE_RDMA_WRITE)
 861                         newattr.enable_rdma_write = attrs->enable_rdma_write;
 862                 if (mask & IWCH_QP_ATTR_ENABLE_RDMA_BIND)
 863                         newattr.enable_bind = attrs->enable_bind;
 864                 if (mask & IWCH_QP_ATTR_MAX_ORD) {
 865                         if (attrs->max_ord >
 866                             rhp->attr.max_rdma_read_qp_depth) {
 867                                 ret = -EINVAL;
 868                                 goto out;
 869                         }
 870                         newattr.max_ord = attrs->max_ord;
 871                 }
 872                 if (mask & IWCH_QP_ATTR_MAX_IRD) {
 873                         if (attrs->max_ird >
 874                             rhp->attr.max_rdma_reads_per_qp) {
 875                                 ret = -EINVAL;
 876                                 goto out;
 877                         }
 878                         newattr.max_ird = attrs->max_ird;
 879                 }
 880                 qhp->attr = newattr;
 881         }
 882
 883         if (!(mask & IWCH_QP_ATTR_NEXT_STATE))
 884                 goto out;
 885         if (qhp->attr.state == attrs->next_state)
 886                 goto out;
 887
 888         switch (qhp->attr.state) {
 889         case IWCH_QP_STATE_IDLE:
 890                 switch (attrs->next_state) {
 891                 case IWCH_QP_STATE_RTS:
 892                         if (!(mask & IWCH_QP_ATTR_LLP_STREAM_HANDLE)) {
 893                                 ret = -EINVAL;
 894                                 goto out;
 895                         }
 896                         if (!(mask & IWCH_QP_ATTR_MPA_ATTR)) {
 897                                 ret = -EINVAL;
 898                                 goto out;
 899                         }
 900                         qhp->attr.mpa_attr = attrs->mpa_attr;
 901                         qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
 902                         qhp->ep = qhp->attr.llp_stream_handle;
 903                         qhp->attr.state = IWCH_QP_STATE_RTS;
 904
 905                         /*
 906                          * Ref the endpoint here and deref when we
 907                          * disassociate the endpoint from the QP.  This
 908                          * happens in CLOSING->IDLE transition or *->ERROR
 909                          * transition.
 910                          */
 911                         get_ep(&qhp->ep->com);
 912                         spin_unlock_irqrestore(&qhp->lock, flag);
 913                         ret = rdma_init(rhp, qhp, mask, attrs);
 914                         spin_lock_irqsave(&qhp->lock, flag);
 915                         if (ret)
 916                                 goto err;
 917                         break;
 918                 case IWCH_QP_STATE_ERROR:
 919                         qhp->attr.state = IWCH_QP_STATE_ERROR;
 920                         flush_qp(qhp, &flag);
 921                         break;
 922                 default:
 923                         ret = -EINVAL;
 924                         goto out;
 925                 }
 926                 break;
 927         case IWCH_QP_STATE_RTS:
 928                 switch (attrs->next_state) {
 929                 case IWCH_QP_STATE_CLOSING:
 930                         BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
 931                         qhp->attr.state = IWCH_QP_STATE_CLOSING;
 932                         if (!internal) {
 933                                 abort=0;
 934                                 disconnect = 1;
 935                                 ep = qhp->ep;
 936                                 get_ep(&ep->com);
 937                         }
 938                         break;
 939                 case IWCH_QP_STATE_TERMINATE:
 940                         qhp->attr.state = IWCH_QP_STATE_TERMINATE;
 941                         if (qhp->ibqp.uobject)
 942                                 cxio_set_wq_in_error(&qhp->wq);
 943                         if (!internal)
 944                                 terminate = 1;
 945                         break;
 946                 case IWCH_QP_STATE_ERROR:
 947                         qhp->attr.state = IWCH_QP_STATE_ERROR;
 948                         if (!internal) {
 949                                 abort=1;
 950                                 disconnect = 1;
 951                                 ep = qhp->ep;
 952                                 get_ep(&ep->com);
 953                         }
 954                         goto err;
 955                         break;
 956                 default:
 957                         ret = -EINVAL;
 958                         goto out;
 959                 }
 960                 break;
 961         case IWCH_QP_STATE_CLOSING:
 962                 if (!internal) {
 963                         ret = -EINVAL;
 964                         goto out;
 965                 }
 966                 switch (attrs->next_state) {
 967                         case IWCH_QP_STATE_IDLE:
 968                                 flush_qp(qhp, &flag);
 969                                 qhp->attr.state = IWCH_QP_STATE_IDLE;
 970                                 qhp->attr.llp_stream_handle = NULL;
 971                                 put_ep(&qhp->ep->com);
 972                                 qhp->ep = NULL;
 973                                 wake_up(&qhp->wait);
 974                                 break;
 975                         case IWCH_QP_STATE_ERROR:
 976                                 goto err;
 977                         default:
 978                                 ret = -EINVAL;
 979                                 goto err;
 980                 }
 981                 break;
 982         case IWCH_QP_STATE_ERROR:
 983                 if (attrs->next_state != IWCH_QP_STATE_IDLE) {
 984                         ret = -EINVAL;
 985                         goto out;
 986                 }
 987
 988                 if (!Q_EMPTY(qhp->wq.sq_rptr, qhp->wq.sq_wptr) ||
 989                     !Q_EMPTY(qhp->wq.rq_rptr, qhp->wq.rq_wptr)) {
 990                         ret = -EINVAL;
 991                         goto out;
 992                 }
 993                 qhp->attr.state = IWCH_QP_STATE_IDLE;
 994                 memset(&qhp->attr, 0, sizeof(qhp->attr));
 995                 break;
 996         case IWCH_QP_STATE_TERMINATE:
 997                 if (!internal) {
 998                         ret = -EINVAL;
 999                         goto out;
1000                 }
1001                 goto err;
1002                 break;
1003         default:
1004                 printk(KERN_ERR "%s in a bad state %d\n",
1005                        __func__, qhp->attr.state);
1006                 ret = -EINVAL;
1007                 goto err;
1008                 break;
1009         }
1010         goto out;
1011 err:
1012         PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1013              qhp->wq.qpid);
1014
1015         /* disassociate the LLP connection */
1016         qhp->attr.llp_stream_handle = NULL;
1017         ep = qhp->ep;
1018         qhp->ep = NULL;
1019         qhp->attr.state = IWCH_QP_STATE_ERROR;
1020         free=1;
1021         wake_up(&qhp->wait);
1022         BUG_ON(!ep);
1023         flush_qp(qhp, &flag);
1024 out:
1025         spin_unlock_irqrestore(&qhp->lock, flag);
1026
1027         if (terminate)
1028                 iwch_post_terminate(qhp, NULL);
1029
1030         /*
1031          * If disconnect is 1, then we need to initiate a disconnect
1032          * on the EP.  This can be a normal close (RTS->CLOSING) or
1033          * an abnormal close (RTS/CLOSING->ERROR).
1034          */
1035         if (disconnect) {
1036                 iwch_ep_disconnect(ep, abort, GFP_KERNEL);
1037                 put_ep(&ep->com);
1038         }
1039
1040         /*
1041          * If free is 1, then we've disassociated the EP from the QP
1042          * and we need to dereference the EP.
1043          */
1044         if (free)
1045                 put_ep(&ep->com);
1046
1047         PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1048         return ret;
1049 }
1050
1051 static int quiesce_qp(struct iwch_qp *qhp)
1052 {
1053         spin_lock_irq(&qhp->lock);
1054         iwch_quiesce_tid(qhp->ep);
1055         qhp->flags |= QP_QUIESCED;
1056         spin_unlock_irq(&qhp->lock);
1057         return 0;
1058 }
1059
1060 static int resume_qp(struct iwch_qp *qhp)
1061 {
1062         spin_lock_irq(&qhp->lock);
1063         iwch_resume_tid(qhp->ep);
1064         qhp->flags &= ~QP_QUIESCED;
1065         spin_unlock_irq(&qhp->lock);
1066         return 0;
1067 }
1068
1069 int iwch_quiesce_qps(struct iwch_cq *chp)
1070 {
1071         int i;
1072         struct iwch_qp *qhp;
1073
1074         for (i=0; i < T3_MAX_NUM_QP; i++) {
1075                 qhp = get_qhp(chp->rhp, i);
1076                 if (!qhp)
1077                         continue;
1078                 if ((qhp->attr.rcq == chp->cq.cqid) && !qp_quiesced(qhp)) {
1079                         quiesce_qp(qhp);
1080                         continue;
1081                 }
1082                 if ((qhp->attr.scq == chp->cq.cqid) && !qp_quiesced(qhp))
1083                         quiesce_qp(qhp);
1084         }
1085         return 0;
1086 }
1087
1088 int iwch_resume_qps(struct iwch_cq *chp)
1089 {
1090         int i;
1091         struct iwch_qp *qhp;
1092
1093         for (i=0; i < T3_MAX_NUM_QP; i++) {
1094                 qhp = get_qhp(chp->rhp, i);
1095                 if (!qhp)
1096                         continue;
1097                 if ((qhp->attr.rcq == chp->cq.cqid) && qp_quiesced(qhp)) {
1098                         resume_qp(qhp);
1099                         continue;
1100                 }
1101                 if ((qhp->attr.scq == chp->cq.cqid) && qp_quiesced(qhp))
1102                         resume_qp(qhp);
1103         }
1104         return 0;
1105 }