2 * linux/drivers/ide/ide-pmac.c
4 * Support for IDE interfaces on PowerMacs.
5 * These IDE interfaces are memory-mapped and have a DBDMA channel
8 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
15 * Some code taken from drivers/ide/ide-dma.c:
17 * Copyright (c) 1995-1998 Mark Lord
19 * TODO: - Use pre-calculated (kauai) timing tables all the time and
20 * get rid of the "rounded" tables used previously, so we have the
21 * same table format for all controllers and can then just have one
25 #include <linux/config.h>
26 #include <linux/types.h>
27 #include <linux/kernel.h>
28 #include <linux/sched.h>
29 #include <linux/init.h>
30 #include <linux/delay.h>
31 #include <linux/ide.h>
32 #include <linux/notifier.h>
33 #include <linux/reboot.h>
34 #include <linux/pci.h>
35 #include <linux/adb.h>
36 #include <linux/pmu.h>
37 #include <linux/scatterlist.h>
41 #include <asm/dbdma.h>
43 #include <asm/pci-bridge.h>
44 #include <asm/machdep.h>
45 #include <asm/pmac_feature.h>
46 #include <asm/sections.h>
50 #include <asm/mediabay.h>
53 #include "ide-timing.h"
57 #define DMA_WAIT_TIMEOUT 50
59 typedef struct pmac_ide_hwif {
60 unsigned long regbase;
64 unsigned cable_80 : 1;
65 unsigned mediabay : 1;
66 unsigned broken_dma : 1;
67 unsigned broken_dma_warn : 1;
68 struct device_node* node;
69 struct macio_dev *mdev;
71 volatile u32 __iomem * *kauai_fcr;
72 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
73 /* Those fields are duplicating what is in hwif. We currently
74 * can't use the hwif ones because of some assumptions that are
75 * beeing done by the generic code about the kind of dma controller
76 * and format of the dma table. This will have to be fixed though.
78 volatile struct dbdma_regs __iomem * dma_regs;
79 struct dbdma_cmd* dma_table_cpu;
84 static pmac_ide_hwif_t pmac_ide[MAX_HWIFS];
85 static int pmac_ide_count;
88 controller_ohare, /* OHare based */
89 controller_heathrow, /* Heathrow/Paddington */
90 controller_kl_ata3, /* KeyLargo ATA-3 */
91 controller_kl_ata4, /* KeyLargo ATA-4 */
92 controller_un_ata6, /* UniNorth2 ATA-6 */
93 controller_k2_ata6, /* K2 ATA-6 */
94 controller_sh_ata6, /* Shasta ATA-6 */
97 static const char* model_name[] = {
98 "OHare ATA", /* OHare based */
99 "Heathrow ATA", /* Heathrow/Paddington */
100 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
101 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
102 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
103 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
104 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
108 * Extra registers, both 32-bit little-endian
110 #define IDE_TIMING_CONFIG 0x200
111 #define IDE_INTERRUPT 0x300
113 /* Kauai (U2) ATA has different register setup */
114 #define IDE_KAUAI_PIO_CONFIG 0x200
115 #define IDE_KAUAI_ULTRA_CONFIG 0x210
116 #define IDE_KAUAI_POLL_CONFIG 0x220
119 * Timing configuration register definitions
122 /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
123 #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
124 #define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
125 #define IDE_SYSCLK_NS 30 /* 33Mhz cell */
126 #define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
128 /* 133Mhz cell, found in shasta.
129 * See comments about 100 Mhz Uninorth 2...
130 * Note that PIO_MASK and MDMA_MASK seem to overlap
132 #define TR_133_PIOREG_PIO_MASK 0xff000fff
133 #define TR_133_PIOREG_MDMA_MASK 0x00fff800
134 #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
135 #define TR_133_UDMAREG_UDMA_EN 0x00000001
137 /* 100Mhz cell, found in Uninorth 2. I don't have much infos about
138 * this one yet, it appears as a pci device (106b/0033) on uninorth
139 * internal PCI bus and it's clock is controlled like gem or fw. It
140 * appears to be an evolution of keylargo ATA4 with a timing register
141 * extended to 2 32bits registers and a similar DBDMA channel. Other
142 * registers seem to exist but I can't tell much about them.
144 * So far, I'm using pre-calculated tables for this extracted from
145 * the values used by the MacOS X driver.
147 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
148 * register controls the UDMA timings. At least, it seems bit 0
149 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
150 * cycle time in units of 10ns. Bits 8..15 are used by I don't
151 * know their meaning yet
153 #define TR_100_PIOREG_PIO_MASK 0xff000fff
154 #define TR_100_PIOREG_MDMA_MASK 0x00fff000
155 #define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
156 #define TR_100_UDMAREG_UDMA_EN 0x00000001
159 /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
160 * 40 connector cable and to 4 on 80 connector one.
161 * Clock unit is 15ns (66Mhz)
163 * 3 Values can be programmed:
164 * - Write data setup, which appears to match the cycle time. They
165 * also call it DIOW setup.
166 * - Ready to pause time (from spec)
167 * - Address setup. That one is weird. I don't see where exactly
168 * it fits in UDMA cycles, I got it's name from an obscure piece
169 * of commented out code in Darwin. They leave it to 0, we do as
170 * well, despite a comment that would lead to think it has a
172 * Apple also add 60ns to the write data setup (or cycle time ?) on
175 #define TR_66_UDMA_MASK 0xfff00000
176 #define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
177 #define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
178 #define TR_66_UDMA_ADDRSETUP_SHIFT 29
179 #define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
180 #define TR_66_UDMA_RDY2PAUS_SHIFT 25
181 #define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
182 #define TR_66_UDMA_WRDATASETUP_SHIFT 21
183 #define TR_66_MDMA_MASK 0x000ffc00
184 #define TR_66_MDMA_RECOVERY_MASK 0x000f8000
185 #define TR_66_MDMA_RECOVERY_SHIFT 15
186 #define TR_66_MDMA_ACCESS_MASK 0x00007c00
187 #define TR_66_MDMA_ACCESS_SHIFT 10
188 #define TR_66_PIO_MASK 0x000003ff
189 #define TR_66_PIO_RECOVERY_MASK 0x000003e0
190 #define TR_66_PIO_RECOVERY_SHIFT 5
191 #define TR_66_PIO_ACCESS_MASK 0x0000001f
192 #define TR_66_PIO_ACCESS_SHIFT 0
194 /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
195 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
197 * The access time and recovery time can be programmed. Some older
198 * Darwin code base limit OHare to 150ns cycle time. I decided to do
199 * the same here fore safety against broken old hardware ;)
200 * The HalfTick bit, when set, adds half a clock (15ns) to the access
201 * time and removes one from recovery. It's not supported on KeyLargo
202 * implementation afaik. The E bit appears to be set for PIO mode 0 and
203 * is used to reach long timings used in this mode.
205 #define TR_33_MDMA_MASK 0x003ff800
206 #define TR_33_MDMA_RECOVERY_MASK 0x001f0000
207 #define TR_33_MDMA_RECOVERY_SHIFT 16
208 #define TR_33_MDMA_ACCESS_MASK 0x0000f800
209 #define TR_33_MDMA_ACCESS_SHIFT 11
210 #define TR_33_MDMA_HALFTICK 0x00200000
211 #define TR_33_PIO_MASK 0x000007ff
212 #define TR_33_PIO_E 0x00000400
213 #define TR_33_PIO_RECOVERY_MASK 0x000003e0
214 #define TR_33_PIO_RECOVERY_SHIFT 5
215 #define TR_33_PIO_ACCESS_MASK 0x0000001f
216 #define TR_33_PIO_ACCESS_SHIFT 0
219 * Interrupt register definitions
221 #define IDE_INTR_DMA 0x80000000
222 #define IDE_INTR_DEVICE 0x40000000
225 * FCR Register on Kauai. Not sure what bit 0x4 is ...
227 #define KAUAI_FCR_UATA_MAGIC 0x00000004
228 #define KAUAI_FCR_UATA_RESET_N 0x00000002
229 #define KAUAI_FCR_UATA_ENABLE 0x00000001
231 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
233 /* Rounded Multiword DMA timings
235 * I gave up finding a generic formula for all controller
236 * types and instead, built tables based on timing values
237 * used by Apple in Darwin's implementation.
239 struct mdma_timings_t {
245 struct mdma_timings_t mdma_timings_33[] =
258 struct mdma_timings_t mdma_timings_33k[] =
271 struct mdma_timings_t mdma_timings_66[] =
284 /* KeyLargo ATA-4 Ultra DMA timings (rounded) */
286 int addrSetup; /* ??? */
289 } kl66_udma_timings[] =
291 { 0, 180, 120 }, /* Mode 0 */
292 { 0, 150, 90 }, /* 1 */
293 { 0, 120, 60 }, /* 2 */
294 { 0, 90, 45 }, /* 3 */
295 { 0, 90, 30 } /* 4 */
298 /* UniNorth 2 ATA/100 timings */
299 struct kauai_timing {
304 static struct kauai_timing kauai_pio_timings[] =
306 { 930 , 0x08000fff },
307 { 600 , 0x08000a92 },
308 { 383 , 0x0800060f },
309 { 360 , 0x08000492 },
310 { 330 , 0x0800048f },
311 { 300 , 0x080003cf },
312 { 270 , 0x080003cc },
313 { 240 , 0x0800038b },
314 { 239 , 0x0800030c },
315 { 180 , 0x05000249 },
319 static struct kauai_timing kauai_mdma_timings[] =
321 { 1260 , 0x00fff000 },
322 { 480 , 0x00618000 },
323 { 360 , 0x00492000 },
324 { 270 , 0x0038e000 },
325 { 240 , 0x0030c000 },
326 { 210 , 0x002cb000 },
327 { 180 , 0x00249000 },
328 { 150 , 0x00209000 },
329 { 120 , 0x00148000 },
333 static struct kauai_timing kauai_udma_timings[] =
335 { 120 , 0x000070c0 },
344 static struct kauai_timing shasta_pio_timings[] =
346 { 930 , 0x08000fff },
347 { 600 , 0x0A000c97 },
348 { 383 , 0x07000712 },
349 { 360 , 0x040003cd },
350 { 330 , 0x040003cd },
351 { 300 , 0x040003cd },
352 { 270 , 0x040003cd },
353 { 240 , 0x040003cd },
354 { 239 , 0x040003cd },
355 { 180 , 0x0400028b },
359 static struct kauai_timing shasta_mdma_timings[] =
361 { 1260 , 0x00fff000 },
362 { 480 , 0x00820800 },
363 { 360 , 0x00820800 },
364 { 270 , 0x00820800 },
365 { 240 , 0x00820800 },
366 { 210 , 0x00820800 },
367 { 180 , 0x00820800 },
368 { 150 , 0x0028b000 },
369 { 120 , 0x001ca000 },
373 static struct kauai_timing shasta_udma133_timings[] =
375 { 120 , 0x00035901, },
376 { 90 , 0x000348b1, },
377 { 60 , 0x00033881, },
378 { 45 , 0x00033861, },
379 { 30 , 0x00033841, },
380 { 20 , 0x00033031, },
381 { 15 , 0x00033021, },
387 kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
391 for (i=0; table[i].cycle_time; i++)
392 if (cycle_time > table[i+1].cycle_time)
393 return table[i].timing_reg;
397 /* allow up to 256 DBDMA commands per xfer */
398 #define MAX_DCMDS 256
401 * Wait 1s for disk to answer on IDE bus after a hard reset
402 * of the device (via GPIO/FCR).
404 * Some devices seem to "pollute" the bus even after dropping
405 * the BSY bit (typically some combo drives slave on the UDMA
406 * bus) after a hard reset. Since we hard reset all drives on
407 * KeyLargo ATA66, we have to keep that delay around. I may end
408 * up not hard resetting anymore on these and keep the delay only
409 * for older interfaces instead (we have to reset when coming
410 * from MacOS...) --BenH.
412 #define IDE_WAKEUP_DELAY (1*HZ)
414 static void pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif);
415 static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq);
416 static int pmac_ide_tune_chipset(ide_drive_t *drive, u8 speed);
417 static void pmac_ide_tuneproc(ide_drive_t *drive, u8 pio);
418 static void pmac_ide_selectproc(ide_drive_t *drive);
419 static void pmac_ide_kauai_selectproc(ide_drive_t *drive);
421 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
424 * Below is the code for blinking the laptop LED along with hard
428 #ifdef CONFIG_BLK_DEV_IDE_PMAC_BLINK
430 /* Set to 50ms minimum led-on time (also used to limit frequency
431 * of requests sent to the PMU
433 #define PMU_HD_BLINK_TIME (HZ/50)
435 static struct adb_request pmu_blink_on, pmu_blink_off;
436 static spinlock_t pmu_blink_lock;
437 static unsigned long pmu_blink_stoptime;
438 static int pmu_blink_ledstate;
439 static struct timer_list pmu_blink_timer;
440 static int pmu_ide_blink_enabled;
444 pmu_hd_blink_timeout(unsigned long data)
448 spin_lock_irqsave(&pmu_blink_lock, flags);
450 /* We may have been triggered again in a racy way, check
451 * that we really want to switch it off
453 if (time_after(pmu_blink_stoptime, jiffies))
456 /* Previous req. not complete, try 100ms more */
457 if (pmu_blink_off.complete == 0)
458 mod_timer(&pmu_blink_timer, jiffies + PMU_HD_BLINK_TIME);
459 else if (pmu_blink_ledstate) {
460 pmu_request(&pmu_blink_off, NULL, 4, 0xee, 4, 0, 0);
461 pmu_blink_ledstate = 0;
464 spin_unlock_irqrestore(&pmu_blink_lock, flags);
468 pmu_hd_kick_blink(void *data, int rw)
472 pmu_blink_stoptime = jiffies + PMU_HD_BLINK_TIME;
474 mod_timer(&pmu_blink_timer, pmu_blink_stoptime);
475 /* Fast path when LED is already ON */
476 if (pmu_blink_ledstate == 1)
478 spin_lock_irqsave(&pmu_blink_lock, flags);
479 if (pmu_blink_on.complete && !pmu_blink_ledstate) {
480 pmu_request(&pmu_blink_on, NULL, 4, 0xee, 4, 0, 1);
481 pmu_blink_ledstate = 1;
483 spin_unlock_irqrestore(&pmu_blink_lock, flags);
487 pmu_hd_blink_init(void)
489 struct device_node *dt;
492 /* Currently, I only enable this feature on KeyLargo based laptops,
493 * older laptops may support it (at least heathrow/paddington) but
494 * I don't feel like loading those venerable old machines with so
495 * much additional interrupt & PMU activity...
497 if (pmu_get_model() != PMU_KEYLARGO_BASED)
500 dt = of_find_node_by_path("/");
503 model = (const char *)get_property(dt, "model", NULL);
506 if (strncmp(model, "PowerBook", strlen("PowerBook")) != 0 &&
507 strncmp(model, "iBook", strlen("iBook")) != 0) {
513 pmu_blink_on.complete = 1;
514 pmu_blink_off.complete = 1;
515 spin_lock_init(&pmu_blink_lock);
516 init_timer(&pmu_blink_timer);
517 pmu_blink_timer.function = pmu_hd_blink_timeout;
522 #endif /* CONFIG_BLK_DEV_IDE_PMAC_BLINK */
525 * N.B. this can't be an initfunc, because the media-bay task can
526 * call ide_[un]register at any time.
529 pmac_ide_init_hwif_ports(hw_regs_t *hw,
530 unsigned long data_port, unsigned long ctrl_port,
538 for (ix = 0; ix < MAX_HWIFS; ++ix)
539 if (data_port == pmac_ide[ix].regbase)
542 if (ix >= MAX_HWIFS) {
543 /* Probably a PCI interface... */
544 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; ++i)
545 hw->io_ports[i] = data_port + i - IDE_DATA_OFFSET;
546 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
550 for (i = 0; i < 8; ++i)
551 hw->io_ports[i] = data_port + i * 0x10;
552 hw->io_ports[8] = data_port + 0x160;
555 *irq = pmac_ide[ix].irq;
558 #define PMAC_IDE_REG(x) ((void __iomem *)(IDE_DATA_REG+(x)))
561 * Apply the timings of the proper unit (master/slave) to the shared
562 * timing register when selecting that unit. This version is for
563 * ASICs with a single timing register
566 pmac_ide_selectproc(ide_drive_t *drive)
568 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
573 if (drive->select.b.unit & 0x01)
574 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
576 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
577 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
581 * Apply the timings of the proper unit (master/slave) to the shared
582 * timing register when selecting that unit. This version is for
583 * ASICs with a dual timing register (Kauai)
586 pmac_ide_kauai_selectproc(ide_drive_t *drive)
588 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
593 if (drive->select.b.unit & 0x01) {
594 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
595 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
597 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
598 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
600 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
604 * Force an update of controller timing values for a given drive
607 pmac_ide_do_update_timings(ide_drive_t *drive)
609 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
614 if (pmif->kind == controller_sh_ata6 ||
615 pmif->kind == controller_un_ata6 ||
616 pmif->kind == controller_k2_ata6)
617 pmac_ide_kauai_selectproc(drive);
619 pmac_ide_selectproc(drive);
623 pmac_outbsync(ide_drive_t *drive, u8 value, unsigned long port)
627 writeb(value, (void __iomem *) port);
628 tmp = readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
632 * Send the SET_FEATURE IDE command to the drive and update drive->id with
633 * the new state. We currently don't use the generic routine as it used to
634 * cause various trouble, especially with older mediabays.
635 * This code is sometimes triggering a spurrious interrupt though, I need
636 * to sort that out sooner or later and see if I can finally get the
637 * common version to work properly in all cases
640 pmac_ide_do_setfeature(ide_drive_t *drive, u8 command)
642 ide_hwif_t *hwif = HWIF(drive);
645 disable_irq_nosync(hwif->irq);
648 SELECT_MASK(drive, 0);
650 /* Get rid of pending error state */
651 (void) hwif->INB(IDE_STATUS_REG);
652 /* Timeout bumped for some powerbooks */
653 if (wait_for_ready(drive, 2000)) {
654 /* Timeout bumped for some powerbooks */
655 printk(KERN_ERR "%s: pmac_ide_do_setfeature disk not ready "
656 "before SET_FEATURE!\n", drive->name);
660 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
661 hwif->OUTB(command, IDE_NSECTOR_REG);
662 hwif->OUTB(SETFEATURES_XFER, IDE_FEATURE_REG);
663 hwif->OUTBSYNC(drive, WIN_SETFEATURES, IDE_COMMAND_REG);
665 /* Timeout bumped for some powerbooks */
666 result = wait_for_ready(drive, 2000);
667 hwif->OUTB(drive->ctl, IDE_CONTROL_REG);
669 printk(KERN_ERR "%s: pmac_ide_do_setfeature disk not ready "
670 "after SET_FEATURE !\n", drive->name);
672 SELECT_MASK(drive, 0);
674 drive->id->dma_ultra &= ~0xFF00;
675 drive->id->dma_mword &= ~0x0F00;
676 drive->id->dma_1word &= ~0x0F00;
679 drive->id->dma_ultra |= 0x8080; break;
681 drive->id->dma_ultra |= 0x4040; break;
683 drive->id->dma_ultra |= 0x2020; break;
685 drive->id->dma_ultra |= 0x1010; break;
687 drive->id->dma_ultra |= 0x0808; break;
689 drive->id->dma_ultra |= 0x0404; break;
691 drive->id->dma_ultra |= 0x0202; break;
693 drive->id->dma_ultra |= 0x0101; break;
695 drive->id->dma_mword |= 0x0404; break;
697 drive->id->dma_mword |= 0x0202; break;
699 drive->id->dma_mword |= 0x0101; break;
701 drive->id->dma_1word |= 0x0404; break;
703 drive->id->dma_1word |= 0x0202; break;
705 drive->id->dma_1word |= 0x0101; break;
709 enable_irq(hwif->irq);
714 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
717 pmac_ide_tuneproc(ide_drive_t *drive, u8 pio)
721 unsigned accessTicks, recTicks;
722 unsigned accessTime, recTime;
723 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
728 /* which drive is it ? */
729 timings = &pmif->timings[drive->select.b.unit & 0x01];
731 pio = ide_get_best_pio_mode(drive, pio, 4, &d);
733 switch (pmif->kind) {
734 case controller_sh_ata6: {
736 u32 tr = kauai_lookup_timing(shasta_pio_timings, d.cycle_time);
739 *timings = ((*timings) & ~TR_133_PIOREG_PIO_MASK) | tr;
742 case controller_un_ata6:
743 case controller_k2_ata6: {
745 u32 tr = kauai_lookup_timing(kauai_pio_timings, d.cycle_time);
748 *timings = ((*timings) & ~TR_100_PIOREG_PIO_MASK) | tr;
751 case controller_kl_ata4:
753 recTime = d.cycle_time - ide_pio_timings[pio].active_time
754 - ide_pio_timings[pio].setup_time;
755 recTime = max(recTime, 150U);
756 accessTime = ide_pio_timings[pio].active_time;
757 accessTime = max(accessTime, 150U);
758 accessTicks = SYSCLK_TICKS_66(accessTime);
759 accessTicks = min(accessTicks, 0x1fU);
760 recTicks = SYSCLK_TICKS_66(recTime);
761 recTicks = min(recTicks, 0x1fU);
762 *timings = ((*timings) & ~TR_66_PIO_MASK) |
763 (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
764 (recTicks << TR_66_PIO_RECOVERY_SHIFT);
769 recTime = d.cycle_time - ide_pio_timings[pio].active_time
770 - ide_pio_timings[pio].setup_time;
771 recTime = max(recTime, 150U);
772 accessTime = ide_pio_timings[pio].active_time;
773 accessTime = max(accessTime, 150U);
774 accessTicks = SYSCLK_TICKS(accessTime);
775 accessTicks = min(accessTicks, 0x1fU);
776 accessTicks = max(accessTicks, 4U);
777 recTicks = SYSCLK_TICKS(recTime);
778 recTicks = min(recTicks, 0x1fU);
779 recTicks = max(recTicks, 5U) - 4;
781 recTicks--; /* guess, but it's only for PIO0, so... */
784 *timings = ((*timings) & ~TR_33_PIO_MASK) |
785 (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
786 (recTicks << TR_33_PIO_RECOVERY_SHIFT);
788 *timings |= TR_33_PIO_E;
793 #ifdef IDE_PMAC_DEBUG
794 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
795 drive->name, pio, *timings);
798 if (drive->select.all == HWIF(drive)->INB(IDE_SELECT_REG))
799 pmac_ide_do_update_timings(drive);
802 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
805 * Calculate KeyLargo ATA/66 UDMA timings
808 set_timings_udma_ata4(u32 *timings, u8 speed)
810 unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
812 if (speed > XFER_UDMA_4)
815 rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
816 wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
817 addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
819 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
820 (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) |
821 (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
822 (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
824 #ifdef IDE_PMAC_DEBUG
825 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
826 speed & 0xf, *timings);
833 * Calculate Kauai ATA/100 UDMA timings
836 set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
838 struct ide_timing *t = ide_timing_find_mode(speed);
841 if (speed > XFER_UDMA_5 || t == NULL)
843 tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
846 *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
847 *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
853 * Calculate Shasta ATA/133 UDMA timings
856 set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
858 struct ide_timing *t = ide_timing_find_mode(speed);
861 if (speed > XFER_UDMA_6 || t == NULL)
863 tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
866 *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
867 *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
873 * Calculate MDMA timings for all cells
876 set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
877 u8 speed, int drive_cycle_time)
879 int cycleTime, accessTime = 0, recTime = 0;
880 unsigned accessTicks, recTicks;
881 struct mdma_timings_t* tm = NULL;
884 /* Get default cycle time for mode */
885 switch(speed & 0xf) {
886 case 0: cycleTime = 480; break;
887 case 1: cycleTime = 150; break;
888 case 2: cycleTime = 120; break;
892 /* Adjust for drive */
893 if (drive_cycle_time && drive_cycle_time > cycleTime)
894 cycleTime = drive_cycle_time;
895 /* OHare limits according to some old Apple sources */
896 if ((intf_type == controller_ohare) && (cycleTime < 150))
898 /* Get the proper timing array for this controller */
900 case controller_sh_ata6:
901 case controller_un_ata6:
902 case controller_k2_ata6:
904 case controller_kl_ata4:
905 tm = mdma_timings_66;
907 case controller_kl_ata3:
908 tm = mdma_timings_33k;
911 tm = mdma_timings_33;
915 /* Lookup matching access & recovery times */
918 if (tm[i+1].cycleTime < cycleTime)
924 cycleTime = tm[i].cycleTime;
925 accessTime = tm[i].accessTime;
926 recTime = tm[i].recoveryTime;
928 #ifdef IDE_PMAC_DEBUG
929 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
930 drive->name, cycleTime, accessTime, recTime);
934 case controller_sh_ata6: {
936 u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
939 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
940 *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
942 case controller_un_ata6:
943 case controller_k2_ata6: {
945 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
948 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
949 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
952 case controller_kl_ata4:
954 accessTicks = SYSCLK_TICKS_66(accessTime);
955 accessTicks = min(accessTicks, 0x1fU);
956 accessTicks = max(accessTicks, 0x1U);
957 recTicks = SYSCLK_TICKS_66(recTime);
958 recTicks = min(recTicks, 0x1fU);
959 recTicks = max(recTicks, 0x3U);
960 /* Clear out mdma bits and disable udma */
961 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
962 (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
963 (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
965 case controller_kl_ata3:
966 /* 33Mhz cell on KeyLargo */
967 accessTicks = SYSCLK_TICKS(accessTime);
968 accessTicks = max(accessTicks, 1U);
969 accessTicks = min(accessTicks, 0x1fU);
970 accessTime = accessTicks * IDE_SYSCLK_NS;
971 recTicks = SYSCLK_TICKS(recTime);
972 recTicks = max(recTicks, 1U);
973 recTicks = min(recTicks, 0x1fU);
974 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
975 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
976 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
979 /* 33Mhz cell on others */
981 int origAccessTime = accessTime;
982 int origRecTime = recTime;
984 accessTicks = SYSCLK_TICKS(accessTime);
985 accessTicks = max(accessTicks, 1U);
986 accessTicks = min(accessTicks, 0x1fU);
987 accessTime = accessTicks * IDE_SYSCLK_NS;
988 recTicks = SYSCLK_TICKS(recTime);
989 recTicks = max(recTicks, 2U) - 1;
990 recTicks = min(recTicks, 0x1fU);
991 recTime = (recTicks + 1) * IDE_SYSCLK_NS;
992 if ((accessTicks > 1) &&
993 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
994 ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
998 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
999 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
1000 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
1002 *timings |= TR_33_MDMA_HALFTICK;
1005 #ifdef IDE_PMAC_DEBUG
1006 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
1007 drive->name, speed & 0xf, *timings);
1011 #endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
1014 * Speedproc. This function is called by the core to set any of the standard
1015 * timing (PIO, MDMA or UDMA) to both the drive and the controller.
1016 * You may notice we don't use this function on normal "dma check" operation,
1017 * our dedicated function is more precise as it uses the drive provided
1018 * cycle time value. We should probably fix this one to deal with that too...
1021 pmac_ide_tune_chipset (ide_drive_t *drive, byte speed)
1023 int unit = (drive->select.b.unit & 0x01);
1025 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1026 u32 *timings, *timings2;
1031 timings = &pmif->timings[unit];
1032 timings2 = &pmif->timings[unit+2];
1035 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1037 if (pmif->kind != controller_sh_ata6)
1040 if (pmif->kind != controller_un_ata6 &&
1041 pmif->kind != controller_k2_ata6 &&
1042 pmif->kind != controller_sh_ata6)
1046 if (HWIF(drive)->udma_four == 0)
1051 if (pmif->kind == controller_kl_ata4)
1052 ret = set_timings_udma_ata4(timings, speed);
1053 else if (pmif->kind == controller_un_ata6
1054 || pmif->kind == controller_k2_ata6)
1055 ret = set_timings_udma_ata6(timings, timings2, speed);
1056 else if (pmif->kind == controller_sh_ata6)
1057 ret = set_timings_udma_shasta(timings, timings2, speed);
1064 ret = set_timings_mdma(drive, pmif->kind, timings, timings2, speed, 0);
1070 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1076 pmac_ide_tuneproc(drive, speed & 0x07);
1084 ret = pmac_ide_do_setfeature(drive, speed);
1088 pmac_ide_do_update_timings(drive);
1089 drive->current_speed = speed;
1095 * Blast some well known "safe" values to the timing registers at init or
1096 * wakeup from sleep time, before we do real calculation
1099 sanitize_timings(pmac_ide_hwif_t *pmif)
1101 unsigned int value, value2 = 0;
1103 switch(pmif->kind) {
1104 case controller_sh_ata6:
1106 value2 = 0x00033031;
1108 case controller_un_ata6:
1109 case controller_k2_ata6:
1111 value2 = 0x00002921;
1113 case controller_kl_ata4:
1116 case controller_kl_ata3:
1119 case controller_heathrow:
1120 case controller_ohare:
1125 pmif->timings[0] = pmif->timings[1] = value;
1126 pmif->timings[2] = pmif->timings[3] = value2;
1130 pmac_ide_get_base(int index)
1132 return pmac_ide[index].regbase;
1136 pmac_ide_check_base(unsigned long base)
1140 for (ix = 0; ix < MAX_HWIFS; ++ix)
1141 if (base == pmac_ide[ix].regbase)
1147 pmac_ide_get_irq(unsigned long base)
1151 for (ix = 0; ix < MAX_HWIFS; ++ix)
1152 if (base == pmac_ide[ix].regbase)
1153 return pmac_ide[ix].irq;
1157 static int ide_majors[] = { 3, 22, 33, 34, 56, 57 };
1160 pmac_find_ide_boot(char *bootdevice, int n)
1165 * Look through the list of IDE interfaces for this one.
1167 for (i = 0; i < pmac_ide_count; ++i) {
1169 if (!pmac_ide[i].node || !pmac_ide[i].node->full_name)
1171 name = pmac_ide[i].node->full_name;
1172 if (memcmp(name, bootdevice, n) == 0 && name[n] == 0) {
1173 /* XXX should cope with the 2nd drive as well... */
1174 return MKDEV(ide_majors[i], 0);
1181 /* Suspend call back, should be called after the child devices
1182 * have actually been suspended
1185 pmac_ide_do_suspend(ide_hwif_t *hwif)
1187 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1189 /* We clear the timings */
1190 pmif->timings[0] = 0;
1191 pmif->timings[1] = 0;
1193 #ifdef CONFIG_BLK_DEV_IDE_PMAC_BLINK
1194 /* Note: This code will be called for every hwif, thus we'll
1195 * try several time to stop the LED blinker timer, but that
1196 * should be harmless
1198 if (pmu_ide_blink_enabled) {
1199 unsigned long flags;
1201 /* Make sure we don't hit the PMU blink */
1202 spin_lock_irqsave(&pmu_blink_lock, flags);
1203 if (pmu_blink_ledstate)
1204 del_timer(&pmu_blink_timer);
1205 pmu_blink_ledstate = 0;
1206 spin_unlock_irqrestore(&pmu_blink_lock, flags);
1208 #endif /* CONFIG_BLK_DEV_IDE_PMAC_BLINK */
1210 disable_irq(pmif->irq);
1212 /* The media bay will handle itself just fine */
1216 /* Kauai has bus control FCRs directly here */
1217 if (pmif->kauai_fcr) {
1218 u32 fcr = readl(pmif->kauai_fcr);
1219 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
1220 writel(fcr, pmif->kauai_fcr);
1223 /* Disable the bus on older machines and the cell on kauai */
1224 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
1230 /* Resume call back, should be called before the child devices
1234 pmac_ide_do_resume(ide_hwif_t *hwif)
1236 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1238 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
1239 if (!pmif->mediabay) {
1240 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
1241 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
1243 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
1245 /* Kauai has it different */
1246 if (pmif->kauai_fcr) {
1247 u32 fcr = readl(pmif->kauai_fcr);
1248 fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
1249 writel(fcr, pmif->kauai_fcr);
1252 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1255 /* Sanitize drive timings */
1256 sanitize_timings(pmif);
1258 enable_irq(pmif->irq);
1264 * Setup, register & probe an IDE channel driven by this driver, this is
1265 * called by one of the 2 probe functions (macio or PCI). Note that a channel
1266 * that ends up beeing free of any device is not kept around by this driver
1267 * (it is kept in 2.4). This introduce an interface numbering change on some
1268 * rare machines unfortunately, but it's better this way.
1271 pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
1273 struct device_node *np = pmif->node;
1277 pmif->broken_dma = pmif->broken_dma_warn = 0;
1278 if (device_is_compatible(np, "shasta-ata"))
1279 pmif->kind = controller_sh_ata6;
1280 else if (device_is_compatible(np, "kauai-ata"))
1281 pmif->kind = controller_un_ata6;
1282 else if (device_is_compatible(np, "K2-UATA"))
1283 pmif->kind = controller_k2_ata6;
1284 else if (device_is_compatible(np, "keylargo-ata")) {
1285 if (strcmp(np->name, "ata-4") == 0)
1286 pmif->kind = controller_kl_ata4;
1288 pmif->kind = controller_kl_ata3;
1289 } else if (device_is_compatible(np, "heathrow-ata"))
1290 pmif->kind = controller_heathrow;
1292 pmif->kind = controller_ohare;
1293 pmif->broken_dma = 1;
1296 bidp = (int *)get_property(np, "AAPL,bus-id", NULL);
1297 pmif->aapl_bus_id = bidp ? *bidp : 0;
1299 /* Get cable type from device-tree */
1300 if (pmif->kind == controller_kl_ata4 || pmif->kind == controller_un_ata6
1301 || pmif->kind == controller_k2_ata6
1302 || pmif->kind == controller_sh_ata6) {
1303 char* cable = get_property(np, "cable-type", NULL);
1304 if (cable && !strncmp(cable, "80-", 3))
1307 /* G5's seem to have incorrect cable type in device-tree. Let's assume
1308 * they have a 80 conductor cable, this seem to be always the case unless
1309 * the user mucked around
1311 if (device_is_compatible(np, "K2-UATA") ||
1312 device_is_compatible(np, "shasta-ata"))
1315 /* On Kauai-type controllers, we make sure the FCR is correct */
1316 if (pmif->kauai_fcr)
1317 writel(KAUAI_FCR_UATA_MAGIC |
1318 KAUAI_FCR_UATA_RESET_N |
1319 KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
1323 /* Make sure we have sane timings */
1324 sanitize_timings(pmif);
1326 #ifndef CONFIG_PPC64
1327 /* XXX FIXME: Media bay stuff need re-organizing */
1328 if (np->parent && np->parent->name
1329 && strcasecmp(np->parent->name, "media-bay") == 0) {
1330 #ifdef CONFIG_PMAC_MEDIABAY
1331 media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq, hwif->index);
1332 #endif /* CONFIG_PMAC_MEDIABAY */
1335 pmif->aapl_bus_id = 1;
1336 } else if (pmif->kind == controller_ohare) {
1337 /* The code below is having trouble on some ohare machines
1338 * (timing related ?). Until I can put my hand on one of these
1339 * units, I keep the old way
1341 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1345 /* This is necessary to enable IDE when net-booting */
1346 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1347 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1349 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1350 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1353 /* Setup MMIO ops */
1354 default_hwif_mmiops(hwif);
1355 hwif->OUTBSYNC = pmac_outbsync;
1357 /* Tell common code _not_ to mess with resources */
1359 hwif->hwif_data = pmif;
1360 pmac_ide_init_hwif_ports(&hwif->hw, pmif->regbase, 0, &hwif->irq);
1361 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
1362 hwif->chipset = ide_pmac;
1363 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET] || pmif->mediabay;
1364 hwif->hold = pmif->mediabay;
1365 hwif->udma_four = pmif->cable_80;
1366 hwif->drives[0].unmask = 1;
1367 hwif->drives[1].unmask = 1;
1368 hwif->tuneproc = pmac_ide_tuneproc;
1369 if (pmif->kind == controller_un_ata6
1370 || pmif->kind == controller_k2_ata6
1371 || pmif->kind == controller_sh_ata6)
1372 hwif->selectproc = pmac_ide_kauai_selectproc;
1374 hwif->selectproc = pmac_ide_selectproc;
1375 hwif->speedproc = pmac_ide_tune_chipset;
1377 #ifdef CONFIG_BLK_DEV_IDE_PMAC_BLINK
1378 pmu_ide_blink_enabled = pmu_hd_blink_init();
1380 if (pmu_ide_blink_enabled)
1381 hwif->led_act = pmu_hd_kick_blink;
1384 printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n",
1385 hwif->index, model_name[pmif->kind], pmif->aapl_bus_id,
1386 pmif->mediabay ? " (mediabay)" : "", hwif->irq);
1388 #ifdef CONFIG_PMAC_MEDIABAY
1389 if (pmif->mediabay && check_media_bay_by_base(pmif->regbase, MB_CD) == 0)
1391 #endif /* CONFIG_PMAC_MEDIABAY */
1393 hwif->sg_max_nents = MAX_DCMDS;
1395 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1396 /* has a DBDMA controller channel */
1398 pmac_ide_setup_dma(pmif, hwif);
1399 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1401 /* We probe the hwif now */
1402 probe_hwif_init(hwif);
1404 /* The code IDE code will have set hwif->present if we have devices attached,
1405 * if we don't, the discard the interface except if we are on a media bay slot
1407 if (!hwif->present && !pmif->mediabay) {
1408 printk(KERN_INFO "ide%d: Bus empty, interface released.\n",
1410 default_hwif_iops(hwif);
1411 for (i = IDE_DATA_OFFSET; i <= IDE_CONTROL_OFFSET; ++i)
1412 hwif->io_ports[i] = 0;
1413 hwif->chipset = ide_unknown;
1422 * Attach to a macio probed interface
1424 static int __devinit
1425 pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match)
1428 unsigned long regbase;
1431 pmac_ide_hwif_t *pmif;
1435 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1436 || pmac_ide[i].node != NULL))
1438 if (i >= MAX_HWIFS) {
1439 printk(KERN_ERR "ide-pmac: MacIO interface attach with no slot\n");
1440 printk(KERN_ERR " %s\n", mdev->ofdev.node->full_name);
1444 pmif = &pmac_ide[i];
1445 hwif = &ide_hwifs[i];
1447 if (mdev->ofdev.node->n_addrs == 0) {
1448 printk(KERN_WARNING "ide%d: no address for %s\n",
1449 i, mdev->ofdev.node->full_name);
1453 /* Request memory resource for IO ports */
1454 if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
1455 printk(KERN_ERR "ide%d: can't request mmio resource !\n", i);
1459 /* XXX This is bogus. Should be fixed in the registry by checking
1460 * the kind of host interrupt controller, a bit like gatwick
1461 * fixes in irq.c. That works well enough for the single case
1462 * where that happens though...
1464 if (macio_irq_count(mdev) == 0) {
1465 printk(KERN_WARNING "ide%d: no intrs for device %s, using 13\n",
1466 i, mdev->ofdev.node->full_name);
1469 irq = macio_irq(mdev, 0);
1471 base = ioremap(macio_resource_start(mdev, 0), 0x400);
1472 regbase = (unsigned long) base;
1474 hwif->pci_dev = mdev->bus->pdev;
1475 hwif->gendev.parent = &mdev->ofdev.dev;
1478 pmif->node = mdev->ofdev.node;
1479 pmif->regbase = regbase;
1481 pmif->kauai_fcr = NULL;
1482 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1483 if (macio_resource_count(mdev) >= 2) {
1484 if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
1485 printk(KERN_WARNING "ide%d: can't request DMA resource !\n", i);
1487 pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1489 pmif->dma_regs = NULL;
1490 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1491 dev_set_drvdata(&mdev->ofdev.dev, hwif);
1493 rc = pmac_ide_setup_device(pmif, hwif);
1495 /* The inteface is released to the common IDE layer */
1496 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1499 iounmap(pmif->dma_regs);
1500 memset(pmif, 0, sizeof(*pmif));
1501 macio_release_resource(mdev, 0);
1503 macio_release_resource(mdev, 1);
1510 pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t state)
1512 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1515 if (state.event != mdev->ofdev.dev.power.power_state.event && state.event >= PM_EVENT_SUSPEND) {
1516 rc = pmac_ide_do_suspend(hwif);
1518 mdev->ofdev.dev.power.power_state = state;
1525 pmac_ide_macio_resume(struct macio_dev *mdev)
1527 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1530 if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) {
1531 rc = pmac_ide_do_resume(hwif);
1533 mdev->ofdev.dev.power.power_state = PMSG_ON;
1540 * Attach to a PCI probed interface
1542 static int __devinit
1543 pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1546 struct device_node *np;
1547 pmac_ide_hwif_t *pmif;
1549 unsigned long rbase, rlen;
1552 np = pci_device_to_OF_node(pdev);
1554 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1558 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1559 || pmac_ide[i].node != NULL))
1561 if (i >= MAX_HWIFS) {
1562 printk(KERN_ERR "ide-pmac: PCI interface attach with no slot\n");
1563 printk(KERN_ERR " %s\n", np->full_name);
1567 pmif = &pmac_ide[i];
1568 hwif = &ide_hwifs[i];
1570 if (pci_enable_device(pdev)) {
1571 printk(KERN_WARNING "ide%i: Can't enable PCI device for %s\n",
1575 pci_set_master(pdev);
1577 if (pci_request_regions(pdev, "Kauai ATA")) {
1578 printk(KERN_ERR "ide%d: Cannot obtain PCI resources for %s\n",
1583 hwif->pci_dev = pdev;
1584 hwif->gendev.parent = &pdev->dev;
1588 rbase = pci_resource_start(pdev, 0);
1589 rlen = pci_resource_len(pdev, 0);
1591 base = ioremap(rbase, rlen);
1592 pmif->regbase = (unsigned long) base + 0x2000;
1593 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1594 pmif->dma_regs = base + 0x1000;
1595 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1596 pmif->kauai_fcr = base;
1597 pmif->irq = pdev->irq;
1599 pci_set_drvdata(pdev, hwif);
1601 rc = pmac_ide_setup_device(pmif, hwif);
1603 /* The inteface is released to the common IDE layer */
1604 pci_set_drvdata(pdev, NULL);
1606 memset(pmif, 0, sizeof(*pmif));
1607 pci_release_regions(pdev);
1614 pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1616 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1619 if (state.event != pdev->dev.power.power_state.event && state.event >= 2) {
1620 rc = pmac_ide_do_suspend(hwif);
1622 pdev->dev.power.power_state = state;
1629 pmac_ide_pci_resume(struct pci_dev *pdev)
1631 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1634 if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
1635 rc = pmac_ide_do_resume(hwif);
1637 pdev->dev.power.power_state = PMSG_ON;
1643 static struct of_device_id pmac_ide_macio_match[] =
1660 static struct macio_driver pmac_ide_macio_driver =
1663 .match_table = pmac_ide_macio_match,
1664 .probe = pmac_ide_macio_attach,
1665 .suspend = pmac_ide_macio_suspend,
1666 .resume = pmac_ide_macio_resume,
1669 static struct pci_device_id pmac_ide_pci_match[] = {
1670 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1671 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1672 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1673 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_ATA,
1674 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1677 static struct pci_driver pmac_ide_pci_driver = {
1679 .id_table = pmac_ide_pci_match,
1680 .probe = pmac_ide_pci_attach,
1681 .suspend = pmac_ide_pci_suspend,
1682 .resume = pmac_ide_pci_resume,
1684 MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1687 pmac_ide_probe(void)
1689 if (_machine != _MACH_Pmac)
1692 #ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
1693 pci_register_driver(&pmac_ide_pci_driver);
1694 macio_register_driver(&pmac_ide_macio_driver);
1696 macio_register_driver(&pmac_ide_macio_driver);
1697 pci_register_driver(&pmac_ide_pci_driver);
1701 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1704 * pmac_ide_build_dmatable builds the DBDMA command list
1705 * for a transfer and sets the DBDMA channel to point to it.
1708 pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq)
1710 struct dbdma_cmd *table;
1712 ide_hwif_t *hwif = HWIF(drive);
1713 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1714 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1715 struct scatterlist *sg;
1716 int wr = (rq_data_dir(rq) == WRITE);
1718 /* DMA table is already aligned */
1719 table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1721 /* Make sure DMA controller is stopped (necessary ?) */
1722 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1723 while (readl(&dma->status) & RUN)
1726 hwif->sg_nents = i = ide_build_sglist(drive, rq);
1731 /* Build DBDMA commands list */
1732 sg = hwif->sg_table;
1733 while (i && sg_dma_len(sg)) {
1737 cur_addr = sg_dma_address(sg);
1738 cur_len = sg_dma_len(sg);
1740 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1741 if (pmif->broken_dma_warn == 0) {
1742 printk(KERN_WARNING "%s: DMA on non aligned address,"
1743 "switching to PIO on Ohare chipset\n", drive->name);
1744 pmif->broken_dma_warn = 1;
1746 goto use_pio_instead;
1749 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1751 if (count++ >= MAX_DCMDS) {
1752 printk(KERN_WARNING "%s: DMA table too small\n",
1754 goto use_pio_instead;
1756 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE);
1757 st_le16(&table->req_count, tc);
1758 st_le32(&table->phy_addr, cur_addr);
1760 table->xfer_status = 0;
1761 table->res_count = 0;
1770 /* convert the last command to an input/output last command */
1772 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST);
1773 /* add the stop command to the end of the list */
1774 memset(table, 0, sizeof(struct dbdma_cmd));
1775 st_le16(&table->command, DBDMA_STOP);
1777 writel(hwif->dmatable_dma, &dma->cmdptr);
1781 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
1783 pci_unmap_sg(hwif->pci_dev,
1786 hwif->sg_dma_direction);
1787 return 0; /* revert to PIO for this request */
1790 /* Teardown mappings after DMA has completed. */
1792 pmac_ide_destroy_dmatable (ide_drive_t *drive)
1794 ide_hwif_t *hwif = drive->hwif;
1795 struct pci_dev *dev = HWIF(drive)->pci_dev;
1796 struct scatterlist *sg = hwif->sg_table;
1797 int nents = hwif->sg_nents;
1800 pci_unmap_sg(dev, sg, nents, hwif->sg_dma_direction);
1806 * Pick up best MDMA timing for the drive and apply it
1809 pmac_ide_mdma_enable(ide_drive_t *drive, u16 mode)
1811 ide_hwif_t *hwif = HWIF(drive);
1812 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1813 int drive_cycle_time;
1814 struct hd_driveid *id = drive->id;
1815 u32 *timings, *timings2;
1816 u32 timing_local[2];
1819 /* which drive is it ? */
1820 timings = &pmif->timings[drive->select.b.unit & 0x01];
1821 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1823 /* Check if drive provide explicit cycle time */
1824 if ((id->field_valid & 2) && (id->eide_dma_time))
1825 drive_cycle_time = id->eide_dma_time;
1827 drive_cycle_time = 0;
1829 /* Copy timings to local image */
1830 timing_local[0] = *timings;
1831 timing_local[1] = *timings2;
1833 /* Calculate controller timings */
1834 ret = set_timings_mdma( drive, pmif->kind,
1842 /* Set feature on drive */
1843 printk(KERN_INFO "%s: Enabling MultiWord DMA %d\n", drive->name, mode & 0xf);
1844 ret = pmac_ide_do_setfeature(drive, mode);
1846 printk(KERN_WARNING "%s: Failed !\n", drive->name);
1850 /* Apply timings to controller */
1851 *timings = timing_local[0];
1852 *timings2 = timing_local[1];
1854 /* Set speed info in drive */
1855 drive->current_speed = mode;
1856 if (!drive->init_speed)
1857 drive->init_speed = mode;
1863 * Pick up best UDMA timing for the drive and apply it
1866 pmac_ide_udma_enable(ide_drive_t *drive, u16 mode)
1868 ide_hwif_t *hwif = HWIF(drive);
1869 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1870 u32 *timings, *timings2;
1871 u32 timing_local[2];
1874 /* which drive is it ? */
1875 timings = &pmif->timings[drive->select.b.unit & 0x01];
1876 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1878 /* Copy timings to local image */
1879 timing_local[0] = *timings;
1880 timing_local[1] = *timings2;
1882 /* Calculate timings for interface */
1883 if (pmif->kind == controller_un_ata6
1884 || pmif->kind == controller_k2_ata6)
1885 ret = set_timings_udma_ata6( &timing_local[0],
1888 else if (pmif->kind == controller_sh_ata6)
1889 ret = set_timings_udma_shasta( &timing_local[0],
1893 ret = set_timings_udma_ata4(&timing_local[0], mode);
1897 /* Set feature on drive */
1898 printk(KERN_INFO "%s: Enabling Ultra DMA %d\n", drive->name, mode & 0x0f);
1899 ret = pmac_ide_do_setfeature(drive, mode);
1901 printk(KERN_WARNING "%s: Failed !\n", drive->name);
1905 /* Apply timings to controller */
1906 *timings = timing_local[0];
1907 *timings2 = timing_local[1];
1909 /* Set speed info in drive */
1910 drive->current_speed = mode;
1911 if (!drive->init_speed)
1912 drive->init_speed = mode;
1918 * Check what is the best DMA timing setting for the drive and
1919 * call appropriate functions to apply it.
1922 pmac_ide_dma_check(ide_drive_t *drive)
1924 struct hd_driveid *id = drive->id;
1925 ide_hwif_t *hwif = HWIF(drive);
1926 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1929 drive->using_dma = 0;
1931 if (drive->media == ide_floppy)
1933 if (((id->capability & 1) == 0) && !__ide_dma_good_drive(drive))
1935 if (__ide_dma_bad_drive(drive))
1942 if (pmif->kind == controller_kl_ata4
1943 || pmif->kind == controller_un_ata6
1944 || pmif->kind == controller_k2_ata6
1945 || pmif->kind == controller_sh_ata6) {
1947 if (pmif->cable_80) {
1948 map |= XFER_UDMA_66;
1949 if (pmif->kind == controller_un_ata6 ||
1950 pmif->kind == controller_k2_ata6 ||
1951 pmif->kind == controller_sh_ata6)
1952 map |= XFER_UDMA_100;
1953 if (pmif->kind == controller_sh_ata6)
1954 map |= XFER_UDMA_133;
1957 mode = ide_find_best_mode(drive, map);
1958 if (mode & XFER_UDMA)
1959 drive->using_dma = pmac_ide_udma_enable(drive, mode);
1960 else if (mode & XFER_MWDMA)
1961 drive->using_dma = pmac_ide_mdma_enable(drive, mode);
1962 hwif->OUTB(0, IDE_CONTROL_REG);
1963 /* Apply settings to controller */
1964 pmac_ide_do_update_timings(drive);
1970 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1971 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1974 pmac_ide_dma_setup(ide_drive_t *drive)
1976 ide_hwif_t *hwif = HWIF(drive);
1977 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1978 struct request *rq = HWGROUP(drive)->rq;
1979 u8 unit = (drive->select.b.unit & 0x01);
1984 ata4 = (pmif->kind == controller_kl_ata4);
1986 if (!pmac_ide_build_dmatable(drive, rq)) {
1987 ide_map_sg(drive, rq);
1991 /* Apple adds 60ns to wrDataSetup on reads */
1992 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1993 writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0),
1994 PMAC_IDE_REG(IDE_TIMING_CONFIG));
1995 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1998 drive->waiting_for_dma = 1;
2004 pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
2006 /* issue cmd to drive */
2007 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, NULL);
2011 * Kick the DMA controller into life after the DMA command has been issued
2015 pmac_ide_dma_start(ide_drive_t *drive)
2017 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
2018 volatile struct dbdma_regs __iomem *dma;
2020 dma = pmif->dma_regs;
2022 writel((RUN << 16) | RUN, &dma->control);
2023 /* Make sure it gets to the controller right now */
2024 (void)readl(&dma->control);
2028 * After a DMA transfer, make sure the controller is stopped
2031 pmac_ide_dma_end (ide_drive_t *drive)
2033 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
2034 volatile struct dbdma_regs __iomem *dma;
2039 dma = pmif->dma_regs;
2041 drive->waiting_for_dma = 0;
2042 dstat = readl(&dma->status);
2043 writel(((RUN|WAKE|DEAD) << 16), &dma->control);
2044 pmac_ide_destroy_dmatable(drive);
2045 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
2046 * in theory, but with ATAPI decices doing buffer underruns, that would
2047 * cause us to disable DMA, which isn't what we want
2049 return (dstat & (RUN|DEAD)) != RUN;
2053 * Check out that the interrupt we got was for us. We can't always know this
2054 * for sure with those Apple interfaces (well, we could on the recent ones but
2055 * that's not implemented yet), on the other hand, we don't have shared interrupts
2056 * so it's not really a problem
2059 pmac_ide_dma_test_irq (ide_drive_t *drive)
2061 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
2062 volatile struct dbdma_regs __iomem *dma;
2063 unsigned long status, timeout;
2067 dma = pmif->dma_regs;
2069 /* We have to things to deal with here:
2071 * - The dbdma won't stop if the command was started
2072 * but completed with an error without transferring all
2073 * datas. This happens when bad blocks are met during
2074 * a multi-block transfer.
2076 * - The dbdma fifo hasn't yet finished flushing to
2077 * to system memory when the disk interrupt occurs.
2081 /* If ACTIVE is cleared, the STOP command have passed and
2082 * transfer is complete.
2084 status = readl(&dma->status);
2085 if (!(status & ACTIVE))
2087 if (!drive->waiting_for_dma)
2088 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
2089 called while not waiting\n", HWIF(drive)->index);
2091 /* If dbdma didn't execute the STOP command yet, the
2092 * active bit is still set. We consider that we aren't
2093 * sharing interrupts (which is hopefully the case with
2094 * those controllers) and so we just try to flush the
2095 * channel for pending data in the fifo
2098 writel((FLUSH << 16) | FLUSH, &dma->control);
2102 status = readl(&dma->status);
2103 if ((status & FLUSH) == 0)
2105 if (++timeout > 100) {
2106 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
2107 timeout flushing channel\n", HWIF(drive)->index);
2115 pmac_ide_dma_host_off (ide_drive_t *drive)
2121 pmac_ide_dma_host_on (ide_drive_t *drive)
2127 pmac_ide_dma_lostirq (ide_drive_t *drive)
2129 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
2130 volatile struct dbdma_regs __iomem *dma;
2131 unsigned long status;
2135 dma = pmif->dma_regs;
2137 status = readl(&dma->status);
2138 printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
2143 * Allocate the data structures needed for using DMA with an interface
2144 * and fill the proper list of functions pointers
2147 pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
2149 /* We won't need pci_dev if we switch to generic consistent
2152 if (hwif->pci_dev == NULL)
2155 * Allocate space for the DBDMA commands.
2156 * The +2 is +1 for the stop command and +1 to allow for
2157 * aligning the start address to a multiple of 16 bytes.
2159 pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent(
2161 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
2162 &hwif->dmatable_dma);
2163 if (pmif->dma_table_cpu == NULL) {
2164 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
2169 hwif->ide_dma_off_quietly = &__ide_dma_off_quietly;
2170 hwif->ide_dma_on = &__ide_dma_on;
2171 hwif->ide_dma_check = &pmac_ide_dma_check;
2172 hwif->dma_setup = &pmac_ide_dma_setup;
2173 hwif->dma_exec_cmd = &pmac_ide_dma_exec_cmd;
2174 hwif->dma_start = &pmac_ide_dma_start;
2175 hwif->ide_dma_end = &pmac_ide_dma_end;
2176 hwif->ide_dma_test_irq = &pmac_ide_dma_test_irq;
2177 hwif->ide_dma_host_off = &pmac_ide_dma_host_off;
2178 hwif->ide_dma_host_on = &pmac_ide_dma_host_on;
2179 hwif->ide_dma_timeout = &__ide_dma_timeout;
2180 hwif->ide_dma_lostirq = &pmac_ide_dma_lostirq;
2182 hwif->atapi_dma = 1;
2183 switch(pmif->kind) {
2184 case controller_sh_ata6:
2185 hwif->ultra_mask = pmif->cable_80 ? 0x7f : 0x07;
2186 hwif->mwdma_mask = 0x07;
2187 hwif->swdma_mask = 0x00;
2189 case controller_un_ata6:
2190 case controller_k2_ata6:
2191 hwif->ultra_mask = pmif->cable_80 ? 0x3f : 0x07;
2192 hwif->mwdma_mask = 0x07;
2193 hwif->swdma_mask = 0x00;
2195 case controller_kl_ata4:
2196 hwif->ultra_mask = pmif->cable_80 ? 0x1f : 0x07;
2197 hwif->mwdma_mask = 0x07;
2198 hwif->swdma_mask = 0x00;
2201 hwif->ultra_mask = 0x00;
2202 hwif->mwdma_mask = 0x07;
2203 hwif->swdma_mask = 0x00;
2208 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */