2 * Copyright (C) 2000, 2001 Wolfgang Denk, wd@denx.de
3 * Modified for direct IDE interface
4 * by Thomas Lange, thomas@corelatus.com
5 * Modified for direct IDE interface on 8xx without using the PCMCIA
7 * by Steven.Scholz@imc-berlin.de
8 * Moved out of arch/ppc/kernel/m8xx_setup.c, other minor cleanups
9 * by Mathew Locke <mattl@mvista.com>
12 #include <linux/errno.h>
13 #include <linux/kernel.h>
15 #include <linux/stddef.h>
16 #include <linux/unistd.h>
17 #include <linux/ptrace.h>
18 #include <linux/slab.h>
19 #include <linux/user.h>
20 #include <linux/tty.h>
21 #include <linux/major.h>
22 #include <linux/interrupt.h>
23 #include <linux/reboot.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/ide.h>
27 #include <linux/bootmem.h>
29 #include <asm/mpc8xx.h>
31 #include <asm/processor.h>
33 #include <asm/pgtable.h>
35 #include <asm/8xx_immap.h>
36 #include <asm/machdep.h>
39 static int identify (volatile u8 *p);
40 static void print_fixed (volatile u8 *p);
41 static void print_funcid (int func);
42 static int check_ide_device (unsigned long base);
44 static void ide_interrupt_ack (void *dev);
45 static void m8xx_ide_set_pio_mode(ide_drive_t *drive, const u8 pio);
47 typedef struct ide_ioport_desc {
48 unsigned long base_off; /* Offset to PCMCIA memory */
49 unsigned long reg_off[IDE_NR_PORTS]; /* controller register offsets */
53 ide_ioport_desc_t ioport_dsc[MAX_HWIFS] = {
54 #ifdef IDE0_BASE_OFFSET
58 IDE0_ERROR_REG_OFFSET,
59 IDE0_NSECTOR_REG_OFFSET,
60 IDE0_SECTOR_REG_OFFSET,
63 IDE0_SELECT_REG_OFFSET,
64 IDE0_STATUS_REG_OFFSET,
65 IDE0_CONTROL_REG_OFFSET,
70 #ifdef IDE1_BASE_OFFSET
74 IDE1_ERROR_REG_OFFSET,
75 IDE1_NSECTOR_REG_OFFSET,
76 IDE1_SECTOR_REG_OFFSET,
79 IDE1_SELECT_REG_OFFSET,
80 IDE1_STATUS_REG_OFFSET,
81 IDE1_CONTROL_REG_OFFSET,
86 #endif /* IDE1_BASE_OFFSET */
87 #endif /* IDE0_BASE_OFFSET */
90 ide_pio_timings_t ide_pio_clocks[6];
91 int hold_time[6] = {30, 20, 15, 10, 10, 10 }; /* PIO Mode 5 with IORDY (nonstandard) */
94 * Warning: only 1 (ONE) PCMCIA slot supported here,
95 * which must be correctly initialized by the firmware (PPCBoot).
97 static int _slot_ = -1; /* will be read from PCMCIA registers */
99 /* Make clock cycles and always round up */
100 #define PCMCIA_MK_CLKS( t, T ) (( (t) * ((T)/1000000) + 999U ) / 1000U )
102 #define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4))
103 #define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4))
106 * The TQM850L hardware has two pins swapped! Grrrrgh!
108 #ifdef CONFIG_TQM850L
109 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXOE
110 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXRESET
112 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXRESET
113 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXOE
116 #if defined(CONFIG_BLK_DEV_MPC8xx_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
117 #define PCMCIA_SCHLVL IDE0_INTERRUPT /* Status Change Interrupt Level */
118 static int pcmcia_schlvl = PCMCIA_SCHLVL;
122 * See include/linux/ide.h for definition of hw_regs_t (p, base)
126 * m8xx_ide_init_ports() for a direct IDE interface _using_
127 * MPC8xx's internal PCMCIA interface
129 #if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT)
130 static int __init m8xx_ide_init_ports(hw_regs_t *hw, unsigned long data_port)
132 unsigned long *p = hw->io_ports;
139 volatile pcmcia_win_t *win;
140 volatile pcmconf8xx_t *pcmp;
145 static unsigned long pcmcia_base = 0;
150 pcmp = (pcmconf8xx_t *)(&(((immap_t *)IMAP_ADDR)->im_pcmcia));
154 * Read out PCMCIA registers. Since the reset values
155 * are undefined, we sure hope that they have been
159 /* Scan all registers for valid settings */
160 pcmcia_phy_base = 0xFFFFFFFF;
162 /* br0 is start of brX and orX regs */
163 win = (pcmcia_win_t *) \
164 (&(((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0));
165 for (i = 0; i < 8; i++) {
166 if (win->or & 1) { /* This bank is marked as valid */
167 if (win->br < pcmcia_phy_base) {
168 pcmcia_phy_base = win->br;
170 if ((win->br + PCMCIA_MEM_SIZE) > pcmcia_phy_end) {
171 pcmcia_phy_end = win->br + PCMCIA_MEM_SIZE;
173 /* Check which slot that has been defined */
174 _slot_ = (win->or >> 2) & 1;
180 printk ("PCMCIA slot %c: phys mem %08x...%08x (size %08x)\n",
182 pcmcia_phy_base, pcmcia_phy_end,
183 pcmcia_phy_end - pcmcia_phy_base);
185 pcmcia_base=(unsigned long)ioremap(pcmcia_phy_base,
186 pcmcia_phy_end-pcmcia_phy_base);
189 printk ("PCMCIA virt base: %08lx\n", pcmcia_base);
191 /* Compute clock cycles for PIO timings */
192 for (i=0; i<6; ++i) {
193 bd_t *binfo = (bd_t *)__res;
196 PCMCIA_MK_CLKS (hold_time[i],
198 ide_pio_clocks[i].setup_time =
199 PCMCIA_MK_CLKS (ide_pio_timings[i].setup_time,
201 ide_pio_clocks[i].active_time =
202 PCMCIA_MK_CLKS (ide_pio_timings[i].active_time,
204 ide_pio_clocks[i].cycle_time =
205 PCMCIA_MK_CLKS (ide_pio_timings[i].cycle_time,
208 printk ("PIO mode %d timings: %d/%d/%d => %d/%d/%d\n",
210 ide_pio_clocks[i].setup_time,
211 ide_pio_clocks[i].active_time,
212 ide_pio_clocks[i].hold_time,
213 ide_pio_clocks[i].cycle_time,
214 ide_pio_timings[i].setup_time,
215 ide_pio_timings[i].active_time,
216 ide_pio_timings[i].hold_time,
217 ide_pio_timings[i].cycle_time);
223 printk ("PCMCIA slot has not been defined! Using A as default\n");
227 #ifdef CONFIG_IDE_8xx_PCCARD
230 printk ("PIPR = 0x%08X slot %c ==> mask = 0x%X\n",
233 M8XX_PCMCIA_CD1(_slot_) | M8XX_PCMCIA_CD2(_slot_) );
236 if (pcmp->pcmc_pipr & (M8XX_PCMCIA_CD1(_slot_)|M8XX_PCMCIA_CD2(_slot_))) {
237 printk ("No card in slot %c: PIPR=%08x\n",
238 'A' + _slot_, (u32) pcmp->pcmc_pipr);
239 return -ENODEV; /* No card in slot */
242 check_ide_device (pcmcia_base);
244 #endif /* CONFIG_IDE_8xx_PCCARD */
246 base = pcmcia_base + ioport_dsc[data_port].base_off;
248 printk ("base: %08x + %08x = %08x\n",
249 pcmcia_base, ioport_dsc[data_port].base_off, base);
252 for (i = 0; i < IDE_NR_PORTS; ++i) {
254 printk ("port[%d]: %08x + %08x = %08x\n",
257 ioport_dsc[data_port].reg_off[i],
258 i, base + ioport_dsc[data_port].reg_off[i]);
260 *p++ = base + ioport_dsc[data_port].reg_off[i];
263 hw->irq = ioport_dsc[data_port].irq;
264 hw->ack_intr = (ide_ack_intr_t *)ide_interrupt_ack;
266 #ifdef CONFIG_IDE_8xx_PCCARD
271 pgcrx = &((immap_t *) IMAP_ADDR)->im_pcmcia.pcmc_pgcrb;
273 pgcrx = &((immap_t *) IMAP_ADDR)->im_pcmcia.pcmc_pgcra;
276 reg |= mk_int_int_mask (pcmcia_schlvl) << 24;
277 reg |= mk_int_int_mask (pcmcia_schlvl) << 16;
280 #endif /* CONFIG_IDE_8xx_PCCARD */
282 /* Enable Harddisk Interrupt,
283 * and make it edge sensitive
285 /* (11-18) Set edge detect for irq, no wakeup from low power mode */
286 ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel |=
287 (0x80000000 >> ioport_dsc[data_port].irq);
289 #ifdef CONFIG_IDE_8xx_PCCARD
290 /* Make sure we don't get garbage irq */
291 ((immap_t *) IMAP_ADDR)->im_pcmcia.pcmc_pscr = 0xFFFF;
293 /* Enable falling edge irq */
294 pcmp->pcmc_per = 0x100000 >> (16 * _slot_);
295 #endif /* CONFIG_IDE_8xx_PCCARD */
299 #endif /* CONFIG_IDE_8xx_PCCARD || CONFIG_IDE_8xx_DIRECT */
302 * m8xx_ide_init_ports() for a direct IDE interface _not_ using
303 * MPC8xx's internal PCMCIA interface
305 #if defined(CONFIG_IDE_EXT_DIRECT)
306 static int __init m8xx_ide_init_ports(hw_regs_t *hw, unsigned long data_port)
308 unsigned long *p = hw->io_ports;
313 static unsigned long ide_base = 0;
321 * - add code to read ORx, BRx
323 ide_phy_base = CFG_ATA_BASE_ADDR;
324 ide_phy_end = CFG_ATA_BASE_ADDR + 0x200;
326 printk ("IDE phys mem : %08x...%08x (size %08x)\n",
327 ide_phy_base, ide_phy_end,
328 ide_phy_end - ide_phy_base);
330 ide_base=(unsigned long)ioremap(ide_phy_base,
331 ide_phy_end-ide_phy_base);
334 printk ("IDE virt base: %08lx\n", ide_base);
338 base = ide_base + ioport_dsc[data_port].base_off;
340 printk ("base: %08x + %08x = %08x\n",
341 ide_base, ioport_dsc[data_port].base_off, base);
344 for (i = 0; i < IDE_NR_PORTS; ++i) {
346 printk ("port[%d]: %08x + %08x = %08x\n",
349 ioport_dsc[data_port].reg_off[i],
350 i, base + ioport_dsc[data_port].reg_off[i]);
352 *p++ = base + ioport_dsc[data_port].reg_off[i];
355 /* direct connected IDE drive, i.e. external IRQ */
356 hw->irq = ioport_dsc[data_port].irq;
357 hw->ack_intr = (ide_ack_intr_t *)ide_interrupt_ack;
359 /* Enable Harddisk Interrupt,
360 * and make it edge sensitive
362 /* (11-18) Set edge detect for irq, no wakeup from low power mode */
363 ((immap_t *) IMAP_ADDR)->im_siu_conf.sc_siel |=
364 (0x80000000 >> ioport_dsc[data_port].irq);
368 #endif /* CONFIG_IDE_8xx_DIRECT */
371 /* -------------------------------------------------------------------- */
376 #define PCMCIA_SHT(t) ((t & 0x0F)<<16) /* Strobe Hold Time */
377 #define PCMCIA_SST(t) ((t & 0x0F)<<12) /* Strobe Setup Time */
378 #define PCMCIA_SL(t) ((t==32) ? 0 : ((t & 0x1F)<<7)) /* Strobe Length */
381 /* Calculate PIO timings */
382 static void m8xx_ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
384 #if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT)
385 volatile pcmconf8xx_t *pcmp;
386 ulong timing, mask, reg;
388 pcmp = (pcmconf8xx_t *)(&(((immap_t *)IMAP_ADDR)->im_pcmcia));
390 mask = ~(PCMCIA_SHT(0xFF) | PCMCIA_SST(0xFF) | PCMCIA_SL(0xFF));
392 timing = PCMCIA_SHT(hold_time[pio] )
393 | PCMCIA_SST(ide_pio_clocks[pio].setup_time )
394 | PCMCIA_SL (ide_pio_clocks[pio].active_time)
398 printk ("Setting timing bits 0x%08lx in PCMCIA controller\n", timing);
400 if ((reg = pcmp->pcmc_por0 & mask) != 0)
401 pcmp->pcmc_por0 = reg | timing;
403 if ((reg = pcmp->pcmc_por1 & mask) != 0)
404 pcmp->pcmc_por1 = reg | timing;
406 if ((reg = pcmp->pcmc_por2 & mask) != 0)
407 pcmp->pcmc_por2 = reg | timing;
409 if ((reg = pcmp->pcmc_por3 & mask) != 0)
410 pcmp->pcmc_por3 = reg | timing;
412 if ((reg = pcmp->pcmc_por4 & mask) != 0)
413 pcmp->pcmc_por4 = reg | timing;
415 if ((reg = pcmp->pcmc_por5 & mask) != 0)
416 pcmp->pcmc_por5 = reg | timing;
418 if ((reg = pcmp->pcmc_por6 & mask) != 0)
419 pcmp->pcmc_por6 = reg | timing;
421 if ((reg = pcmp->pcmc_por7 & mask) != 0)
422 pcmp->pcmc_por7 = reg | timing;
424 #elif defined(CONFIG_IDE_EXT_DIRECT)
426 printk("%s[%d] %s: not implemented yet!\n",
427 __FILE__,__LINE__,__FUNCTION__);
428 #endif /* defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_PCMCIA */
432 ide_interrupt_ack (void *dev)
434 #ifdef CONFIG_IDE_8xx_PCCARD
437 #if (PCMCIA_SOCKETS_NO == 2)
441 /* get interrupt sources */
443 pscr = ((volatile immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr;
444 pipr = ((volatile immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr;
447 * report only if both card detect signals are the same
449 * we depend on that CD2 is the bit to the left of CD1...
453 printk("PCMCIA slot has not been defined! Using A as default\n");
457 if(((pipr & M8XX_PCMCIA_CD2(_slot_)) >> 1) ^
458 (pipr & M8XX_PCMCIA_CD1(_slot_)) ) {
459 printk ("card detect interrupt\n");
461 /* clear the interrupt sources */
462 ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr = pscr;
464 #else /* ! CONFIG_IDE_8xx_PCCARD */
466 * Only CONFIG_IDE_8xx_PCCARD is using the interrupt of the
467 * MPC8xx's PCMCIA controller, so there is nothing to be done here
468 * for CONFIG_IDE_8xx_DIRECT and CONFIG_IDE_EXT_DIRECT.
469 * The interrupt is handled somewhere else. -- Steven
471 #endif /* CONFIG_IDE_8xx_PCCARD */
479 #define CISTPL_NULL 0x00
480 #define CISTPL_DEVICE 0x01
481 #define CISTPL_LONGLINK_CB 0x02
482 #define CISTPL_INDIRECT 0x03
483 #define CISTPL_CONFIG_CB 0x04
484 #define CISTPL_CFTABLE_ENTRY_CB 0x05
485 #define CISTPL_LONGLINK_MFC 0x06
486 #define CISTPL_BAR 0x07
487 #define CISTPL_PWR_MGMNT 0x08
488 #define CISTPL_EXTDEVICE 0x09
489 #define CISTPL_CHECKSUM 0x10
490 #define CISTPL_LONGLINK_A 0x11
491 #define CISTPL_LONGLINK_C 0x12
492 #define CISTPL_LINKTARGET 0x13
493 #define CISTPL_NO_LINK 0x14
494 #define CISTPL_VERS_1 0x15
495 #define CISTPL_ALTSTR 0x16
496 #define CISTPL_DEVICE_A 0x17
497 #define CISTPL_JEDEC_C 0x18
498 #define CISTPL_JEDEC_A 0x19
499 #define CISTPL_CONFIG 0x1a
500 #define CISTPL_CFTABLE_ENTRY 0x1b
501 #define CISTPL_DEVICE_OC 0x1c
502 #define CISTPL_DEVICE_OA 0x1d
503 #define CISTPL_DEVICE_GEO 0x1e
504 #define CISTPL_DEVICE_GEO_A 0x1f
505 #define CISTPL_MANFID 0x20
506 #define CISTPL_FUNCID 0x21
507 #define CISTPL_FUNCE 0x22
508 #define CISTPL_SWIL 0x23
509 #define CISTPL_END 0xff
512 * CIS Function ID codes
514 #define CISTPL_FUNCID_MULTI 0x00
515 #define CISTPL_FUNCID_MEMORY 0x01
516 #define CISTPL_FUNCID_SERIAL 0x02
517 #define CISTPL_FUNCID_PARALLEL 0x03
518 #define CISTPL_FUNCID_FIXED 0x04
519 #define CISTPL_FUNCID_VIDEO 0x05
520 #define CISTPL_FUNCID_NETWORK 0x06
521 #define CISTPL_FUNCID_AIMS 0x07
522 #define CISTPL_FUNCID_SCSI 0x08
525 * Fixed Disk FUNCE codes
527 #define CISTPL_IDE_INTERFACE 0x01
529 #define CISTPL_FUNCE_IDE_IFACE 0x01
530 #define CISTPL_FUNCE_IDE_MASTER 0x02
531 #define CISTPL_FUNCE_IDE_SLAVE 0x03
533 /* First feature byte */
534 #define CISTPL_IDE_SILICON 0x04
535 #define CISTPL_IDE_UNIQUE 0x08
536 #define CISTPL_IDE_DUAL 0x10
538 /* Second feature byte */
539 #define CISTPL_IDE_HAS_SLEEP 0x01
540 #define CISTPL_IDE_HAS_STANDBY 0x02
541 #define CISTPL_IDE_HAS_IDLE 0x04
542 #define CISTPL_IDE_LOW_POWER 0x08
543 #define CISTPL_IDE_REG_INHIBIT 0x10
544 #define CISTPL_IDE_HAS_INDEX 0x20
545 #define CISTPL_IDE_IOIS16 0x40
548 /* -------------------------------------------------------------------- */
551 #define MAX_TUPEL_SZ 512
552 #define MAX_FEATURES 4
554 static int check_ide_device (unsigned long base)
556 volatile u8 *ident = NULL;
557 volatile u8 *feature_p[MAX_FEATURES];
558 volatile u8 *p, *start;
562 unsigned short config_base = 0;
567 printk ("PCMCIA MEM: %08lX\n", base);
569 start = p = (volatile u8 *) base;
571 while ((p - start) < MAX_TUPEL_SZ) {
575 if (code == 0xFF) { /* End of chain */
581 { volatile u8 *q = p;
582 printk ("\nTuple code %02x length %d\n\tData:",
585 for (i = 0; i < len; ++i) {
586 printk (" %02x", *q);
590 #endif /* DEBUG_PCMCIA */
599 if (n_features < MAX_FEATURES)
600 feature_p[n_features++] = p;
603 config_base = (*(p+6) << 8) + (*(p+4));
610 found = identify (ident);
612 if (func_id != ((u8)~0)) {
613 print_funcid (func_id);
615 if (func_id == CISTPL_FUNCID_FIXED)
618 return (1); /* no disk drive */
621 for (i=0; i<n_features; ++i) {
622 print_fixed (feature_p[i]);
626 printk ("unknown card type\n");
630 /* set level mode irq and I/O mapped device in config reg*/
631 *((u8 *)(base + config_base)) = 0x41;
636 /* ------------------------------------------------------------------------- */
638 static void print_funcid (int func)
641 case CISTPL_FUNCID_MULTI:
642 printk (" Multi-Function");
644 case CISTPL_FUNCID_MEMORY:
647 case CISTPL_FUNCID_SERIAL:
648 printk (" Serial Port");
650 case CISTPL_FUNCID_PARALLEL:
651 printk (" Parallel Port");
653 case CISTPL_FUNCID_FIXED:
654 printk (" Fixed Disk");
656 case CISTPL_FUNCID_VIDEO:
657 printk (" Video Adapter");
659 case CISTPL_FUNCID_NETWORK:
660 printk (" Network Adapter");
662 case CISTPL_FUNCID_AIMS:
663 printk (" AIMS Card");
665 case CISTPL_FUNCID_SCSI:
666 printk (" SCSI Adapter");
675 /* ------------------------------------------------------------------------- */
677 static void print_fixed (volatile u8 *p)
683 case CISTPL_FUNCE_IDE_IFACE:
686 printk ((iface == CISTPL_IDE_INTERFACE) ? " IDE" : " unknown");
687 printk (" interface ");
690 case CISTPL_FUNCE_IDE_MASTER:
691 case CISTPL_FUNCE_IDE_SLAVE:
695 printk ((f1 & CISTPL_IDE_SILICON) ? " [silicon]" : " [rotating]");
697 if (f1 & CISTPL_IDE_UNIQUE)
698 printk (" [unique]");
700 printk ((f1 & CISTPL_IDE_DUAL) ? " [dual]" : " [single]");
702 if (f2 & CISTPL_IDE_HAS_SLEEP)
705 if (f2 & CISTPL_IDE_HAS_STANDBY)
706 printk (" [standby]");
708 if (f2 & CISTPL_IDE_HAS_IDLE)
711 if (f2 & CISTPL_IDE_LOW_POWER)
712 printk (" [low power]");
714 if (f2 & CISTPL_IDE_REG_INHIBIT)
715 printk (" [reg inhibit]");
717 if (f2 & CISTPL_IDE_HAS_INDEX)
720 if (f2 & CISTPL_IDE_IOIS16)
721 printk (" [IOis16]");
729 /* ------------------------------------------------------------------------- */
732 #define MAX_IDENT_CHARS 64
733 #define MAX_IDENT_FIELDS 4
735 static u8 *known_cards[] = {
740 static int identify (volatile u8 *p)
742 u8 id_str[MAX_IDENT_CHARS];
749 return (0); /* Don't know */
754 for (i=0; i<=4 && !done; ++i, p+=2) {
755 while ((data = *p) != '\0') {
761 if (t == &id_str[MAX_IDENT_CHARS-1]) {
771 while (--t > id_str) {
777 printk ("Card ID: %s\n", id_str);
779 for (card=known_cards; *card; ++card) {
780 if (strcmp(*card, id_str) == 0) { /* found! */
785 return (0); /* don't know */
788 static int __init mpc8xx_ide_probe(void)
791 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
793 #ifdef IDE0_BASE_OFFSET
794 memset(&hw, 0, sizeof(hw));
795 if (!m8xx_ide_init_ports(&hw, 0)) {
796 ide_hwif_t *hwif = &ide_hwifs[0];
798 ide_init_port_hw(hwif, &hw);
799 hwif->pio_mask = ATA_PIO4;
800 hwif->set_pio_mode = m8xx_ide_set_pio_mode;
804 #ifdef IDE1_BASE_OFFSET
805 memset(&hw, 0, sizeof(hw));
806 if (!m8xx_ide_init_ports(&hw, 1)) {
807 ide_hwif_t *mate = &ide_hwifs[1];
809 ide_init_port_hw(mate, &hw);
810 mate->pio_mask = ATA_PIO4;
811 mate->set_pio_mode = m8xx_ide_set_pio_mode;
818 ide_device_add(idx, NULL);
823 module_init(mpc8xx_ide_probe);
825 MODULE_LICENSE("GPL");