2 * linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003
4 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2003 Red Hat <alan@redhat.com>
7 * May be copied or modified under the terms of the GNU General Public License
9 * Documentation for CMD680:
10 * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
12 * Documentation for SiI 3112:
13 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
15 * Errata and other documentation only available under NDA.
19 * If you are using Marvell SATA-IDE adapters with Maxtor drives
20 * ensure the system is set up for ATA100/UDMA5 not UDMA6.
22 * If you are using WD drives with SATA bridges you must set the
23 * drive to "Single". "Master" will hang
25 * If you have strange problems with nVidia chipset systems please
26 * see the SI support documentation and update your system BIOS
30 #include <linux/config.h>
31 #include <linux/types.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/delay.h>
35 #include <linux/hdreg.h>
36 #include <linux/ide.h>
37 #include <linux/init.h>
42 * pdev_is_sata - check if device is SATA
43 * @pdev: PCI device to check
45 * Returns true if this is a SATA controller
48 static int pdev_is_sata(struct pci_dev *pdev)
52 case PCI_DEVICE_ID_SII_3112:
53 case PCI_DEVICE_ID_SII_1210SA:
55 case PCI_DEVICE_ID_SII_680:
63 * is_sata - check if hwif is SATA
64 * @hwif: interface to check
66 * Returns true if this is a SATA controller
69 static inline int is_sata(ide_hwif_t *hwif)
71 return pdev_is_sata(hwif->pci_dev);
75 * siimage_selreg - return register base
79 * Turn a config register offset into the right address in either
80 * PCI space or MMIO space to access the control register in question
81 * Thankfully this is a configuration operation so isnt performance
85 static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
87 unsigned long base = (unsigned long)hwif->hwif_data;
90 base += (hwif->channel << 6);
92 base += (hwif->channel << 4);
97 * siimage_seldev - return register base
101 * Turn a config register offset into the right address in either
102 * PCI space or MMIO space to access the control register in question
103 * including accounting for the unit shift.
106 static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
108 ide_hwif_t *hwif = HWIF(drive);
109 unsigned long base = (unsigned long)hwif->hwif_data;
112 base += (hwif->channel << 6);
114 base += (hwif->channel << 4);
115 base |= drive->select.b.unit << drive->select.b.unit;
120 * siimage_ratemask - Compute available modes
123 * Compute the available speeds for the devices on the interface.
124 * For the CMD680 this depends on the clocking mode (scsc), for the
125 * SI3312 SATA controller life is a bit simpler. Enforce UDMA33
126 * as a limit if there is no 80pin cable present.
129 static byte siimage_ratemask (ide_drive_t *drive)
131 ide_hwif_t *hwif = HWIF(drive);
132 u8 mode = 0, scsc = 0;
133 unsigned long base = (unsigned long) hwif->hwif_data;
136 scsc = hwif->INB(base + 0x4A);
138 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
142 if(strstr(drive->id->model, "Maxtor"))
147 if ((scsc & 0x30) == 0x10) /* 133 */
149 else if ((scsc & 0x30) == 0x20) /* 2xPCI */
151 else if ((scsc & 0x30) == 0x00) /* 100 */
153 else /* Disabled ? */
156 if (!eighty_ninty_three(drive))
157 mode = min(mode, (u8)1);
162 * siimage_taskfile_timing - turn timing data to a mode
163 * @hwif: interface to query
165 * Read the timing data for the interface and return the
166 * mode that is being used.
169 static byte siimage_taskfile_timing (ide_hwif_t *hwif)
172 unsigned long addr = siimage_selreg(hwif, 2);
175 timing = hwif->INW(addr);
177 pci_read_config_word(hwif->pci_dev, addr, &timing);
180 case 0x10c1: return 4;
181 case 0x10c3: return 3;
183 case 0x1281: return 2;
184 case 0x2283: return 1;
191 * simmage_tuneproc - tune a drive
192 * @drive: drive to tune
193 * @mode_wanted: the target operating mode
195 * Load the timing settings for this device mode into the
196 * controller. If we are in PIO mode 3 or 4 turn on IORDY
197 * monitoring (bit 9). The TF timing is bits 31:16
200 static void siimage_tuneproc (ide_drive_t *drive, byte mode_wanted)
202 ide_hwif_t *hwif = HWIF(drive);
205 unsigned long addr = siimage_seldev(drive, 0x04);
206 unsigned long tfaddr = siimage_selreg(hwif, 0x02);
208 /* cheat for now and use the docs */
209 switch(mode_wanted) {
234 hwif->OUTW(speedt, addr);
235 hwif->OUTW(speedp, tfaddr);
236 /* Now set up IORDY */
237 if(mode_wanted == 3 || mode_wanted == 4)
238 hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2);
240 hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2);
244 pci_write_config_word(hwif->pci_dev, addr, speedp);
245 pci_write_config_word(hwif->pci_dev, tfaddr, speedt);
246 pci_read_config_word(hwif->pci_dev, tfaddr-2, &speedp);
248 /* Set IORDY for mode 3 or 4 */
249 if(mode_wanted == 3 || mode_wanted == 4)
251 pci_write_config_word(hwif->pci_dev, tfaddr-2, speedp);
256 * config_siimage_chipset_for_pio - set drive timings
257 * @drive: drive to tune
260 * Compute the best pio mode we can for a given device. Also honour
261 * the timings for the driver when dealing with mixed devices. Some
262 * of this is ugly but its all wrapped up here
264 * The SI680 can also do VDMA - we need to start using that
266 * FIXME: we use the BIOS channel timings to avoid driving the task
267 * files too fast at the disk. We need to compute the master/slave
268 * drive PIO mode properly so that we can up the speed on a hotplug
272 static void config_siimage_chipset_for_pio (ide_drive_t *drive, byte set_speed)
274 u8 channel_timings = siimage_taskfile_timing(HWIF(drive));
275 u8 speed = 0, set_pio = ide_get_best_pio_mode(drive, 4, 5, NULL);
277 /* WARNING PIO timing mess is going to happen b/w devices, argh */
278 if ((channel_timings != set_pio) && (set_pio > channel_timings))
279 set_pio = channel_timings;
281 siimage_tuneproc(drive, set_pio);
282 speed = XFER_PIO_0 + set_pio;
284 (void) ide_config_drive_speed(drive, speed);
287 static void config_chipset_for_pio (ide_drive_t *drive, byte set_speed)
289 config_siimage_chipset_for_pio(drive, set_speed);
293 * siimage_tune_chipset - set controller timings
294 * @drive: Drive to set up
295 * @xferspeed: speed we want to achieve
297 * Tune the SII chipset for the desired mode. If we can't achieve
298 * the desired mode then tune for a lower one, but ultimately
299 * make the thing work.
302 static int siimage_tune_chipset (ide_drive_t *drive, byte xferspeed)
304 u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
305 u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
306 u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
308 ide_hwif_t *hwif = HWIF(drive);
309 u16 ultra = 0, multi = 0;
310 u8 mode = 0, unit = drive->select.b.unit;
311 u8 speed = ide_rate_filter(siimage_ratemask(drive), xferspeed);
312 unsigned long base = (unsigned long)hwif->hwif_data;
313 u8 scsc = 0, addr_mask = ((hwif->channel) ?
314 ((hwif->mmio) ? 0xF4 : 0x84) :
315 ((hwif->mmio) ? 0xB4 : 0x80));
317 unsigned long ma = siimage_seldev(drive, 0x08);
318 unsigned long ua = siimage_seldev(drive, 0x0C);
321 scsc = hwif->INB(base + 0x4A);
322 mode = hwif->INB(base + addr_mask);
323 multi = hwif->INW(ma);
324 ultra = hwif->INW(ua);
326 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
327 pci_read_config_byte(hwif->pci_dev, addr_mask, &mode);
328 pci_read_config_word(hwif->pci_dev, ma, &multi);
329 pci_read_config_word(hwif->pci_dev, ua, &ultra);
332 mode &= ~((unit) ? 0x30 : 0x03);
334 scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
336 scsc = is_sata(hwif) ? 1 : scsc;
344 siimage_tuneproc(drive, (speed - XFER_PIO_0));
345 mode |= ((unit) ? 0x10 : 0x01);
350 multi = dma[speed - XFER_MW_DMA_0];
351 mode |= ((unit) ? 0x20 : 0x02);
352 config_siimage_chipset_for_pio(drive, 0);
362 ultra |= ((scsc) ? (ultra6[speed - XFER_UDMA_0]) :
363 (ultra5[speed - XFER_UDMA_0]));
364 mode |= ((unit) ? 0x30 : 0x03);
365 config_siimage_chipset_for_pio(drive, 0);
372 hwif->OUTB(mode, base + addr_mask);
373 hwif->OUTW(multi, ma);
374 hwif->OUTW(ultra, ua);
376 pci_write_config_byte(hwif->pci_dev, addr_mask, mode);
377 pci_write_config_word(hwif->pci_dev, ma, multi);
378 pci_write_config_word(hwif->pci_dev, ua, ultra);
380 return (ide_config_drive_speed(drive, speed));
384 * config_chipset_for_dma - configure for DMA
385 * @drive: drive to configure
387 * Called by the IDE layer when it wants the timings set up.
388 * For the CMD680 we also need to set up the PIO timings and
392 static int config_chipset_for_dma (ide_drive_t *drive)
394 u8 speed = ide_dma_speed(drive, siimage_ratemask(drive));
396 config_chipset_for_pio(drive, !speed);
401 if (ide_set_xfer_rate(drive, speed))
404 if (!drive->init_speed)
405 drive->init_speed = speed;
407 return ide_dma_enable(drive);
411 * siimage_configure_drive_for_dma - set up for DMA transfers
412 * @drive: drive we are going to set up
414 * Set up the drive for DMA, tune the controller and drive as
415 * required. If the drive isn't suitable for DMA or we hit
416 * other problems then we will drop down to PIO and set up
420 static int siimage_config_drive_for_dma (ide_drive_t *drive)
422 ide_hwif_t *hwif = HWIF(drive);
423 struct hd_driveid *id = drive->id;
425 if ((id->capability & 1) != 0 && drive->autodma) {
427 if (ide_use_dma(drive)) {
428 if (config_chipset_for_dma(drive))
429 return hwif->ide_dma_on(drive);
434 } else if ((id->capability & 8) || (id->field_valid & 2)) {
436 config_chipset_for_pio(drive, 1);
437 return hwif->ide_dma_off_quietly(drive);
439 /* IORDY not supported */
443 /* returns 1 if dma irq issued, 0 otherwise */
444 static int siimage_io_ide_dma_test_irq (ide_drive_t *drive)
446 ide_hwif_t *hwif = HWIF(drive);
448 unsigned long addr = siimage_selreg(hwif, 1);
450 /* return 1 if INTR asserted */
451 if ((hwif->INB(hwif->dma_status) & 4) == 4)
454 /* return 1 if Device INTR asserted */
455 pci_read_config_byte(hwif->pci_dev, addr, &dma_altstat);
457 return 0; //return 1;
462 * siimage_mmio_ide_dma_test_irq - check we caused an IRQ
463 * @drive: drive we are testing
465 * Check if we caused an IDE DMA interrupt. We may also have caused
466 * SATA status interrupts, if so we clean them up and continue.
469 static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive)
471 ide_hwif_t *hwif = HWIF(drive);
472 unsigned long base = (unsigned long)hwif->hwif_data;
473 unsigned long addr = siimage_selreg(hwif, 0x1);
475 if (SATA_ERROR_REG) {
476 u32 ext_stat = hwif->INL(base + 0x10);
478 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
479 u32 sata_error = hwif->INL(SATA_ERROR_REG);
480 hwif->OUTL(sata_error, SATA_ERROR_REG);
481 watchdog = (sata_error & 0x00680000) ? 1 : 0;
482 printk(KERN_WARNING "%s: sata_error = 0x%08x, "
483 "watchdog = %d, %s\n",
484 drive->name, sata_error, watchdog,
488 watchdog = (ext_stat & 0x8000) ? 1 : 0;
492 if (!(ext_stat & 0x0404) && !watchdog)
496 /* return 1 if INTR asserted */
497 if ((hwif->INB(hwif->dma_status) & 0x04) == 0x04)
500 /* return 1 if Device INTR asserted */
501 if ((hwif->INB(addr) & 8) == 8)
502 return 0; //return 1;
508 * siimage_busproc - bus isolation ioctl
509 * @drive: drive to isolate/restore
510 * @state: bus state to set
512 * Used by the SII3112 to handle bus isolation. As this is a
513 * SATA controller the work required is quite limited, we
514 * just have to clean up the statistics
517 static int siimage_busproc (ide_drive_t * drive, int state)
519 ide_hwif_t *hwif = HWIF(drive);
521 unsigned long addr = siimage_selreg(hwif, 0);
524 stat_config = hwif->INL(addr);
526 pci_read_config_dword(hwif->pci_dev, addr, &stat_config);
530 hwif->drives[0].failures = 0;
531 hwif->drives[1].failures = 0;
534 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
535 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
537 case BUSSTATE_TRISTATE:
538 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
539 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
544 hwif->bus_state = state;
549 * siimage_reset_poll - wait for sata reset
550 * @drive: drive we are resetting
552 * Poll the SATA phy and see whether it has come back from the dead
556 static int siimage_reset_poll (ide_drive_t *drive)
558 if (SATA_STATUS_REG) {
559 ide_hwif_t *hwif = HWIF(drive);
561 if ((hwif->INL(SATA_STATUS_REG) & 0x03) != 0x03) {
562 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
563 hwif->name, hwif->INL(SATA_STATUS_REG));
564 HWGROUP(drive)->polling = 0;
574 * siimage_pre_reset - reset hook
575 * @drive: IDE device being reset
577 * For the SATA devices we need to handle recalibration/geometry
581 static void siimage_pre_reset (ide_drive_t *drive)
583 if (drive->media != ide_disk)
586 if (is_sata(HWIF(drive)))
588 drive->special.b.set_geometry = 0;
589 drive->special.b.recalibrate = 0;
594 * siimage_reset - reset a device on an siimage controller
595 * @drive: drive to reset
597 * Perform a controller level reset fo the device. For
598 * SATA we must also check the PHY.
601 static void siimage_reset (ide_drive_t *drive)
603 ide_hwif_t *hwif = HWIF(drive);
605 unsigned long addr = siimage_selreg(hwif, 0);
608 reset = hwif->INB(addr);
609 hwif->OUTB((reset|0x03), addr);
612 hwif->OUTB(reset, addr);
613 (void) hwif->INB(addr);
615 pci_read_config_byte(hwif->pci_dev, addr, &reset);
616 pci_write_config_byte(hwif->pci_dev, addr, reset|0x03);
618 pci_write_config_byte(hwif->pci_dev, addr, reset);
619 pci_read_config_byte(hwif->pci_dev, addr, &reset);
622 if (SATA_STATUS_REG) {
623 u32 sata_stat = hwif->INL(SATA_STATUS_REG);
624 printk(KERN_WARNING "%s: reset phy, status=0x%08x, %s\n",
625 hwif->name, sata_stat, __FUNCTION__);
627 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
628 hwif->name, sata_stat);
636 * proc_reports_siimage - add siimage controller to proc
638 * @clocking: SCSC value
639 * @name: controller name
641 * Report the clocking mode of the controller and add it to
642 * the /proc interface layer
645 static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name)
647 if (!pdev_is_sata(dev)) {
648 printk(KERN_INFO "%s: BASE CLOCK ", name);
651 case 0x03: printk("DISABLED!\n"); break;
652 case 0x02: printk("== 2X PCI\n"); break;
653 case 0x01: printk("== 133\n"); break;
654 case 0x00: printk("== 100\n"); break;
660 * setup_mmio_siimage - switch an SI controller into MMIO
661 * @dev: PCI device we are configuring
664 * Attempt to put the device into mmio mode. There are some slight
665 * complications here with certain systems where the mmio bar isnt
666 * mapped so we have to be sure we can fall back to I/O.
669 static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
671 unsigned long bar5 = pci_resource_start(dev, 5);
672 unsigned long barsize = pci_resource_len(dev, 5);
674 void __iomem *ioaddr;
678 * Drop back to PIO if we can't map the mmio. Some
679 * systems seem to get terminally confused in the PCI
683 if(!request_mem_region(bar5, barsize, name))
685 printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
689 ioaddr = ioremap(bar5, barsize);
693 release_mem_region(bar5, barsize);
698 pci_set_drvdata(dev, (void *) ioaddr);
700 if (pdev_is_sata(dev)) {
701 /* make sure IDE0/1 interrupts are not masked */
702 irq_mask = (1 << 22) | (1 << 23);
703 tmp = readl(ioaddr + 0x48);
704 if (tmp & irq_mask) {
706 writel(tmp, ioaddr + 0x48);
707 readl(ioaddr + 0x48); /* flush */
709 writel(0, ioaddr + 0x148);
710 writel(0, ioaddr + 0x1C8);
713 writeb(0, ioaddr + 0xB4);
714 writeb(0, ioaddr + 0xF4);
715 tmpbyte = readb(ioaddr + 0x4A);
717 switch(tmpbyte & 0x30) {
719 /* In 100 MHz clocking, try and switch to 133 */
720 writeb(tmpbyte|0x10, ioaddr + 0x4A);
723 /* On 133Mhz clocking */
726 /* On PCIx2 clocking */
729 /* Clocking is disabled */
730 /* 133 clock attempt to force it on */
731 writeb(tmpbyte & ~0x20, ioaddr + 0x4A);
735 writeb( 0x72, ioaddr + 0xA1);
736 writew( 0x328A, ioaddr + 0xA2);
737 writel(0x62DD62DD, ioaddr + 0xA4);
738 writel(0x43924392, ioaddr + 0xA8);
739 writel(0x40094009, ioaddr + 0xAC);
740 writeb( 0x72, ioaddr + 0xE1);
741 writew( 0x328A, ioaddr + 0xE2);
742 writel(0x62DD62DD, ioaddr + 0xE4);
743 writel(0x43924392, ioaddr + 0xE8);
744 writel(0x40094009, ioaddr + 0xEC);
746 if (pdev_is_sata(dev)) {
747 writel(0xFFFF0000, ioaddr + 0x108);
748 writel(0xFFFF0000, ioaddr + 0x188);
749 writel(0x00680000, ioaddr + 0x148);
750 writel(0x00680000, ioaddr + 0x1C8);
753 tmpbyte = readb(ioaddr + 0x4A);
755 proc_reports_siimage(dev, (tmpbyte>>4), name);
760 * init_chipset_siimage - set up an SI device
764 * Perform the initial PCI set up for this device. Attempt to switch
765 * to 133MHz clocking if the system isn't already set up to do it.
768 static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name)
774 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
776 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
778 pci_read_config_byte(dev, 0x8A, &BA5_EN);
779 if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) {
780 if (setup_mmio_siimage(dev, name)) {
785 pci_write_config_byte(dev, 0x80, 0x00);
786 pci_write_config_byte(dev, 0x84, 0x00);
787 pci_read_config_byte(dev, 0x8A, &tmpbyte);
788 switch(tmpbyte & 0x30) {
790 /* 133 clock attempt to force it on */
791 pci_write_config_byte(dev, 0x8A, tmpbyte|0x10);
793 /* if clocking is disabled */
794 /* 133 clock attempt to force it on */
795 pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20);
800 /* BIOS set PCI x2 clocking */
804 pci_read_config_byte(dev, 0x8A, &tmpbyte);
806 pci_write_config_byte(dev, 0xA1, 0x72);
807 pci_write_config_word(dev, 0xA2, 0x328A);
808 pci_write_config_dword(dev, 0xA4, 0x62DD62DD);
809 pci_write_config_dword(dev, 0xA8, 0x43924392);
810 pci_write_config_dword(dev, 0xAC, 0x40094009);
811 pci_write_config_byte(dev, 0xB1, 0x72);
812 pci_write_config_word(dev, 0xB2, 0x328A);
813 pci_write_config_dword(dev, 0xB4, 0x62DD62DD);
814 pci_write_config_dword(dev, 0xB8, 0x43924392);
815 pci_write_config_dword(dev, 0xBC, 0x40094009);
817 proc_reports_siimage(dev, (tmpbyte>>4), name);
822 * init_mmio_iops_siimage - set up the iops for MMIO
823 * @hwif: interface to set up
825 * The basic setup here is fairly simple, we can use standard MMIO
826 * operations. However we do have to set the taskfile register offsets
827 * by hand as there isnt a standard defined layout for them this
830 * The hardware supports buffered taskfiles and also some rather nice
831 * extended PRD tables. For better SI3112 support use the libata driver
834 static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
836 struct pci_dev *dev = hwif->pci_dev;
837 void *addr = pci_get_drvdata(dev);
838 u8 ch = hwif->channel;
843 * Fill in the basic HWIF bits
846 default_hwif_mmiops(hwif);
847 hwif->hwif_data = addr;
850 * Now set up the hw. We have to do this ourselves as
851 * the MMIO layout isnt the same as the the standard port
855 memset(&hw, 0, sizeof(hw_regs_t));
857 base = (unsigned long)addr;
864 * The buffered task file doesn't have status/control
865 * so we can't currently use it sanely since we want to
868 hw.io_ports[IDE_DATA_OFFSET] = base;
869 hw.io_ports[IDE_ERROR_OFFSET] = base + 1;
870 hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2;
871 hw.io_ports[IDE_SECTOR_OFFSET] = base + 3;
872 hw.io_ports[IDE_LCYL_OFFSET] = base + 4;
873 hw.io_ports[IDE_HCYL_OFFSET] = base + 5;
874 hw.io_ports[IDE_SELECT_OFFSET] = base + 6;
875 hw.io_ports[IDE_STATUS_OFFSET] = base + 7;
876 hw.io_ports[IDE_CONTROL_OFFSET] = base + 10;
878 hw.io_ports[IDE_IRQ_OFFSET] = 0;
880 if (pdev_is_sata(dev)) {
881 base = (unsigned long)addr;
884 hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
885 hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
886 hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100;
887 hwif->sata_misc[SATA_MISC_OFFSET] = base + 0x140;
888 hwif->sata_misc[SATA_PHY_OFFSET] = base + 0x144;
889 hwif->sata_misc[SATA_IEN_OFFSET] = base + 0x148;
892 hw.irq = hwif->pci_dev->irq;
894 memcpy(&hwif->hw, &hw, sizeof(hw));
895 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->hw.io_ports));
899 base = (unsigned long) addr;
901 hwif->dma_base = base + (ch ? 0x08 : 0x00);
902 hwif->dma_base2 = base + (ch ? 0x18 : 0x10);
906 static int is_dev_seagate_sata(ide_drive_t *drive)
908 const char *s = &drive->id->model[0];
914 len = strnlen(s, sizeof(drive->id->model));
916 if ((len > 4) && (!memcmp(s, "ST", 2))) {
917 if ((!memcmp(s + len - 2, "AS", 2)) ||
918 (!memcmp(s + len - 3, "ASL", 3))) {
919 printk(KERN_INFO "%s: applying pessimistic Seagate "
920 "errata fix\n", drive->name);
928 * siimage_fixup - post probe fixups
929 * @hwif: interface to fix up
931 * Called after drive probe we use this to decide whether the
932 * Seagate fixup must be applied. This used to be in init_iops but
933 * that can occur before we know what drives are present.
936 static void __devinit siimage_fixup(ide_hwif_t *hwif)
938 /* Try and raise the rqsize */
939 if (!is_sata(hwif) || !is_dev_seagate_sata(&hwif->drives[0]))
944 * init_iops_siimage - set up iops
945 * @hwif: interface to set up
947 * Do the basic setup for the SIIMAGE hardware interface
948 * and then do the MMIO setup if we can. This is the first
949 * look in we get for setting up the hwif so that we
950 * can get the iops right before using them.
953 static void __devinit init_iops_siimage(ide_hwif_t *hwif)
955 struct pci_dev *dev = hwif->pci_dev;
958 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
961 hwif->hwif_data = NULL;
963 /* Pessimal until we finish probing */
966 if (pci_get_drvdata(dev) == NULL)
968 init_mmio_iops_siimage(hwif);
972 * ata66_siimage - check for 80 pin cable
973 * @hwif: interface to check
975 * Check for the presence of an ATA66 capable cable on the
979 static unsigned int __devinit ata66_siimage(ide_hwif_t *hwif)
981 unsigned long addr = siimage_selreg(hwif, 0);
982 if (pci_get_drvdata(hwif->pci_dev) == NULL) {
984 pci_read_config_byte(hwif->pci_dev, addr, &ata66);
985 return (ata66 & 0x01) ? 1 : 0;
988 return (hwif->INB(addr) & 0x01) ? 1 : 0;
992 * init_hwif_siimage - set up hwif structs
993 * @hwif: interface to set up
995 * We do the basic set up of the interface structure. The SIIMAGE
996 * requires several custom handlers so we override the default
997 * ide DMA handlers appropriately
1000 static void __devinit init_hwif_siimage(ide_hwif_t *hwif)
1004 hwif->resetproc = &siimage_reset;
1005 hwif->speedproc = &siimage_tune_chipset;
1006 hwif->tuneproc = &siimage_tuneproc;
1007 hwif->reset_poll = &siimage_reset_poll;
1008 hwif->pre_reset = &siimage_pre_reset;
1011 static int first = 1;
1013 hwif->busproc = &siimage_busproc;
1016 printk(KERN_INFO "siimage: For full SATA support you should use the libata sata_sil module.\n");
1020 if (!hwif->dma_base) {
1021 hwif->drives[0].autotune = 1;
1022 hwif->drives[1].autotune = 1;
1026 hwif->ultra_mask = 0x7f;
1027 hwif->mwdma_mask = 0x07;
1028 hwif->swdma_mask = 0x07;
1031 hwif->atapi_dma = 1;
1033 hwif->ide_dma_check = &siimage_config_drive_for_dma;
1034 if (!(hwif->udma_four))
1035 hwif->udma_four = ata66_siimage(hwif);
1038 hwif->ide_dma_test_irq = &siimage_mmio_ide_dma_test_irq;
1040 hwif->ide_dma_test_irq = & siimage_io_ide_dma_test_irq;
1044 * The BIOS often doesn't set up DMA on this controller
1045 * so we always do it.
1049 hwif->drives[0].autodma = hwif->autodma;
1050 hwif->drives[1].autodma = hwif->autodma;
1053 #define DECLARE_SII_DEV(name_str) \
1056 .init_chipset = init_chipset_siimage, \
1057 .init_iops = init_iops_siimage, \
1058 .init_hwif = init_hwif_siimage, \
1059 .fixup = siimage_fixup, \
1061 .autodma = AUTODMA, \
1062 .bootable = ON_BOARD, \
1065 static ide_pci_device_t siimage_chipsets[] __devinitdata = {
1066 /* 0 */ DECLARE_SII_DEV("SiI680"),
1067 /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"),
1068 /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA")
1072 * siimage_init_one - pci layer discovery entry
1074 * @id: ident table entry
1076 * Called by the PCI code when it finds an SI680 or SI3112 controller.
1077 * We then use the IDE PCI generic helper to do most of the work.
1080 static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1082 return ide_setup_pci_device(dev, &siimage_chipsets[id->driver_data]);
1085 static struct pci_device_id siimage_pci_tbl[] = {
1086 { PCI_DEVICE(PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680), 0},
1087 #ifdef CONFIG_BLK_DEV_IDE_SATA
1088 { PCI_DEVICE(PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_3112), 1},
1089 { PCI_DEVICE(PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_1210SA), 2},
1093 MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
1095 static struct pci_driver driver = {
1097 .id_table = siimage_pci_tbl,
1098 .probe = siimage_init_one,
1101 static int siimage_ide_init(void)
1103 return ide_pci_register_driver(&driver);
1106 module_init(siimage_ide_init);
1108 MODULE_AUTHOR("Andre Hedrick, Alan Cox");
1109 MODULE_DESCRIPTION("PCI driver module for SiI IDE");
1110 MODULE_LICENSE("GPL");