2 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2003 Red Hat <alan@redhat.com>
4 * Copyright (C) 2007-2008 MontaVista Software, Inc.
5 * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
7 * May be copied or modified under the terms of the GNU General Public License
9 * Documentation for CMD680:
10 * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
12 * Documentation for SiI 3112:
13 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
15 * Errata and other documentation only available under NDA.
19 * If you are using Marvell SATA-IDE adapters with Maxtor drives
20 * ensure the system is set up for ATA100/UDMA5, not UDMA6.
22 * If you are using WD drives with SATA bridges you must set the
23 * drive to "Single". "Master" will hang.
25 * If you have strange problems with nVidia chipset systems please
26 * see the SI support documentation and update your system BIOS
29 * The Dell DRAC4 has some interesting features including effectively hot
30 * unplugging/replugging the virtual CD interface when the DRAC is reset.
31 * This often causes drivers/ide/siimage to panic but is ok with the rather
32 * smarter code in libata.
39 #include <linux/types.h>
40 #include <linux/module.h>
41 #include <linux/pci.h>
42 #include <linux/hdreg.h>
43 #include <linux/ide.h>
44 #include <linux/init.h>
48 * pdev_is_sata - check if device is SATA
49 * @pdev: PCI device to check
51 * Returns true if this is a SATA controller
54 static int pdev_is_sata(struct pci_dev *pdev)
56 #ifdef CONFIG_BLK_DEV_IDE_SATA
57 switch (pdev->device) {
58 case PCI_DEVICE_ID_SII_3112:
59 case PCI_DEVICE_ID_SII_1210SA:
61 case PCI_DEVICE_ID_SII_680:
70 * is_sata - check if hwif is SATA
71 * @hwif: interface to check
73 * Returns true if this is a SATA controller
76 static inline int is_sata(ide_hwif_t *hwif)
78 return pdev_is_sata(to_pci_dev(hwif->dev));
82 * siimage_selreg - return register base
86 * Turn a config register offset into the right address in either
87 * PCI space or MMIO space to access the control register in question
88 * Thankfully this is a configuration operation, so isn't performance
92 static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
94 unsigned long base = (unsigned long)hwif->hwif_data;
97 if (hwif->host_flags & IDE_HFLAG_MMIO)
98 base += hwif->channel << 6;
100 base += hwif->channel << 4;
105 * siimage_seldev - return register base
109 * Turn a config register offset into the right address in either
110 * PCI space or MMIO space to access the control register in question
111 * including accounting for the unit shift.
114 static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
116 ide_hwif_t *hwif = HWIF(drive);
117 unsigned long base = (unsigned long)hwif->hwif_data;
120 if (hwif->host_flags & IDE_HFLAG_MMIO)
121 base += hwif->channel << 6;
123 base += hwif->channel << 4;
124 base |= drive->select.b.unit << drive->select.b.unit;
128 static u8 sil_ioread8(struct pci_dev *dev, unsigned long addr)
130 struct ide_host *host = pci_get_drvdata(dev);
134 tmp = readb((void __iomem *)addr);
136 pci_read_config_byte(dev, addr, &tmp);
141 static u16 sil_ioread16(struct pci_dev *dev, unsigned long addr)
143 struct ide_host *host = pci_get_drvdata(dev);
147 tmp = readw((void __iomem *)addr);
149 pci_read_config_word(dev, addr, &tmp);
154 static void sil_iowrite8(struct pci_dev *dev, u8 val, unsigned long addr)
156 struct ide_host *host = pci_get_drvdata(dev);
159 writeb(val, (void __iomem *)addr);
161 pci_write_config_byte(dev, addr, val);
164 static void sil_iowrite16(struct pci_dev *dev, u16 val, unsigned long addr)
166 struct ide_host *host = pci_get_drvdata(dev);
169 writew(val, (void __iomem *)addr);
171 pci_write_config_word(dev, addr, val);
174 static void sil_iowrite32(struct pci_dev *dev, u32 val, unsigned long addr)
176 struct ide_host *host = pci_get_drvdata(dev);
179 writel(val, (void __iomem *)addr);
181 pci_write_config_dword(dev, addr, val);
185 * sil_udma_filter - compute UDMA mask
188 * Compute the available UDMA speeds for the device on the interface.
190 * For the CMD680 this depends on the clocking mode (scsc), for the
191 * SI3112 SATA controller life is a bit simpler.
194 static u8 sil_pata_udma_filter(ide_drive_t *drive)
196 ide_hwif_t *hwif = drive->hwif;
197 struct pci_dev *dev = to_pci_dev(hwif->dev);
198 unsigned long base = (unsigned long)hwif->hwif_data;
201 base += (hwif->host_flags & IDE_HFLAG_MMIO) ? 0x4A : 0x8A;
203 scsc = sil_ioread8(dev, base);
205 switch (scsc & 0x30) {
209 case 0x20: /* 2xPCI */
215 default: /* Disabled ? */
222 static u8 sil_sata_udma_filter(ide_drive_t *drive)
224 return strstr(drive->id->model, "Maxtor") ? ATA_UDMA5 : ATA_UDMA6;
228 * sil_set_pio_mode - set host controller for PIO mode
230 * @pio: PIO mode number
232 * Load the timing settings for this device mode into the
233 * controller. If we are in PIO mode 3 or 4 turn on IORDY
234 * monitoring (bit 9). The TF timing is bits 31:16
237 static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
239 static const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
240 static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
242 ide_hwif_t *hwif = HWIF(drive);
243 struct pci_dev *dev = to_pci_dev(hwif->dev);
244 ide_drive_t *pair = ide_get_paired_drive(drive);
247 unsigned long addr = siimage_seldev(drive, 0x04);
248 unsigned long tfaddr = siimage_selreg(hwif, 0x02);
249 unsigned long base = (unsigned long)hwif->hwif_data;
251 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
252 u8 addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84)
253 : (mmio ? 0xB4 : 0x80);
255 u8 unit = drive->select.b.unit;
257 /* trim *taskfile* PIO to the slowest of the master/slave */
259 u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4);
261 if (pair_pio < tf_pio)
265 /* cheat for now and use the docs */
266 speedp = data_speed[pio];
267 speedt = tf_speed[tf_pio];
269 sil_iowrite16(dev, speedp, addr);
270 sil_iowrite16(dev, speedt, tfaddr);
272 /* now set up IORDY */
273 speedp = sil_ioread16(dev, tfaddr - 2);
277 sil_iowrite16(dev, speedp, tfaddr - 2);
279 mode = sil_ioread8(dev, base + addr_mask);
280 mode &= ~(unit ? 0x30 : 0x03);
281 mode |= unit ? 0x10 : 0x01;
282 sil_iowrite8(dev, mode, base + addr_mask);
286 * sil_set_dma_mode - set host controller for DMA mode
290 * Tune the SiI chipset for the desired DMA mode.
293 static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed)
295 static const u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
296 static const u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
297 static const u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
299 ide_hwif_t *hwif = HWIF(drive);
300 struct pci_dev *dev = to_pci_dev(hwif->dev);
301 u16 ultra = 0, multi = 0;
302 u8 mode = 0, unit = drive->select.b.unit;
303 unsigned long base = (unsigned long)hwif->hwif_data;
304 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
305 u8 scsc = 0, addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84)
306 : (mmio ? 0xB4 : 0x80);
307 unsigned long ma = siimage_seldev(drive, 0x08);
308 unsigned long ua = siimage_seldev(drive, 0x0C);
310 scsc = sil_ioread8 (dev, base + (mmio ? 0x4A : 0x8A));
311 mode = sil_ioread8 (dev, base + addr_mask);
312 multi = sil_ioread16(dev, ma);
313 ultra = sil_ioread16(dev, ua);
315 mode &= ~(unit ? 0x30 : 0x03);
317 scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
319 scsc = is_sata(hwif) ? 1 : scsc;
321 if (speed >= XFER_UDMA_0) {
323 ultra |= scsc ? ultra6[speed - XFER_UDMA_0] :
324 ultra5[speed - XFER_UDMA_0];
325 mode |= unit ? 0x30 : 0x03;
327 multi = dma[speed - XFER_MW_DMA_0];
328 mode |= unit ? 0x20 : 0x02;
331 sil_iowrite8 (dev, mode, base + addr_mask);
332 sil_iowrite16(dev, multi, ma);
333 sil_iowrite16(dev, ultra, ua);
336 /* returns 1 if dma irq issued, 0 otherwise */
337 static int siimage_io_dma_test_irq(ide_drive_t *drive)
339 ide_hwif_t *hwif = HWIF(drive);
340 struct pci_dev *dev = to_pci_dev(hwif->dev);
342 unsigned long addr = siimage_selreg(hwif, 1);
344 /* return 1 if INTR asserted */
345 if (inb(hwif->dma_base + ATA_DMA_STATUS) & 4)
348 /* return 1 if Device INTR asserted */
349 pci_read_config_byte(dev, addr, &dma_altstat);
351 return 0; /* return 1; */
357 * siimage_mmio_dma_test_irq - check we caused an IRQ
358 * @drive: drive we are testing
360 * Check if we caused an IDE DMA interrupt. We may also have caused
361 * SATA status interrupts, if so we clean them up and continue.
364 static int siimage_mmio_dma_test_irq(ide_drive_t *drive)
366 ide_hwif_t *hwif = HWIF(drive);
367 unsigned long addr = siimage_selreg(hwif, 0x1);
368 void __iomem *sata_error_addr
369 = (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET];
371 if (sata_error_addr) {
372 unsigned long base = (unsigned long)hwif->hwif_data;
373 u32 ext_stat = readl((void __iomem *)(base + 0x10));
376 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
377 u32 sata_error = readl(sata_error_addr);
379 writel(sata_error, sata_error_addr);
380 watchdog = (sata_error & 0x00680000) ? 1 : 0;
381 printk(KERN_WARNING "%s: sata_error = 0x%08x, "
382 "watchdog = %d, %s\n",
383 drive->name, sata_error, watchdog, __func__);
385 watchdog = (ext_stat & 0x8000) ? 1 : 0;
388 if (!(ext_stat & 0x0404) && !watchdog)
392 /* return 1 if INTR asserted */
393 if (readb((void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)) & 4)
396 /* return 1 if Device INTR asserted */
397 if (readb((void __iomem *)addr) & 8)
398 return 0; /* return 1; */
403 static int siimage_dma_test_irq(ide_drive_t *drive)
405 if (drive->hwif->host_flags & IDE_HFLAG_MMIO)
406 return siimage_mmio_dma_test_irq(drive);
408 return siimage_io_dma_test_irq(drive);
412 * sil_sata_reset_poll - wait for SATA reset
413 * @drive: drive we are resetting
415 * Poll the SATA phy and see whether it has come back from the dead
419 static int sil_sata_reset_poll(ide_drive_t *drive)
421 ide_hwif_t *hwif = drive->hwif;
422 void __iomem *sata_status_addr
423 = (void __iomem *)hwif->sata_scr[SATA_STATUS_OFFSET];
425 if (sata_status_addr) {
426 /* SATA Status is available only when in MMIO mode */
427 u32 sata_stat = readl(sata_status_addr);
429 if ((sata_stat & 0x03) != 0x03) {
430 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
431 hwif->name, sata_stat);
440 * sil_sata_pre_reset - reset hook
441 * @drive: IDE device being reset
443 * For the SATA devices we need to handle recalibration/geometry
447 static void sil_sata_pre_reset(ide_drive_t *drive)
449 if (drive->media == ide_disk) {
450 drive->special.b.set_geometry = 0;
451 drive->special.b.recalibrate = 0;
456 * init_chipset_siimage - set up an SI device
460 * Perform the initial PCI set up for this device. Attempt to switch
461 * to 133 MHz clocking if the system isn't already set up to do it.
464 static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev,
467 struct ide_host *host = pci_get_drvdata(dev);
468 void __iomem *ioaddr = host->host_priv;
469 unsigned long base, scsc_addr;
470 u8 rev = dev->revision, tmp;
472 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255);
477 base = (unsigned long)ioaddr;
479 if (ioaddr && pdev_is_sata(dev)) {
482 /* make sure IDE0/1 interrupts are not masked */
483 irq_mask = (1 << 22) | (1 << 23);
484 tmp32 = readl(ioaddr + 0x48);
485 if (tmp32 & irq_mask) {
487 writel(tmp32, ioaddr + 0x48);
488 readl(ioaddr + 0x48); /* flush */
490 writel(0, ioaddr + 0x148);
491 writel(0, ioaddr + 0x1C8);
494 sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80);
495 sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84);
497 scsc_addr = base ? (base + 0x4A) : 0x8A;
498 tmp = sil_ioread8(dev, scsc_addr);
500 switch (tmp & 0x30) {
502 /* On 100 MHz clocking, try and switch to 133 MHz */
503 sil_iowrite8(dev, tmp | 0x10, scsc_addr);
506 /* Clocking is disabled, attempt to force 133MHz clocking. */
507 sil_iowrite8(dev, tmp & ~0x20, scsc_addr);
509 /* On 133Mhz clocking. */
512 /* On PCIx2 clocking. */
516 tmp = sil_ioread8(dev, scsc_addr);
518 sil_iowrite8 (dev, 0x72, base + 0xA1);
519 sil_iowrite16(dev, 0x328A, base + 0xA2);
520 sil_iowrite32(dev, 0x62DD62DD, base + 0xA4);
521 sil_iowrite32(dev, 0x43924392, base + 0xA8);
522 sil_iowrite32(dev, 0x40094009, base + 0xAC);
523 sil_iowrite8 (dev, 0x72, base ? (base + 0xE1) : 0xB1);
524 sil_iowrite16(dev, 0x328A, base ? (base + 0xE2) : 0xB2);
525 sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4);
526 sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8);
527 sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC);
529 if (base && pdev_is_sata(dev)) {
530 writel(0xFFFF0000, ioaddr + 0x108);
531 writel(0xFFFF0000, ioaddr + 0x188);
532 writel(0x00680000, ioaddr + 0x148);
533 writel(0x00680000, ioaddr + 0x1C8);
536 /* report the clocking mode of the controller */
537 if (!pdev_is_sata(dev)) {
538 static const char *clk_str[] =
539 { "== 100", "== 133", "== 2X PCI", "DISABLED!" };
542 printk(KERN_INFO "%s: BASE CLOCK %s\n", name, clk_str[tmp & 3]);
549 * init_mmio_iops_siimage - set up the iops for MMIO
550 * @hwif: interface to set up
552 * The basic setup here is fairly simple, we can use standard MMIO
553 * operations. However we do have to set the taskfile register offsets
554 * by hand as there isn't a standard defined layout for them this time.
556 * The hardware supports buffered taskfiles and also some rather nice
557 * extended PRD tables. For better SI3112 support use the libata driver
560 static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
562 struct pci_dev *dev = to_pci_dev(hwif->dev);
563 struct ide_host *host = pci_get_drvdata(dev);
564 void *addr = host->host_priv;
565 u8 ch = hwif->channel;
566 struct ide_io_ports *io_ports = &hwif->io_ports;
570 * Fill in the basic hwif bits
572 hwif->host_flags |= IDE_HFLAG_MMIO;
574 hwif->hwif_data = addr;
577 * Now set up the hw. We have to do this ourselves as the
578 * MMIO layout isn't the same as the standard port based I/O.
580 memset(io_ports, 0, sizeof(*io_ports));
582 base = (unsigned long)addr;
589 * The buffered task file doesn't have status/control, so we
590 * can't currently use it sanely since we want to use LBA48 mode.
592 io_ports->data_addr = base;
593 io_ports->error_addr = base + 1;
594 io_ports->nsect_addr = base + 2;
595 io_ports->lbal_addr = base + 3;
596 io_ports->lbam_addr = base + 4;
597 io_ports->lbah_addr = base + 5;
598 io_ports->device_addr = base + 6;
599 io_ports->status_addr = base + 7;
600 io_ports->ctl_addr = base + 10;
602 if (pdev_is_sata(dev)) {
603 base = (unsigned long)addr;
606 hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
607 hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
608 hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100;
611 hwif->irq = dev->irq;
613 hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00);
616 static int is_dev_seagate_sata(ide_drive_t *drive)
618 const char *s = &drive->id->model[0];
619 unsigned len = strnlen(s, sizeof(drive->id->model));
621 if ((len > 4) && (!memcmp(s, "ST", 2)))
622 if ((!memcmp(s + len - 2, "AS", 2)) ||
623 (!memcmp(s + len - 3, "ASL", 3))) {
624 printk(KERN_INFO "%s: applying pessimistic Seagate "
625 "errata fix\n", drive->name);
633 * sil_quirkproc - post probe fixups
636 * Called after drive probe we use this to decide whether the
637 * Seagate fixup must be applied. This used to be in init_iops but
638 * that can occur before we know what drives are present.
641 static void __devinit sil_quirkproc(ide_drive_t *drive)
643 ide_hwif_t *hwif = drive->hwif;
645 /* Try and rise the rqsize */
646 if (!is_sata(hwif) || !is_dev_seagate_sata(drive))
651 * init_iops_siimage - set up iops
652 * @hwif: interface to set up
654 * Do the basic setup for the SIIMAGE hardware interface
655 * and then do the MMIO setup if we can. This is the first
656 * look in we get for setting up the hwif so that we
657 * can get the iops right before using them.
660 static void __devinit init_iops_siimage(ide_hwif_t *hwif)
662 struct pci_dev *dev = to_pci_dev(hwif->dev);
663 struct ide_host *host = pci_get_drvdata(dev);
665 hwif->hwif_data = NULL;
667 /* Pessimal until we finish probing */
671 init_mmio_iops_siimage(hwif);
675 * sil_cable_detect - cable detection
676 * @hwif: interface to check
678 * Check for the presence of an ATA66 capable cable on the interface.
681 static u8 __devinit sil_cable_detect(ide_hwif_t *hwif)
683 struct pci_dev *dev = to_pci_dev(hwif->dev);
684 unsigned long addr = siimage_selreg(hwif, 0);
685 u8 ata66 = sil_ioread8(dev, addr);
687 return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
690 static const struct ide_port_ops sil_pata_port_ops = {
691 .set_pio_mode = sil_set_pio_mode,
692 .set_dma_mode = sil_set_dma_mode,
693 .quirkproc = sil_quirkproc,
694 .udma_filter = sil_pata_udma_filter,
695 .cable_detect = sil_cable_detect,
698 static const struct ide_port_ops sil_sata_port_ops = {
699 .set_pio_mode = sil_set_pio_mode,
700 .set_dma_mode = sil_set_dma_mode,
701 .reset_poll = sil_sata_reset_poll,
702 .pre_reset = sil_sata_pre_reset,
703 .quirkproc = sil_quirkproc,
704 .udma_filter = sil_sata_udma_filter,
705 .cable_detect = sil_cable_detect,
708 static const struct ide_dma_ops sil_dma_ops = {
709 .dma_host_set = ide_dma_host_set,
710 .dma_setup = ide_dma_setup,
711 .dma_exec_cmd = ide_dma_exec_cmd,
712 .dma_start = ide_dma_start,
713 .dma_end = __ide_dma_end,
714 .dma_test_irq = siimage_dma_test_irq,
715 .dma_timeout = ide_dma_timeout,
716 .dma_lost_irq = ide_dma_lost_irq,
719 #define DECLARE_SII_DEV(name_str, p_ops) \
722 .init_chipset = init_chipset_siimage, \
723 .init_iops = init_iops_siimage, \
725 .dma_ops = &sil_dma_ops, \
726 .pio_mask = ATA_PIO4, \
727 .mwdma_mask = ATA_MWDMA2, \
728 .udma_mask = ATA_UDMA6, \
731 static const struct ide_port_info siimage_chipsets[] __devinitdata = {
732 /* 0 */ DECLARE_SII_DEV("SiI680", &sil_pata_port_ops),
733 /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA", &sil_sata_port_ops),
734 /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA", &sil_sata_port_ops)
738 * siimage_init_one - PCI layer discovery entry
740 * @id: ident table entry
742 * Called by the PCI code when it finds an SiI680 or SiI3112 controller.
743 * We then use the IDE PCI generic helper to do most of the work.
746 static int __devinit siimage_init_one(struct pci_dev *dev,
747 const struct pci_device_id *id)
749 void __iomem *ioaddr = NULL;
750 resource_size_t bar5 = pci_resource_start(dev, 5);
751 unsigned long barsize = pci_resource_len(dev, 5);
753 struct ide_port_info d;
754 u8 idx = id->driver_data;
757 d = siimage_chipsets[idx];
760 static int first = 1;
763 printk(KERN_INFO "siimage: For full SATA support you "
764 "should use the libata sata_sil module.\n");
768 d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
771 rc = pci_enable_device(dev);
775 pci_read_config_byte(dev, 0x8A, &BA5_EN);
776 if ((BA5_EN & 0x01) || bar5) {
778 * Drop back to PIO if we can't map the MMIO. Some systems
779 * seem to get terminally confused in the PCI spaces.
781 if (!request_mem_region(bar5, barsize, d.name)) {
782 printk(KERN_WARNING "siimage: IDE controller MMIO "
783 "ports not available.\n");
785 ioaddr = ioremap(bar5, barsize);
787 release_mem_region(bar5, barsize);
791 rc = ide_pci_init_one(dev, &d, ioaddr);
795 release_mem_region(bar5, barsize);
797 pci_disable_device(dev);
803 static void __devexit siimage_remove(struct pci_dev *dev)
805 struct ide_host *host = pci_get_drvdata(dev);
806 void __iomem *ioaddr = host->host_priv;
811 resource_size_t bar5 = pci_resource_start(dev, 5);
812 unsigned long barsize = pci_resource_len(dev, 5);
815 release_mem_region(bar5, barsize);
818 pci_disable_device(dev);
821 static const struct pci_device_id siimage_pci_tbl[] = {
822 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), 0 },
823 #ifdef CONFIG_BLK_DEV_IDE_SATA
824 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_3112), 1 },
825 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_1210SA), 2 },
829 MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
831 static struct pci_driver driver = {
833 .id_table = siimage_pci_tbl,
834 .probe = siimage_init_one,
835 .remove = siimage_remove,
838 static int __init siimage_ide_init(void)
840 return ide_pci_register_driver(&driver);
843 static void __exit siimage_ide_exit(void)
845 pci_unregister_driver(&driver);
848 module_init(siimage_ide_init);
849 module_exit(siimage_ide_exit);
851 MODULE_AUTHOR("Andre Hedrick, Alan Cox");
852 MODULE_DESCRIPTION("PCI driver module for SiI IDE");
853 MODULE_LICENSE("GPL");