2 * linux/drivers/ide/pci/pdc202xx_old.c Version 0.36 Sept 11, 2002
4 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
6 * Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
7 * compiled into the kernel if you have more than one card installed.
8 * Note that BIOS v1.29 is reported to fix the problem. Since this is
9 * safe chipset tuning, including this support is harmless
11 * Promise Ultra66 cards with BIOS v1.11 this
12 * compiled into the kernel if you have more than one card installed.
14 * Promise Ultra100 cards.
16 * The latest chipset code will support the following ::
17 * Three Ultra33 controllers and 12 drives.
18 * 8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
19 * The 8/4 ratio is a BIOS code limit by promise.
21 * UNLESS you enable "CONFIG_PDC202XX_BURST"
26 * Portions Copyright (C) 1999 Promise Technology, Inc.
27 * Author: Frank Tiernan (frankt@promise.com)
28 * Released under terms of General Public License
31 #include <linux/config.h>
32 #include <linux/types.h>
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/delay.h>
36 #include <linux/timer.h>
38 #include <linux/ioport.h>
39 #include <linux/blkdev.h>
40 #include <linux/hdreg.h>
41 #include <linux/interrupt.h>
42 #include <linux/pci.h>
43 #include <linux/init.h>
44 #include <linux/ide.h>
49 #define PDC202_DEBUG_CABLE 0
50 #define PDC202XX_DEBUG_DRIVE_INFO 0
52 static const char *pdc_quirk_drives[] = {
53 "QUANTUM FIREBALLlct08 08",
54 "QUANTUM FIREBALLP KA6.4",
55 "QUANTUM FIREBALLP KA9.1",
56 "QUANTUM FIREBALLP LM20.4",
57 "QUANTUM FIREBALLP KX13.6",
58 "QUANTUM FIREBALLP KX20.5",
59 "QUANTUM FIREBALLP KX27.3",
60 "QUANTUM FIREBALLP LM20.5",
65 #define SYNC_ERRDY_EN 0xC0
67 #define SYNC_IN 0x80 /* control bit, different for master vs. slave drives */
68 #define ERRDY_EN 0x40 /* control bit, different for master vs. slave drives */
69 #define IORDY_EN 0x20 /* PIO: IOREADY */
70 #define PREFETCH_EN 0x10 /* PIO: PREFETCH */
72 #define PA3 0x08 /* PIO"A" timing */
73 #define PA2 0x04 /* PIO"A" timing */
74 #define PA1 0x02 /* PIO"A" timing */
75 #define PA0 0x01 /* PIO"A" timing */
79 #define MB2 0x80 /* DMA"B" timing */
80 #define MB1 0x40 /* DMA"B" timing */
81 #define MB0 0x20 /* DMA"B" timing */
83 #define PB4 0x10 /* PIO_FORCE 1:0 */
85 #define PB3 0x08 /* PIO"B" timing */ /* PIO flow Control mode */
86 #define PB2 0x04 /* PIO"B" timing */ /* PIO 4 */
87 #define PB1 0x02 /* PIO"B" timing */ /* PIO 3 half */
88 #define PB0 0x01 /* PIO"B" timing */ /* PIO 3 other half */
91 #define IORDYp_NO_SPEED 0x4F
92 #define SPEED_DIS 0x0F
99 #define MC3 0x08 /* DMA"C" timing */
100 #define MC2 0x04 /* DMA"C" timing */
101 #define MC1 0x02 /* DMA"C" timing */
102 #define MC0 0x01 /* DMA"C" timing */
105 unsigned long bibma = pci_resource_start(dev, 4);
108 u8 sc1c = inb_p((u16)bibma + 0x1c);
109 u8 sc1e = inb_p((u16)bibma + 0x1e);
110 u8 sc1f = inb_p((u16)bibma + 0x1f);
112 p += sprintf(p, "Host Mode : %s\n",
113 (sc1f & 0x08) ? "Tri-Stated" : "Normal");
114 p += sprintf(p, "Bus Clocking : %s\n",
115 ((sc1f & 0xC0) == 0xC0) ? "100 External" :
116 ((sc1f & 0x80) == 0x80) ? "66 External" :
117 ((sc1f & 0x40) == 0x40) ? "33 External" : "33 PCI Internal");
118 p += sprintf(p, "IO pad select : %s mA\n",
119 ((sc1c & 0x03) == 0x03) ? "10" :
120 ((sc1c & 0x02) == 0x02) ? "8" :
121 ((sc1c & 0x01) == 0x01) ? "6" :
122 ((sc1c & 0x00) == 0x00) ? "4" : "??");
125 p += sprintf(p, "Status Polling Period : %d\n", hi);
126 p += sprintf(p, "Interrupt Check Status Polling Delay : %d\n", lo);
129 static u8 pdc202xx_ratemask (ide_drive_t *drive)
133 switch(HWIF(drive)->pci_dev->device) {
134 case PCI_DEVICE_ID_PROMISE_20267:
135 case PCI_DEVICE_ID_PROMISE_20265:
138 case PCI_DEVICE_ID_PROMISE_20263:
139 case PCI_DEVICE_ID_PROMISE_20262:
142 case PCI_DEVICE_ID_PROMISE_20246:
147 if (!eighty_ninty_three(drive))
148 mode = min(mode, (u8)1);
152 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
154 struct hd_driveid *id = drive->id;
156 if (pdc_quirk_drives == list) {
158 if (strstr(id->model, *list++)) {
164 if (!strcmp(*list++,id->model)) {
172 static int pdc202xx_tune_chipset (ide_drive_t *drive, u8 xferspeed)
174 ide_hwif_t *hwif = HWIF(drive);
175 struct pci_dev *dev = hwif->pci_dev;
176 u8 drive_pci = 0x60 + (drive->dn << 2);
177 u8 speed = ide_rate_filter(pdc202xx_ratemask(drive), xferspeed);
181 u8 TA = 0, TB = 0, TC = 0;
183 if ((drive->media != ide_disk) && (speed < XFER_SW_DMA_0))
186 pci_read_config_dword(dev, drive_pci, &drive_conf);
187 pci_read_config_byte(dev, (drive_pci), &AP);
188 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
189 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
190 pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
192 if (speed < XFER_SW_DMA_0) {
193 if ((AP & 0x0F) || (BP & 0x07)) {
194 /* clear PIO modes of lower 8421 bits of A Register */
195 pci_write_config_byte(dev, (drive_pci), AP &~0x0F);
196 pci_read_config_byte(dev, (drive_pci), &AP);
198 /* clear PIO modes of lower 421 bits of B Register */
199 pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0x07);
200 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
202 pci_read_config_byte(dev, (drive_pci), &AP);
203 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
206 if ((BP & 0xF0) && (CP & 0x0F)) {
207 /* clear DMA modes of upper 842 bits of B Register */
208 /* clear PIO forced mode upper 1 bit of B Register */
209 pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0xF0);
210 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
212 /* clear DMA modes of lower 8421 bits of C Register */
213 pci_write_config_byte(dev, (drive_pci)|0x02, CP &~0x0F);
214 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
218 pci_read_config_byte(dev, (drive_pci), &AP);
219 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
220 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
223 case XFER_UDMA_6: speed = XFER_UDMA_5;
225 case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
226 case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
228 case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
230 case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
231 case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
233 case XFER_SW_DMA_2: TB = 0x60; TC = 0x05; break;
234 case XFER_SW_DMA_1: TB = 0x80; TC = 0x06; break;
235 case XFER_SW_DMA_0: TB = 0xC0; TC = 0x0B; break;
236 case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
237 case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
238 case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
239 case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
241 default: TA = 0x09; TB = 0x13; break;
244 if (speed < XFER_SW_DMA_0) {
245 pci_write_config_byte(dev, (drive_pci), AP|TA);
246 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
248 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
249 pci_write_config_byte(dev, (drive_pci)|0x02, CP|TC);
252 #if PDC202XX_DEBUG_DRIVE_INFO
253 printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
254 drive->name, ide_xfer_verbose(speed),
255 drive->dn, drive_conf);
256 pci_read_config_dword(dev, drive_pci, &drive_conf);
257 printk("0x%08x\n", drive_conf);
258 #endif /* PDC202XX_DEBUG_DRIVE_INFO */
260 return (ide_config_drive_speed(drive, speed));
265 * 960, 480, 390, 300, 240, 180, 120, 90, 60
266 * 180, 150, 120, 90, 60
268 * 180, 120, 90, 90, 90, 60, 30
269 * 11, 5, 4, 3, 2, 1, 0
271 static void config_chipset_for_pio (ide_drive_t *drive, u8 pio)
275 if (pio == 5) pio = 4;
276 speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, pio, NULL);
278 pdc202xx_tune_chipset(drive, speed);
281 static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
283 u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
284 pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
285 return (CIS & mask) ? 1 : 0;
289 * Set the control register to use the 66MHz system
290 * clock for UDMA 3/4/5 mode operation when necessary.
292 * It may also be possible to leave the 66MHz clock on
293 * and readjust the timing parameters.
295 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
297 unsigned long clock_reg = hwif->dma_master + 0x11;
298 u8 clock = hwif->INB(clock_reg);
300 hwif->OUTB(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
303 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
305 unsigned long clock_reg = hwif->dma_master + 0x11;
306 u8 clock = hwif->INB(clock_reg);
308 hwif->OUTB(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
311 static int config_chipset_for_dma (ide_drive_t *drive)
313 struct hd_driveid *id = drive->id;
314 ide_hwif_t *hwif = HWIF(drive);
315 struct pci_dev *dev = hwif->pci_dev;
317 u8 drive_pci = 0x60 + (drive->dn << 2);
318 u8 test1 = 0, test2 = 0, speed = -1;
319 u8 AP = 0, cable = 0;
321 u8 ultra_66 = ((id->dma_ultra & 0x0010) ||
322 (id->dma_ultra & 0x0008)) ? 1 : 0;
324 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
325 cable = pdc202xx_old_cable_detect(hwif);
329 if (ultra_66 && cable) {
330 printk(KERN_WARNING "Warning: %s channel requires an 80-pin cable for operation.\n", hwif->channel ? "Secondary":"Primary");
331 printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
334 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
335 pdc_old_disable_66MHz_clock(drive->hwif);
337 drive_pci = 0x60 + (drive->dn << 2);
338 pci_read_config_dword(dev, drive_pci, &drive_conf);
339 if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
342 pci_read_config_byte(dev, drive_pci, &test1);
343 if (!(test1 & SYNC_ERRDY_EN)) {
344 if (drive->select.b.unit & 0x01) {
345 pci_read_config_byte(dev, drive_pci - 4, &test2);
346 if ((test2 & SYNC_ERRDY_EN) &&
347 !(test1 & SYNC_ERRDY_EN)) {
348 pci_write_config_byte(dev, drive_pci,
349 test1|SYNC_ERRDY_EN);
352 pci_write_config_byte(dev, drive_pci,
353 test1|SYNC_ERRDY_EN);
359 if (drive->media == ide_disk) {
360 pci_read_config_byte(dev, (drive_pci), &AP);
361 if (id->capability & 4) /* IORDY_EN */
362 pci_write_config_byte(dev, (drive_pci), AP|IORDY_EN);
363 pci_read_config_byte(dev, (drive_pci), &AP);
364 if (drive->media == ide_disk) /* PREFETCH_EN */
365 pci_write_config_byte(dev, (drive_pci), AP|PREFETCH_EN);
368 speed = ide_dma_speed(drive, pdc202xx_ratemask(drive));
371 /* restore original pci-config space */
372 pci_write_config_dword(dev, drive_pci, drive_conf);
376 (void) hwif->speedproc(drive, speed);
377 return ide_dma_enable(drive);
380 static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
382 ide_hwif_t *hwif = HWIF(drive);
383 struct hd_driveid *id = drive->id;
385 drive->init_speed = 0;
387 if (id && (id->capability & 1) && drive->autodma) {
389 if (ide_use_dma(drive)) {
390 if (config_chipset_for_dma(drive))
391 return hwif->ide_dma_on(drive);
396 } else if ((id->capability & 8) || (id->field_valid & 2)) {
398 hwif->tuneproc(drive, 5);
399 return hwif->ide_dma_off_quietly(drive);
401 /* IORDY not supported */
405 static int pdc202xx_quirkproc (ide_drive_t *drive)
407 return ((int) check_in_drive_lists(drive, pdc_quirk_drives));
410 static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
412 if (drive->current_speed > XFER_UDMA_2)
413 pdc_old_enable_66MHz_clock(drive->hwif);
414 if (drive->addressing == 1) {
415 struct request *rq = HWGROUP(drive)->rq;
416 ide_hwif_t *hwif = HWIF(drive);
417 // struct pci_dev *dev = hwif->pci_dev;
418 // unsgned long high_16 = pci_resource_start(dev, 4);
419 unsigned long high_16 = hwif->dma_master;
420 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
422 u8 clock = hwif->INB(high_16 + 0x11);
424 hwif->OUTB(clock|(hwif->channel ? 0x08 : 0x02), high_16+0x11);
425 word_count = (rq->nr_sectors << 8);
426 word_count = (rq_data_dir(rq) == READ) ?
427 word_count | 0x05000000 :
428 word_count | 0x06000000;
429 hwif->OUTL(word_count, atapi_reg);
431 ide_dma_start(drive);
434 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
436 if (drive->addressing == 1) {
437 ide_hwif_t *hwif = HWIF(drive);
438 // unsigned long high_16 = pci_resource_start(hwif->pci_dev, 4);
439 unsigned long high_16 = hwif->dma_master;
440 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
443 hwif->OUTL(0, atapi_reg); /* zero out extra */
444 clock = hwif->INB(high_16 + 0x11);
445 hwif->OUTB(clock & ~(hwif->channel ? 0x08:0x02), high_16+0x11);
447 if (drive->current_speed > XFER_UDMA_2)
448 pdc_old_disable_66MHz_clock(drive->hwif);
449 return __ide_dma_end(drive);
452 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
454 ide_hwif_t *hwif = HWIF(drive);
455 // struct pci_dev *dev = hwif->pci_dev;
456 // unsigned long high_16 = pci_resource_start(dev, 4);
457 unsigned long high_16 = hwif->dma_master;
458 u8 dma_stat = hwif->INB(hwif->dma_status);
459 u8 sc1d = hwif->INB((high_16 + 0x001d));
462 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
463 if ((sc1d & 0x50) == 0x50)
465 else if ((sc1d & 0x40) == 0x40)
466 return (dma_stat & 4) == 4;
468 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
469 if ((sc1d & 0x05) == 0x05)
471 else if ((sc1d & 0x04) == 0x04)
472 return (dma_stat & 4) == 4;
475 return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
478 static int pdc202xx_ide_dma_lostirq(ide_drive_t *drive)
480 if (HWIF(drive)->resetproc != NULL)
481 HWIF(drive)->resetproc(drive);
482 return __ide_dma_lostirq(drive);
485 static int pdc202xx_ide_dma_timeout(ide_drive_t *drive)
487 if (HWIF(drive)->resetproc != NULL)
488 HWIF(drive)->resetproc(drive);
489 return __ide_dma_timeout(drive);
492 static void pdc202xx_reset_host (ide_hwif_t *hwif)
494 #ifdef CONFIG_BLK_DEV_IDEDMA
495 // unsigned long high_16 = hwif->dma_base - (8*(hwif->channel));
496 unsigned long high_16 = hwif->dma_master;
497 #else /* !CONFIG_BLK_DEV_IDEDMA */
498 unsigned long high_16 = pci_resource_start(hwif->pci_dev, 4);
499 #endif /* CONFIG_BLK_DEV_IDEDMA */
500 u8 udma_speed_flag = hwif->INB(high_16|0x001f);
502 hwif->OUTB((udma_speed_flag | 0x10), (high_16|0x001f));
504 hwif->OUTB((udma_speed_flag & ~0x10), (high_16|0x001f));
505 mdelay(2000); /* 2 seconds ?! */
507 printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
508 hwif->channel ? "Secondary" : "Primary");
511 static void pdc202xx_reset (ide_drive_t *drive)
513 ide_hwif_t *hwif = HWIF(drive);
514 ide_hwif_t *mate = hwif->mate;
516 pdc202xx_reset_host(hwif);
517 pdc202xx_reset_host(mate);
520 * FIXME: Have to kick all the drives again :-/
521 * What a pain in the ACE!
525 for (hunit = 0; hunit < MAX_DRIVES; ++hunit) {
526 ide_drive_t *hdrive = &hwif->drives[hunit];
527 if (hdrive->present) {
528 if (hwif->ide_dma_check)
529 hwif->ide_dma_check(hdrive);
531 hwif->tuneproc(hdrive, 5);
537 for (munit = 0; munit < MAX_DRIVES; ++munit) {
538 ide_drive_t *mdrive = &mate->drives[munit];
539 if (mdrive->present) {
540 if (mate->ide_dma_check)
541 mate->ide_dma_check(mdrive);
543 mate->tuneproc(mdrive, 5);
548 hwif->tuneproc(drive, 5);
552 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev, const char *name)
554 if (dev->resource[PCI_ROM_RESOURCE].start) {
555 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
556 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
557 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n",
558 name, dev->resource[PCI_ROM_RESOURCE].start);
562 * software reset - this is required because the bios
563 * will set UDMA timing on if the hdd supports it. The
564 * user may want to turn udma off. A bug in the pdc20262
565 * is that it cannot handle a downgrade in timing from
566 * UDMA to DMA. Disk accesses after issuing a set
567 * feature command will result in errors. A software
568 * reset leaves the timing registers intact,
569 * but resets the drives.
572 if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
573 (dev->device == PCI_DEVICE_ID_PROMISE_20265) ||
574 (dev->device == PCI_DEVICE_ID_PROMISE_20263) ||
575 (dev->device == PCI_DEVICE_ID_PROMISE_20262)) {
576 unsigned long high_16 = pci_resource_start(dev, 4);
577 byte udma_speed_flag = inb(high_16 + 0x001f);
578 outb(udma_speed_flag | 0x10, high_16 + 0x001f);
580 outb(udma_speed_flag & ~0x10, high_16 + 0x001f);
581 mdelay(2000); /* 2 seconds ?! */
588 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
590 struct pci_dev *dev = hwif->pci_dev;
592 /* PDC20265 has problems with large LBA48 requests */
593 if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
594 (dev->device == PCI_DEVICE_ID_PROMISE_20265))
598 hwif->tuneproc = &config_chipset_for_pio;
599 hwif->quirkproc = &pdc202xx_quirkproc;
601 if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
602 hwif->resetproc = &pdc202xx_reset;
604 hwif->speedproc = &pdc202xx_tune_chipset;
606 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
608 hwif->ultra_mask = 0x3f;
609 hwif->mwdma_mask = 0x07;
610 hwif->swdma_mask = 0x07;
612 hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
613 hwif->ide_dma_lostirq = &pdc202xx_ide_dma_lostirq;
614 hwif->ide_dma_timeout = &pdc202xx_ide_dma_timeout;
616 if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
617 if (!(hwif->udma_four))
618 hwif->udma_four = (pdc202xx_old_cable_detect(hwif)) ? 0 : 1;
619 hwif->dma_start = &pdc202xx_old_ide_dma_start;
620 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
622 hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
626 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
627 #if PDC202_DEBUG_CABLE
628 printk(KERN_DEBUG "%s: %s-pin cable\n",
629 hwif->name, hwif->udma_four ? "80" : "40");
630 #endif /* PDC202_DEBUG_CABLE */
633 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
635 u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
638 ide_setup_dma(hwif, dmabase, 8);
642 udma_speed_flag = hwif->INB((dmabase|0x1f));
643 primary_mode = hwif->INB((dmabase|0x1a));
644 secondary_mode = hwif->INB((dmabase|0x1b));
645 printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
647 "Secondary %s Mode.\n", hwif->cds->name,
648 (udma_speed_flag & 1) ? "EN" : "DIS",
649 (primary_mode & 1) ? "MASTER" : "PCI",
650 (secondary_mode & 1) ? "MASTER" : "PCI" );
652 #ifdef CONFIG_PDC202XX_BURST
653 if (!(udma_speed_flag & 1)) {
654 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
655 hwif->cds->name, udma_speed_flag,
656 (udma_speed_flag|1));
657 hwif->OUTB(udma_speed_flag|1,(dmabase|0x1f));
659 (hwif->INB(dmabase|0x1f)&1) ? "":"IN");
661 #endif /* CONFIG_PDC202XX_BURST */
662 #ifdef CONFIG_PDC202XX_MASTER
663 if (!(primary_mode & 1)) {
664 printk(KERN_INFO "%s: FORCING PRIMARY MODE BIT "
665 "0x%02x -> 0x%02x ", hwif->cds->name,
666 primary_mode, (primary_mode|1));
667 hwif->OUTB(primary_mode|1, (dmabase|0x1a));
669 (hwif->INB((dmabase|0x1a)) & 1) ? "MASTER" : "PCI");
672 if (!(secondary_mode & 1)) {
673 printk(KERN_INFO "%s: FORCING SECONDARY MODE BIT "
674 "0x%02x -> 0x%02x ", hwif->cds->name,
675 secondary_mode, (secondary_mode|1));
676 hwif->OUTB(secondary_mode|1, (dmabase|0x1b));
678 (hwif->INB((dmabase|0x1b)) & 1) ? "MASTER" : "PCI");
680 #endif /* CONFIG_PDC202XX_MASTER */
682 ide_setup_dma(hwif, dmabase, 8);
685 static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
688 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
689 u8 irq = 0, irq2 = 0;
690 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
692 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
694 pci_write_config_byte(dev,
695 (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */
696 printk(KERN_INFO "%s: pci-config space interrupt "
697 "mirror fixed.\n", d->name);
702 if (dev->device == PCI_DEVICE_ID_PROMISE_20262)
703 if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) ||
704 (tmp & e->mask) != e->val))
706 if (d->enablebits[0].reg != d->enablebits[1].reg) {
707 d->enablebits[0].reg = d->enablebits[1].reg;
708 d->enablebits[0].mask = d->enablebits[1].mask;
709 d->enablebits[0].val = d->enablebits[1].val;
713 return ide_setup_pci_device(dev, d);
716 static int __devinit init_setup_pdc20265(struct pci_dev *dev,
719 if ((dev->bus->self) &&
720 (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
721 ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
722 (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
723 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
724 "attached to I2O RAID controller.\n");
732 if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) ||
733 (tmp & e->mask) != e->val))
735 if (d->enablebits[0].reg != d->enablebits[1].reg) {
736 d->enablebits[0].reg = d->enablebits[1].reg;
737 d->enablebits[0].mask = d->enablebits[1].mask;
738 d->enablebits[0].val = d->enablebits[1].val;
743 return ide_setup_pci_device(dev, d);
746 static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
749 return ide_setup_pci_device(dev, d);
752 static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
755 .init_setup = init_setup_pdc202ata4,
756 .init_chipset = init_chipset_pdc202xx,
757 .init_hwif = init_hwif_pdc202xx,
758 .init_dma = init_dma_pdc202xx,
761 .bootable = OFF_BOARD,
765 .init_setup = init_setup_pdc202ata4,
766 .init_chipset = init_chipset_pdc202xx,
767 .init_hwif = init_hwif_pdc202xx,
768 .init_dma = init_dma_pdc202xx,
771 .bootable = OFF_BOARD,
775 .init_setup = init_setup_pdc202ata4,
776 .init_chipset = init_chipset_pdc202xx,
777 .init_hwif = init_hwif_pdc202xx,
778 .init_dma = init_dma_pdc202xx,
781 .bootable = OFF_BOARD,
785 .init_setup = init_setup_pdc20265,
786 .init_chipset = init_chipset_pdc202xx,
787 .init_hwif = init_hwif_pdc202xx,
788 .init_dma = init_dma_pdc202xx,
791 .bootable = OFF_BOARD,
795 .init_setup = init_setup_pdc202xx,
796 .init_chipset = init_chipset_pdc202xx,
797 .init_hwif = init_hwif_pdc202xx,
798 .init_dma = init_dma_pdc202xx,
801 .bootable = OFF_BOARD,
807 * pdc202xx_init_one - called when a PDC202xx is found
808 * @dev: the pdc202xx device
809 * @id: the matching pci id
811 * Called when the PCI registration layer (or the IDE initialization)
812 * finds a device matching our IDE device tables.
815 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
817 ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
819 return d->init_setup(dev, d);
822 static struct pci_device_id pdc202xx_pci_tbl[] = {
823 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
824 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
825 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
826 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
827 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
830 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
832 static struct pci_driver driver = {
833 .name = "Promise_Old_IDE",
834 .id_table = pdc202xx_pci_tbl,
835 .probe = pdc202xx_init_one,
838 static int pdc202xx_ide_init(void)
840 return ide_pci_register_driver(&driver);
843 module_init(pdc202xx_ide_init);
845 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
846 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
847 MODULE_LICENSE("GPL");