err.no Git - linux-2.6/blob - drivers/ide/pci/pdc202xx_old.c

   1 /*
   2  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
   3  *  Copyright (C) 2006-2007             MontaVista Software, Inc.
   4  *  Copyright (C) 2007                  Bartlomiej Zolnierkiewicz
   5  *
   6  *  Portions Copyright (C) 1999 Promise Technology, Inc.
   7  *  Author: Frank Tiernan (frankt@promise.com)
   8  *  Released under terms of General Public License
   9  */
  10
  11 #include <linux/types.h>
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/delay.h>
  15 #include <linux/blkdev.h>
  16 #include <linux/hdreg.h>
  17 #include <linux/pci.h>
  18 #include <linux/init.h>
  19 #include <linux/ide.h>
  20
  21 #include <asm/io.h>
  22
  23 #define PDC202XX_DEBUG_DRIVE_INFO       0
  24
  25 static const char *pdc_quirk_drives[] = {
  26         "QUANTUM FIREBALLlct08 08",
  27         "QUANTUM FIREBALLP KA6.4",
  28         "QUANTUM FIREBALLP KA9.1",
  29         "QUANTUM FIREBALLP LM20.4",
  30         "QUANTUM FIREBALLP KX13.6",
  31         "QUANTUM FIREBALLP KX20.5",
  32         "QUANTUM FIREBALLP KX27.3",
  33         "QUANTUM FIREBALLP LM20.5",
  34         NULL
  35 };
  36
  37 static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
  38
  39 static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
  40 {
  41         ide_hwif_t *hwif        = HWIF(drive);
  42         struct pci_dev *dev     = to_pci_dev(hwif->dev);
  43         u8 drive_pci            = 0x60 + (drive->dn << 2);
  44
  45         u8                      AP = 0, BP = 0, CP = 0;
  46         u8                      TA = 0, TB = 0, TC = 0;
  47
  48 #if PDC202XX_DEBUG_DRIVE_INFO
  49         u32                     drive_conf = 0;
  50         pci_read_config_dword(dev, drive_pci, &drive_conf);
  51 #endif
  52
  53         /*
  54          * TODO: do this once per channel
  55          */
  56         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
  57                 pdc_old_disable_66MHz_clock(hwif);
  58
  59         pci_read_config_byte(dev, drive_pci,     &AP);
  60         pci_read_config_byte(dev, drive_pci + 1, &BP);
  61         pci_read_config_byte(dev, drive_pci + 2, &CP);
  62
  63         switch(speed) {
  64                 case XFER_UDMA_5:
  65                 case XFER_UDMA_4:       TB = 0x20; TC = 0x01; break;
  66                 case XFER_UDMA_2:       TB = 0x20; TC = 0x01; break;
  67                 case XFER_UDMA_3:
  68                 case XFER_UDMA_1:       TB = 0x40; TC = 0x02; break;
  69                 case XFER_UDMA_0:
  70                 case XFER_MW_DMA_2:     TB = 0x60; TC = 0x03; break;
  71                 case XFER_MW_DMA_1:     TB = 0x60; TC = 0x04; break;
  72                 case XFER_MW_DMA_0:     TB = 0xE0; TC = 0x0F; break;
  73                 case XFER_PIO_4:        TA = 0x01; TB = 0x04; break;
  74                 case XFER_PIO_3:        TA = 0x02; TB = 0x06; break;
  75                 case XFER_PIO_2:        TA = 0x03; TB = 0x08; break;
  76                 case XFER_PIO_1:        TA = 0x05; TB = 0x0C; break;
  77                 case XFER_PIO_0:
  78                 default:                TA = 0x09; TB = 0x13; break;
  79         }
  80
  81         if (speed < XFER_SW_DMA_0) {
  82                 /*
  83                  * preserve SYNC_INT / ERDDY_EN bits while clearing
  84                  * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
  85                  */
  86                 AP &= ~0x3f;
  87                 if (drive->id->capability & 4)
  88                         AP |= 0x20;     /* set IORDY_EN bit */
  89                 if (drive->media == ide_disk)
  90                         AP |= 0x10;     /* set Prefetch_EN bit */
  91                 /* clear PB[4:0] bits of register B */
  92                 BP &= ~0x1f;
  93                 pci_write_config_byte(dev, drive_pci,     AP | TA);
  94                 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
  95         } else {
  96                 /* clear MB[2:0] bits of register B */
  97                 BP &= ~0xe0;
  98                 /* clear MC[3:0] bits of register C */
  99                 CP &= ~0x0f;
 100                 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
 101                 pci_write_config_byte(dev, drive_pci + 2, CP | TC);
 102         }
 103
 104 #if PDC202XX_DEBUG_DRIVE_INFO
 105         printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
 106                 drive->name, ide_xfer_verbose(speed),
 107                 drive->dn, drive_conf);
 108         pci_read_config_dword(dev, drive_pci, &drive_conf);
 109         printk("0x%08x\n", drive_conf);
 110 #endif
 111 }
 112
 113 static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
 114 {
 115         pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
 116 }
 117
 118 static u8 __devinit pdc2026x_cable_detect(ide_hwif_t *hwif)
 119 {
 120         struct pci_dev *dev = to_pci_dev(hwif->dev);
 121         u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);
 122
 123         pci_read_config_word(dev, 0x50, &CIS);
 124
 125         return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
 126 }
 127
 128 /*
 129  * Set the control register to use the 66MHz system
 130  * clock for UDMA 3/4/5 mode operation when necessary.
 131  *
 132  * FIXME: this register is shared by both channels, some locking is needed
 133  *
 134  * It may also be possible to leave the 66MHz clock on
 135  * and readjust the timing parameters.
 136  */
 137 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
 138 {
 139         unsigned long clock_reg = hwif->extra_base + 0x01;
 140         u8 clock = inb(clock_reg);
 141
 142         outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
 143 }
 144
 145 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
 146 {
 147         unsigned long clock_reg = hwif->extra_base + 0x01;
 148         u8 clock = inb(clock_reg);
 149
 150         outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
 151 }
 152
 153 static void pdc202xx_quirkproc(ide_drive_t *drive)
 154 {
 155         const char **list, *model = drive->id->model;
 156
 157         for (list = pdc_quirk_drives; *list != NULL; list++)
 158                 if (strstr(model, *list) != NULL) {
 159                         drive->quirk_list = 2;
 160                         return;
 161                 }
 162
 163         drive->quirk_list = 0;
 164 }
 165
 166 static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
 167 {
 168         if (drive->current_speed > XFER_UDMA_2)
 169                 pdc_old_enable_66MHz_clock(drive->hwif);
 170         if (drive->media != ide_disk || drive->addressing == 1) {
 171                 struct request *rq      = HWGROUP(drive)->rq;
 172                 ide_hwif_t *hwif        = HWIF(drive);
 173                 unsigned long high_16   = hwif->extra_base - 16;
 174                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 175                 u32 word_count  = 0;
 176                 u8 clock = inb(high_16 + 0x11);
 177
 178                 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
 179                 word_count = (rq->nr_sectors << 8);
 180                 word_count = (rq_data_dir(rq) == READ) ?
 181                                         word_count | 0x05000000 :
 182                                         word_count | 0x06000000;
 183                 outl(word_count, atapi_reg);
 184         }
 185         ide_dma_start(drive);
 186 }
 187
 188 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
 189 {
 190         if (drive->media != ide_disk || drive->addressing == 1) {
 191                 ide_hwif_t *hwif        = HWIF(drive);
 192                 unsigned long high_16   = hwif->extra_base - 16;
 193                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 194                 u8 clock                = 0;
 195
 196                 outl(0, atapi_reg); /* zero out extra */
 197                 clock = inb(high_16 + 0x11);
 198                 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
 199         }
 200         if (drive->current_speed > XFER_UDMA_2)
 201                 pdc_old_disable_66MHz_clock(drive->hwif);
 202         return __ide_dma_end(drive);
 203 }
 204
 205 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
 206 {
 207         ide_hwif_t *hwif        = HWIF(drive);
 208         unsigned long high_16   = hwif->extra_base - 16;
 209         u8 dma_stat             = inb(hwif->dma_status);
 210         u8 sc1d                 = inb(high_16 + 0x001d);
 211
 212         if (hwif->channel) {
 213                 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
 214                 if ((sc1d & 0x50) == 0x50)
 215                         goto somebody_else;
 216                 else if ((sc1d & 0x40) == 0x40)
 217                         return (dma_stat & 4) == 4;
 218         } else {
 219                 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
 220                 if ((sc1d & 0x05) == 0x05)
 221                         goto somebody_else;
 222                 else if ((sc1d & 0x04) == 0x04)
 223                         return (dma_stat & 4) == 4;
 224         }
 225 somebody_else:
 226         return (dma_stat & 4) == 4;     /* return 1 if INTR asserted */
 227 }
 228
 229 static void pdc202xx_reset_host (ide_hwif_t *hwif)
 230 {
 231         unsigned long high_16   = hwif->extra_base - 16;
 232         u8 udma_speed_flag      = inb(high_16 | 0x001f);
 233
 234         outb(udma_speed_flag | 0x10, high_16 | 0x001f);
 235         mdelay(100);
 236         outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
 237         mdelay(2000);   /* 2 seconds ?! */
 238
 239         printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
 240                 hwif->channel ? "Secondary" : "Primary");
 241 }
 242
 243 static void pdc202xx_reset (ide_drive_t *drive)
 244 {
 245         ide_hwif_t *hwif        = HWIF(drive);
 246         ide_hwif_t *mate        = hwif->mate;
 247
 248         pdc202xx_reset_host(hwif);
 249         pdc202xx_reset_host(mate);
 250
 251         ide_set_max_pio(drive);
 252 }
 253
 254 static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
 255 {
 256         pdc202xx_reset(drive);
 257         ide_dma_lost_irq(drive);
 258 }
 259
 260 static void pdc202xx_dma_timeout(ide_drive_t *drive)
 261 {
 262         pdc202xx_reset(drive);
 263         ide_dma_timeout(drive);
 264 }
 265
 266 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
 267 {
 268         struct pci_dev *dev = to_pci_dev(hwif->dev);
 269
 270         if (hwif->dma_base == 0)
 271                 return;
 272
 273         hwif->dma_lost_irq = &pdc202xx_dma_lost_irq;
 274         hwif->dma_timeout = &pdc202xx_dma_timeout;
 275
 276         if (dev->device != PCI_DEVICE_ID_PROMISE_20246) {
 277                 hwif->dma_start = &pdc202xx_old_ide_dma_start;
 278                 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
 279         }
 280         hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
 281 }
 282
 283 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
 284                                                     const char *name)
 285 {
 286         unsigned long dmabase = pci_resource_start(dev, 4);
 287         u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
 288
 289         if (dmabase == 0)
 290                 goto out;
 291
 292         udma_speed_flag = inb(dmabase | 0x1f);
 293         primary_mode    = inb(dmabase | 0x1a);
 294         secondary_mode  = inb(dmabase | 0x1b);
 295         printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
 296                 "Primary %s Mode " \
 297                 "Secondary %s Mode.\n", pci_name(dev),
 298                 (udma_speed_flag & 1) ? "EN" : "DIS",
 299                 (primary_mode & 1) ? "MASTER" : "PCI",
 300                 (secondary_mode & 1) ? "MASTER" : "PCI" );
 301
 302         if (!(udma_speed_flag & 1)) {
 303                 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
 304                         pci_name(dev), udma_speed_flag,
 305                         (udma_speed_flag|1));
 306                 outb(udma_speed_flag | 1, dmabase | 0x1f);
 307                 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
 308         }
 309 out:
 310         return dev->irq;
 311 }
 312
 313 static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
 314                                            const char *name)
 315 {
 316         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
 317                 u8 irq = 0, irq2 = 0;
 318                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 319                 /* 0xbc */
 320                 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
 321                 if (irq != irq2) {
 322                         pci_write_config_byte(dev,
 323                                 (PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
 324                         printk(KERN_INFO "%s: PCI config space interrupt "
 325                                          "mirror fixed\n", name);
 326                 }
 327         }
 328 }
 329
 330 #define IDE_HFLAGS_PDC202XX \
 331         (IDE_HFLAG_ERROR_STOPS_FIFO | \
 332          IDE_HFLAG_ABUSE_SET_DMA_MODE | \
 333          IDE_HFLAG_OFF_BOARD)
 334
 335 static const struct ide_port_ops pdc20246_port_ops = {
 336         .set_pio_mode           = pdc202xx_set_pio_mode,
 337         .set_dma_mode           = pdc202xx_set_mode,
 338         .quirkproc              = pdc202xx_quirkproc,
 339 };
 340
 341 static const struct ide_port_ops pdc2026x_port_ops = {
 342         .set_pio_mode           = pdc202xx_set_pio_mode,
 343         .set_dma_mode           = pdc202xx_set_mode,
 344         .quirkproc              = pdc202xx_quirkproc,
 345         .resetproc              = pdc202xx_reset,
 346         .cable_detect           = pdc2026x_cable_detect,
 347 };
 348
 349 #define DECLARE_PDC2026X_DEV(name_str, udma, extra_flags) \
 350         { \
 351                 .name           = name_str, \
 352                 .init_chipset   = init_chipset_pdc202xx, \
 353                 .init_hwif      = init_hwif_pdc202xx, \
 354                 .port_ops       = &pdc2026x_port_ops, \
 355                 .host_flags     = IDE_HFLAGS_PDC202XX | extra_flags, \
 356                 .pio_mask       = ATA_PIO4, \
 357                 .mwdma_mask     = ATA_MWDMA2, \
 358                 .udma_mask      = udma, \
 359         }
 360
 361 static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
 362         {       /* 0 */
 363                 .name           = "PDC20246",
 364                 .init_chipset   = init_chipset_pdc202xx,
 365                 .init_hwif      = init_hwif_pdc202xx,
 366                 .port_ops       = &pdc20246_port_ops,
 367                 .host_flags     = IDE_HFLAGS_PDC202XX,
 368                 .pio_mask       = ATA_PIO4,
 369                 .mwdma_mask     = ATA_MWDMA2,
 370                 .udma_mask      = ATA_UDMA2,
 371         },
 372
 373         /* 1 */ DECLARE_PDC2026X_DEV("PDC20262", ATA_UDMA4, 0),
 374         /* 2 */ DECLARE_PDC2026X_DEV("PDC20263", ATA_UDMA4, 0),
 375         /* 3 */ DECLARE_PDC2026X_DEV("PDC20265", ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
 376         /* 4 */ DECLARE_PDC2026X_DEV("PDC20267", ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
 377 };
 378
 379 /**
 380  *      pdc202xx_init_one       -       called when a PDC202xx is found
 381  *      @dev: the pdc202xx device
 382  *      @id: the matching pci id
 383  *
 384  *      Called when the PCI registration layer (or the IDE initialization)
 385  *      finds a device matching our IDE device tables.
 386  */
 387
 388 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 389 {
 390         const struct ide_port_info *d;
 391         u8 idx = id->driver_data;
 392
 393         d = &pdc202xx_chipsets[idx];
 394
 395         if (idx < 3)
 396                 pdc202ata4_fixup_irq(dev, d->name);
 397
 398         if (idx == 3) {
 399                 struct pci_dev *bridge = dev->bus->self;
 400
 401                 if (bridge &&
 402                     bridge->vendor == PCI_VENDOR_ID_INTEL &&
 403                     (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
 404                      bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
 405                         printk(KERN_INFO "ide: Skipping Promise PDC20265 "
 406                                 "attached to I2O RAID controller\n");
 407                         return -ENODEV;
 408                 }
 409         }
 410
 411         return ide_setup_pci_device(dev, d);
 412 }
 413
 414 static const struct pci_device_id pdc202xx_pci_tbl[] = {
 415         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
 416         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
 417         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 2 },
 418         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 3 },
 419         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 4 },
 420         { 0, },
 421 };
 422 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
 423
 424 static struct pci_driver driver = {
 425         .name           = "Promise_Old_IDE",
 426         .id_table       = pdc202xx_pci_tbl,
 427         .probe          = pdc202xx_init_one,
 428 };
 429
 430 static int __init pdc202xx_ide_init(void)
 431 {
 432         return ide_pci_register_driver(&driver);
 433 }
 434
 435 module_init(pdc202xx_ide_init);
 436
 437 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
 438 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
 439 MODULE_LICENSE("GPL");