2 * Copyright (C) 2004 Red Hat <alan@redhat.com>
3 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
5 * May be copied or modified under the terms of the GNU General Public License
6 * Based in part on the ITE vendor provided SCSI driver.
8 * Documentation available from
9 * http://www.ite.com.tw/pc/IT8212F_V04.pdf
10 * Some other documents are NDA.
12 * The ITE8212 isn't exactly a standard IDE controller. It has two
13 * modes. In pass through mode then it is an IDE controller. In its smart
14 * mode its actually quite a capable hardware raid controller disguised
15 * as an IDE controller. Smart mode only understands DMA read/write and
16 * identify, none of the fancier commands apply. The IT8211 is identical
17 * in other respects but lacks the raid mode.
20 * o Rev 0x10 also requires master/slave hold the same DMA timings and
21 * cannot do ATAPI MWDMA.
22 * o The identify data for raid volumes lacks CHS info (technically ok)
23 * but also fails to set the LBA28 and other bits. We fix these in
24 * the IDE probe quirk code.
25 * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
26 * raid then the controller firmware dies
27 * o Smart mode without RAID doesn't clear all the necessary identify
28 * bits to reduce the command set to the one used
30 * This has a few impacts on the driver
31 * - In pass through mode we do all the work you would expect
32 * - In smart mode the clocking set up is done by the controller generally
33 * but we must watch the other limits and filter.
34 * - There are a few extra vendor commands that actually talk to the
35 * controller but only work PIO with no IRQ.
37 * Vendor areas of the identify block in smart mode are used for the
38 * timing and policy set up. Each HDD in raid mode also has a serial
39 * block on the disk. The hardware extra commands are get/set chip status,
40 * rebuild, get rebuild status.
42 * In Linux the driver supports pass through mode as if the device was
43 * just another IDE controller. If the smart mode is running then
44 * volumes are managed by the controller firmware and each IDE "disk"
45 * is a raid volume. Even more cute - the controller can do automated
46 * hotplug and rebuild.
48 * The pass through controller itself is a little demented. It has a
49 * flaw that it has a single set of PIO/MWDMA timings per channel so
50 * non UDMA devices restrict each others performance. It also has a
51 * single clock source per channel so mixed UDMA100/133 performance
52 * isn't perfect and we have to pick a clock. Thankfully none of this
53 * matters in smart mode. ATAPI DMA is not currently supported.
55 * It seems the smart mode is a win for RAID1/RAID10 but otherwise not.
58 * - ATAPI UDMA is ok but not MWDMA it seems
59 * - RAID configuration ioctls
60 * - Move to libata once it grows up
63 #include <linux/types.h>
64 #include <linux/module.h>
65 #include <linux/pci.h>
66 #include <linux/delay.h>
67 #include <linux/hdreg.h>
68 #include <linux/ide.h>
69 #include <linux/init.h>
75 unsigned int smart:1, /* Are we in smart raid mode */
76 timing10:1; /* Rev 0x10 */
77 u8 clock_mode; /* 0, ATA_50 or ATA_66 */
78 u8 want[2][2]; /* Mode/Pri log for master slave */
79 /* We need these for switching the clock when DMA goes on/off
80 The high byte is the 66Mhz timing */
81 u16 pio[2]; /* Cached PIO values */
82 u16 mwdma[2]; /* Cached MWDMA values */
83 u16 udma[2]; /* Cached UDMA values (per drive) */
94 * We allow users to force the card into non raid mode without
95 * flashing the alternative BIOS. This is also necessary right now
96 * for embedded platforms that cannot run a PC BIOS but are using this
100 static int it8212_noraid;
103 * it821x_program - program the PIO/MWDMA registers
104 * @drive: drive to tune
105 * @timing: timing info
107 * Program the PIO/MWDMA timing for this channel according to the
111 static void it821x_program(ide_drive_t *drive, u16 timing)
113 ide_hwif_t *hwif = drive->hwif;
114 struct pci_dev *dev = to_pci_dev(hwif->dev);
115 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
116 int channel = hwif->channel;
119 /* Program PIO/MWDMA timing bits */
120 if(itdev->clock_mode == ATA_66)
123 conf = timing & 0xFF;
125 pci_write_config_byte(dev, 0x54 + 4 * channel, conf);
129 * it821x_program_udma - program the UDMA registers
130 * @drive: drive to tune
131 * @timing: timing info
133 * Program the UDMA timing for this drive according to the
137 static void it821x_program_udma(ide_drive_t *drive, u16 timing)
139 ide_hwif_t *hwif = drive->hwif;
140 struct pci_dev *dev = to_pci_dev(hwif->dev);
141 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
142 int channel = hwif->channel;
143 int unit = drive->select.b.unit;
146 /* Program UDMA timing bits */
147 if(itdev->clock_mode == ATA_66)
150 conf = timing & 0xFF;
152 if (itdev->timing10 == 0)
153 pci_write_config_byte(dev, 0x56 + 4 * channel + unit, conf);
155 pci_write_config_byte(dev, 0x56 + 4 * channel, conf);
156 pci_write_config_byte(dev, 0x56 + 4 * channel + 1, conf);
161 * it821x_clock_strategy
162 * @drive: drive to set up
164 * Select between the 50 and 66Mhz base clocks to get the best
165 * results for this interface.
168 static void it821x_clock_strategy(ide_drive_t *drive)
170 ide_hwif_t *hwif = drive->hwif;
171 struct pci_dev *dev = to_pci_dev(hwif->dev);
172 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
174 u8 unit = drive->select.b.unit;
175 ide_drive_t *pair = &hwif->drives[1-unit];
181 if(itdev->want[0][0] > itdev->want[1][0]) {
182 clock = itdev->want[0][1];
183 altclock = itdev->want[1][1];
185 clock = itdev->want[1][1];
186 altclock = itdev->want[0][1];
190 * if both clocks can be used for the mode with the higher priority
191 * use the clock needed by the mode with the lower priority
193 if (clock == ATA_ANY)
196 /* Nobody cares - keep the same clock */
200 if(clock == itdev->clock_mode)
203 /* Load this into the controller ? */
205 itdev->clock_mode = ATA_66;
207 itdev->clock_mode = ATA_50;
211 pci_read_config_byte(dev, 0x50, &v);
212 v &= ~(1 << (1 + hwif->channel));
213 v |= sel << (1 + hwif->channel);
214 pci_write_config_byte(dev, 0x50, v);
217 * Reprogram the UDMA/PIO of the pair drive for the switch
218 * MWDMA will be dealt with by the dma switcher
220 if(pair && itdev->udma[1-unit] != UDMA_OFF) {
221 it821x_program_udma(pair, itdev->udma[1-unit]);
222 it821x_program(pair, itdev->pio[1-unit]);
225 * Reprogram the UDMA/PIO of our drive for the switch.
226 * MWDMA will be dealt with by the dma switcher
228 if(itdev->udma[unit] != UDMA_OFF) {
229 it821x_program_udma(drive, itdev->udma[unit]);
230 it821x_program(drive, itdev->pio[unit]);
235 * it821x_set_pio_mode - set host controller for PIO mode
237 * @pio: PIO mode number
239 * Tune the host to the desired PIO mode taking into the consideration
240 * the maximum PIO mode supported by the other device on the cable.
243 static void it821x_set_pio_mode(ide_drive_t *drive, const u8 pio)
245 ide_hwif_t *hwif = drive->hwif;
246 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
247 int unit = drive->select.b.unit;
248 ide_drive_t *pair = &hwif->drives[1 - unit];
251 /* Spec says 89 ref driver uses 88 */
252 static u16 pio_timings[]= { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 };
253 static u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY };
256 * Compute the best PIO mode we can for a given device. We must
257 * pick a speed that does not cause problems with the other device
261 u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4);
262 /* trim PIO to the slowest of the master/slave */
263 if (pair_pio < set_pio)
267 /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */
268 itdev->want[unit][1] = pio_want[set_pio];
269 itdev->want[unit][0] = 1; /* PIO is lowest priority */
270 itdev->pio[unit] = pio_timings[set_pio];
271 it821x_clock_strategy(drive);
272 it821x_program(drive, itdev->pio[unit]);
276 * it821x_tune_mwdma - tune a channel for MWDMA
277 * @drive: drive to set up
278 * @mode_wanted: the target operating mode
280 * Load the timing settings for this device mode into the
281 * controller when doing MWDMA in pass through mode. The caller
282 * must manage the whole lack of per device MWDMA/PIO timings and
283 * the shared MWDMA/PIO timing register.
286 static void it821x_tune_mwdma (ide_drive_t *drive, byte mode_wanted)
288 ide_hwif_t *hwif = drive->hwif;
289 struct pci_dev *dev = to_pci_dev(hwif->dev);
290 struct it821x_dev *itdev = (void *)ide_get_hwifdata(hwif);
291 int unit = drive->select.b.unit;
292 int channel = hwif->channel;
295 static u16 dma[] = { 0x8866, 0x3222, 0x3121 };
296 static u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY };
298 itdev->want[unit][1] = mwdma_want[mode_wanted];
299 itdev->want[unit][0] = 2; /* MWDMA is low priority */
300 itdev->mwdma[unit] = dma[mode_wanted];
301 itdev->udma[unit] = UDMA_OFF;
303 /* UDMA bits off - Revision 0x10 do them in pairs */
304 pci_read_config_byte(dev, 0x50, &conf);
306 conf |= channel ? 0x60: 0x18;
308 conf |= 1 << (3 + 2 * channel + unit);
309 pci_write_config_byte(dev, 0x50, conf);
311 it821x_clock_strategy(drive);
312 /* FIXME: do we need to program this ? */
313 /* it821x_program(drive, itdev->mwdma[unit]); */
317 * it821x_tune_udma - tune a channel for UDMA
318 * @drive: drive to set up
319 * @mode_wanted: the target operating mode
321 * Load the timing settings for this device mode into the
322 * controller when doing UDMA modes in pass through.
325 static void it821x_tune_udma (ide_drive_t *drive, byte mode_wanted)
327 ide_hwif_t *hwif = drive->hwif;
328 struct pci_dev *dev = to_pci_dev(hwif->dev);
329 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
330 int unit = drive->select.b.unit;
331 int channel = hwif->channel;
334 static u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 };
335 static u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 };
337 itdev->want[unit][1] = udma_want[mode_wanted];
338 itdev->want[unit][0] = 3; /* UDMA is high priority */
339 itdev->mwdma[unit] = MWDMA_OFF;
340 itdev->udma[unit] = udma[mode_wanted];
342 itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */
344 /* UDMA on. Again revision 0x10 must do the pair */
345 pci_read_config_byte(dev, 0x50, &conf);
347 conf &= channel ? 0x9F: 0xE7;
349 conf &= ~ (1 << (3 + 2 * channel + unit));
350 pci_write_config_byte(dev, 0x50, conf);
352 it821x_clock_strategy(drive);
353 it821x_program_udma(drive, itdev->udma[unit]);
358 * it821x_dma_read - DMA hook
359 * @drive: drive for DMA
361 * The IT821x has a single timing register for MWDMA and for PIO
362 * operations. As we flip back and forth we have to reload the
363 * clock. In addition the rev 0x10 device only works if the same
364 * timing value is loaded into the master and slave UDMA clock
365 * so we must also reload that.
367 * FIXME: we could figure out in advance if we need to do reloads
370 static void it821x_dma_start(ide_drive_t *drive)
372 ide_hwif_t *hwif = drive->hwif;
373 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
374 int unit = drive->select.b.unit;
375 if(itdev->mwdma[unit] != MWDMA_OFF)
376 it821x_program(drive, itdev->mwdma[unit]);
377 else if(itdev->udma[unit] != UDMA_OFF && itdev->timing10)
378 it821x_program_udma(drive, itdev->udma[unit]);
379 ide_dma_start(drive);
383 * it821x_dma_write - DMA hook
384 * @drive: drive for DMA stop
386 * The IT821x has a single timing register for MWDMA and for PIO
387 * operations. As we flip back and forth we have to reload the
391 static int it821x_dma_end(ide_drive_t *drive)
393 ide_hwif_t *hwif = drive->hwif;
394 int unit = drive->select.b.unit;
395 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
396 int ret = __ide_dma_end(drive);
397 if(itdev->mwdma[unit] != MWDMA_OFF)
398 it821x_program(drive, itdev->pio[unit]);
403 * it821x_set_dma_mode - set host controller for DMA mode
407 * Tune the ITE chipset for the desired DMA mode.
410 static void it821x_set_dma_mode(ide_drive_t *drive, const u8 speed)
413 * MWDMA tuning is really hard because our MWDMA and PIO
414 * timings are kept in the same place. We can switch in the
415 * host dma on/off callbacks.
417 if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_6)
418 it821x_tune_udma(drive, speed - XFER_UDMA_0);
419 else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
420 it821x_tune_mwdma(drive, speed - XFER_MW_DMA_0);
424 * ata66_it821x - check for 80 pin cable
425 * @hwif: interface to check
427 * Check for the presence of an ATA66 capable cable on the
428 * interface. Problematic as it seems some cards don't have
429 * the needed logic onboard.
432 static u8 __devinit ata66_it821x(ide_hwif_t *hwif)
434 /* The reference driver also only does disk side */
435 return ATA_CBL_PATA80;
439 * it821x_quirkproc - post init callback
442 * This callback is run after the drive has been probed but
443 * before anything gets attached. It allows drivers to do any
444 * final tuning that is needed, or fixups to work around bugs.
447 static void __devinit it821x_quirkproc(ide_drive_t *drive)
449 struct it821x_dev *itdev = ide_get_hwifdata(drive->hwif);
450 struct hd_driveid *id = drive->id;
451 u16 *idbits = (u16 *)drive->id;
455 * If we are in pass through mode then not much
456 * needs to be done, but we do bother to clear the
457 * IRQ mask as we may well be in PIO (eg rev 0x10)
458 * for now and we know unmasking is safe on this chipset.
463 * Perform fixups on smart mode. We need to "lose" some
464 * capabilities the firmware lacks but does not filter, and
465 * also patch up some capability bits that it forgets to set
469 /* Check for RAID v native */
470 if(strstr(id->model, "Integrated Technology Express")) {
471 /* In raid mode the ident block is slightly buggy
472 We need to set the bits so that the IDE layer knows
473 LBA28. LBA48 and DMA ar valid */
474 id->capability |= 3; /* LBA28, DMA */
475 id->command_set_2 |= 0x0400; /* LBA48 valid */
476 id->cfs_enable_2 |= 0x0400; /* LBA48 on */
477 /* Reporting logic */
478 printk(KERN_INFO "%s: IT8212 %sRAID %d volume",
480 idbits[147] ? "Bootable ":"",
483 printk("(%dK stripe)", idbits[146]);
486 /* Non RAID volume. Fixups to stop the core code
487 doing unsupported things */
488 id->field_valid &= 3;
490 id->command_set_1 = 0;
491 id->command_set_2 &= 0xC400;
493 id->cfs_enable_1 = 0;
494 id->cfs_enable_2 &= 0xC400;
495 id->csf_default &= 0xC000;
500 printk(KERN_INFO "%s: Performing identify fixups.\n",
505 * Set MWDMA0 mode as enabled/support - just to tell
506 * IDE core that DMA is supported (it821x hardware
507 * takes care of DMA mode programming).
509 if (id->capability & 1) {
510 id->dma_mword |= 0x0101;
511 drive->current_speed = XFER_MW_DMA_0;
518 * init_hwif_it821x - set up hwif structs
519 * @hwif: interface to set up
521 * We do the basic set up of the interface structure. The IT8212
522 * requires several custom handlers so we override the default
523 * ide DMA handlers appropriately
526 static void __devinit init_hwif_it821x(ide_hwif_t *hwif)
528 struct pci_dev *dev = to_pci_dev(hwif->dev);
529 struct it821x_dev *idev = kzalloc(sizeof(struct it821x_dev), GFP_KERNEL);
532 hwif->quirkproc = &it821x_quirkproc;
535 printk(KERN_ERR "it821x: out of memory, falling back to legacy behaviour.\n");
539 ide_set_hwifdata(hwif, idev);
541 pci_read_config_byte(dev, 0x50, &conf);
544 hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
545 /* Long I/O's although allowed in LBA48 space cause the
546 onboard firmware to enter the twighlight zone */
550 /* Pull the current clocks from 0x50 also */
551 if (conf & (1 << (1 + hwif->channel)))
552 idev->clock_mode = ATA_50;
554 idev->clock_mode = ATA_66;
556 idev->want[0][1] = ATA_ANY;
557 idev->want[1][1] = ATA_ANY;
560 * Not in the docs but according to the reference driver
564 pci_read_config_byte(dev, 0x08, &conf);
567 hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
568 if (idev->smart == 0)
569 printk(KERN_WARNING "it821x: Revision 0x10, workarounds activated.\n");
572 if (idev->smart == 0) {
573 hwif->set_pio_mode = &it821x_set_pio_mode;
574 hwif->set_dma_mode = &it821x_set_dma_mode;
576 /* MWDMA/PIO clock switching for pass through mode */
577 hwif->dma_start = &it821x_dma_start;
578 hwif->ide_dma_end = &it821x_dma_end;
580 hwif->host_flags |= IDE_HFLAG_NO_SET_MODE;
582 if (hwif->dma_base == 0)
585 hwif->ultra_mask = ATA_UDMA6;
586 hwif->mwdma_mask = ATA_MWDMA2;
588 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
589 hwif->cbl = ata66_it821x(hwif);
592 static void __devinit it8212_disable_raid(struct pci_dev *dev)
594 /* Reset local CPU, and set BIOS not ready */
595 pci_write_config_byte(dev, 0x5E, 0x01);
597 /* Set to bypass mode, and reset PCI bus */
598 pci_write_config_byte(dev, 0x50, 0x00);
599 pci_write_config_word(dev, PCI_COMMAND,
600 PCI_COMMAND_PARITY | PCI_COMMAND_IO |
601 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
602 pci_write_config_word(dev, 0x40, 0xA0F3);
604 pci_write_config_dword(dev,0x4C, 0x02040204);
605 pci_write_config_byte(dev, 0x42, 0x36);
606 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
609 static unsigned int __devinit init_chipset_it821x(struct pci_dev *dev, const char *name)
612 static char *mode[2] = { "pass through", "smart" };
614 /* Force the card into bypass mode if so requested */
616 printk(KERN_INFO "it8212: forcing bypass mode.\n");
617 it8212_disable_raid(dev);
619 pci_read_config_byte(dev, 0x50, &conf);
620 printk(KERN_INFO "it821x: controller in %s mode.\n", mode[conf & 1]);
625 #define DECLARE_ITE_DEV(name_str) \
628 .init_chipset = init_chipset_it821x, \
629 .init_hwif = init_hwif_it821x, \
630 .host_flags = IDE_HFLAG_BOOTABLE, \
631 .pio_mask = ATA_PIO4, \
634 static const struct ide_port_info it821x_chipsets[] __devinitdata = {
635 /* 0 */ DECLARE_ITE_DEV("IT8212"),
639 * it821x_init_one - pci layer discovery entry
641 * @id: ident table entry
643 * Called by the PCI code when it finds an ITE821x controller.
644 * We then use the IDE PCI generic helper to do most of the work.
647 static int __devinit it821x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
649 return ide_setup_pci_device(dev, &it821x_chipsets[id->driver_data]);
652 static const struct pci_device_id it821x_pci_tbl[] = {
653 { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), 0 },
654 { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), 0 },
658 MODULE_DEVICE_TABLE(pci, it821x_pci_tbl);
660 static struct pci_driver driver = {
661 .name = "ITE821x IDE",
662 .id_table = it821x_pci_tbl,
663 .probe = it821x_init_one,
666 static int __init it821x_ide_init(void)
668 return ide_pci_register_driver(&driver);
671 module_init(it821x_ide_init);
673 module_param_named(noraid, it8212_noraid, int, S_IRUGO);
674 MODULE_PARM_DESC(it8212_noraid, "Force card into bypass mode");
676 MODULE_AUTHOR("Alan Cox");
677 MODULE_DESCRIPTION("PCI driver module for the ITE 821x");
678 MODULE_LICENSE("GPL");