err.no Git - linux-2.6/blob - drivers/ide/pci/hpt366.c

   1 /*
   2  * linux/drivers/ide/pci/hpt366.c               Version 0.36    April 25, 2003
   3  *
   4  * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
   5  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
   6  * Portions Copyright (C) 2003          Red Hat Inc
   7  * Portions Copyright (C) 2005-2006     MontaVista Software, Inc.
   8  *
   9  * Thanks to HighPoint Technologies for their assistance, and hardware.
  10  * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
  11  * donation of an ABit BP6 mainboard, processor, and memory acellerated
  12  * development and support.
  13  *
  14  *
  15  * HighPoint has its own drivers (open source except for the RAID part)
  16  * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
  17  * This may be useful to anyone wanting to work on this driver, however  do not
  18  * trust  them too much since the code tends to become less and less meaningful
  19  * as the time passes... :-/
  20  *
  21  * Note that final HPT370 support was done by force extraction of GPL.
  22  *
  23  * - add function for getting/setting power status of drive
  24  * - the HPT370's state machine can get confused. reset it before each dma
  25  *   xfer to prevent that from happening.
  26  * - reset state engine whenever we get an error.
  27  * - check for busmaster state at end of dma.
  28  * - use new highpoint timings.
  29  * - detect bus speed using highpoint register.
  30  * - use pll if we don't have a clock table. added a 66MHz table that's
  31  *   just 2x the 33MHz table.
  32  * - removed turnaround. NOTE: we never want to switch between pll and
  33  *   pci clocks as the chip can glitch in those cases. the highpoint
  34  *   approved workaround slows everything down too much to be useful. in
  35  *   addition, we would have to serialize access to each chip.
  36  *      Adrian Sun <a.sun@sun.com>
  37  *
  38  * add drive timings for 66MHz PCI bus,
  39  * fix ATA Cable signal detection, fix incorrect /proc info
  40  * add /proc display for per-drive PIO/DMA/UDMA mode and
  41  * per-channel ATA-33/66 Cable detect.
  42  *      Duncan Laurie <void@sun.com>
  43  *
  44  * fixup /proc output for multiple controllers
  45  *      Tim Hockin <thockin@sun.com>
  46  *
  47  * On hpt366:
  48  * Reset the hpt366 on error, reset on dma
  49  * Fix disabling Fast Interrupt hpt366.
  50  *      Mike Waychison <crlf@sun.com>
  51  *
  52  * Added support for 372N clocking and clock switching. The 372N needs
  53  * different clocks on read/write. This requires overloading rw_disk and
  54  * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
  55  * keeping me sane.
  56  *              Alan Cox <alan@redhat.com>
  57  *
  58  * - fix the clock turnaround code: it was writing to the wrong ports when
  59  *   called for the secondary channel, caching the current clock mode per-
  60  *   channel caused the cached register value to get out of sync with the
  61  *   actual one, the channels weren't serialized, the turnaround shouldn't
  62  *   be done on 66 MHz PCI bus
  63  * - avoid calibrating PLL twice as the second time results in a wrong PCI
  64  *   frequency and thus in the wrong timings for the secondary channel
  65  * - disable UltraATA/133 for HPT372 by default (50 MHz DPLL clock do not
  66  *   allow for this speed anyway)
  67  * - add support for HPT302N and HPT371N clocking (the same as for HPT372N)
  68  * - HPT371/N are single channel chips, so avoid touching the primary channel
  69  *   which exists only virtually (there's no pins for it)
  70  *              <source@mvista.com>
  71  *
  72  */
  73
  74
  75 #include <linux/types.h>
  76 #include <linux/module.h>
  77 #include <linux/kernel.h>
  78 #include <linux/delay.h>
  79 #include <linux/timer.h>
  80 #include <linux/mm.h>
  81 #include <linux/ioport.h>
  82 #include <linux/blkdev.h>
  83 #include <linux/hdreg.h>
  84
  85 #include <linux/interrupt.h>
  86 #include <linux/pci.h>
  87 #include <linux/init.h>
  88 #include <linux/ide.h>
  89
  90 #include <asm/uaccess.h>
  91 #include <asm/io.h>
  92 #include <asm/irq.h>
  93
  94 /* various tuning parameters */
  95 #define HPT_RESET_STATE_ENGINE
  96 #undef  HPT_DELAY_INTERRUPT
  97 #define HPT_SERIALIZE_IO        0
  98
  99 static const char *quirk_drives[] = {
 100         "QUANTUM FIREBALLlct08 08",
 101         "QUANTUM FIREBALLP KA6.4",
 102         "QUANTUM FIREBALLP LM20.4",
 103         "QUANTUM FIREBALLP LM20.5",
 104         NULL
 105 };
 106
 107 static const char *bad_ata100_5[] = {
 108         "IBM-DTLA-307075",
 109         "IBM-DTLA-307060",
 110         "IBM-DTLA-307045",
 111         "IBM-DTLA-307030",
 112         "IBM-DTLA-307020",
 113         "IBM-DTLA-307015",
 114         "IBM-DTLA-305040",
 115         "IBM-DTLA-305030",
 116         "IBM-DTLA-305020",
 117         "IC35L010AVER07-0",
 118         "IC35L020AVER07-0",
 119         "IC35L030AVER07-0",
 120         "IC35L040AVER07-0",
 121         "IC35L060AVER07-0",
 122         "WDC AC310200R",
 123         NULL
 124 };
 125
 126 static const char *bad_ata66_4[] = {
 127         "IBM-DTLA-307075",
 128         "IBM-DTLA-307060",
 129         "IBM-DTLA-307045",
 130         "IBM-DTLA-307030",
 131         "IBM-DTLA-307020",
 132         "IBM-DTLA-307015",
 133         "IBM-DTLA-305040",
 134         "IBM-DTLA-305030",
 135         "IBM-DTLA-305020",
 136         "IC35L010AVER07-0",
 137         "IC35L020AVER07-0",
 138         "IC35L030AVER07-0",
 139         "IC35L040AVER07-0",
 140         "IC35L060AVER07-0",
 141         "WDC AC310200R",
 142         NULL
 143 };
 144
 145 static const char *bad_ata66_3[] = {
 146         "WDC AC310200R",
 147         NULL
 148 };
 149
 150 static const char *bad_ata33[] = {
 151         "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
 152         "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
 153         "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
 154         "Maxtor 90510D4",
 155         "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
 156         "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
 157         "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
 158         NULL
 159 };
 160
 161 struct chipset_bus_clock_list_entry {
 162         u8              xfer_speed;
 163         unsigned int    chipset_settings;
 164 };
 165
 166 /* key for bus clock timings
 167  * bit
 168  * 0:3    data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
 169  *        DMA. cycles = value + 1
 170  * 4:8    data_low_time. active time of DIOW_/DIOR_ for PIO and MW
 171  *        DMA. cycles = value + 1
 172  * 9:12   cmd_high_time. inactive time of DIOW_/DIOR_ during task file
 173  *        register access.
 174  * 13:17  cmd_low_time. active time of DIOW_/DIOR_ during task file
 175  *        register access.
 176  * 18:21  udma_cycle_time. clock freq and clock cycles for UDMA xfer.
 177  *        during task file register access.
 178  * 22:24  pre_high_time. time to initialize 1st cycle for PIO and MW DMA
 179  *        xfer.
 180  * 25:27  cmd_pre_high_time. time to initialize 1st PIO cycle for task
 181  *        register access.
 182  * 28     UDMA enable
 183  * 29     DMA enable
 184  * 30     PIO_MST enable. if set, the chip is in bus master mode during
 185  *        PIO.
 186  * 31     FIFO enable.
 187  */
 188 static struct chipset_bus_clock_list_entry forty_base_hpt366[] = {
 189         {       XFER_UDMA_4,    0x900fd943      },
 190         {       XFER_UDMA_3,    0x900ad943      },
 191         {       XFER_UDMA_2,    0x900bd943      },
 192         {       XFER_UDMA_1,    0x9008d943      },
 193         {       XFER_UDMA_0,    0x9008d943      },
 194
 195         {       XFER_MW_DMA_2,  0xa008d943      },
 196         {       XFER_MW_DMA_1,  0xa010d955      },
 197         {       XFER_MW_DMA_0,  0xa010d9fc      },
 198
 199         {       XFER_PIO_4,     0xc008d963      },
 200         {       XFER_PIO_3,     0xc010d974      },
 201         {       XFER_PIO_2,     0xc010d997      },
 202         {       XFER_PIO_1,     0xc010d9c7      },
 203         {       XFER_PIO_0,     0xc018d9d9      },
 204         {       0,              0x0120d9d9      }
 205 };
 206
 207 static struct chipset_bus_clock_list_entry thirty_three_base_hpt366[] = {
 208         {       XFER_UDMA_4,    0x90c9a731      },
 209         {       XFER_UDMA_3,    0x90cfa731      },
 210         {       XFER_UDMA_2,    0x90caa731      },
 211         {       XFER_UDMA_1,    0x90cba731      },
 212         {       XFER_UDMA_0,    0x90c8a731      },
 213
 214         {       XFER_MW_DMA_2,  0xa0c8a731      },
 215         {       XFER_MW_DMA_1,  0xa0c8a732      },      /* 0xa0c8a733 */
 216         {       XFER_MW_DMA_0,  0xa0c8a797      },
 217
 218         {       XFER_PIO_4,     0xc0c8a731      },
 219         {       XFER_PIO_3,     0xc0c8a742      },
 220         {       XFER_PIO_2,     0xc0d0a753      },
 221         {       XFER_PIO_1,     0xc0d0a7a3      },      /* 0xc0d0a793 */
 222         {       XFER_PIO_0,     0xc0d0a7aa      },      /* 0xc0d0a7a7 */
 223         {       0,              0x0120a7a7      }
 224 };
 225
 226 static struct chipset_bus_clock_list_entry twenty_five_base_hpt366[] = {
 227         {       XFER_UDMA_4,    0x90c98521      },
 228         {       XFER_UDMA_3,    0x90cf8521      },
 229         {       XFER_UDMA_2,    0x90cf8521      },
 230         {       XFER_UDMA_1,    0x90cb8521      },
 231         {       XFER_UDMA_0,    0x90cb8521      },
 232
 233         {       XFER_MW_DMA_2,  0xa0ca8521      },
 234         {       XFER_MW_DMA_1,  0xa0ca8532      },
 235         {       XFER_MW_DMA_0,  0xa0ca8575      },
 236
 237         {       XFER_PIO_4,     0xc0ca8521      },
 238         {       XFER_PIO_3,     0xc0ca8532      },
 239         {       XFER_PIO_2,     0xc0ca8542      },
 240         {       XFER_PIO_1,     0xc0d08572      },
 241         {       XFER_PIO_0,     0xc0d08585      },
 242         {       0,              0x01208585      }
 243 };
 244
 245 /* from highpoint documentation. these are old values */
 246 static struct chipset_bus_clock_list_entry thirty_three_base_hpt370[] = {
 247 /*      {       XFER_UDMA_5,    0x1A85F442,     0x16454e31      }, */
 248         {       XFER_UDMA_5,    0x16454e31      },
 249         {       XFER_UDMA_4,    0x16454e31      },
 250         {       XFER_UDMA_3,    0x166d4e31      },
 251         {       XFER_UDMA_2,    0x16494e31      },
 252         {       XFER_UDMA_1,    0x164d4e31      },
 253         {       XFER_UDMA_0,    0x16514e31      },
 254
 255         {       XFER_MW_DMA_2,  0x26514e21      },
 256         {       XFER_MW_DMA_1,  0x26514e33      },
 257         {       XFER_MW_DMA_0,  0x26514e97      },
 258
 259         {       XFER_PIO_4,     0x06514e21      },
 260         {       XFER_PIO_3,     0x06514e22      },
 261         {       XFER_PIO_2,     0x06514e33      },
 262         {       XFER_PIO_1,     0x06914e43      },
 263         {       XFER_PIO_0,     0x06914e57      },
 264         {       0,              0x06514e57      }
 265 };
 266
 267 static struct chipset_bus_clock_list_entry sixty_six_base_hpt370[] = {
 268         {       XFER_UDMA_5,    0x14846231      },
 269         {       XFER_UDMA_4,    0x14886231      },
 270         {       XFER_UDMA_3,    0x148c6231      },
 271         {       XFER_UDMA_2,    0x148c6231      },
 272         {       XFER_UDMA_1,    0x14906231      },
 273         {       XFER_UDMA_0,    0x14986231      },
 274
 275         {       XFER_MW_DMA_2,  0x26514e21      },
 276         {       XFER_MW_DMA_1,  0x26514e33      },
 277         {       XFER_MW_DMA_0,  0x26514e97      },
 278
 279         {       XFER_PIO_4,     0x06514e21      },
 280         {       XFER_PIO_3,     0x06514e22      },
 281         {       XFER_PIO_2,     0x06514e33      },
 282         {       XFER_PIO_1,     0x06914e43      },
 283         {       XFER_PIO_0,     0x06914e57      },
 284         {       0,              0x06514e57      }
 285 };
 286
 287 /* these are the current (4 sep 2001) timings from highpoint */
 288 static struct chipset_bus_clock_list_entry thirty_three_base_hpt370a[] = {
 289         {       XFER_UDMA_5,    0x12446231      },
 290         {       XFER_UDMA_4,    0x12446231      },
 291         {       XFER_UDMA_3,    0x126c6231      },
 292         {       XFER_UDMA_2,    0x12486231      },
 293         {       XFER_UDMA_1,    0x124c6233      },
 294         {       XFER_UDMA_0,    0x12506297      },
 295
 296         {       XFER_MW_DMA_2,  0x22406c31      },
 297         {       XFER_MW_DMA_1,  0x22406c33      },
 298         {       XFER_MW_DMA_0,  0x22406c97      },
 299
 300         {       XFER_PIO_4,     0x06414e31      },
 301         {       XFER_PIO_3,     0x06414e42      },
 302         {       XFER_PIO_2,     0x06414e53      },
 303         {       XFER_PIO_1,     0x06814e93      },
 304         {       XFER_PIO_0,     0x06814ea7      },
 305         {       0,              0x06814ea7      }
 306 };
 307
 308 /* 2x 33MHz timings */
 309 static struct chipset_bus_clock_list_entry sixty_six_base_hpt370a[] = {
 310         {       XFER_UDMA_5,    0x1488e673      },
 311         {       XFER_UDMA_4,    0x1488e673      },
 312         {       XFER_UDMA_3,    0x1498e673      },
 313         {       XFER_UDMA_2,    0x1490e673      },
 314         {       XFER_UDMA_1,    0x1498e677      },
 315         {       XFER_UDMA_0,    0x14a0e73f      },
 316
 317         {       XFER_MW_DMA_2,  0x2480fa73      },
 318         {       XFER_MW_DMA_1,  0x2480fa77      },
 319         {       XFER_MW_DMA_0,  0x2480fb3f      },
 320
 321         {       XFER_PIO_4,     0x0c82be73      },
 322         {       XFER_PIO_3,     0x0c82be95      },
 323         {       XFER_PIO_2,     0x0c82beb7      },
 324         {       XFER_PIO_1,     0x0d02bf37      },
 325         {       XFER_PIO_0,     0x0d02bf5f      },
 326         {       0,              0x0d02bf5f      }
 327 };
 328
 329 static struct chipset_bus_clock_list_entry fifty_base_hpt370a[] = {
 330         {       XFER_UDMA_5,    0x12848242      },
 331         {       XFER_UDMA_4,    0x12ac8242      },
 332         {       XFER_UDMA_3,    0x128c8242      },
 333         {       XFER_UDMA_2,    0x120c8242      },
 334         {       XFER_UDMA_1,    0x12148254      },
 335         {       XFER_UDMA_0,    0x121882ea      },
 336
 337         {       XFER_MW_DMA_2,  0x22808242      },
 338         {       XFER_MW_DMA_1,  0x22808254      },
 339         {       XFER_MW_DMA_0,  0x228082ea      },
 340
 341         {       XFER_PIO_4,     0x0a81f442      },
 342         {       XFER_PIO_3,     0x0a81f443      },
 343         {       XFER_PIO_2,     0x0a81f454      },
 344         {       XFER_PIO_1,     0x0ac1f465      },
 345         {       XFER_PIO_0,     0x0ac1f48a      },
 346         {       0,              0x0ac1f48a      }
 347 };
 348
 349 static struct chipset_bus_clock_list_entry thirty_three_base_hpt372[] = {
 350         {       XFER_UDMA_6,    0x1c81dc62      },
 351         {       XFER_UDMA_5,    0x1c6ddc62      },
 352         {       XFER_UDMA_4,    0x1c8ddc62      },
 353         {       XFER_UDMA_3,    0x1c8edc62      },      /* checkme */
 354         {       XFER_UDMA_2,    0x1c91dc62      },
 355         {       XFER_UDMA_1,    0x1c9adc62      },      /* checkme */
 356         {       XFER_UDMA_0,    0x1c82dc62      },      /* checkme */
 357
 358         {       XFER_MW_DMA_2,  0x2c829262      },
 359         {       XFER_MW_DMA_1,  0x2c829266      },      /* checkme */
 360         {       XFER_MW_DMA_0,  0x2c82922e      },      /* checkme */
 361
 362         {       XFER_PIO_4,     0x0c829c62      },
 363         {       XFER_PIO_3,     0x0c829c84      },
 364         {       XFER_PIO_2,     0x0c829ca6      },
 365         {       XFER_PIO_1,     0x0d029d26      },
 366         {       XFER_PIO_0,     0x0d029d5e      },
 367         {       0,              0x0d029d5e      }
 368 };
 369
 370 static struct chipset_bus_clock_list_entry fifty_base_hpt372[] = {
 371         {       XFER_UDMA_5,    0x12848242      },
 372         {       XFER_UDMA_4,    0x12ac8242      },
 373         {       XFER_UDMA_3,    0x128c8242      },
 374         {       XFER_UDMA_2,    0x120c8242      },
 375         {       XFER_UDMA_1,    0x12148254      },
 376         {       XFER_UDMA_0,    0x121882ea      },
 377
 378         {       XFER_MW_DMA_2,  0x22808242      },
 379         {       XFER_MW_DMA_1,  0x22808254      },
 380         {       XFER_MW_DMA_0,  0x228082ea      },
 381
 382         {       XFER_PIO_4,     0x0a81f442      },
 383         {       XFER_PIO_3,     0x0a81f443      },
 384         {       XFER_PIO_2,     0x0a81f454      },
 385         {       XFER_PIO_1,     0x0ac1f465      },
 386         {       XFER_PIO_0,     0x0ac1f48a      },
 387         {       0,              0x0a81f443      }
 388 };
 389
 390 static struct chipset_bus_clock_list_entry sixty_six_base_hpt372[] = {
 391         {       XFER_UDMA_6,    0x1c869c62      },
 392         {       XFER_UDMA_5,    0x1cae9c62      },
 393         {       XFER_UDMA_4,    0x1c8a9c62      },
 394         {       XFER_UDMA_3,    0x1c8e9c62      },
 395         {       XFER_UDMA_2,    0x1c929c62      },
 396         {       XFER_UDMA_1,    0x1c9a9c62      },
 397         {       XFER_UDMA_0,    0x1c829c62      },
 398
 399         {       XFER_MW_DMA_2,  0x2c829c62      },
 400         {       XFER_MW_DMA_1,  0x2c829c66      },
 401         {       XFER_MW_DMA_0,  0x2c829d2e      },
 402
 403         {       XFER_PIO_4,     0x0c829c62      },
 404         {       XFER_PIO_3,     0x0c829c84      },
 405         {       XFER_PIO_2,     0x0c829ca6      },
 406         {       XFER_PIO_1,     0x0d029d26      },
 407         {       XFER_PIO_0,     0x0d029d5e      },
 408         {       0,              0x0d029d26      }
 409 };
 410
 411 static struct chipset_bus_clock_list_entry thirty_three_base_hpt374[] = {
 412         {       XFER_UDMA_6,    0x12808242      },
 413         {       XFER_UDMA_5,    0x12848242      },
 414         {       XFER_UDMA_4,    0x12ac8242      },
 415         {       XFER_UDMA_3,    0x128c8242      },
 416         {       XFER_UDMA_2,    0x120c8242      },
 417         {       XFER_UDMA_1,    0x12148254      },
 418         {       XFER_UDMA_0,    0x121882ea      },
 419
 420         {       XFER_MW_DMA_2,  0x22808242      },
 421         {       XFER_MW_DMA_1,  0x22808254      },
 422         {       XFER_MW_DMA_0,  0x228082ea      },
 423
 424         {       XFER_PIO_4,     0x0a81f442      },
 425         {       XFER_PIO_3,     0x0a81f443      },
 426         {       XFER_PIO_2,     0x0a81f454      },
 427         {       XFER_PIO_1,     0x0ac1f465      },
 428         {       XFER_PIO_0,     0x0ac1f48a      },
 429         {       0,              0x06814e93      }
 430 };
 431
 432 /* FIXME: 50MHz timings for HPT374 */
 433
 434 #if 0
 435 static struct chipset_bus_clock_list_entry sixty_six_base_hpt374[] = {
 436         {       XFER_UDMA_6,    0x12406231      },      /* checkme */
 437         {       XFER_UDMA_5,    0x12446231      },      /* 0x14846231 */
 438         {       XFER_UDMA_4,    0x16814ea7      },      /* 0x14886231 */
 439         {       XFER_UDMA_3,    0x16814ea7      },      /* 0x148c6231 */
 440         {       XFER_UDMA_2,    0x16814ea7      },      /* 0x148c6231 */
 441         {       XFER_UDMA_1,    0x16814ea7      },      /* 0x14906231 */
 442         {       XFER_UDMA_0,    0x16814ea7      },      /* 0x14986231 */
 443         {       XFER_MW_DMA_2,  0x16814ea7      },      /* 0x26514e21 */
 444         {       XFER_MW_DMA_1,  0x16814ea7      },      /* 0x26514e97 */
 445         {       XFER_MW_DMA_0,  0x16814ea7      },      /* 0x26514e97 */
 446         {       XFER_PIO_4,     0x06814ea7      },      /* 0x06514e21 */
 447         {       XFER_PIO_3,     0x06814ea7      },      /* 0x06514e22 */
 448         {       XFER_PIO_2,     0x06814ea7      },      /* 0x06514e33 */
 449         {       XFER_PIO_1,     0x06814ea7      },      /* 0x06914e43 */
 450         {       XFER_PIO_0,     0x06814ea7      },      /* 0x06914e57 */
 451         {       0,              0x06814ea7      }
 452 };
 453 #endif
 454
 455 #define HPT366_DEBUG_DRIVE_INFO         0
 456 #define HPT374_ALLOW_ATA133_6           0
 457 #define HPT371_ALLOW_ATA133_6           0
 458 #define HPT302_ALLOW_ATA133_6           0
 459 #define HPT372_ALLOW_ATA133_6           0
 460 #define HPT370_ALLOW_ATA100_5           1
 461 #define HPT366_ALLOW_ATA66_4            1
 462 #define HPT366_ALLOW_ATA66_3            1
 463 #define HPT366_MAX_DEVS                 8
 464
 465 #define F_LOW_PCI_33    0x23
 466 #define F_LOW_PCI_40    0x29
 467 #define F_LOW_PCI_50    0x2d
 468 #define F_LOW_PCI_66    0x42
 469
 470 /*
 471  *      Hold all the highpoint quirks and revision information in one
 472  *      place.
 473  */
 474
 475 struct hpt_info
 476 {
 477         u8 max_mode;            /* Speeds allowed */
 478         int revision;           /* Chipset revision */
 479         int flags;              /* Chipset properties */
 480 #define PLL_MODE        1
 481 #define IS_3xxN         2
 482 #define PCI_66MHZ       4
 483                                 /* Speed table */
 484         struct chipset_bus_clock_list_entry *speed;
 485 };
 486
 487 /*
 488  *      This wants fixing so that we do everything not by classrev
 489  *      (which breaks on the newest chips) but by creating an
 490  *      enumeration of chip variants and using that
 491  */
 492
 493 static __devinit u32 hpt_revision (struct pci_dev *dev)
 494 {
 495         u32 class_rev;
 496         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
 497         class_rev &= 0xff;
 498
 499         switch(dev->device) {
 500                 /* Remap new 372N onto 372 */
 501                 case PCI_DEVICE_ID_TTI_HPT372N:
 502                         class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
 503                 case PCI_DEVICE_ID_TTI_HPT374:
 504                         class_rev = PCI_DEVICE_ID_TTI_HPT374; break;
 505                 case PCI_DEVICE_ID_TTI_HPT371:
 506                         class_rev = PCI_DEVICE_ID_TTI_HPT371; break;
 507                 case PCI_DEVICE_ID_TTI_HPT302:
 508                         class_rev = PCI_DEVICE_ID_TTI_HPT302; break;
 509                 case PCI_DEVICE_ID_TTI_HPT372:
 510                         class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
 511                 default:
 512                         break;
 513         }
 514         return class_rev;
 515 }
 516
 517 static int check_in_drive_lists(ide_drive_t *drive, const char **list);
 518
 519 static u8 hpt3xx_ratemask (ide_drive_t *drive)
 520 {
 521         ide_hwif_t *hwif        = drive->hwif;
 522         struct hpt_info *info   = ide_get_hwifdata(hwif);
 523         u8 mode                 = 0;
 524
 525         /* FIXME: TODO - move this to set info->mode once at boot */
 526
 527         if (info->revision >= 8) {              /* HPT374 */
 528                 mode = (HPT374_ALLOW_ATA133_6) ? 4 : 3;
 529         } else if (info->revision >= 7) {       /* HPT371 */
 530                 mode = (HPT371_ALLOW_ATA133_6) ? 4 : 3;
 531         } else if (info->revision >= 6) {       /* HPT302 */
 532                 mode = (HPT302_ALLOW_ATA133_6) ? 4 : 3;
 533         } else if (info->revision >= 5) {       /* HPT372 */
 534                 mode = (HPT372_ALLOW_ATA133_6) ? 4 : 3;
 535         } else if (info->revision >= 4) {       /* HPT370A */
 536                 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
 537         } else if (info->revision >= 3) {       /* HPT370 */
 538                 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
 539                 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : mode;
 540         } else {                                /* HPT366 and HPT368 */
 541                 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : 2;
 542         }
 543         if (!eighty_ninty_three(drive) && mode)
 544                 mode = min(mode, (u8)1);
 545         return mode;
 546 }
 547
 548 /*
 549  *      Note for the future; the SATA hpt37x we must set
 550  *      either PIO or UDMA modes 0,4,5
 551  */
 552
 553 static u8 hpt3xx_ratefilter (ide_drive_t *drive, u8 speed)
 554 {
 555         ide_hwif_t *hwif        = drive->hwif;
 556         struct hpt_info *info   = ide_get_hwifdata(hwif);
 557         u8 mode                 = hpt3xx_ratemask(drive);
 558
 559         if (drive->media != ide_disk)
 560                 return min(speed, (u8)XFER_PIO_4);
 561
 562         switch(mode) {
 563                 case 0x04:
 564                         speed = min(speed, (u8)XFER_UDMA_6);
 565                         break;
 566                 case 0x03:
 567                         speed = min(speed, (u8)XFER_UDMA_5);
 568                         if (info->revision >= 5)
 569                                 break;
 570                         if (check_in_drive_lists(drive, bad_ata100_5))
 571                                 speed = min(speed, (u8)XFER_UDMA_4);
 572                         break;
 573                 case 0x02:
 574                         speed = min(speed, (u8)XFER_UDMA_4);
 575         /*
 576          * CHECK ME, Does this need to be set to 5 ??
 577          */
 578                         if (info->revision >= 3)
 579                                 break;
 580                         if ((check_in_drive_lists(drive, bad_ata66_4)) ||
 581                             (!(HPT366_ALLOW_ATA66_4)))
 582                                 speed = min(speed, (u8)XFER_UDMA_3);
 583                         if ((check_in_drive_lists(drive, bad_ata66_3)) ||
 584                             (!(HPT366_ALLOW_ATA66_3)))
 585                                 speed = min(speed, (u8)XFER_UDMA_2);
 586                         break;
 587                 case 0x01:
 588                         speed = min(speed, (u8)XFER_UDMA_2);
 589         /*
 590          * CHECK ME, Does this need to be set to 5 ??
 591          */
 592                         if (info->revision >= 3)
 593                                 break;
 594                         if (check_in_drive_lists(drive, bad_ata33))
 595                                 speed = min(speed, (u8)XFER_MW_DMA_2);
 596                         break;
 597                 case 0x00:
 598                 default:
 599                         speed = min(speed, (u8)XFER_MW_DMA_2);
 600                         break;
 601         }
 602         return speed;
 603 }
 604
 605 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
 606 {
 607         struct hd_driveid *id = drive->id;
 608
 609         if (quirk_drives == list) {
 610                 while (*list)
 611                         if (strstr(id->model, *list++))
 612                                 return 1;
 613         } else {
 614                 while (*list)
 615                         if (!strcmp(*list++,id->model))
 616                                 return 1;
 617         }
 618         return 0;
 619 }
 620
 621 static unsigned int pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
 622 {
 623         for ( ; chipset_table->xfer_speed ; chipset_table++)
 624                 if (chipset_table->xfer_speed == speed)
 625                         return chipset_table->chipset_settings;
 626         return chipset_table->chipset_settings;
 627 }
 628
 629 static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 630 {
 631         ide_hwif_t *hwif        = drive->hwif;
 632         struct pci_dev *dev     = hwif->pci_dev;
 633         struct hpt_info *info   = ide_get_hwifdata(hwif);
 634         u8 speed                = hpt3xx_ratefilter(drive, xferspeed);
 635         u8 regtime              = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
 636         u8 regfast              = (hwif->channel) ? 0x55 : 0x51;
 637         u8 drive_fast           = 0;
 638         u32 reg1 = 0, reg2      = 0;
 639
 640         /*
 641          * Disable the "fast interrupt" prediction.
 642          */
 643         pci_read_config_byte(dev, regfast, &drive_fast);
 644         if (drive_fast & 0x80)
 645                 pci_write_config_byte(dev, regfast, drive_fast & ~0x80);
 646
 647         reg2 = pci_bus_clock_list(speed, info->speed);
 648
 649         /*
 650          * Disable on-chip PIO FIFO/buffer
 651          *  (to avoid problems handling I/O errors later)
 652          */
 653         pci_read_config_dword(dev, regtime, &reg1);
 654         if (speed >= XFER_MW_DMA_0) {
 655                 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
 656         } else {
 657                 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
 658         }
 659         reg2 &= ~0x80000000;
 660
 661         pci_write_config_dword(dev, regtime, reg2);
 662
 663         return ide_config_drive_speed(drive, speed);
 664 }
 665
 666 static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 667 {
 668         ide_hwif_t *hwif        = drive->hwif;
 669         struct pci_dev *dev = hwif->pci_dev;
 670         struct hpt_info *info   = ide_get_hwifdata(hwif);
 671         u8 speed        = hpt3xx_ratefilter(drive, xferspeed);
 672         u8 regfast      = (drive->hwif->channel) ? 0x55 : 0x51;
 673         u8 drive_pci    = 0x40 + (drive->dn * 4);
 674         u8 new_fast     = 0, drive_fast = 0;
 675         u32 list_conf   = 0, drive_conf = 0;
 676         u32 conf_mask   = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
 677
 678         /*
 679          * Disable the "fast interrupt" prediction.
 680          * don't holdoff on interrupts. (== 0x01 despite what the docs say)
 681          */
 682         pci_read_config_byte(dev, regfast, &drive_fast);
 683         new_fast = drive_fast;
 684         if (new_fast & 0x02)
 685                 new_fast &= ~0x02;
 686
 687 #ifdef HPT_DELAY_INTERRUPT
 688         if (new_fast & 0x01)
 689                 new_fast &= ~0x01;
 690 #else
 691         if ((new_fast & 0x01) == 0)
 692                 new_fast |= 0x01;
 693 #endif
 694         if (new_fast != drive_fast)
 695                 pci_write_config_byte(dev, regfast, new_fast);
 696
 697         list_conf = pci_bus_clock_list(speed, info->speed);
 698
 699         pci_read_config_dword(dev, drive_pci, &drive_conf);
 700         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
 701
 702         if (speed < XFER_MW_DMA_0)
 703                 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 704         pci_write_config_dword(dev, drive_pci, list_conf);
 705
 706         return ide_config_drive_speed(drive, speed);
 707 }
 708
 709 static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 710 {
 711         ide_hwif_t *hwif        = drive->hwif;
 712         struct pci_dev *dev     = hwif->pci_dev;
 713         struct hpt_info *info   = ide_get_hwifdata(hwif);
 714         u8 speed        = hpt3xx_ratefilter(drive, xferspeed);
 715         u8 regfast      = (drive->hwif->channel) ? 0x55 : 0x51;
 716         u8 drive_fast   = 0, drive_pci = 0x40 + (drive->dn * 4);
 717         u32 list_conf   = 0, drive_conf = 0;
 718         u32 conf_mask   = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
 719
 720         /*
 721          * Disable the "fast interrupt" prediction.
 722          * don't holdoff on interrupts. (== 0x01 despite what the docs say)
 723          */
 724         pci_read_config_byte(dev, regfast, &drive_fast);
 725         drive_fast &= ~0x07;
 726         pci_write_config_byte(dev, regfast, drive_fast);
 727
 728         list_conf = pci_bus_clock_list(speed, info->speed);
 729         pci_read_config_dword(dev, drive_pci, &drive_conf);
 730         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
 731         if (speed < XFER_MW_DMA_0)
 732                 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 733         pci_write_config_dword(dev, drive_pci, list_conf);
 734
 735         return ide_config_drive_speed(drive, speed);
 736 }
 737
 738 static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed)
 739 {
 740         ide_hwif_t *hwif        = drive->hwif;
 741         struct hpt_info *info   = ide_get_hwifdata(hwif);
 742
 743         if (info->revision >= 8)
 744                 return hpt372_tune_chipset(drive, speed); /* not a typo */
 745         else if (info->revision >= 5)
 746                 return hpt372_tune_chipset(drive, speed);
 747         else if (info->revision >= 3)
 748                 return hpt370_tune_chipset(drive, speed);
 749         else    /* hpt368: hpt_minimum_revision(dev, 2) */
 750                 return hpt36x_tune_chipset(drive, speed);
 751 }
 752
 753 static void hpt3xx_tune_drive (ide_drive_t *drive, u8 pio)
 754 {
 755         pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
 756         (void) hpt3xx_tune_chipset(drive, (XFER_PIO_0 + pio));
 757 }
 758
 759 /*
 760  * This allows the configuration of ide_pci chipset registers
 761  * for cards that learn about the drive's UDMA, DMA, PIO capabilities
 762  * after the drive is reported by the OS.  Initially for designed for
 763  * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
 764  *
 765  * check_in_drive_lists(drive, bad_ata66_4)
 766  * check_in_drive_lists(drive, bad_ata66_3)
 767  * check_in_drive_lists(drive, bad_ata33)
 768  *
 769  */
 770 static int config_chipset_for_dma (ide_drive_t *drive)
 771 {
 772         u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
 773         ide_hwif_t *hwif = drive->hwif;
 774         struct hpt_info *info   = ide_get_hwifdata(hwif);
 775
 776         if (!speed)
 777                 return 0;
 778
 779         /* If we don't have any timings we can't do a lot */
 780         if (info->speed == NULL)
 781                 return 0;
 782
 783         (void) hpt3xx_tune_chipset(drive, speed);
 784         return ide_dma_enable(drive);
 785 }
 786
 787 static int hpt3xx_quirkproc (ide_drive_t *drive)
 788 {
 789         return ((int) check_in_drive_lists(drive, quirk_drives));
 790 }
 791
 792 static void hpt3xx_intrproc (ide_drive_t *drive)
 793 {
 794         ide_hwif_t *hwif = drive->hwif;
 795
 796         if (drive->quirk_list)
 797                 return;
 798         /* drives in the quirk_list may not like intr setups/cleanups */
 799         hwif->OUTB(drive->ctl|2, IDE_CONTROL_REG);
 800 }
 801
 802 static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
 803 {
 804         ide_hwif_t *hwif = drive->hwif;
 805         struct hpt_info *info = ide_get_hwifdata(hwif);
 806         struct pci_dev *dev = hwif->pci_dev;
 807
 808         if (drive->quirk_list) {
 809                 if (info->revision >= 3) {
 810                         u8 reg5a = 0;
 811                         pci_read_config_byte(dev, 0x5a, &reg5a);
 812                         if (((reg5a & 0x10) >> 4) != mask)
 813                                 pci_write_config_byte(dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10));
 814                 } else {
 815                         if (mask) {
 816                                 disable_irq(hwif->irq);
 817                         } else {
 818                                 enable_irq(hwif->irq);
 819                         }
 820                 }
 821         } else {
 822                 if (IDE_CONTROL_REG)
 823                         hwif->OUTB(mask ? (drive->ctl | 2) :
 824                                                  (drive->ctl & ~2),
 825                                                  IDE_CONTROL_REG);
 826         }
 827 }
 828
 829 static int hpt366_config_drive_xfer_rate (ide_drive_t *drive)
 830 {
 831         ide_hwif_t *hwif        = drive->hwif;
 832         struct hd_driveid *id   = drive->id;
 833
 834         drive->init_speed = 0;
 835
 836         if ((id->capability & 1) && drive->autodma) {
 837
 838                 if (ide_use_dma(drive)) {
 839                         if (config_chipset_for_dma(drive))
 840                                 return hwif->ide_dma_on(drive);
 841                 }
 842
 843                 goto fast_ata_pio;
 844
 845         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 846 fast_ata_pio:
 847                 hpt3xx_tune_drive(drive, 5);
 848                 return hwif->ide_dma_off_quietly(drive);
 849         }
 850         /* IORDY not supported */
 851         return 0;
 852 }
 853
 854 /*
 855  * This is specific to the HPT366 UDMA bios chipset
 856  * by HighPoint|Triones Technologies, Inc.
 857  */
 858 static int hpt366_ide_dma_lostirq (ide_drive_t *drive)
 859 {
 860         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 861         u8 reg50h = 0, reg52h = 0, reg5ah = 0;
 862
 863         pci_read_config_byte(dev, 0x50, &reg50h);
 864         pci_read_config_byte(dev, 0x52, &reg52h);
 865         pci_read_config_byte(dev, 0x5a, &reg5ah);
 866         printk("%s: (%s)  reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n",
 867                 drive->name, __FUNCTION__, reg50h, reg52h, reg5ah);
 868         if (reg5ah & 0x10)
 869                 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
 870         return __ide_dma_lostirq(drive);
 871 }
 872
 873 static void hpt370_clear_engine (ide_drive_t *drive)
 874 {
 875         u8 regstate = HWIF(drive)->channel ? 0x54 : 0x50;
 876         pci_write_config_byte(HWIF(drive)->pci_dev, regstate, 0x37);
 877         udelay(10);
 878 }
 879
 880 static void hpt370_ide_dma_start(ide_drive_t *drive)
 881 {
 882 #ifdef HPT_RESET_STATE_ENGINE
 883         hpt370_clear_engine(drive);
 884 #endif
 885         ide_dma_start(drive);
 886 }
 887
 888 static int hpt370_ide_dma_end (ide_drive_t *drive)
 889 {
 890         ide_hwif_t *hwif        = HWIF(drive);
 891         u8 dma_stat             = hwif->INB(hwif->dma_status);
 892
 893         if (dma_stat & 0x01) {
 894                 /* wait a little */
 895                 udelay(20);
 896                 dma_stat = hwif->INB(hwif->dma_status);
 897         }
 898         if ((dma_stat & 0x01) != 0)
 899                 /* fallthrough */
 900                 (void) HWIF(drive)->ide_dma_timeout(drive);
 901
 902         return __ide_dma_end(drive);
 903 }
 904
 905 static void hpt370_lostirq_timeout (ide_drive_t *drive)
 906 {
 907         ide_hwif_t *hwif        = HWIF(drive);
 908         u8 bfifo = 0, reginfo   = hwif->channel ? 0x56 : 0x52;
 909         u8 dma_stat = 0, dma_cmd = 0;
 910
 911         pci_read_config_byte(HWIF(drive)->pci_dev, reginfo, &bfifo);
 912         printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo);
 913         hpt370_clear_engine(drive);
 914         /* get dma command mode */
 915         dma_cmd = hwif->INB(hwif->dma_command);
 916         /* stop dma */
 917         hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
 918         dma_stat = hwif->INB(hwif->dma_status);
 919         /* clear errors */
 920         hwif->OUTB(dma_stat | 0x6, hwif->dma_status);
 921 }
 922
 923 static int hpt370_ide_dma_timeout (ide_drive_t *drive)
 924 {
 925         hpt370_lostirq_timeout(drive);
 926         hpt370_clear_engine(drive);
 927         return __ide_dma_timeout(drive);
 928 }
 929
 930 static int hpt370_ide_dma_lostirq (ide_drive_t *drive)
 931 {
 932         hpt370_lostirq_timeout(drive);
 933         hpt370_clear_engine(drive);
 934         return __ide_dma_lostirq(drive);
 935 }
 936
 937 /* returns 1 if DMA IRQ issued, 0 otherwise */
 938 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
 939 {
 940         ide_hwif_t *hwif        = HWIF(drive);
 941         u16 bfifo               = 0;
 942         u8 reginfo              = hwif->channel ? 0x56 : 0x52;
 943         u8 dma_stat;
 944
 945         pci_read_config_word(hwif->pci_dev, reginfo, &bfifo);
 946         if (bfifo & 0x1FF) {
 947 //              printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
 948                 return 0;
 949         }
 950
 951         dma_stat = hwif->INB(hwif->dma_status);
 952         /* return 1 if INTR asserted */
 953         if ((dma_stat & 4) == 4)
 954                 return 1;
 955
 956         if (!drive->waiting_for_dma)
 957                 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
 958                                 drive->name, __FUNCTION__);
 959         return 0;
 960 }
 961
 962 static int hpt374_ide_dma_end (ide_drive_t *drive)
 963 {
 964         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 965         ide_hwif_t *hwif        = HWIF(drive);
 966         u8 msc_stat = 0, mscreg = hwif->channel ? 0x54 : 0x50;
 967         u8 bwsr_stat = 0, bwsr_mask = hwif->channel ? 0x02 : 0x01;
 968
 969         pci_read_config_byte(dev, 0x6a, &bwsr_stat);
 970         pci_read_config_byte(dev, mscreg, &msc_stat);
 971         if ((bwsr_stat & bwsr_mask) == bwsr_mask)
 972                 pci_write_config_byte(dev, mscreg, msc_stat|0x30);
 973         return __ide_dma_end(drive);
 974 }
 975
 976 /**
 977  *      hpt3xxn_set_clock       -       perform clock switching dance
 978  *      @hwif: hwif to switch
 979  *      @mode: clocking mode (0x21 for write, 0x23 otherwise)
 980  *
 981  *      Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
 982  *      NOTE: avoid touching the disabled primary channel on HPT371N -- it
 983  *      doesn't physically exist anyway...
 984  */
 985
 986 static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
 987 {
 988         u8 mcr1, scr2 = hwif->INB(hwif->dma_master + 0x7b);
 989
 990         if ((scr2 & 0x7f) == mode)
 991                 return;
 992
 993         /* MISC. control register 1 has the channel enable bit... */
 994         mcr1 = hwif->INB(hwif->dma_master + 0x70);
 995
 996         /* Tristate the bus */
 997         if (mcr1 & 0x04)
 998                 hwif->OUTB(0x80, hwif->dma_master + 0x73);
 999         hwif->OUTB(0x80, hwif->dma_master + 0x77);
1000
1001         /* Switch clock and reset channels */
1002         hwif->OUTB(mode, hwif->dma_master + 0x7b);
1003         hwif->OUTB(0xc0, hwif->dma_master + 0x79);
1004
1005         /* Reset state machines */
1006         if (mcr1 & 0x04)
1007                 hwif->OUTB(0x37, hwif->dma_master + 0x70);
1008         hwif->OUTB(0x37, hwif->dma_master + 0x74);
1009
1010         /* Complete reset */
1011         hwif->OUTB(0x00, hwif->dma_master + 0x79);
1012
1013         /* Reconnect channels to bus */
1014         if (mcr1 & 0x04)
1015                 hwif->OUTB(0x00, hwif->dma_master + 0x73);
1016         hwif->OUTB(0x00, hwif->dma_master + 0x77);
1017 }
1018
1019 /**
1020  *      hpt3xxn_rw_disk         -       prepare for I/O
1021  *      @drive: drive for command
1022  *      @rq: block request structure
1023  *
1024  *      This is called when a disk I/O is issued to HPT3xxN.
1025  *      We need it because of the clock switching.
1026  */
1027
1028 static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
1029 {
1030         ide_hwif_t *hwif        = HWIF(drive);
1031         u8 wantclock            = rq_data_dir(rq) ? 0x23 : 0x21;
1032
1033         hpt3xxn_set_clock(hwif, wantclock);
1034 }
1035
1036 /*
1037  * Since SUN Cobalt is attempting to do this operation, I should disclose
1038  * this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
1039  * HOTSWAP ATA Infrastructure.
1040  */
1041
1042 static void hpt3xx_reset (ide_drive_t *drive)
1043 {
1044 }
1045
1046 static int hpt3xx_tristate (ide_drive_t * drive, int state)
1047 {
1048         ide_hwif_t *hwif        = HWIF(drive);
1049         struct pci_dev *dev     = hwif->pci_dev;
1050         u8 reg59h = 0, reset    = (hwif->channel) ? 0x80 : 0x40;
1051         u8 regXXh = 0, state_reg= (hwif->channel) ? 0x57 : 0x53;
1052
1053         pci_read_config_byte(dev, 0x59, &reg59h);
1054         pci_read_config_byte(dev, state_reg, &regXXh);
1055
1056         if (state) {
1057                 (void) ide_do_reset(drive);
1058                 pci_write_config_byte(dev, state_reg, regXXh|0x80);
1059                 pci_write_config_byte(dev, 0x59, reg59h|reset);
1060         } else {
1061                 pci_write_config_byte(dev, 0x59, reg59h & ~(reset));
1062                 pci_write_config_byte(dev, state_reg, regXXh & ~(0x80));
1063                 (void) ide_do_reset(drive);
1064         }
1065         return 0;
1066 }
1067
1068 /*
1069  * set/get power state for a drive.
1070  * turning the power off does the following things:
1071  *   1) soft-reset the drive
1072  *   2) tri-states the ide bus
1073  *
1074  * when we turn things back on, we need to re-initialize things.
1075  */
1076 #define TRISTATE_BIT  0x8000
1077 static int hpt370_busproc(ide_drive_t * drive, int state)
1078 {
1079         ide_hwif_t *hwif        = drive->hwif;
1080         struct pci_dev *dev     = hwif->pci_dev;
1081         u8 tristate = 0, resetmask = 0, bus_reg = 0;
1082         u16 tri_reg;
1083
1084         hwif->bus_state = state;
1085
1086         if (hwif->channel) {
1087                 /* secondary channel */
1088                 tristate = 0x56;
1089                 resetmask = 0x80;
1090         } else {
1091                 /* primary channel */
1092                 tristate = 0x52;
1093                 resetmask = 0x40;
1094         }
1095
1096         /* grab status */
1097         pci_read_config_word(dev, tristate, &tri_reg);
1098         pci_read_config_byte(dev, 0x59, &bus_reg);
1099
1100         /* set the state. we don't set it if we don't need to do so.
1101          * make sure that the drive knows that it has failed if it's off */
1102         switch (state) {
1103         case BUSSTATE_ON:
1104                 hwif->drives[0].failures = 0;
1105                 hwif->drives[1].failures = 0;
1106                 if ((bus_reg & resetmask) == 0)
1107                         return 0;
1108                 tri_reg &= ~TRISTATE_BIT;
1109                 bus_reg &= ~resetmask;
1110                 break;
1111         case BUSSTATE_OFF:
1112                 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
1113                 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
1114                 if ((tri_reg & TRISTATE_BIT) == 0 && (bus_reg & resetmask))
1115                         return 0;
1116                 tri_reg &= ~TRISTATE_BIT;
1117                 bus_reg |= resetmask;
1118                 break;
1119         case BUSSTATE_TRISTATE:
1120                 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
1121                 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
1122                 if ((tri_reg & TRISTATE_BIT) && (bus_reg & resetmask))
1123                         return 0;
1124                 tri_reg |= TRISTATE_BIT;
1125                 bus_reg |= resetmask;
1126                 break;
1127         }
1128         pci_write_config_byte(dev, 0x59, bus_reg);
1129         pci_write_config_word(dev, tristate, tri_reg);
1130
1131         return 0;
1132 }
1133
1134 static void __devinit hpt366_clocking(ide_hwif_t *hwif)
1135 {
1136         u32 reg1        = 0;
1137         struct hpt_info *info = ide_get_hwifdata(hwif);
1138
1139         pci_read_config_dword(hwif->pci_dev, 0x40, &reg1);
1140
1141         /* detect bus speed by looking at control reg timing: */
1142         switch((reg1 >> 8) & 7) {
1143                 case 5:
1144                         info->speed = forty_base_hpt366;
1145                         break;
1146                 case 9:
1147                         info->speed = twenty_five_base_hpt366;
1148                         break;
1149                 case 7:
1150                 default:
1151                         info->speed = thirty_three_base_hpt366;
1152                         break;
1153         }
1154 }
1155
1156 static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
1157 {
1158         struct hpt_info *info = ide_get_hwifdata(hwif);
1159         struct pci_dev *dev = hwif->pci_dev;
1160         int adjust, i;
1161         u16 freq;
1162         u32 pll;
1163         u8 reg5bh = 0, mcr1 = 0;
1164
1165         /*
1166          * default to pci clock. make sure MA15/16 are set to output
1167          * to prevent drives having problems with 40-pin cables. Needed
1168          * for some drives such as IBM-DTLA which will not enter ready
1169          * state on reset when PDIAG is a input.
1170          *
1171          * ToDo: should we set 0x21 when using PLL mode ?
1172          */
1173         pci_write_config_byte(dev, 0x5b, 0x23);
1174
1175         /*
1176          * set up the PLL. we need to adjust it so that it's stable.
1177          * freq = Tpll * 192 / Tpci
1178          *
1179          * Todo. For non x86 should probably check the dword is
1180          * set to 0xABCDExxx indicating the BIOS saved f_CNT
1181          */
1182         pci_read_config_word(dev, 0x78, &freq);
1183         freq &= 0x1FF;
1184
1185         /*
1186          * HPT3xxN chips use different PCI clock information.
1187          * Currently we always set up the PLL for them.
1188          */
1189
1190         if (info->flags & IS_3xxN) {
1191                 if(freq < 0x55)
1192                         pll = F_LOW_PCI_33;
1193                 else if(freq < 0x70)
1194                         pll = F_LOW_PCI_40;
1195                 else if(freq < 0x7F)
1196                         pll = F_LOW_PCI_50;
1197                 else
1198                         pll = F_LOW_PCI_66;
1199
1200                 printk(KERN_INFO "HPT3xxN detected, FREQ: %d, PLL: %d\n", freq, pll);
1201         }
1202         else
1203         {
1204                 if(freq < 0x9C)
1205                         pll = F_LOW_PCI_33;
1206                 else if(freq < 0xb0)
1207                         pll = F_LOW_PCI_40;
1208                 else if(freq <0xc8)
1209                         pll = F_LOW_PCI_50;
1210                 else
1211                         pll = F_LOW_PCI_66;
1212
1213                 if (pll == F_LOW_PCI_33) {
1214                         if (info->revision >= 8)
1215                                 info->speed = thirty_three_base_hpt374;
1216                         else if (info->revision >= 5)
1217                                 info->speed = thirty_three_base_hpt372;
1218                         else if (info->revision >= 4)
1219                                 info->speed = thirty_three_base_hpt370a;
1220                         else
1221                                 info->speed = thirty_three_base_hpt370;
1222                         printk(KERN_DEBUG "HPT37X: using 33MHz PCI clock\n");
1223                 } else if (pll == F_LOW_PCI_40) {
1224                         /* Unsupported */
1225                 } else if (pll == F_LOW_PCI_50) {
1226                         if (info->revision >= 8)
1227                                 info->speed = fifty_base_hpt370a;
1228                         else if (info->revision >= 5)
1229                                 info->speed = fifty_base_hpt372;
1230                         else if (info->revision >= 4)
1231                                 info->speed = fifty_base_hpt370a;
1232                         else
1233                                 info->speed = fifty_base_hpt370a;
1234                         printk(KERN_DEBUG "HPT37X: using 50MHz PCI clock\n");
1235                 } else {
1236                         if (info->revision >= 8) {
1237                                 printk(KERN_ERR "HPT37x: 66MHz timings are not supported.\n");
1238                         }
1239                         else if (info->revision >= 5)
1240                                 info->speed = sixty_six_base_hpt372;
1241                         else if (info->revision >= 4)
1242                                 info->speed = sixty_six_base_hpt370a;
1243                         else
1244                                 info->speed = sixty_six_base_hpt370;
1245                         printk(KERN_DEBUG "HPT37X: using 66MHz PCI clock\n");
1246                 }
1247         }
1248
1249         if (pll == F_LOW_PCI_66)
1250                 info->flags |= PCI_66MHZ;
1251
1252         /*
1253          * only try the pll if we don't have a table for the clock
1254          * speed that we're running at. NOTE: the internal PLL will
1255          * result in slow reads when using a 33MHz PCI clock. we also
1256          * don't like to use the PLL because it will cause glitches
1257          * on PRST/SRST when the HPT state engine gets reset.
1258          *
1259          * ToDo: Use 66MHz PLL when ATA133 devices are present on a
1260          * 372 device so we can get ATA133 support
1261          */
1262         if (info->speed)
1263                 goto init_hpt37X_done;
1264
1265         info->flags |= PLL_MODE;
1266
1267         /*
1268          * FIXME: make this work correctly, esp with 372N as per
1269          * reference driver code.
1270          *
1271          * adjust PLL based upon PCI clock, enable it, and wait for
1272          * stabilization.
1273          */
1274         adjust = 0;
1275         freq = (pll < F_LOW_PCI_50) ? 2 : 4;
1276         while (adjust++ < 6) {
1277                 pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
1278                                        pll | 0x100);
1279
1280                 /* wait for clock stabilization */
1281                 for (i = 0; i < 0x50000; i++) {
1282                         pci_read_config_byte(dev, 0x5b, &reg5bh);
1283                         if (reg5bh & 0x80) {
1284                                 /* spin looking for the clock to destabilize */
1285                                 for (i = 0; i < 0x1000; ++i) {
1286                                         pci_read_config_byte(dev, 0x5b,
1287                                                              &reg5bh);
1288                                         if ((reg5bh & 0x80) == 0)
1289                                                 goto pll_recal;
1290                                 }
1291                                 pci_read_config_dword(dev, 0x5c, &pll);
1292                                 pci_write_config_dword(dev, 0x5c,
1293                                                        pll & ~0x100);
1294                                 pci_write_config_byte(dev, 0x5b, 0x21);
1295                                 if (info->revision >= 8)
1296                                         info->speed = fifty_base_hpt370a;
1297                                 else if (info->revision >= 5)
1298                                         info->speed = fifty_base_hpt372;
1299                                 else if (info->revision >= 4)
1300                                         info->speed = fifty_base_hpt370a;
1301                                 else
1302                                         info->speed = fifty_base_hpt370a;
1303                                 printk("HPT37X: using 50MHz internal PLL\n");
1304                                 goto init_hpt37X_done;
1305                         }
1306                 }
1307 pll_recal:
1308                 if (adjust & 1)
1309                         pll -= (adjust >> 1);
1310                 else
1311                         pll += (adjust >> 1);
1312         }
1313
1314 init_hpt37X_done:
1315         if (!info->speed)
1316                 printk(KERN_ERR "HPT37x%s: unknown bus timing [%d %d].\n",
1317                        (info->flags & IS_3xxN) ? "N" : "", pll, freq);
1318         /*
1319          * Reset the state engines.
1320          * NOTE: avoid accidentally enabling the primary channel on HPT371N.
1321          */
1322         pci_read_config_byte(dev, 0x50, &mcr1);
1323         if (mcr1 & 0x04)
1324                 pci_write_config_byte(dev, 0x50, 0x37);
1325         pci_write_config_byte(dev, 0x54, 0x37);
1326         udelay(100);
1327 }
1328
1329 static int __devinit init_hpt37x(struct pci_dev *dev)
1330 {
1331         u8 reg5ah;
1332
1333         pci_read_config_byte(dev, 0x5a, &reg5ah);
1334         /* interrupt force enable */
1335         pci_write_config_byte(dev, 0x5a, (reg5ah & ~0x10));
1336         return 0;
1337 }
1338
1339 static int __devinit init_hpt366(struct pci_dev *dev)
1340 {
1341         u32 reg1        = 0;
1342         u8 drive_fast   = 0;
1343
1344         /*
1345          * Disable the "fast interrupt" prediction.
1346          */
1347         pci_read_config_byte(dev, 0x51, &drive_fast);
1348         if (drive_fast & 0x80)
1349                 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
1350         pci_read_config_dword(dev, 0x40, &reg1);
1351
1352         return 0;
1353 }
1354
1355 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1356 {
1357         int ret = 0;
1358
1359         /*
1360          * FIXME: Not portable. Also, why do we enable the ROM in the first place?
1361          * We don't seem to be using it.
1362          */
1363         if (dev->resource[PCI_ROM_RESOURCE].start)
1364                 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
1365                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1366
1367         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1368         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1369         pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1370         pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1371
1372         if (hpt_revision(dev) >= 3)
1373                 ret = init_hpt37x(dev);
1374         else
1375                 ret = init_hpt366(dev);
1376
1377         if (ret)
1378                 return ret;
1379
1380         return dev->irq;
1381 }
1382
1383 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1384 {
1385         struct pci_dev *dev             = hwif->pci_dev;
1386         struct hpt_info *info           = ide_get_hwifdata(hwif);
1387         u8 ata66 = 0, regmask           = (hwif->channel) ? 0x01 : 0x02;
1388         int serialize                   = HPT_SERIALIZE_IO;
1389
1390         hwif->tuneproc                  = &hpt3xx_tune_drive;
1391         hwif->speedproc                 = &hpt3xx_tune_chipset;
1392         hwif->quirkproc                 = &hpt3xx_quirkproc;
1393         hwif->intrproc                  = &hpt3xx_intrproc;
1394         hwif->maskproc                  = &hpt3xx_maskproc;
1395
1396         /*
1397          * HPT3xxN chips have some complications:
1398          *
1399          * - on 33 MHz PCI we must clock switch
1400          * - on 66 MHz PCI we must NOT use the PCI clock
1401          */
1402         if ((info->flags & (IS_3xxN | PCI_66MHZ)) == IS_3xxN) {
1403                 /*
1404                  * Clock is shared between the channels,
1405                  * so we'll have to serialize them... :-(
1406                  */
1407                 serialize = 1;
1408                 hwif->rw_disk = &hpt3xxn_rw_disk;
1409         }
1410
1411         /*
1412          * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1413          * address lines to access an external eeprom.  To read valid
1414          * cable detect state the pins must be enabled as inputs.
1415          */
1416         if (info->revision >= 8 && (PCI_FUNC(dev->devfn) & 1)) {
1417                 /*
1418                  * HPT374 PCI function 1
1419                  * - set bit 15 of reg 0x52 to enable TCBLID as input
1420                  * - set bit 15 of reg 0x56 to enable FCBLID as input
1421                  */
1422                 u16 mcr3, mcr6;
1423                 pci_read_config_word(dev, 0x52, &mcr3);
1424                 pci_read_config_word(dev, 0x56, &mcr6);
1425                 pci_write_config_word(dev, 0x52, mcr3 | 0x8000);
1426                 pci_write_config_word(dev, 0x56, mcr6 | 0x8000);
1427                 /* now read cable id register */
1428                 pci_read_config_byte(dev, 0x5a, &ata66);
1429                 pci_write_config_word(dev, 0x52, mcr3);
1430                 pci_write_config_word(dev, 0x56, mcr6);
1431         } else if (info->revision >= 3) {
1432                 /*
1433                  * HPT370/372 and 374 pcifn 0
1434                  * - clear bit 0 of 0x5b to enable P/SCBLID as inputs
1435                  */
1436                 u8 scr2;
1437                 pci_read_config_byte(dev, 0x5b, &scr2);
1438                 pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1439                 /* now read cable id register */
1440                 pci_read_config_byte(dev, 0x5a, &ata66);
1441                 pci_write_config_byte(dev, 0x5b, scr2);
1442         } else {
1443                 pci_read_config_byte(dev, 0x5a, &ata66);
1444         }
1445
1446 #ifdef DEBUG
1447         printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
1448                 ata66, (ata66 & regmask) ? "33" : "66",
1449                 PCI_FUNC(hwif->pci_dev->devfn));
1450 #endif /* DEBUG */
1451
1452         /* Serialize access to this device */
1453         if (serialize && hwif->mate)
1454                 hwif->serialized = hwif->mate->serialized = 1;
1455
1456         if (info->revision >= 3) {
1457                 u8 reg5ah = 0;
1458                         pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
1459                 /*
1460                  * set up ioctl for power status.
1461                  * note: power affects both
1462                  * drives on each channel
1463                  */
1464                 hwif->resetproc = &hpt3xx_reset;
1465                 hwif->busproc   = &hpt370_busproc;
1466         } else if (info->revision >= 2) {
1467                 hwif->resetproc = &hpt3xx_reset;
1468                 hwif->busproc   = &hpt3xx_tristate;
1469         } else {
1470                 hwif->resetproc = &hpt3xx_reset;
1471                 hwif->busproc   = &hpt3xx_tristate;
1472         }
1473
1474         if (!hwif->dma_base) {
1475                 hwif->drives[0].autotune = 1;
1476                 hwif->drives[1].autotune = 1;
1477                 return;
1478         }
1479
1480         hwif->ultra_mask = 0x7f;
1481         hwif->mwdma_mask = 0x07;
1482
1483         if (!(hwif->udma_four))
1484                 hwif->udma_four = ((ata66 & regmask) ? 0 : 1);
1485         hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1486
1487         if (info->revision >= 8) {
1488                 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1489                 hwif->ide_dma_end = &hpt374_ide_dma_end;
1490         } else if (info->revision >= 5) {
1491                 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1492                 hwif->ide_dma_end = &hpt374_ide_dma_end;
1493         } else if (info->revision >= 3) {
1494                 hwif->dma_start = &hpt370_ide_dma_start;
1495                 hwif->ide_dma_end = &hpt370_ide_dma_end;
1496                 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1497                 hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
1498         } else if (info->revision >= 2)
1499                 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1500         else
1501                 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1502
1503         if (!noautodma)
1504                 hwif->autodma = 1;
1505         hwif->drives[0].autodma = hwif->autodma;
1506         hwif->drives[1].autodma = hwif->autodma;
1507 }
1508
1509 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1510 {
1511         struct hpt_info *info   = ide_get_hwifdata(hwif);
1512         u8 masterdma    = 0, slavedma = 0;
1513         u8 dma_new      = 0, dma_old = 0;
1514         u8 primary      = hwif->channel ? 0x4b : 0x43;
1515         u8 secondary    = hwif->channel ? 0x4f : 0x47;
1516         unsigned long flags;
1517
1518         if (!dmabase)
1519                 return;
1520
1521         if(info->speed == NULL) {
1522                 printk(KERN_WARNING "hpt366: no known IDE timings, disabling DMA.\n");
1523                 return;
1524         }
1525
1526         dma_old = hwif->INB(dmabase+2);
1527
1528         local_irq_save(flags);
1529
1530         dma_new = dma_old;
1531         pci_read_config_byte(hwif->pci_dev, primary, &masterdma);
1532         pci_read_config_byte(hwif->pci_dev, secondary, &slavedma);
1533
1534         if (masterdma & 0x30)   dma_new |= 0x20;
1535         if (slavedma & 0x30)    dma_new |= 0x40;
1536         if (dma_new != dma_old)
1537                 hwif->OUTB(dma_new, dmabase+2);
1538
1539         local_irq_restore(flags);
1540
1541         ide_setup_dma(hwif, dmabase, 8);
1542 }
1543
1544 /*
1545  *      We "borrow" this hook in order to set the data structures
1546  *      up early enough before dma or init_hwif calls are made.
1547  */
1548
1549 static void __devinit init_iops_hpt366(ide_hwif_t *hwif)
1550 {
1551         struct hpt_info *info   = kzalloc(sizeof(struct hpt_info), GFP_KERNEL);
1552         struct pci_dev  *dev    = hwif->pci_dev;
1553         u16 did                 = dev->device;
1554         u8  rid                 = 0;
1555
1556         if(info == NULL) {
1557                 printk(KERN_WARNING "hpt366: out of memory.\n");
1558                 return;
1559         }
1560         ide_set_hwifdata(hwif, info);
1561
1562         /* Avoid doing the same thing twice. */
1563         if (hwif->channel && hwif->mate) {
1564                 memcpy(info, ide_get_hwifdata(hwif->mate), sizeof(struct hpt_info));
1565                 return;
1566         }
1567
1568         pci_read_config_byte(dev, PCI_CLASS_REVISION, &rid);
1569
1570         if (( did == PCI_DEVICE_ID_TTI_HPT366  && rid == 6) ||
1571             ((did == PCI_DEVICE_ID_TTI_HPT372  ||
1572               did == PCI_DEVICE_ID_TTI_HPT302  ||
1573               did == PCI_DEVICE_ID_TTI_HPT371) && rid > 1) ||
1574               did == PCI_DEVICE_ID_TTI_HPT372N)
1575                 info->flags |= IS_3xxN;
1576
1577         info->revision = hpt_revision(dev);
1578
1579         if (info->revision >= 3)
1580                 hpt37x_clocking(hwif);
1581         else
1582                 hpt366_clocking(hwif);
1583 }
1584
1585 static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1586 {
1587         struct pci_dev *findev = NULL;
1588
1589         if (PCI_FUNC(dev->devfn) & 1)
1590                 return -ENODEV;
1591
1592         while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1593                 if ((findev->vendor == dev->vendor) &&
1594                     (findev->device == dev->device) &&
1595                     ((findev->devfn - dev->devfn) == 1) &&
1596                     (PCI_FUNC(findev->devfn) & 1)) {
1597                         if (findev->irq != dev->irq) {
1598                                 /* FIXME: we need a core pci_set_interrupt() */
1599                                 findev->irq = dev->irq;
1600                                 printk(KERN_WARNING "%s: pci-config space interrupt "
1601                                         "fixed.\n", d->name);
1602                         }
1603                         return ide_setup_pci_devices(dev, findev, d);
1604                 }
1605         }
1606         return ide_setup_pci_device(dev, d);
1607 }
1608
1609 static int __devinit init_setup_hpt37x(struct pci_dev *dev, ide_pci_device_t *d)
1610 {
1611         return ide_setup_pci_device(dev, d);
1612 }
1613
1614 static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1615 {
1616         u8 mcr1 = 0;
1617
1618         /*
1619          * HPT371 chips physically have only one channel, the secondary one,
1620          * but the primary channel registers do exist!  Go figure...
1621          * So,  we manually disable the non-existing channel here
1622          * (if the BIOS hasn't done this already).
1623          */
1624         pci_read_config_byte(dev, 0x50, &mcr1);
1625         if (mcr1 & 0x04)
1626                 pci_write_config_byte(dev, 0x50, (mcr1 & ~0x04));
1627
1628         return ide_setup_pci_device(dev, d);
1629 }
1630
1631 static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1632 {
1633         struct pci_dev *findev = NULL;
1634         u8 pin1 = 0, pin2 = 0;
1635         unsigned int class_rev;
1636         char *chipset_names[] = {"HPT366", "HPT366",  "HPT368",
1637                                  "HPT370", "HPT370A", "HPT372",
1638                                  "HPT372N" };
1639
1640         if (PCI_FUNC(dev->devfn) & 1)
1641                 return -ENODEV;
1642
1643         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1644         class_rev &= 0xff;
1645
1646         if(dev->device == PCI_DEVICE_ID_TTI_HPT372N)
1647                 class_rev = 6;
1648
1649         if(class_rev <= 6)
1650                 d->name = chipset_names[class_rev];
1651
1652         switch(class_rev) {
1653                 case 6:
1654                 case 5:
1655                 case 4:
1656                 case 3:
1657                         goto init_single;
1658                 default:
1659                         break;
1660         }
1661
1662         d->channels = 1;
1663
1664         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1665         while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1666                 if ((findev->vendor == dev->vendor) &&
1667                     (findev->device == dev->device) &&
1668                     ((findev->devfn - dev->devfn) == 1) &&
1669                     (PCI_FUNC(findev->devfn) & 1)) {
1670                         pci_read_config_byte(findev, PCI_INTERRUPT_PIN, &pin2);
1671                         if ((pin1 != pin2) && (dev->irq == findev->irq)) {
1672                                 d->bootable = ON_BOARD;
1673                                 printk("%s: onboard version of chipset, "
1674                                         "pin1=%d pin2=%d\n", d->name,
1675                                         pin1, pin2);
1676                         }
1677                         return ide_setup_pci_devices(dev, findev, d);
1678                 }
1679         }
1680 init_single:
1681         return ide_setup_pci_device(dev, d);
1682 }
1683
1684 static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1685         {       /* 0 */
1686                 .name           = "HPT366",
1687                 .init_setup     = init_setup_hpt366,
1688                 .init_chipset   = init_chipset_hpt366,
1689                 .init_iops      = init_iops_hpt366,
1690                 .init_hwif      = init_hwif_hpt366,
1691                 .init_dma       = init_dma_hpt366,
1692                 .channels       = 2,
1693                 .autodma        = AUTODMA,
1694                 .bootable       = OFF_BOARD,
1695                 .extra          = 240
1696         },{     /* 1 */
1697                 .name           = "HPT372A",
1698                 .init_setup     = init_setup_hpt37x,
1699                 .init_chipset   = init_chipset_hpt366,
1700                 .init_iops      = init_iops_hpt366,
1701                 .init_hwif      = init_hwif_hpt366,
1702                 .init_dma       = init_dma_hpt366,
1703                 .channels       = 2,
1704                 .autodma        = AUTODMA,
1705                 .bootable       = OFF_BOARD,
1706         },{     /* 2 */
1707                 .name           = "HPT302",
1708                 .init_setup     = init_setup_hpt37x,
1709                 .init_chipset   = init_chipset_hpt366,
1710                 .init_iops      = init_iops_hpt366,
1711                 .init_hwif      = init_hwif_hpt366,
1712                 .init_dma       = init_dma_hpt366,
1713                 .channels       = 2,
1714                 .autodma        = AUTODMA,
1715                 .bootable       = OFF_BOARD,
1716         },{     /* 3 */
1717                 .name           = "HPT371",
1718                 .init_setup     = init_setup_hpt371,
1719                 .init_chipset   = init_chipset_hpt366,
1720                 .init_iops      = init_iops_hpt366,
1721                 .init_hwif      = init_hwif_hpt366,
1722                 .init_dma       = init_dma_hpt366,
1723                 .channels       = 2,
1724                 .autodma        = AUTODMA,
1725                 .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1726                 .bootable       = OFF_BOARD,
1727         },{     /* 4 */
1728                 .name           = "HPT374",
1729                 .init_setup     = init_setup_hpt374,
1730                 .init_chipset   = init_chipset_hpt366,
1731                 .init_iops      = init_iops_hpt366,
1732                 .init_hwif      = init_hwif_hpt366,
1733                 .init_dma       = init_dma_hpt366,
1734                 .channels       = 2,    /* 4 */
1735                 .autodma        = AUTODMA,
1736                 .bootable       = OFF_BOARD,
1737         },{     /* 5 */
1738                 .name           = "HPT372N",
1739                 .init_setup     = init_setup_hpt37x,
1740                 .init_chipset   = init_chipset_hpt366,
1741                 .init_iops      = init_iops_hpt366,
1742                 .init_hwif      = init_hwif_hpt366,
1743                 .init_dma       = init_dma_hpt366,
1744                 .channels       = 2,    /* 4 */
1745                 .autodma        = AUTODMA,
1746                 .bootable       = OFF_BOARD,
1747         }
1748 };
1749
1750 /**
1751  *      hpt366_init_one -       called when an HPT366 is found
1752  *      @dev: the hpt366 device
1753  *      @id: the matching pci id
1754  *
1755  *      Called when the PCI registration layer (or the IDE initialization)
1756  *      finds a device matching our IDE device tables.
1757  */
1758
1759 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1760 {
1761         ide_pci_device_t *d = &hpt366_chipsets[id->driver_data];
1762
1763         return d->init_setup(dev, d);
1764 }
1765
1766 static struct pci_device_id hpt366_pci_tbl[] = {
1767         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1768         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1769         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1770         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1771         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1772         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1773         { 0, },
1774 };
1775 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1776
1777 static struct pci_driver driver = {
1778         .name           = "HPT366_IDE",
1779         .id_table       = hpt366_pci_tbl,
1780         .probe          = hpt366_init_one,
1781 };
1782
1783 static int hpt366_ide_init(void)
1784 {
1785         return ide_pci_register_driver(&driver);
1786 }
1787
1788 module_init(hpt366_ide_init);
1789
1790 MODULE_AUTHOR("Andre Hedrick");
1791 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1792 MODULE_LICENSE("GPL");