2 * linux/drivers/ide/pci/hpt366.c Version 1.13 Sep 29, 2007
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
6 * Portions Copyright (C) 2003 Red Hat Inc
7 * Portions Copyright (C) 2005-2007 MontaVista Software, Inc.
9 * Thanks to HighPoint Technologies for their assistance, and hardware.
10 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
11 * donation of an ABit BP6 mainboard, processor, and memory acellerated
12 * development and support.
15 * HighPoint has its own drivers (open source except for the RAID part)
16 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
17 * This may be useful to anyone wanting to work on this driver, however do not
18 * trust them too much since the code tends to become less and less meaningful
19 * as the time passes... :-/
21 * Note that final HPT370 support was done by force extraction of GPL.
23 * - add function for getting/setting power status of drive
24 * - the HPT370's state machine can get confused. reset it before each dma
25 * xfer to prevent that from happening.
26 * - reset state engine whenever we get an error.
27 * - check for busmaster state at end of dma.
28 * - use new highpoint timings.
29 * - detect bus speed using highpoint register.
30 * - use pll if we don't have a clock table. added a 66MHz table that's
31 * just 2x the 33MHz table.
32 * - removed turnaround. NOTE: we never want to switch between pll and
33 * pci clocks as the chip can glitch in those cases. the highpoint
34 * approved workaround slows everything down too much to be useful. in
35 * addition, we would have to serialize access to each chip.
36 * Adrian Sun <a.sun@sun.com>
38 * add drive timings for 66MHz PCI bus,
39 * fix ATA Cable signal detection, fix incorrect /proc info
40 * add /proc display for per-drive PIO/DMA/UDMA mode and
41 * per-channel ATA-33/66 Cable detect.
42 * Duncan Laurie <void@sun.com>
44 * fixup /proc output for multiple controllers
45 * Tim Hockin <thockin@sun.com>
48 * Reset the hpt366 on error, reset on dma
49 * Fix disabling Fast Interrupt hpt366.
50 * Mike Waychison <crlf@sun.com>
52 * Added support for 372N clocking and clock switching. The 372N needs
53 * different clocks on read/write. This requires overloading rw_disk and
54 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
56 * Alan Cox <alan@redhat.com>
58 * - fix the clock turnaround code: it was writing to the wrong ports when
59 * called for the secondary channel, caching the current clock mode per-
60 * channel caused the cached register value to get out of sync with the
61 * actual one, the channels weren't serialized, the turnaround shouldn't
62 * be done on 66 MHz PCI bus
63 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
64 * does not allow for this speed anyway
65 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
66 * their primary channel is kind of virtual, it isn't tied to any pins)
67 * - fix/remove bad/unused timing tables and use one set of tables for the whole
68 * HPT37x chip family; save space by introducing the separate transfer mode
69 * table in which the mode lookup is done
70 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
71 * the wrong PCI frequency since DPLL has already been calibrated by BIOS;
72 * read it only from the function 0 of HPT374 chips
73 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
74 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
75 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
76 * they tamper with its fields
77 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
78 * since they may tamper with its fields
79 * - prefix the driver startup messages with the real chip name
80 * - claim the extra 240 bytes of I/O space for all chips
81 * - optimize the UltraDMA filtering and the drive list lookup code
82 * - use pci_get_slot() to get to the function 1 of HPT36x/374
83 * - cache offset of the channel's misc. control registers (MCRs) being used
84 * throughout the driver
85 * - only touch the relevant MCR when detecting the cable type on HPT374's
87 * - rename all the register related variables consistently
88 * - move all the interrupt twiddling code from the speedproc handlers into
89 * init_hwif_hpt366(), also grouping all the DMA related code together there
90 * - merge two HPT37x speedproc handlers, fix the PIO timing register mask and
91 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
92 * when setting an UltraDMA mode
93 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
94 * the best possible one
95 * - clean up DMA timeout handling for HPT370
96 * - switch to using the enumeration type to differ between the numerous chip
97 * variants, matching PCI device/revision ID with the chip type early, at the
99 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
100 * stop duplicating it for each channel by storing the pointer in the pci_dev
101 * structure: first, at the init_setup stage, point it to a static "template"
102 * with only the chip type and its specific base DPLL frequency, the highest
103 * UltraDMA mode, and the chip settings table pointer filled, then, at the
104 * init_chipset stage, allocate per-chip instance and fill it with the rest
105 * of the necessary information
106 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
107 * switch to calculating PCI clock frequency based on the chip's base DPLL
109 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
110 * anything newer than HPT370/A (except HPT374 that is not capable of this
111 * mode according to the manual)
112 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
113 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
114 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
115 * the register setting lists into the table indexed by the clock selected
116 * - set the correct hwif->ultra_mask for each individual chip
117 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
118 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
121 #include <linux/types.h>
122 #include <linux/module.h>
123 #include <linux/kernel.h>
124 #include <linux/delay.h>
125 #include <linux/timer.h>
126 #include <linux/mm.h>
127 #include <linux/ioport.h>
128 #include <linux/blkdev.h>
129 #include <linux/hdreg.h>
131 #include <linux/interrupt.h>
132 #include <linux/pci.h>
133 #include <linux/init.h>
134 #include <linux/ide.h>
136 #include <asm/uaccess.h>
140 /* various tuning parameters */
141 #define HPT_RESET_STATE_ENGINE
142 #undef HPT_DELAY_INTERRUPT
143 #define HPT_SERIALIZE_IO 0
145 static const char *quirk_drives[] = {
146 "QUANTUM FIREBALLlct08 08",
147 "QUANTUM FIREBALLP KA6.4",
148 "QUANTUM FIREBALLP LM20.4",
149 "QUANTUM FIREBALLP LM20.5",
153 static const char *bad_ata100_5[] = {
172 static const char *bad_ata66_4[] = {
188 "MAXTOR STM3320620A",
192 static const char *bad_ata66_3[] = {
197 static const char *bad_ata33[] = {
198 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
199 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
200 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
202 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
203 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
204 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
208 static u8 xfer_speeds[] = {
228 /* Key for bus clock timings
231 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
233 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
235 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
237 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
239 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
240 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
241 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
243 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
244 * task file register access.
247 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
252 static u32 forty_base_hpt36x[] = {
253 /* XFER_UDMA_6 */ 0x900fd943,
254 /* XFER_UDMA_5 */ 0x900fd943,
255 /* XFER_UDMA_4 */ 0x900fd943,
256 /* XFER_UDMA_3 */ 0x900ad943,
257 /* XFER_UDMA_2 */ 0x900bd943,
258 /* XFER_UDMA_1 */ 0x9008d943,
259 /* XFER_UDMA_0 */ 0x9008d943,
261 /* XFER_MW_DMA_2 */ 0xa008d943,
262 /* XFER_MW_DMA_1 */ 0xa010d955,
263 /* XFER_MW_DMA_0 */ 0xa010d9fc,
265 /* XFER_PIO_4 */ 0xc008d963,
266 /* XFER_PIO_3 */ 0xc010d974,
267 /* XFER_PIO_2 */ 0xc010d997,
268 /* XFER_PIO_1 */ 0xc010d9c7,
269 /* XFER_PIO_0 */ 0xc018d9d9
272 static u32 thirty_three_base_hpt36x[] = {
273 /* XFER_UDMA_6 */ 0x90c9a731,
274 /* XFER_UDMA_5 */ 0x90c9a731,
275 /* XFER_UDMA_4 */ 0x90c9a731,
276 /* XFER_UDMA_3 */ 0x90cfa731,
277 /* XFER_UDMA_2 */ 0x90caa731,
278 /* XFER_UDMA_1 */ 0x90cba731,
279 /* XFER_UDMA_0 */ 0x90c8a731,
281 /* XFER_MW_DMA_2 */ 0xa0c8a731,
282 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
283 /* XFER_MW_DMA_0 */ 0xa0c8a797,
285 /* XFER_PIO_4 */ 0xc0c8a731,
286 /* XFER_PIO_3 */ 0xc0c8a742,
287 /* XFER_PIO_2 */ 0xc0d0a753,
288 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
289 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
292 static u32 twenty_five_base_hpt36x[] = {
293 /* XFER_UDMA_6 */ 0x90c98521,
294 /* XFER_UDMA_5 */ 0x90c98521,
295 /* XFER_UDMA_4 */ 0x90c98521,
296 /* XFER_UDMA_3 */ 0x90cf8521,
297 /* XFER_UDMA_2 */ 0x90cf8521,
298 /* XFER_UDMA_1 */ 0x90cb8521,
299 /* XFER_UDMA_0 */ 0x90cb8521,
301 /* XFER_MW_DMA_2 */ 0xa0ca8521,
302 /* XFER_MW_DMA_1 */ 0xa0ca8532,
303 /* XFER_MW_DMA_0 */ 0xa0ca8575,
305 /* XFER_PIO_4 */ 0xc0ca8521,
306 /* XFER_PIO_3 */ 0xc0ca8532,
307 /* XFER_PIO_2 */ 0xc0ca8542,
308 /* XFER_PIO_1 */ 0xc0d08572,
309 /* XFER_PIO_0 */ 0xc0d08585
312 static u32 thirty_three_base_hpt37x[] = {
313 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
314 /* XFER_UDMA_5 */ 0x12446231,
315 /* XFER_UDMA_4 */ 0x12446231,
316 /* XFER_UDMA_3 */ 0x126c6231,
317 /* XFER_UDMA_2 */ 0x12486231,
318 /* XFER_UDMA_1 */ 0x124c6233,
319 /* XFER_UDMA_0 */ 0x12506297,
321 /* XFER_MW_DMA_2 */ 0x22406c31,
322 /* XFER_MW_DMA_1 */ 0x22406c33,
323 /* XFER_MW_DMA_0 */ 0x22406c97,
325 /* XFER_PIO_4 */ 0x06414e31,
326 /* XFER_PIO_3 */ 0x06414e42,
327 /* XFER_PIO_2 */ 0x06414e53,
328 /* XFER_PIO_1 */ 0x06814e93,
329 /* XFER_PIO_0 */ 0x06814ea7
332 static u32 fifty_base_hpt37x[] = {
333 /* XFER_UDMA_6 */ 0x12848242,
334 /* XFER_UDMA_5 */ 0x12848242,
335 /* XFER_UDMA_4 */ 0x12ac8242,
336 /* XFER_UDMA_3 */ 0x128c8242,
337 /* XFER_UDMA_2 */ 0x120c8242,
338 /* XFER_UDMA_1 */ 0x12148254,
339 /* XFER_UDMA_0 */ 0x121882ea,
341 /* XFER_MW_DMA_2 */ 0x22808242,
342 /* XFER_MW_DMA_1 */ 0x22808254,
343 /* XFER_MW_DMA_0 */ 0x228082ea,
345 /* XFER_PIO_4 */ 0x0a81f442,
346 /* XFER_PIO_3 */ 0x0a81f443,
347 /* XFER_PIO_2 */ 0x0a81f454,
348 /* XFER_PIO_1 */ 0x0ac1f465,
349 /* XFER_PIO_0 */ 0x0ac1f48a
352 static u32 sixty_six_base_hpt37x[] = {
353 /* XFER_UDMA_6 */ 0x1c869c62,
354 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
355 /* XFER_UDMA_4 */ 0x1c8a9c62,
356 /* XFER_UDMA_3 */ 0x1c8e9c62,
357 /* XFER_UDMA_2 */ 0x1c929c62,
358 /* XFER_UDMA_1 */ 0x1c9a9c62,
359 /* XFER_UDMA_0 */ 0x1c829c62,
361 /* XFER_MW_DMA_2 */ 0x2c829c62,
362 /* XFER_MW_DMA_1 */ 0x2c829c66,
363 /* XFER_MW_DMA_0 */ 0x2c829d2e,
365 /* XFER_PIO_4 */ 0x0c829c62,
366 /* XFER_PIO_3 */ 0x0c829c84,
367 /* XFER_PIO_2 */ 0x0c829ca6,
368 /* XFER_PIO_1 */ 0x0d029d26,
369 /* XFER_PIO_0 */ 0x0d029d5e
372 #define HPT366_DEBUG_DRIVE_INFO 0
373 #define HPT371_ALLOW_ATA133_6 1
374 #define HPT302_ALLOW_ATA133_6 1
375 #define HPT372_ALLOW_ATA133_6 1
376 #define HPT370_ALLOW_ATA100_5 0
377 #define HPT366_ALLOW_ATA66_4 1
378 #define HPT366_ALLOW_ATA66_3 1
379 #define HPT366_MAX_DEVS 8
381 /* Supported ATA clock frequencies */
392 * Hold all the HighPoint chip information in one place.
396 u8 chip_type; /* Chip type */
397 u8 max_ultra; /* Max. UltraDMA mode allowed */
398 u8 dpll_clk; /* DPLL clock in MHz */
399 u8 pci_clk; /* PCI clock in MHz */
400 u32 **settings; /* Chipset settings table */
403 /* Supported HighPoint chips */
418 static u32 *hpt36x_settings[NUM_ATA_CLOCKS] = {
419 twenty_five_base_hpt36x,
420 thirty_three_base_hpt36x,
426 static u32 *hpt37x_settings[NUM_ATA_CLOCKS] = {
428 thirty_three_base_hpt37x,
431 sixty_six_base_hpt37x
434 static struct hpt_info hpt36x __devinitdata = {
436 .max_ultra = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? 4 : 3) : 2,
437 .dpll_clk = 0, /* no DPLL */
438 .settings = hpt36x_settings
441 static struct hpt_info hpt370 __devinitdata = {
443 .max_ultra = HPT370_ALLOW_ATA100_5 ? 5 : 4,
445 .settings = hpt37x_settings
448 static struct hpt_info hpt370a __devinitdata = {
449 .chip_type = HPT370A,
450 .max_ultra = HPT370_ALLOW_ATA100_5 ? 5 : 4,
452 .settings = hpt37x_settings
455 static struct hpt_info hpt374 __devinitdata = {
459 .settings = hpt37x_settings
462 static struct hpt_info hpt372 __devinitdata = {
464 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
466 .settings = hpt37x_settings
469 static struct hpt_info hpt372a __devinitdata = {
470 .chip_type = HPT372A,
471 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
473 .settings = hpt37x_settings
476 static struct hpt_info hpt302 __devinitdata = {
478 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
480 .settings = hpt37x_settings
483 static struct hpt_info hpt371 __devinitdata = {
485 .max_ultra = HPT371_ALLOW_ATA133_6 ? 6 : 5,
487 .settings = hpt37x_settings
490 static struct hpt_info hpt372n __devinitdata = {
491 .chip_type = HPT372N,
492 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
494 .settings = hpt37x_settings
497 static struct hpt_info hpt302n __devinitdata = {
498 .chip_type = HPT302N,
499 .max_ultra = HPT302_ALLOW_ATA133_6 ? 6 : 5,
501 .settings = hpt37x_settings
504 static struct hpt_info hpt371n __devinitdata = {
505 .chip_type = HPT371N,
506 .max_ultra = HPT371_ALLOW_ATA133_6 ? 6 : 5,
508 .settings = hpt37x_settings
511 static int check_in_drive_list(ide_drive_t *drive, const char **list)
513 struct hd_driveid *id = drive->id;
516 if (!strcmp(*list++,id->model))
522 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
523 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
526 static u8 hpt3xx_udma_filter(ide_drive_t *drive)
528 ide_hwif_t *hwif = HWIF(drive);
529 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev);
530 u8 mask = hwif->ultra_mask;
532 switch (info->chip_type) {
534 if (!HPT366_ALLOW_ATA66_4 ||
535 check_in_drive_list(drive, bad_ata66_4))
538 if (!HPT366_ALLOW_ATA66_3 ||
539 check_in_drive_list(drive, bad_ata66_3))
543 if (!HPT370_ALLOW_ATA100_5 ||
544 check_in_drive_list(drive, bad_ata100_5))
548 if (!HPT370_ALLOW_ATA100_5 ||
549 check_in_drive_list(drive, bad_ata100_5))
555 if (ide_dev_is_sata(drive->id))
562 return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask;
565 static u8 hpt3xx_mdma_filter(ide_drive_t *drive)
567 ide_hwif_t *hwif = HWIF(drive);
568 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev);
570 switch (info->chip_type) {
575 if (ide_dev_is_sata(drive->id))
583 static u32 get_speed_setting(u8 speed, struct hpt_info *info)
588 * Lookup the transfer mode table to get the index into
591 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
593 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
594 if (xfer_speeds[i] == speed)
597 * NOTE: info->settings only points to the pointer
598 * to the list of the actual register values
600 return (*info->settings)[i];
603 static int hpt36x_tune_chipset(ide_drive_t *drive, const u8 speed)
605 ide_hwif_t *hwif = HWIF(drive);
606 struct pci_dev *dev = hwif->pci_dev;
607 struct hpt_info *info = pci_get_drvdata(dev);
608 u8 itr_addr = drive->dn ? 0x44 : 0x40;
610 u32 itr_mask, new_itr;
612 itr_mask = speed < XFER_MW_DMA_0 ? 0x30070000 :
613 (speed < XFER_UDMA_0 ? 0xc0070000 : 0xc03800ff);
615 new_itr = get_speed_setting(speed, info);
618 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
619 * to avoid problems handling I/O errors later
621 pci_read_config_dword(dev, itr_addr, &old_itr);
622 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
623 new_itr &= ~0xc0000000;
625 pci_write_config_dword(dev, itr_addr, new_itr);
627 return ide_config_drive_speed(drive, speed);
630 static int hpt37x_tune_chipset(ide_drive_t *drive, const u8 speed)
632 ide_hwif_t *hwif = HWIF(drive);
633 struct pci_dev *dev = hwif->pci_dev;
634 struct hpt_info *info = pci_get_drvdata(dev);
635 u8 itr_addr = 0x40 + (drive->dn * 4);
637 u32 itr_mask, new_itr;
639 itr_mask = speed < XFER_MW_DMA_0 ? 0x303c0000 :
640 (speed < XFER_UDMA_0 ? 0xc03c0000 : 0xc1c001ff);
642 new_itr = get_speed_setting(speed, info);
644 pci_read_config_dword(dev, itr_addr, &old_itr);
645 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
647 if (speed < XFER_MW_DMA_0)
648 new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
649 pci_write_config_dword(dev, itr_addr, new_itr);
651 return ide_config_drive_speed(drive, speed);
654 static int hpt3xx_tune_chipset(ide_drive_t *drive, u8 speed)
656 ide_hwif_t *hwif = HWIF(drive);
657 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev);
659 if (info->chip_type >= HPT370)
660 return hpt37x_tune_chipset(drive, speed);
661 else /* hpt368: hpt_minimum_revision(dev, 2) */
662 return hpt36x_tune_chipset(drive, speed);
665 static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
667 (void) hpt3xx_tune_chipset (drive, XFER_PIO_0 + pio);
670 static int hpt3xx_quirkproc(ide_drive_t *drive)
672 struct hd_driveid *id = drive->id;
673 const char **list = quirk_drives;
676 if (strstr(id->model, *list++))
681 static void hpt3xx_intrproc(ide_drive_t *drive)
683 ide_hwif_t *hwif = HWIF(drive);
685 if (drive->quirk_list)
687 /* drives in the quirk_list may not like intr setups/cleanups */
688 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
691 static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
693 ide_hwif_t *hwif = HWIF(drive);
694 struct pci_dev *dev = hwif->pci_dev;
695 struct hpt_info *info = pci_get_drvdata(dev);
697 if (drive->quirk_list) {
698 if (info->chip_type >= HPT370) {
701 pci_read_config_byte(dev, 0x5a, &scr1);
702 if (((scr1 & 0x10) >> 4) != mask) {
707 pci_write_config_byte(dev, 0x5a, scr1);
711 disable_irq(hwif->irq);
713 enable_irq (hwif->irq);
716 hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
720 static int hpt366_config_drive_xfer_rate(ide_drive_t *drive)
722 drive->init_speed = 0;
724 if (ide_tune_dma(drive))
727 if (ide_use_fast_pio(drive))
728 ide_set_max_pio(drive);
734 * This is specific to the HPT366 UDMA chipset
735 * by HighPoint|Triones Technologies, Inc.
737 static void hpt366_dma_lost_irq(ide_drive_t *drive)
739 struct pci_dev *dev = HWIF(drive)->pci_dev;
740 u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
742 pci_read_config_byte(dev, 0x50, &mcr1);
743 pci_read_config_byte(dev, 0x52, &mcr3);
744 pci_read_config_byte(dev, 0x5a, &scr1);
745 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
746 drive->name, __FUNCTION__, mcr1, mcr3, scr1);
748 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
749 ide_dma_lost_irq(drive);
752 static void hpt370_clear_engine(ide_drive_t *drive)
754 ide_hwif_t *hwif = HWIF(drive);
756 pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37);
760 static void hpt370_irq_timeout(ide_drive_t *drive)
762 ide_hwif_t *hwif = HWIF(drive);
766 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
767 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
769 /* get DMA command mode */
770 dma_cmd = hwif->INB(hwif->dma_command);
772 hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
773 hpt370_clear_engine(drive);
776 static void hpt370_ide_dma_start(ide_drive_t *drive)
778 #ifdef HPT_RESET_STATE_ENGINE
779 hpt370_clear_engine(drive);
781 ide_dma_start(drive);
784 static int hpt370_ide_dma_end(ide_drive_t *drive)
786 ide_hwif_t *hwif = HWIF(drive);
787 u8 dma_stat = hwif->INB(hwif->dma_status);
789 if (dma_stat & 0x01) {
792 dma_stat = hwif->INB(hwif->dma_status);
794 hpt370_irq_timeout(drive);
796 return __ide_dma_end(drive);
799 static void hpt370_dma_timeout(ide_drive_t *drive)
801 hpt370_irq_timeout(drive);
802 ide_dma_timeout(drive);
805 /* returns 1 if DMA IRQ issued, 0 otherwise */
806 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
808 ide_hwif_t *hwif = HWIF(drive);
812 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
814 // printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
818 dma_stat = inb(hwif->dma_status);
819 /* return 1 if INTR asserted */
823 if (!drive->waiting_for_dma)
824 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
825 drive->name, __FUNCTION__);
829 static int hpt374_ide_dma_end(ide_drive_t *drive)
831 ide_hwif_t *hwif = HWIF(drive);
832 struct pci_dev *dev = hwif->pci_dev;
833 u8 mcr = 0, mcr_addr = hwif->select_data;
834 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
836 pci_read_config_byte(dev, 0x6a, &bwsr);
837 pci_read_config_byte(dev, mcr_addr, &mcr);
839 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
840 return __ide_dma_end(drive);
844 * hpt3xxn_set_clock - perform clock switching dance
845 * @hwif: hwif to switch
846 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
848 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
851 static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
853 u8 scr2 = hwif->INB(hwif->dma_master + 0x7b);
855 if ((scr2 & 0x7f) == mode)
858 /* Tristate the bus */
859 hwif->OUTB(0x80, hwif->dma_master + 0x73);
860 hwif->OUTB(0x80, hwif->dma_master + 0x77);
862 /* Switch clock and reset channels */
863 hwif->OUTB(mode, hwif->dma_master + 0x7b);
864 hwif->OUTB(0xc0, hwif->dma_master + 0x79);
867 * Reset the state machines.
868 * NOTE: avoid accidentally enabling the disabled channels.
870 hwif->OUTB(hwif->INB(hwif->dma_master + 0x70) | 0x32,
871 hwif->dma_master + 0x70);
872 hwif->OUTB(hwif->INB(hwif->dma_master + 0x74) | 0x32,
873 hwif->dma_master + 0x74);
876 hwif->OUTB(0x00, hwif->dma_master + 0x79);
878 /* Reconnect channels to bus */
879 hwif->OUTB(0x00, hwif->dma_master + 0x73);
880 hwif->OUTB(0x00, hwif->dma_master + 0x77);
884 * hpt3xxn_rw_disk - prepare for I/O
885 * @drive: drive for command
886 * @rq: block request structure
888 * This is called when a disk I/O is issued to HPT3xxN.
889 * We need it because of the clock switching.
892 static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
894 hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21);
898 * Set/get power state for a drive.
899 * NOTE: affects both drives on each channel.
901 * When we turn the power back on, we need to re-initialize things.
903 #define TRISTATE_BIT 0x8000
905 static int hpt3xx_busproc(ide_drive_t *drive, int state)
907 ide_hwif_t *hwif = HWIF(drive);
908 struct pci_dev *dev = hwif->pci_dev;
909 u8 mcr_addr = hwif->select_data + 2;
910 u8 resetmask = hwif->channel ? 0x80 : 0x40;
914 hwif->bus_state = state;
916 /* Grab the status. */
917 pci_read_config_word(dev, mcr_addr, &mcr);
918 pci_read_config_byte(dev, 0x59, &bsr2);
921 * Set the state. We don't set it if we don't need to do so.
922 * Make sure that the drive knows that it has failed if it's off.
926 if (!(bsr2 & resetmask))
928 hwif->drives[0].failures = hwif->drives[1].failures = 0;
930 pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask);
931 pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT);
934 if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT))
936 mcr &= ~TRISTATE_BIT;
938 case BUSSTATE_TRISTATE:
939 if ((bsr2 & resetmask) && (mcr & TRISTATE_BIT))
947 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
948 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
950 pci_write_config_word(dev, mcr_addr, mcr);
951 pci_write_config_byte(dev, 0x59, bsr2 | resetmask);
956 * hpt37x_calibrate_dpll - calibrate the DPLL
959 * Perform a calibration cycle on the DPLL.
960 * Returns 1 if this succeeds
962 static int __devinit hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
964 u32 dpll = (f_high << 16) | f_low | 0x100;
968 pci_write_config_dword(dev, 0x5c, dpll);
970 /* Wait for oscillator ready */
971 for(i = 0; i < 0x5000; ++i) {
973 pci_read_config_byte(dev, 0x5b, &scr2);
977 /* See if it stays ready (we'll just bail out if it's not yet) */
978 for(i = 0; i < 0x1000; ++i) {
979 pci_read_config_byte(dev, 0x5b, &scr2);
980 /* DPLL destabilized? */
984 /* Turn off tuning, we have the DPLL set */
985 pci_read_config_dword (dev, 0x5c, &dpll);
986 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
990 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
992 struct hpt_info *info = kmalloc(sizeof(struct hpt_info), GFP_KERNEL);
993 unsigned long io_base = pci_resource_start(dev, 4);
994 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
996 enum ata_clock clock;
999 printk(KERN_ERR "%s: out of memory!\n", name);
1004 * Copy everything from a static "template" structure
1005 * to just allocated per-chip hpt_info structure.
1007 memcpy(info, pci_get_drvdata(dev), sizeof(struct hpt_info));
1008 chip_type = info->chip_type;
1010 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1011 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1012 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1013 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1016 * First, try to estimate the PCI clock frequency...
1018 if (chip_type >= HPT370) {
1023 /* Interrupt force enable. */
1024 pci_read_config_byte(dev, 0x5a, &scr1);
1026 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
1029 * HighPoint does this for HPT372A.
1030 * NOTE: This register is only writeable via I/O space.
1032 if (chip_type == HPT372A)
1033 outb(0x0e, io_base + 0x9c);
1036 * Default to PCI clock. Make sure MA15/16 are set to output
1037 * to prevent drives having problems with 40-pin cables.
1039 pci_write_config_byte(dev, 0x5b, 0x23);
1042 * We'll have to read f_CNT value in order to determine
1043 * the PCI clock frequency according to the following ratio:
1045 * f_CNT = Fpci * 192 / Fdpll
1047 * First try reading the register in which the HighPoint BIOS
1048 * saves f_CNT value before reprogramming the DPLL from its
1049 * default setting (which differs for the various chips).
1051 * NOTE: This register is only accessible via I/O space;
1052 * HPT374 BIOS only saves it for the function 0, so we have to
1053 * always read it from there -- no need to check the result of
1054 * pci_get_slot() for the function 0 as the whole device has
1055 * been already "pinned" (via function 1) in init_setup_hpt374()
1057 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1058 struct pci_dev *dev1 = pci_get_slot(dev->bus,
1060 unsigned long io_base = pci_resource_start(dev1, 4);
1062 temp = inl(io_base + 0x90);
1065 temp = inl(io_base + 0x90);
1068 * In case the signature check fails, we'll have to
1069 * resort to reading the f_CNT register itself in hopes
1070 * that nobody has touched the DPLL yet...
1072 if ((temp & 0xFFFFF000) != 0xABCDE000) {
1075 printk(KERN_WARNING "%s: no clock data saved by BIOS\n",
1078 /* Calculate the average value of f_CNT. */
1079 for (temp = i = 0; i < 128; i++) {
1080 pci_read_config_word(dev, 0x78, &f_cnt);
1081 temp += f_cnt & 0x1ff;
1086 f_cnt = temp & 0x1ff;
1088 dpll_clk = info->dpll_clk;
1089 pci_clk = (f_cnt * dpll_clk) / 192;
1091 /* Clamp PCI clock to bands. */
1094 else if(pci_clk < 45)
1096 else if(pci_clk < 55)
1101 printk(KERN_INFO "%s: DPLL base: %d MHz, f_CNT: %d, "
1102 "assuming %d MHz PCI\n", name, dpll_clk, f_cnt, pci_clk);
1106 pci_read_config_dword(dev, 0x40, &itr1);
1108 /* Detect PCI clock by looking at cmd_high_time. */
1109 switch((itr1 >> 8) & 0x07) {
1123 /* Let's assume we'll use PCI clock for the ATA clock... */
1126 clock = ATA_CLOCK_25MHZ;
1130 clock = ATA_CLOCK_33MHZ;
1133 clock = ATA_CLOCK_40MHZ;
1136 clock = ATA_CLOCK_50MHZ;
1139 clock = ATA_CLOCK_66MHZ;
1144 * Only try the DPLL if we don't have a table for the PCI clock that
1145 * we are running at for HPT370/A, always use it for anything newer...
1147 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1148 * We also don't like using the DPLL because this causes glitches
1149 * on PRST-/SRST- when the state engine gets reset...
1151 if (chip_type >= HPT374 || info->settings[clock] == NULL) {
1152 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1156 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1157 * supported/enabled, use 50 MHz DPLL clock otherwise...
1159 if (info->max_ultra == 6) {
1161 clock = ATA_CLOCK_66MHZ;
1162 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
1164 clock = ATA_CLOCK_50MHZ;
1167 if (info->settings[clock] == NULL) {
1168 printk(KERN_ERR "%s: unknown bus timing!\n", name);
1173 /* Select the DPLL clock. */
1174 pci_write_config_byte(dev, 0x5b, 0x21);
1177 * Adjust the DPLL based upon PCI clock, enable it,
1178 * and wait for stabilization...
1180 f_low = (pci_clk * 48) / dpll_clk;
1182 for (adjust = 0; adjust < 8; adjust++) {
1183 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1187 * See if it'll settle at a fractionally different clock
1190 f_low -= adjust >> 1;
1192 f_low += adjust >> 1;
1195 printk(KERN_ERR "%s: DPLL did not stabilize!\n", name);
1200 printk("%s: using %d MHz DPLL clock\n", name, dpll_clk);
1202 /* Mark the fact that we're not using the DPLL. */
1205 printk("%s: using %d MHz PCI clock\n", name, pci_clk);
1209 * Advance the table pointer to a slot which points to the list
1210 * of the register values settings matching the clock being used.
1212 info->settings += clock;
1214 /* Store the clock frequencies. */
1215 info->dpll_clk = dpll_clk;
1216 info->pci_clk = pci_clk;
1218 /* Point to this chip's own instance of the hpt_info structure. */
1219 pci_set_drvdata(dev, info);
1221 if (chip_type >= HPT370) {
1225 * Reset the state engines.
1226 * NOTE: Avoid accidentally enabling the disabled channels.
1228 pci_read_config_byte (dev, 0x50, &mcr1);
1229 pci_read_config_byte (dev, 0x54, &mcr4);
1230 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1231 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1236 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1237 * the MISC. register to stretch the UltraDMA Tss timing.
1238 * NOTE: This register is only writeable via I/O space.
1240 if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
1242 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1247 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1249 struct pci_dev *dev = hwif->pci_dev;
1250 struct hpt_info *info = pci_get_drvdata(dev);
1251 int serialize = HPT_SERIALIZE_IO;
1252 u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02;
1253 u8 chip_type = info->chip_type;
1254 u8 new_mcr, old_mcr = 0;
1256 /* Cache the channel's MISC. control registers' offset */
1257 hwif->select_data = hwif->channel ? 0x54 : 0x50;
1259 hwif->set_pio_mode = &hpt3xx_set_pio_mode;
1260 hwif->speedproc = &hpt3xx_tune_chipset;
1261 hwif->quirkproc = &hpt3xx_quirkproc;
1262 hwif->intrproc = &hpt3xx_intrproc;
1263 hwif->maskproc = &hpt3xx_maskproc;
1264 hwif->busproc = &hpt3xx_busproc;
1266 hwif->udma_filter = &hpt3xx_udma_filter;
1267 hwif->mdma_filter = &hpt3xx_mdma_filter;
1270 * HPT3xxN chips have some complications:
1272 * - on 33 MHz PCI we must clock switch
1273 * - on 66 MHz PCI we must NOT use the PCI clock
1275 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
1277 * Clock is shared between the channels,
1278 * so we'll have to serialize them... :-(
1281 hwif->rw_disk = &hpt3xxn_rw_disk;
1284 /* Serialize access to this device if needed */
1285 if (serialize && hwif->mate)
1286 hwif->serialized = hwif->mate->serialized = 1;
1289 * Disable the "fast interrupt" prediction. Don't hold off
1290 * on interrupts. (== 0x01 despite what the docs say)
1292 pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr);
1294 if (info->chip_type >= HPT374)
1295 new_mcr = old_mcr & ~0x07;
1296 else if (info->chip_type >= HPT370) {
1300 #ifdef HPT_DELAY_INTERRUPT
1305 } else /* HPT366 and HPT368 */
1306 new_mcr = old_mcr & ~0x80;
1308 if (new_mcr != old_mcr)
1309 pci_write_config_byte(dev, hwif->select_data + 1, new_mcr);
1311 if (!hwif->dma_base) {
1312 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1316 hwif->ultra_mask = hwif->cds->udma_mask;
1317 hwif->mwdma_mask = 0x07;
1320 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1321 * address lines to access an external EEPROM. To read valid
1322 * cable detect state the pins must be enabled as inputs.
1324 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1326 * HPT374 PCI function 1
1327 * - set bit 15 of reg 0x52 to enable TCBLID as input
1328 * - set bit 15 of reg 0x56 to enable FCBLID as input
1330 u8 mcr_addr = hwif->select_data + 2;
1333 pci_read_config_word (dev, mcr_addr, &mcr);
1334 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
1335 /* now read cable id register */
1336 pci_read_config_byte (dev, 0x5a, &scr1);
1337 pci_write_config_word(dev, mcr_addr, mcr);
1338 } else if (chip_type >= HPT370) {
1340 * HPT370/372 and 374 pcifn 0
1341 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1345 pci_read_config_byte (dev, 0x5b, &scr2);
1346 pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
1347 /* now read cable id register */
1348 pci_read_config_byte (dev, 0x5a, &scr1);
1349 pci_write_config_byte(dev, 0x5b, scr2);
1351 pci_read_config_byte (dev, 0x5a, &scr1);
1353 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
1354 hwif->cbl = (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1356 hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1358 if (chip_type >= HPT374) {
1359 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1360 hwif->ide_dma_end = &hpt374_ide_dma_end;
1361 } else if (chip_type >= HPT370) {
1362 hwif->dma_start = &hpt370_ide_dma_start;
1363 hwif->ide_dma_end = &hpt370_ide_dma_end;
1364 hwif->dma_timeout = &hpt370_dma_timeout;
1366 hwif->dma_lost_irq = &hpt366_dma_lost_irq;
1370 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
1373 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1375 struct pci_dev *dev = hwif->pci_dev;
1376 u8 masterdma = 0, slavedma = 0;
1377 u8 dma_new = 0, dma_old = 0;
1378 unsigned long flags;
1380 dma_old = hwif->INB(dmabase + 2);
1382 local_irq_save(flags);
1385 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1386 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
1388 if (masterdma & 0x30) dma_new |= 0x20;
1389 if ( slavedma & 0x30) dma_new |= 0x40;
1390 if (dma_new != dma_old)
1391 hwif->OUTB(dma_new, dmabase + 2);
1393 local_irq_restore(flags);
1395 ide_setup_dma(hwif, dmabase, 8);
1398 static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1400 struct pci_dev *dev2;
1402 if (PCI_FUNC(dev->devfn) & 1)
1405 pci_set_drvdata(dev, &hpt374);
1407 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1410 pci_set_drvdata(dev2, &hpt374);
1412 if (dev2->irq != dev->irq) {
1413 /* FIXME: we need a core pci_set_interrupt() */
1414 dev2->irq = dev->irq;
1415 printk(KERN_WARNING "%s: PCI config space interrupt "
1416 "fixed.\n", d->name);
1418 ret = ide_setup_pci_devices(dev, dev2, d);
1423 return ide_setup_pci_device(dev, d);
1426 static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d)
1428 pci_set_drvdata(dev, &hpt372n);
1430 return ide_setup_pci_device(dev, d);
1433 static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1435 struct hpt_info *info;
1438 if (dev->revision > 1) {
1439 d->name = "HPT371N";
1446 * HPT371 chips physically have only one channel, the secondary one,
1447 * but the primary channel registers do exist! Go figure...
1448 * So, we manually disable the non-existing channel here
1449 * (if the BIOS hasn't done this already).
1451 pci_read_config_byte(dev, 0x50, &mcr1);
1453 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1455 pci_set_drvdata(dev, info);
1457 return ide_setup_pci_device(dev, d);
1460 static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d)
1462 struct hpt_info *info;
1464 if (dev->revision > 1) {
1465 d->name = "HPT372N";
1470 pci_set_drvdata(dev, info);
1472 return ide_setup_pci_device(dev, d);
1475 static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d)
1477 struct hpt_info *info;
1479 if (dev->revision > 1) {
1480 d->name = "HPT302N";
1485 pci_set_drvdata(dev, info);
1487 return ide_setup_pci_device(dev, d);
1490 static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1492 struct pci_dev *dev2;
1493 u8 rev = dev->revision;
1494 static char *chipset_names[] = { "HPT366", "HPT366", "HPT368",
1495 "HPT370", "HPT370A", "HPT372",
1497 static struct hpt_info *info[] = { &hpt36x, &hpt36x, &hpt36x,
1498 &hpt370, &hpt370a, &hpt372,
1501 if (PCI_FUNC(dev->devfn) & 1)
1509 * HPT36x chips have one channel per function and have
1510 * both channel enable bits located differently and visible
1511 * to both functions -- really stupid design decision... :-(
1512 * Bit 4 is for the primary channel, bit 5 for the secondary.
1514 d->host_flags |= IDE_HFLAG_SINGLE;
1515 d->enablebits[0].mask = d->enablebits[0].val = 0x10;
1517 d->udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ?
1518 ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2;
1522 d->udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4;
1529 d->udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5;
1533 d->name = chipset_names[rev];
1535 pci_set_drvdata(dev, info[rev]);
1540 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1541 u8 mcr1 = 0, pin1 = 0, pin2 = 0;
1544 pci_set_drvdata(dev2, info[rev]);
1547 * Now we'll have to force both channels enabled if
1548 * at least one of them has been enabled by BIOS...
1550 pci_read_config_byte(dev, 0x50, &mcr1);
1552 pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
1554 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1555 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1556 if (pin1 != pin2 && dev->irq == dev2->irq) {
1557 d->bootable = ON_BOARD;
1558 printk("%s: onboard version of chipset, pin1=%d pin2=%d\n",
1559 d->name, pin1, pin2);
1561 ret = ide_setup_pci_devices(dev, dev2, d);
1567 return ide_setup_pci_device(dev, d);
1570 static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1573 .init_setup = init_setup_hpt366,
1574 .init_chipset = init_chipset_hpt366,
1575 .init_hwif = init_hwif_hpt366,
1576 .init_dma = init_dma_hpt366,
1578 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1579 .bootable = OFF_BOARD,
1581 .pio_mask = ATA_PIO4,
1584 .init_setup = init_setup_hpt372a,
1585 .init_chipset = init_chipset_hpt366,
1586 .init_hwif = init_hwif_hpt366,
1587 .init_dma = init_dma_hpt366,
1589 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1590 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
1591 .bootable = OFF_BOARD,
1593 .pio_mask = ATA_PIO4,
1596 .init_setup = init_setup_hpt302,
1597 .init_chipset = init_chipset_hpt366,
1598 .init_hwif = init_hwif_hpt366,
1599 .init_dma = init_dma_hpt366,
1601 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1602 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
1603 .bootable = OFF_BOARD,
1605 .pio_mask = ATA_PIO4,
1608 .init_setup = init_setup_hpt371,
1609 .init_chipset = init_chipset_hpt366,
1610 .init_hwif = init_hwif_hpt366,
1611 .init_dma = init_dma_hpt366,
1613 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1614 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
1615 .bootable = OFF_BOARD,
1617 .pio_mask = ATA_PIO4,
1620 .init_setup = init_setup_hpt374,
1621 .init_chipset = init_chipset_hpt366,
1622 .init_hwif = init_hwif_hpt366,
1623 .init_dma = init_dma_hpt366,
1625 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1626 .udma_mask = ATA_UDMA5,
1627 .bootable = OFF_BOARD,
1629 .pio_mask = ATA_PIO4,
1632 .init_setup = init_setup_hpt372n,
1633 .init_chipset = init_chipset_hpt366,
1634 .init_hwif = init_hwif_hpt366,
1635 .init_dma = init_dma_hpt366,
1637 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1638 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
1639 .bootable = OFF_BOARD,
1641 .pio_mask = ATA_PIO4,
1646 * hpt366_init_one - called when an HPT366 is found
1647 * @dev: the hpt366 device
1648 * @id: the matching pci id
1650 * Called when the PCI registration layer (or the IDE initialization)
1651 * finds a device matching our IDE device tables.
1653 * NOTE: since we'll have to modify some fields of the ide_pci_device_t
1654 * structure depending on the chip's revision, we'd better pass a local
1655 * copy down the call chain...
1657 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1659 ide_pci_device_t d = hpt366_chipsets[id->driver_data];
1661 return d.init_setup(dev, &d);
1664 static struct pci_device_id hpt366_pci_tbl[] = {
1665 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1666 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1667 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1668 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1669 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1670 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1673 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1675 static struct pci_driver driver = {
1676 .name = "HPT366_IDE",
1677 .id_table = hpt366_pci_tbl,
1678 .probe = hpt366_init_one,
1681 static int __init hpt366_ide_init(void)
1683 return ide_pci_register_driver(&driver);
1686 module_init(hpt366_ide_init);
1688 MODULE_AUTHOR("Andre Hedrick");
1689 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1690 MODULE_LICENSE("GPL");