2 * linux/drivers/ide/pci/cs5530.c Version 0.74 Jul 28 2007
4 * Copyright (C) 2000 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2000 Mark Lord <mlord@pobox.com>
6 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
8 * May be copied or modified under the terms of the GNU General Public License
10 * Development of this chipset driver was funded
11 * by the nice folks at National Semiconductor.
14 * CS5530 documentation available from National Semiconductor.
17 #include <linux/module.h>
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/timer.h>
23 #include <linux/ioport.h>
24 #include <linux/blkdev.h>
25 #include <linux/hdreg.h>
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/ide.h>
34 * cs5530_xfer_set_mode - set a new transfer mode at the drive
35 * @drive: drive to tune
38 * Logging wrapper to the IDE driver speed configuration. This can
39 * probably go away now.
42 static int cs5530_set_xfer_mode (ide_drive_t *drive, u8 mode)
44 printk(KERN_DEBUG "%s: cs5530_set_xfer_mode(%s)\n",
45 drive->name, ide_xfer_verbose(mode));
46 return (ide_config_drive_speed(drive, mode));
50 * Here are the standard PIO mode 0-4 timings for each "format".
51 * Format-0 uses fast data reg timings, with slower command reg timings.
52 * Format-1 uses fast timings for all registers, but won't work with all drives.
54 static unsigned int cs5530_pio_timings[2][5] = {
55 {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
56 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
60 * After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
62 #define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
63 #define CS5530_BASEREG(hwif) (((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))
65 static void cs5530_tunepio(ide_drive_t *drive, u8 pio)
67 unsigned long basereg = CS5530_BASEREG(drive->hwif);
68 unsigned int format = (inl(basereg + 4) >> 31) & 1;
70 outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3));
74 * cs5530_tuneproc - select/set PIO modes
76 * cs5530_tuneproc() handles selection/setting of PIO modes
77 * for both the chipset and drive.
79 * The ide_init_cs5530() routine guarantees that all drives
80 * will have valid default PIO timings set up before we get here.
83 static void cs5530_tuneproc (ide_drive_t *drive, u8 pio) /* pio=255 means "autotune" */
85 pio = ide_get_best_pio_mode(drive, pio, 4);
87 if (cs5530_set_xfer_mode(drive, XFER_PIO_0 + pio) == 0)
88 cs5530_tunepio(drive, pio);
92 * cs5530_udma_filter - UDMA filter
95 * cs5530_udma_filter() does UDMA mask filtering for the given drive
96 * taking into the consideration capabilities of the mate device.
98 * The CS5530 specifies that two drives sharing a cable cannot mix
99 * UDMA/MDMA. It has to be one or the other, for the pair, though
100 * different timings can still be chosen for each drive. We could
101 * set the appropriate timing bits on the fly, but that might be
102 * a bit confusing. So, for now we statically handle this requirement
103 * by looking at our mate drive to see what it is capable of, before
104 * choosing a mode for our own drive.
106 * Note: This relies on the fact we never fail from UDMA to MWDMA2
107 * but instead drop to PIO.
110 static u8 cs5530_udma_filter(ide_drive_t *drive)
112 ide_hwif_t *hwif = drive->hwif;
113 ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1];
114 struct hd_driveid *mateid = mate->id;
115 u8 mask = hwif->ultra_mask;
117 if (mate->present == 0)
120 if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) {
121 if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
123 if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
131 * cs5530_config_dma - set DMA/UDMA mode
132 * @drive: drive to tune
134 * cs5530_config_dma() handles setting of DMA/UDMA mode
135 * for both the chipset and drive.
138 static int cs5530_config_dma(ide_drive_t *drive)
140 if (ide_tune_dma(drive))
146 static int cs5530_tune_chipset(ide_drive_t *drive, const u8 mode)
148 unsigned long basereg;
149 unsigned int reg, timings = 0;
152 * Tell the drive to switch to the new mode; abort on failure.
154 if (cs5530_set_xfer_mode(drive, mode))
155 return 1; /* failure */
158 * Now tune the chipset to match the drive:
161 case XFER_UDMA_0: timings = 0x00921250; break;
162 case XFER_UDMA_1: timings = 0x00911140; break;
163 case XFER_UDMA_2: timings = 0x00911030; break;
164 case XFER_MW_DMA_0: timings = 0x00077771; break;
165 case XFER_MW_DMA_1: timings = 0x00012121; break;
166 case XFER_MW_DMA_2: timings = 0x00002020; break;
172 cs5530_tunepio(drive, mode - XFER_PIO_0);
178 basereg = CS5530_BASEREG(drive->hwif);
179 reg = inl(basereg + 4); /* get drive0 config register */
180 timings |= reg & 0x80000000; /* preserve PIO format bit */
181 if ((drive-> dn & 1) == 0) { /* are we configuring drive0? */
182 outl(timings, basereg + 4); /* write drive0 config register */
184 if (timings & 0x00100000)
185 reg |= 0x00100000; /* enable UDMA timings for both drives */
187 reg &= ~0x00100000; /* disable UDMA timings for both drives */
188 outl(reg, basereg + 4); /* write drive0 config register */
189 outl(timings, basereg + 12); /* write drive1 config register */
192 return 0; /* success */
196 * init_chipset_5530 - set up 5530 bridge
200 * Initialize the cs5530 bridge for reliable IDE DMA operation.
203 static unsigned int __devinit init_chipset_cs5530 (struct pci_dev *dev, const char *name)
205 struct pci_dev *master_0 = NULL, *cs5530_0 = NULL;
208 if (pci_resource_start(dev, 4) == 0)
212 while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
213 switch (dev->device) {
214 case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
215 master_0 = pci_dev_get(dev);
217 case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
218 cs5530_0 = pci_dev_get(dev);
223 printk(KERN_ERR "%s: unable to locate PCI MASTER function\n", name);
227 printk(KERN_ERR "%s: unable to locate CS5530 LEGACY function\n", name);
231 spin_lock_irqsave(&ide_lock, flags);
232 /* all CPUs (there should only be one CPU with this chipset) */
235 * Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
236 * --> OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
239 pci_set_master(cs5530_0);
240 pci_try_set_mwi(cs5530_0);
243 * Set PCI CacheLineSize to 16-bytes:
244 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
247 pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
250 * Disable trapping of UDMA register accesses (Win98 hack):
251 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
254 pci_write_config_word(cs5530_0, 0xd0, 0x5006);
257 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
258 * The other settings are what is necessary to get the register
259 * into a sane state for IDE DMA operation.
262 pci_write_config_byte(master_0, 0x40, 0x1e);
265 * Set max PCI burst size (16-bytes seems to work best):
266 * 16bytes: set bit-1 at 0x41 (reg value of 0x16)
267 * all others: clear bit-1 at 0x41, and do:
268 * 128bytes: OR 0x00 at 0x41
269 * 256bytes: OR 0x04 at 0x41
270 * 512bytes: OR 0x08 at 0x41
271 * 1024bytes: OR 0x0c at 0x41
274 pci_write_config_byte(master_0, 0x41, 0x14);
277 * These settings are necessary to get the chip
278 * into a sane state for IDE DMA operation.
281 pci_write_config_byte(master_0, 0x42, 0x00);
282 pci_write_config_byte(master_0, 0x43, 0xc1);
284 spin_unlock_irqrestore(&ide_lock, flags);
287 pci_dev_put(master_0);
288 pci_dev_put(cs5530_0);
293 * init_hwif_cs5530 - initialise an IDE channel
294 * @hwif: IDE to initialize
296 * This gets invoked by the IDE driver once for each channel. It
297 * performs channel-specific pre-initialization before drive probing.
300 static void __devinit init_hwif_cs5530 (ide_hwif_t *hwif)
302 unsigned long basereg;
307 hwif->serialized = hwif->mate->serialized = 1;
309 hwif->tuneproc = &cs5530_tuneproc;
310 hwif->speedproc = &cs5530_tune_chipset;
312 basereg = CS5530_BASEREG(hwif);
313 d0_timings = inl(basereg + 0);
314 if (CS5530_BAD_PIO(d0_timings)) {
315 /* PIO timings not initialized? */
316 outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0);
317 if (!hwif->drives[0].autotune)
318 hwif->drives[0].autotune = 1;
319 /* needs autotuning later */
321 if (CS5530_BAD_PIO(inl(basereg + 8))) {
322 /* PIO timings not initialized? */
323 outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8);
324 if (!hwif->drives[1].autotune)
325 hwif->drives[1].autotune = 1;
326 /* needs autotuning later */
329 if (hwif->dma_base == 0)
333 hwif->ultra_mask = 0x07;
334 hwif->mwdma_mask = 0x07;
336 hwif->udma_filter = cs5530_udma_filter;
337 hwif->ide_dma_check = &cs5530_config_dma;
340 hwif->drives[0].autodma = hwif->autodma;
341 hwif->drives[1].autodma = hwif->autodma;
344 static ide_pci_device_t cs5530_chipset __devinitdata = {
346 .init_chipset = init_chipset_cs5530,
347 .init_hwif = init_hwif_cs5530,
349 .bootable = ON_BOARD,
350 .pio_mask = ATA_PIO4,
353 static int __devinit cs5530_init_one(struct pci_dev *dev, const struct pci_device_id *id)
355 return ide_setup_pci_device(dev, &cs5530_chipset);
358 static struct pci_device_id cs5530_pci_tbl[] = {
359 { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
362 MODULE_DEVICE_TABLE(pci, cs5530_pci_tbl);
364 static struct pci_driver driver = {
365 .name = "CS5530 IDE",
366 .id_table = cs5530_pci_tbl,
367 .probe = cs5530_init_one,
370 static int __init cs5530_ide_init(void)
372 return ide_pci_register_driver(&driver);
375 module_init(cs5530_ide_init);
377 MODULE_AUTHOR("Mark Lord");
378 MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
379 MODULE_LICENSE("GPL");