2 * BRIEF MODULE DESCRIPTION
3 * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
5 * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
7 * This program is free software; you can redistribute it and/or modify it under
8 * the terms of the GNU General Public License as published by the Free Software
9 * Foundation; either version 2 of the License, or (at your option) any later
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
13 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
14 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
15 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
16 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
17 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
18 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
19 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
20 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
21 * POSSIBILITY OF SUCH DAMAGE.
23 * You should have received a copy of the GNU General Public License along with
24 * this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
28 * Interface and Linux Device Driver" Application Note.
30 #include <linux/types.h>
31 #include <linux/module.h>
32 #include <linux/kernel.h>
33 #include <linux/delay.h>
34 #include <linux/platform_device.h>
35 #include <linux/init.h>
36 #include <linux/ide.h>
37 #include <linux/scatterlist.h>
39 #include <asm/mach-au1x00/au1xxx.h>
40 #include <asm/mach-au1x00/au1xxx_dbdma.h>
41 #include <asm/mach-au1x00/au1xxx_ide.h>
43 #define DRV_NAME "au1200-ide"
44 #define DRV_AUTHOR "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
46 /* enable the burstmode in the dbdma */
47 #define IDE_AU1XXX_BURSTMODE 1
49 static _auide_hwif auide_hwif;
51 static int auide_ddma_init(_auide_hwif *auide);
53 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
55 void auide_insw(unsigned long port, void *addr, u32 count)
57 _auide_hwif *ahwif = &auide_hwif;
61 if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1,
63 printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
66 ctp = *((chan_tab_t **)ahwif->rx_chan);
68 while (dp->dscr_cmd0 & DSCR_CMD0_V)
70 ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
73 void auide_outsw(unsigned long port, void *addr, u32 count)
75 _auide_hwif *ahwif = &auide_hwif;
79 if(!put_source_flags(ahwif->tx_chan, (void*)addr,
80 count << 1, DDMA_FLAGS_NOIE)) {
81 printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
84 ctp = *((chan_tab_t **)ahwif->tx_chan);
86 while (dp->dscr_cmd0 & DSCR_CMD0_V)
88 ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
93 static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio)
95 int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
100 mem_sttime = SBC_IDE_TIMING(PIO0);
102 /* set configuration for RCS2# */
103 mem_stcfg |= TS_MASK;
104 mem_stcfg &= ~TCSOE_MASK;
105 mem_stcfg &= ~TOECS_MASK;
106 mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
110 mem_sttime = SBC_IDE_TIMING(PIO1);
112 /* set configuration for RCS2# */
113 mem_stcfg |= TS_MASK;
114 mem_stcfg &= ~TCSOE_MASK;
115 mem_stcfg &= ~TOECS_MASK;
116 mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
120 mem_sttime = SBC_IDE_TIMING(PIO2);
122 /* set configuration for RCS2# */
123 mem_stcfg &= ~TS_MASK;
124 mem_stcfg &= ~TCSOE_MASK;
125 mem_stcfg &= ~TOECS_MASK;
126 mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
130 mem_sttime = SBC_IDE_TIMING(PIO3);
132 /* set configuration for RCS2# */
133 mem_stcfg &= ~TS_MASK;
134 mem_stcfg &= ~TCSOE_MASK;
135 mem_stcfg &= ~TOECS_MASK;
136 mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;
141 mem_sttime = SBC_IDE_TIMING(PIO4);
143 /* set configuration for RCS2# */
144 mem_stcfg &= ~TS_MASK;
145 mem_stcfg &= ~TCSOE_MASK;
146 mem_stcfg &= ~TOECS_MASK;
147 mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
151 au_writel(mem_sttime,MEM_STTIME2);
152 au_writel(mem_stcfg,MEM_STCFG2);
155 static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed)
157 int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
160 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
162 mem_sttime = SBC_IDE_TIMING(MDMA2);
164 /* set configuration for RCS2# */
165 mem_stcfg &= ~TS_MASK;
166 mem_stcfg &= ~TCSOE_MASK;
167 mem_stcfg &= ~TOECS_MASK;
168 mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;
172 mem_sttime = SBC_IDE_TIMING(MDMA1);
174 /* set configuration for RCS2# */
175 mem_stcfg &= ~TS_MASK;
176 mem_stcfg &= ~TCSOE_MASK;
177 mem_stcfg &= ~TOECS_MASK;
178 mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;
182 mem_sttime = SBC_IDE_TIMING(MDMA0);
184 /* set configuration for RCS2# */
185 mem_stcfg |= TS_MASK;
186 mem_stcfg &= ~TCSOE_MASK;
187 mem_stcfg &= ~TOECS_MASK;
188 mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;
194 au_writel(mem_sttime,MEM_STTIME2);
195 au_writel(mem_stcfg,MEM_STCFG2);
199 * Multi-Word DMA + DbDMA functions
202 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
203 static int auide_build_dmatable(ide_drive_t *drive)
205 int i, iswrite, count = 0;
206 ide_hwif_t *hwif = HWIF(drive);
208 struct request *rq = HWGROUP(drive)->rq;
210 _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
211 struct scatterlist *sg;
213 iswrite = (rq_data_dir(rq) == WRITE);
214 /* Save for interrupt context */
215 ahwif->drive = drive;
217 hwif->sg_nents = i = ide_build_sglist(drive, rq);
222 /* fill the descriptors */
224 while (i && sg_dma_len(sg)) {
228 cur_addr = sg_dma_address(sg);
229 cur_len = sg_dma_len(sg);
232 u32 flags = DDMA_FLAGS_NOIE;
233 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
235 if (++count >= PRD_ENTRIES) {
236 printk(KERN_WARNING "%s: DMA table too small\n",
238 goto use_pio_instead;
241 /* Lets enable intr for the last descriptor only */
243 flags = DDMA_FLAGS_IE;
245 flags = DDMA_FLAGS_NOIE;
248 if(!put_source_flags(ahwif->tx_chan,
251 printk(KERN_ERR "%s failed %d\n",
256 if(!put_dest_flags(ahwif->rx_chan,
259 printk(KERN_ERR "%s failed %d\n",
275 ide_destroy_dmatable(drive);
277 return 0; /* revert to PIO for this request */
280 static int auide_dma_end(ide_drive_t *drive)
282 ide_hwif_t *hwif = HWIF(drive);
284 if (hwif->sg_nents) {
285 ide_destroy_dmatable(drive);
292 static void auide_dma_start(ide_drive_t *drive )
297 static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command)
299 /* issue cmd to drive */
300 ide_execute_command(drive, command, &ide_dma_intr,
304 static int auide_dma_setup(ide_drive_t *drive)
306 struct request *rq = HWGROUP(drive)->rq;
308 if (!auide_build_dmatable(drive)) {
309 ide_map_sg(drive, rq);
313 drive->waiting_for_dma = 1;
317 static int auide_dma_test_irq(ide_drive_t *drive)
319 if (drive->waiting_for_dma == 0)
320 printk(KERN_WARNING "%s: ide_dma_test_irq \
321 called while not waiting\n", drive->name);
323 /* If dbdma didn't execute the STOP command yet, the
324 * active bit is still set
326 drive->waiting_for_dma++;
327 if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
328 printk(KERN_WARNING "%s: timeout waiting for ddma to \
329 complete\n", drive->name);
336 static void auide_dma_host_set(ide_drive_t *drive, int on)
340 static void auide_dma_lost_irq(ide_drive_t *drive)
342 printk(KERN_ERR "%s: IRQ lost\n", drive->name);
345 static void auide_ddma_tx_callback(int irq, void *param)
347 _auide_hwif *ahwif = (_auide_hwif*)param;
348 ahwif->drive->waiting_for_dma = 0;
351 static void auide_ddma_rx_callback(int irq, void *param)
353 _auide_hwif *ahwif = (_auide_hwif*)param;
354 ahwif->drive->waiting_for_dma = 0;
357 #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
359 static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
361 dev->dev_id = dev_id;
362 dev->dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR;
363 dev->dev_intlevel = 0;
364 dev->dev_intpolarity = 0;
365 dev->dev_tsize = tsize;
366 dev->dev_devwidth = devwidth;
367 dev->dev_flags = flags;
370 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
372 static void auide_dma_timeout(ide_drive_t *drive)
374 ide_hwif_t *hwif = HWIF(drive);
376 printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
378 if (hwif->ide_dma_test_irq(drive))
381 hwif->ide_dma_end(drive);
384 static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
386 _auide_hwif *auide = (_auide_hwif *)hwif->hwif_data;
387 dbdev_tab_t source_dev_tab, target_dev_tab;
388 u32 dev_id, tsize, devwidth, flags;
390 dev_id = AU1XXX_ATA_DDMA_REQ;
393 devwidth = 32; /* 16 */
395 #ifdef IDE_AU1XXX_BURSTMODE
396 flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
398 flags = DEV_FLAGS_SYNC;
401 /* setup dev_tab for tx channel */
402 auide_init_dbdma_dev( &source_dev_tab,
404 tsize, devwidth, DEV_FLAGS_OUT | flags);
405 auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
407 auide_init_dbdma_dev( &source_dev_tab,
409 tsize, devwidth, DEV_FLAGS_IN | flags);
410 auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
412 /* We also need to add a target device for the DMA */
413 auide_init_dbdma_dev( &target_dev_tab,
414 (u32)DSCR_CMD0_ALWAYS,
415 tsize, devwidth, DEV_FLAGS_ANYUSE);
416 auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);
418 /* Get a channel for TX */
419 auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
421 auide_ddma_tx_callback,
424 /* Get a channel for RX */
425 auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
426 auide->target_dev_id,
427 auide_ddma_rx_callback,
430 auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
432 auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
435 hwif->dmatable_cpu = dma_alloc_coherent(hwif->dev,
436 PRD_ENTRIES * PRD_BYTES, /* 1 Page */
437 &hwif->dmatable_dma, GFP_KERNEL);
439 au1xxx_dbdma_start( auide->tx_chan );
440 au1xxx_dbdma_start( auide->rx_chan );
445 static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
447 _auide_hwif *auide = (_auide_hwif *)hwif->hwif_data;
448 dbdev_tab_t source_dev_tab;
451 #ifdef IDE_AU1XXX_BURSTMODE
452 flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
454 flags = DEV_FLAGS_SYNC;
457 /* setup dev_tab for tx channel */
458 auide_init_dbdma_dev( &source_dev_tab,
459 (u32)DSCR_CMD0_ALWAYS,
460 8, 32, DEV_FLAGS_OUT | flags);
461 auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
463 auide_init_dbdma_dev( &source_dev_tab,
464 (u32)DSCR_CMD0_ALWAYS,
465 8, 32, DEV_FLAGS_IN | flags);
466 auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
468 /* Get a channel for TX */
469 auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
474 /* Get a channel for RX */
475 auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
480 auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
482 auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
485 au1xxx_dbdma_start( auide->tx_chan );
486 au1xxx_dbdma_start( auide->rx_chan );
492 static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
495 unsigned long *ata_regs = hw->io_ports;
498 for (i = 0; i < IDE_CONTROL_OFFSET; i++) {
499 *ata_regs++ = ahwif->regbase + (i << AU1XXX_ATA_REG_OFFSET);
502 /* set the Alternative Status register */
503 *ata_regs = ahwif->regbase + (14 << AU1XXX_ATA_REG_OFFSET);
506 static const struct ide_port_ops au1xxx_port_ops = {
507 .set_pio_mode = au1xxx_set_pio_mode,
508 .set_dma_mode = auide_set_dma_mode,
511 static const struct ide_port_info au1xxx_port_info = {
512 .init_dma = auide_ddma_init,
513 .port_ops = &au1xxx_port_ops,
514 .host_flags = IDE_HFLAG_POST_SET_MODE |
515 IDE_HFLAG_NO_IO_32BIT |
516 IDE_HFLAG_UNMASK_IRQS,
517 .pio_mask = ATA_PIO4,
518 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
519 .mwdma_mask = ATA_MWDMA2,
523 static int au_ide_probe(struct device *dev)
525 struct platform_device *pdev = to_platform_device(dev);
526 _auide_hwif *ahwif = &auide_hwif;
528 struct resource *res;
530 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
533 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
534 char *mode = "MWDMA2";
535 #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
536 char *mode = "PIO+DDMA(offload)";
539 memset(&auide_hwif, 0, sizeof(_auide_hwif));
540 ahwif->irq = platform_get_irq(pdev, 0);
542 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
545 pr_debug("%s %d: no base address\n", DRV_NAME, pdev->id);
549 if (ahwif->irq < 0) {
550 pr_debug("%s %d: no IRQ\n", DRV_NAME, pdev->id);
555 if (!request_mem_region(res->start, res->end - res->start + 1,
557 pr_debug("%s: request_mem_region failed\n", DRV_NAME);
562 ahwif->regbase = (u32)ioremap(res->start, res->end - res->start + 1);
563 if (ahwif->regbase == 0) {
568 hwif = ide_find_port();
574 memset(&hw, 0, sizeof(hw));
575 auide_setup_ports(&hw, ahwif);
578 hw.chipset = ide_au1xxx;
580 ide_init_port_hw(hwif, &hw);
584 /* If the user has selected DDMA assisted copies,
585 then set up a few local I/O function entry points
588 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
589 hwif->INSW = auide_insw;
590 hwif->OUTSW = auide_outsw;
592 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
593 hwif->dma_timeout = &auide_dma_timeout;
594 hwif->dma_host_set = &auide_dma_host_set;
595 hwif->dma_exec_cmd = &auide_dma_exec_cmd;
596 hwif->dma_start = &auide_dma_start;
597 hwif->ide_dma_end = &auide_dma_end;
598 hwif->dma_setup = &auide_dma_setup;
599 hwif->ide_dma_test_irq = &auide_dma_test_irq;
600 hwif->dma_lost_irq = &auide_dma_lost_irq;
602 hwif->select_data = 0; /* no chipset-specific code */
603 hwif->config_data = 0; /* no chipset-specific code */
605 auide_hwif.hwif = hwif;
606 hwif->hwif_data = &auide_hwif;
608 idx[0] = hwif->index;
610 ide_device_add(idx, &au1xxx_port_info);
612 dev_set_drvdata(dev, hwif);
614 printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
620 static int au_ide_remove(struct device *dev)
622 struct platform_device *pdev = to_platform_device(dev);
623 struct resource *res;
624 ide_hwif_t *hwif = dev_get_drvdata(dev);
625 _auide_hwif *ahwif = &auide_hwif;
627 ide_unregister(hwif->index);
629 iounmap((void *)ahwif->regbase);
631 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
632 release_mem_region(res->start, res->end - res->start + 1);
637 static struct device_driver au1200_ide_driver = {
638 .name = "au1200-ide",
639 .bus = &platform_bus_type,
640 .probe = au_ide_probe,
641 .remove = au_ide_remove,
644 static int __init au_ide_init(void)
646 return driver_register(&au1200_ide_driver);
649 static void __exit au_ide_exit(void)
651 driver_unregister(&au1200_ide_driver);
654 MODULE_LICENSE("GPL");
655 MODULE_DESCRIPTION("AU1200 IDE driver");
657 module_init(au_ide_init);
658 module_exit(au_ide_exit);