2 * i2c-au1550.c: SMBus (i2c) adapter for Alchemy PSC interface
3 * Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com>
5 * 2.6 port by Matt Porter <mporter@kernel.crashing.org>
7 * The documentation describes this as an SMBus controller, but it doesn't
8 * understand any of the SMBus protocol in hardware. It's really an I2C
9 * controller that could emulate most of the SMBus in software.
11 * This is just a skeleton adapter to use with the Au1550 PSC
12 * algorithm. It was developed for the Pb1550, but will work with
13 * any Au1550 board that has a similar PSC configuration.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version 2
18 * of the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 #include <linux/config.h>
31 #include <linux/delay.h>
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/init.h>
35 #include <linux/errno.h>
36 #include <linux/i2c.h>
38 #include <asm/mach-au1x00/au1000.h>
39 #include <asm/mach-pb1x00/pb1550.h>
40 #include <asm/mach-au1x00/au1xxx_psc.h>
42 #include "i2c-au1550.h"
45 wait_xfer_done(struct i2c_au1550_data *adap)
49 volatile psc_smb_t *sp;
51 sp = (volatile psc_smb_t *)(adap->psc_base);
53 /* Wait for Tx FIFO Underflow.
55 for (i = 0; i < adap->xfer_timeout; i++) {
56 stat = sp->psc_smbevnt;
58 if ((stat & PSC_SMBEVNT_TU) != 0) {
60 sp->psc_smbevnt = PSC_SMBEVNT_TU;
71 wait_ack(struct i2c_au1550_data *adap)
74 volatile psc_smb_t *sp;
76 if (wait_xfer_done(adap))
79 sp = (volatile psc_smb_t *)(adap->psc_base);
81 stat = sp->psc_smbevnt;
84 if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0)
91 wait_master_done(struct i2c_au1550_data *adap)
95 volatile psc_smb_t *sp;
97 sp = (volatile psc_smb_t *)(adap->psc_base);
99 /* Wait for Master Done.
101 for (i = 0; i < adap->xfer_timeout; i++) {
102 stat = sp->psc_smbevnt;
104 if ((stat & PSC_SMBEVNT_MD) != 0)
113 do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd)
115 volatile psc_smb_t *sp;
118 sp = (volatile psc_smb_t *)(adap->psc_base);
120 /* Reset the FIFOs, clear events.
122 sp->psc_smbpcr = PSC_SMBPCR_DC;
123 sp->psc_smbevnt = PSC_SMBEVNT_ALLCLR;
126 stat = sp->psc_smbpcr;
128 } while ((stat & PSC_SMBPCR_DC) != 0);
130 /* Write out the i2c chip address and specify operation
136 /* Put byte into fifo, start up master.
138 sp->psc_smbtxrx = addr;
140 sp->psc_smbpcr = PSC_SMBPCR_MS;
148 wait_for_rx_byte(struct i2c_au1550_data *adap, u32 *ret_data)
152 volatile psc_smb_t *sp;
154 if (wait_xfer_done(adap))
157 sp = (volatile psc_smb_t *)(adap->psc_base);
159 j = adap->xfer_timeout * 100;
165 stat = sp->psc_smbstat;
167 if ((stat & PSC_SMBSTAT_RE) == 0)
172 data = sp->psc_smbtxrx;
180 i2c_read(struct i2c_au1550_data *adap, unsigned char *buf,
185 volatile psc_smb_t *sp;
190 /* A read is performed by stuffing the transmit fifo with
191 * zero bytes for timing, waiting for bytes to appear in the
192 * receive fifo, then reading the bytes.
195 sp = (volatile psc_smb_t *)(adap->psc_base);
198 while (i < (len-1)) {
201 if (wait_for_rx_byte(adap, &data))
208 /* The last byte has to indicate transfer done.
210 sp->psc_smbtxrx = PSC_SMBTXRX_STP;
212 if (wait_master_done(adap))
215 data = sp->psc_smbtxrx;
222 i2c_write(struct i2c_au1550_data *adap, unsigned char *buf,
227 volatile psc_smb_t *sp;
232 sp = (volatile psc_smb_t *)(adap->psc_base);
235 while (i < (len-1)) {
237 sp->psc_smbtxrx = data;
244 /* The last byte has to indicate transfer done.
247 data |= PSC_SMBTXRX_STP;
248 sp->psc_smbtxrx = data;
250 if (wait_master_done(adap))
256 au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
258 struct i2c_au1550_data *adap = i2c_adap->algo_data;
262 for (i = 0; !err && i < num; i++) {
264 err = do_address(adap, p->addr, p->flags & I2C_M_RD);
267 if (p->flags & I2C_M_RD)
268 err = i2c_read(adap, p->buf, p->len);
270 err = i2c_write(adap, p->buf, p->len);
273 /* Return the number of messages processed, or the error code.
281 au1550_func(struct i2c_adapter *adap)
286 static struct i2c_algorithm au1550_algo = {
287 .name = "Au1550 algorithm",
288 .id = I2C_ALGO_AU1550,
289 .master_xfer = au1550_xfer,
290 .functionality = au1550_func,
294 * registering functions to load algorithms at runtime
295 * Prior to calling us, the 50MHz clock frequency and routing
296 * must have been set up for the PSC indicated by the adapter.
299 i2c_au1550_add_bus(struct i2c_adapter *i2c_adap)
301 struct i2c_au1550_data *adap = i2c_adap->algo_data;
302 volatile psc_smb_t *sp;
305 i2c_adap->algo = &au1550_algo;
307 /* Now, set up the PSC for SMBus PIO mode.
309 sp = (volatile psc_smb_t *)(adap->psc_base);
310 sp->psc_ctrl = PSC_CTRL_DISABLE;
312 sp->psc_sel = PSC_SEL_PS_SMBUSMODE;
315 sp->psc_ctrl = PSC_CTRL_ENABLE;
318 stat = sp->psc_smbstat;
320 } while ((stat & PSC_SMBSTAT_SR) == 0);
322 sp->psc_smbcfg = (PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 |
323 PSC_SMBCFG_DD_DISABLE);
325 /* Divide by 8 to get a 6.25 MHz clock. The later protocol
326 * timings are based on this clock.
328 sp->psc_smbcfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8);
329 sp->psc_smbmsk = PSC_SMBMSK_ALLMASK;
332 /* Set the protocol timer values. See Table 71 in the
333 * Au1550 Data Book for standard timing values.
335 sp->psc_smbtmr = PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(15) | \
336 PSC_SMBTMR_SET_PU(15) | PSC_SMBTMR_SET_SH(15) | \
337 PSC_SMBTMR_SET_SU(15) | PSC_SMBTMR_SET_CL(15) | \
338 PSC_SMBTMR_SET_CH(15);
341 sp->psc_smbcfg |= PSC_SMBCFG_DE_ENABLE;
343 stat = sp->psc_smbstat;
345 } while ((stat & PSC_SMBSTAT_DR) == 0);
347 return i2c_add_adapter(i2c_adap);
352 i2c_au1550_del_bus(struct i2c_adapter *adap)
354 return i2c_del_adapter(adap);
358 pb1550_reg(struct i2c_client *client)
364 pb1550_unreg(struct i2c_client *client)
369 static struct i2c_au1550_data pb1550_i2c_info = {
370 SMBUS_PSC_BASE, 200, 200
373 static struct i2c_adapter pb1550_board_adapter = {
374 name: "pb1550 adapter",
375 id: I2C_HW_AU1550_PSC,
377 algo_data: &pb1550_i2c_info,
378 client_register: pb1550_reg,
379 client_unregister: pb1550_unreg,
382 /* BIG hack to support the control interface on the Wolfson WM8731
383 * audio codec on the Pb1550 board. We get an address and two data
384 * bytes to write, create an i2c message, and send it across the
385 * i2c transfer function. We do this here because we have access to
386 * the i2c adapter structure.
388 static struct i2c_msg wm_i2c_msg; /* We don't want this stuff on the stack */
392 pb1550_wm_codec_write(u8 addr, u8 reg, u8 val)
394 wm_i2c_msg.addr = addr;
395 wm_i2c_msg.flags = 0;
396 wm_i2c_msg.buf = i2cbuf;
401 return pb1550_board_adapter.algo->master_xfer(&pb1550_board_adapter, &wm_i2c_msg, 1);
405 i2c_au1550_init(void)
407 printk(KERN_INFO "Au1550 I2C: ");
409 /* This is where we would set up a 50MHz clock source
410 * and routing. On the Pb1550, the SMBus is PSC2, which
411 * uses a shared clock with USB. This has been already
412 * configured by Yamon as a 48MHz clock, close enough
415 if (i2c_au1550_add_bus(&pb1550_board_adapter) < 0) {
416 printk("failed to initialize.\n");
420 printk("initialized.\n");
425 i2c_au1550_exit(void)
427 i2c_au1550_del_bus(&pb1550_board_adapter);
430 MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC.");
431 MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550");
432 MODULE_LICENSE("GPL");
434 module_init (i2c_au1550_init);
435 module_exit (i2c_au1550_exit);