2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/gfp.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/pci.h>
32 #include <linux/spinlock.h>
35 #include <asm/system.h>
37 #ifdef CONFIG_PPC_PMAC
38 #include <asm/pmac_feature.h>
42 #include "fw-transaction.h"
44 #define DESCRIPTOR_OUTPUT_MORE 0
45 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
46 #define DESCRIPTOR_INPUT_MORE (2 << 12)
47 #define DESCRIPTOR_INPUT_LAST (3 << 12)
48 #define DESCRIPTOR_STATUS (1 << 11)
49 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
50 #define DESCRIPTOR_PING (1 << 7)
51 #define DESCRIPTOR_YY (1 << 6)
52 #define DESCRIPTOR_NO_IRQ (0 << 4)
53 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
54 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
55 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
56 #define DESCRIPTOR_WAIT (3 << 0)
62 __le32 branch_address;
64 __le16 transfer_status;
65 } __attribute__((aligned(16)));
67 struct db_descriptor {
70 __le16 second_req_count;
71 __le16 first_req_count;
72 __le32 branch_address;
73 __le16 second_res_count;
74 __le16 first_res_count;
79 } __attribute__((aligned(16)));
81 #define CONTROL_SET(regs) (regs)
82 #define CONTROL_CLEAR(regs) ((regs) + 4)
83 #define COMMAND_PTR(regs) ((regs) + 12)
84 #define CONTEXT_MATCH(regs) ((regs) + 16)
87 struct descriptor descriptor;
88 struct ar_buffer *next;
94 struct ar_buffer *current_buffer;
95 struct ar_buffer *last_buffer;
98 struct tasklet_struct tasklet;
103 typedef int (*descriptor_callback_t)(struct context *ctx,
104 struct descriptor *d,
105 struct descriptor *last);
108 * A buffer that contains a block of DMA-able coherent memory used for
109 * storing a portion of a DMA descriptor program.
111 struct descriptor_buffer {
112 struct list_head list;
113 dma_addr_t buffer_bus;
116 struct descriptor buffer[0];
120 struct fw_ohci *ohci;
122 int total_allocation;
125 * List of page-sized buffers for storing DMA descriptors.
126 * Head of list contains buffers in use and tail of list contains
129 struct list_head buffer_list;
132 * Pointer to a buffer inside buffer_list that contains the tail
133 * end of the current DMA program.
135 struct descriptor_buffer *buffer_tail;
138 * The descriptor containing the branch address of the first
139 * descriptor that has not yet been filled by the device.
141 struct descriptor *last;
144 * The last descriptor in the DMA program. It contains the branch
145 * address that must be updated upon appending a new descriptor.
147 struct descriptor *prev;
149 descriptor_callback_t callback;
151 struct tasklet_struct tasklet;
154 #define IT_HEADER_SY(v) ((v) << 0)
155 #define IT_HEADER_TCODE(v) ((v) << 4)
156 #define IT_HEADER_CHANNEL(v) ((v) << 8)
157 #define IT_HEADER_TAG(v) ((v) << 14)
158 #define IT_HEADER_SPEED(v) ((v) << 16)
159 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
162 struct fw_iso_context base;
163 struct context context;
166 size_t header_length;
169 #define CONFIG_ROM_SIZE 1024
175 __iomem char *registers;
176 dma_addr_t self_id_bus;
178 struct tasklet_struct bus_reset_tasklet;
181 int request_generation;
186 * Spinlock for accessing fw_ohci data. Never call out of
187 * this driver with this lock held.
190 u32 self_id_buffer[512];
192 /* Config rom buffers */
194 dma_addr_t config_rom_bus;
195 __be32 *next_config_rom;
196 dma_addr_t next_config_rom_bus;
199 struct ar_context ar_request_ctx;
200 struct ar_context ar_response_ctx;
201 struct context at_request_ctx;
202 struct context at_response_ctx;
205 struct iso_context *it_context_list;
207 struct iso_context *ir_context_list;
210 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
212 return container_of(card, struct fw_ohci, card);
215 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
216 #define IR_CONTEXT_BUFFER_FILL 0x80000000
217 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
218 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
219 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
220 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
222 #define CONTEXT_RUN 0x8000
223 #define CONTEXT_WAKE 0x1000
224 #define CONTEXT_DEAD 0x0800
225 #define CONTEXT_ACTIVE 0x0400
227 #define OHCI1394_MAX_AT_REQ_RETRIES 0x2
228 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
229 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
231 #define FW_OHCI_MAJOR 240
232 #define OHCI1394_REGISTER_SIZE 0x800
233 #define OHCI_LOOP_COUNT 500
234 #define OHCI1394_PCI_HCI_Control 0x40
235 #define SELF_ID_BUF_SIZE 0x800
236 #define OHCI_TCODE_PHY_PACKET 0x0e
237 #define OHCI_VERSION_1_1 0x010010
239 static char ohci_driver_name[] = KBUILD_MODNAME;
241 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
243 #define OHCI_PARAM_DEBUG_AT_AR 1
244 #define OHCI_PARAM_DEBUG_SELFIDS 2
245 #define OHCI_PARAM_DEBUG_IRQS 4
246 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
248 static int param_debug;
249 module_param_named(debug, param_debug, int, 0644);
250 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
251 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
252 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
253 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
254 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
255 ", or a combination, or all = -1)");
257 static void log_irqs(u32 evt)
259 if (likely(!(param_debug &
260 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
263 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
264 !(evt & OHCI1394_busReset))
267 printk(KERN_DEBUG KBUILD_MODNAME ": IRQ "
268 "%08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
270 evt & OHCI1394_selfIDComplete ? " selfID" : "",
271 evt & OHCI1394_RQPkt ? " AR_req" : "",
272 evt & OHCI1394_RSPkt ? " AR_resp" : "",
273 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
274 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
275 evt & OHCI1394_isochRx ? " IR" : "",
276 evt & OHCI1394_isochTx ? " IT" : "",
277 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
278 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
279 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
280 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
281 evt & OHCI1394_busReset ? " busReset" : "",
282 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
283 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
284 OHCI1394_respTxComplete | OHCI1394_isochRx |
285 OHCI1394_isochTx | OHCI1394_postedWriteErr |
286 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
287 OHCI1394_regAccessFail | OHCI1394_busReset)
291 static const char *speed[] = {
292 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
294 static const char *power[] = {
295 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
296 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
298 static const char port[] = { '.', '-', 'p', 'c', };
300 static char _p(u32 *s, int shift)
302 return port[*s >> shift & 3];
305 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
307 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
310 printk(KERN_DEBUG KBUILD_MODNAME ": %d selfIDs, generation %d, "
311 "local node ID %04x\n", self_id_count, generation, node_id);
313 for (; self_id_count--; ++s)
314 if ((*s & 1 << 23) == 0)
315 printk(KERN_DEBUG "selfID 0: %08x, phy %d [%c%c%c] "
316 "%s gc=%d %s %s%s%s\n",
317 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
318 speed[*s >> 14 & 3], *s >> 16 & 63,
319 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
320 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
322 printk(KERN_DEBUG "selfID n: %08x, phy %d "
323 "[%c%c%c%c%c%c%c%c]\n",
325 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
326 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
329 static const char *evts[] = {
330 [0x00] = "evt_no_status", [0x01] = "-reserved-",
331 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
332 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
333 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
334 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
335 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
336 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
337 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
338 [0x10] = "-reserved-", [0x11] = "ack_complete",
339 [0x12] = "ack_pending ", [0x13] = "-reserved-",
340 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
341 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
342 [0x18] = "-reserved-", [0x19] = "-reserved-",
343 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
344 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
345 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
346 [0x20] = "pending/cancelled",
348 static const char *tcodes[] = {
349 [0x0] = "QW req", [0x1] = "BW req",
350 [0x2] = "W resp", [0x3] = "-reserved-",
351 [0x4] = "QR req", [0x5] = "BR req",
352 [0x6] = "QR resp", [0x7] = "BR resp",
353 [0x8] = "cycle start", [0x9] = "Lk req",
354 [0xa] = "async stream packet", [0xb] = "Lk resp",
355 [0xc] = "-reserved-", [0xd] = "-reserved-",
356 [0xe] = "link internal", [0xf] = "-reserved-",
358 static const char *phys[] = {
359 [0x0] = "phy config packet", [0x1] = "link-on packet",
360 [0x2] = "self-id packet", [0x3] = "-reserved-",
363 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
365 int tcode = header[0] >> 4 & 0xf;
368 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
371 if (unlikely(evt >= ARRAY_SIZE(evts)))
374 if (evt == OHCI1394_evt_bus_reset) {
375 printk(KERN_DEBUG "A%c evt_bus_reset, generation %d\n",
376 dir, (header[2] >> 16) & 0xff);
380 if (header[0] == ~header[1]) {
381 printk(KERN_DEBUG "A%c %s, %s, %08x\n",
382 dir, evts[evt], phys[header[0] >> 30 & 0x3],
388 case 0x0: case 0x6: case 0x8:
389 snprintf(specific, sizeof(specific), " = %08x",
390 be32_to_cpu((__force __be32)header[3]));
392 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
393 snprintf(specific, sizeof(specific), " %x,%x",
394 header[3] >> 16, header[3] & 0xffff);
402 printk(KERN_DEBUG "A%c %s, %s\n",
403 dir, evts[evt], tcodes[tcode]);
405 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
406 printk(KERN_DEBUG "A%c spd %x tl %02x, "
409 dir, speed, header[0] >> 10 & 0x3f,
410 header[1] >> 16, header[0] >> 16, evts[evt],
411 tcodes[tcode], header[1] & 0xffff, header[2], specific);
414 printk(KERN_DEBUG "A%c spd %x tl %02x, "
417 dir, speed, header[0] >> 10 & 0x3f,
418 header[1] >> 16, header[0] >> 16, evts[evt],
419 tcodes[tcode], specific);
425 #define log_irqs(evt)
426 #define log_selfids(node_id, generation, self_id_count, sid)
427 #define log_ar_at_event(dir, speed, header, evt)
429 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
431 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
433 writel(data, ohci->registers + offset);
436 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
438 return readl(ohci->registers + offset);
441 static inline void flush_writes(const struct fw_ohci *ohci)
443 /* Do a dummy read to flush writes. */
444 reg_read(ohci, OHCI1394_Version);
448 ohci_update_phy_reg(struct fw_card *card, int addr,
449 int clear_bits, int set_bits)
451 struct fw_ohci *ohci = fw_ohci(card);
454 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
457 val = reg_read(ohci, OHCI1394_PhyControl);
458 if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
459 fw_error("failed to set phy reg bits.\n");
463 old = OHCI1394_PhyControl_ReadData(val);
464 old = (old & ~clear_bits) | set_bits;
465 reg_write(ohci, OHCI1394_PhyControl,
466 OHCI1394_PhyControl_Write(addr, old));
471 static int ar_context_add_page(struct ar_context *ctx)
473 struct device *dev = ctx->ohci->card.device;
474 struct ar_buffer *ab;
475 dma_addr_t uninitialized_var(ab_bus);
478 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
482 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
483 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
485 DESCRIPTOR_BRANCH_ALWAYS);
486 offset = offsetof(struct ar_buffer, data);
487 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
488 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
489 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
490 ab->descriptor.branch_address = 0;
492 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
493 ctx->last_buffer->next = ab;
494 ctx->last_buffer = ab;
496 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
497 flush_writes(ctx->ohci);
502 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
503 #define cond_le32_to_cpu(v) \
504 (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
506 #define cond_le32_to_cpu(v) le32_to_cpu(v)
509 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
511 struct fw_ohci *ohci = ctx->ohci;
513 u32 status, length, tcode;
516 p.header[0] = cond_le32_to_cpu(buffer[0]);
517 p.header[1] = cond_le32_to_cpu(buffer[1]);
518 p.header[2] = cond_le32_to_cpu(buffer[2]);
520 tcode = (p.header[0] >> 4) & 0x0f;
522 case TCODE_WRITE_QUADLET_REQUEST:
523 case TCODE_READ_QUADLET_RESPONSE:
524 p.header[3] = (__force __u32) buffer[3];
525 p.header_length = 16;
526 p.payload_length = 0;
529 case TCODE_READ_BLOCK_REQUEST :
530 p.header[3] = cond_le32_to_cpu(buffer[3]);
531 p.header_length = 16;
532 p.payload_length = 0;
535 case TCODE_WRITE_BLOCK_REQUEST:
536 case TCODE_READ_BLOCK_RESPONSE:
537 case TCODE_LOCK_REQUEST:
538 case TCODE_LOCK_RESPONSE:
539 p.header[3] = cond_le32_to_cpu(buffer[3]);
540 p.header_length = 16;
541 p.payload_length = p.header[3] >> 16;
544 case TCODE_WRITE_RESPONSE:
545 case TCODE_READ_QUADLET_REQUEST:
546 case OHCI_TCODE_PHY_PACKET:
547 p.header_length = 12;
548 p.payload_length = 0;
552 p.payload = (void *) buffer + p.header_length;
554 /* FIXME: What to do about evt_* errors? */
555 length = (p.header_length + p.payload_length + 3) / 4;
556 status = cond_le32_to_cpu(buffer[length]);
557 evt = (status >> 16) & 0x1f;
560 p.speed = (status >> 21) & 0x7;
561 p.timestamp = status & 0xffff;
562 p.generation = ohci->request_generation;
564 log_ar_at_event('R', p.speed, p.header, evt);
567 * The OHCI bus reset handler synthesizes a phy packet with
568 * the new generation number when a bus reset happens (see
569 * section 8.4.2.3). This helps us determine when a request
570 * was received and make sure we send the response in the same
571 * generation. We only need this for requests; for responses
572 * we use the unique tlabel for finding the matching
576 if (evt == OHCI1394_evt_bus_reset)
577 ohci->request_generation = (p.header[2] >> 16) & 0xff;
578 else if (ctx == &ohci->ar_request_ctx)
579 fw_core_handle_request(&ohci->card, &p);
581 fw_core_handle_response(&ohci->card, &p);
583 return buffer + length + 1;
586 static void ar_context_tasklet(unsigned long data)
588 struct ar_context *ctx = (struct ar_context *)data;
589 struct fw_ohci *ohci = ctx->ohci;
590 struct ar_buffer *ab;
591 struct descriptor *d;
594 ab = ctx->current_buffer;
597 if (d->res_count == 0) {
598 size_t size, rest, offset;
599 dma_addr_t start_bus;
603 * This descriptor is finished and we may have a
604 * packet split across this and the next buffer. We
605 * reuse the page for reassembling the split packet.
608 offset = offsetof(struct ar_buffer, data);
610 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
614 size = buffer + PAGE_SIZE - ctx->pointer;
615 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
616 memmove(buffer, ctx->pointer, size);
617 memcpy(buffer + size, ab->data, rest);
618 ctx->current_buffer = ab;
619 ctx->pointer = (void *) ab->data + rest;
620 end = buffer + size + rest;
623 buffer = handle_ar_packet(ctx, buffer);
625 dma_free_coherent(ohci->card.device, PAGE_SIZE,
627 ar_context_add_page(ctx);
629 buffer = ctx->pointer;
631 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
634 buffer = handle_ar_packet(ctx, buffer);
639 ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs)
645 ctx->last_buffer = &ab;
646 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
648 ar_context_add_page(ctx);
649 ar_context_add_page(ctx);
650 ctx->current_buffer = ab.next;
651 ctx->pointer = ctx->current_buffer->data;
656 static void ar_context_run(struct ar_context *ctx)
658 struct ar_buffer *ab = ctx->current_buffer;
662 offset = offsetof(struct ar_buffer, data);
663 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
665 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
666 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
667 flush_writes(ctx->ohci);
670 static struct descriptor *
671 find_branch_descriptor(struct descriptor *d, int z)
675 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
676 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
678 /* figure out which descriptor the branch address goes in */
679 if (z == 2 && (b == 3 || key == 2))
685 static void context_tasklet(unsigned long data)
687 struct context *ctx = (struct context *) data;
688 struct descriptor *d, *last;
691 struct descriptor_buffer *desc;
693 desc = list_entry(ctx->buffer_list.next,
694 struct descriptor_buffer, list);
696 while (last->branch_address != 0) {
697 struct descriptor_buffer *old_desc = desc;
698 address = le32_to_cpu(last->branch_address);
702 /* If the branch address points to a buffer outside of the
703 * current buffer, advance to the next buffer. */
704 if (address < desc->buffer_bus ||
705 address >= desc->buffer_bus + desc->used)
706 desc = list_entry(desc->list.next,
707 struct descriptor_buffer, list);
708 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
709 last = find_branch_descriptor(d, z);
711 if (!ctx->callback(ctx, d, last))
714 if (old_desc != desc) {
715 /* If we've advanced to the next buffer, move the
716 * previous buffer to the free list. */
719 spin_lock_irqsave(&ctx->ohci->lock, flags);
720 list_move_tail(&old_desc->list, &ctx->buffer_list);
721 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
728 * Allocate a new buffer and add it to the list of free buffers for this
729 * context. Must be called with ohci->lock held.
732 context_add_buffer(struct context *ctx)
734 struct descriptor_buffer *desc;
735 dma_addr_t uninitialized_var(bus_addr);
739 * 16MB of descriptors should be far more than enough for any DMA
740 * program. This will catch run-away userspace or DoS attacks.
742 if (ctx->total_allocation >= 16*1024*1024)
745 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
746 &bus_addr, GFP_ATOMIC);
750 offset = (void *)&desc->buffer - (void *)desc;
751 desc->buffer_size = PAGE_SIZE - offset;
752 desc->buffer_bus = bus_addr + offset;
755 list_add_tail(&desc->list, &ctx->buffer_list);
756 ctx->total_allocation += PAGE_SIZE;
762 context_init(struct context *ctx, struct fw_ohci *ohci,
763 u32 regs, descriptor_callback_t callback)
767 ctx->total_allocation = 0;
769 INIT_LIST_HEAD(&ctx->buffer_list);
770 if (context_add_buffer(ctx) < 0)
773 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
774 struct descriptor_buffer, list);
776 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
777 ctx->callback = callback;
780 * We put a dummy descriptor in the buffer that has a NULL
781 * branch address and looks like it's been sent. That way we
782 * have a descriptor to append DMA programs to.
784 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
785 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
786 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
787 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
788 ctx->last = ctx->buffer_tail->buffer;
789 ctx->prev = ctx->buffer_tail->buffer;
795 context_release(struct context *ctx)
797 struct fw_card *card = &ctx->ohci->card;
798 struct descriptor_buffer *desc, *tmp;
800 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
801 dma_free_coherent(card->device, PAGE_SIZE, desc,
803 ((void *)&desc->buffer - (void *)desc));
806 /* Must be called with ohci->lock held */
807 static struct descriptor *
808 context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus)
810 struct descriptor *d = NULL;
811 struct descriptor_buffer *desc = ctx->buffer_tail;
813 if (z * sizeof(*d) > desc->buffer_size)
816 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
817 /* No room for the descriptor in this buffer, so advance to the
820 if (desc->list.next == &ctx->buffer_list) {
821 /* If there is no free buffer next in the list,
823 if (context_add_buffer(ctx) < 0)
826 desc = list_entry(desc->list.next,
827 struct descriptor_buffer, list);
828 ctx->buffer_tail = desc;
831 d = desc->buffer + desc->used / sizeof(*d);
832 memset(d, 0, z * sizeof(*d));
833 *d_bus = desc->buffer_bus + desc->used;
838 static void context_run(struct context *ctx, u32 extra)
840 struct fw_ohci *ohci = ctx->ohci;
842 reg_write(ohci, COMMAND_PTR(ctx->regs),
843 le32_to_cpu(ctx->last->branch_address));
844 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
845 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
849 static void context_append(struct context *ctx,
850 struct descriptor *d, int z, int extra)
853 struct descriptor_buffer *desc = ctx->buffer_tail;
855 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
857 desc->used += (z + extra) * sizeof(*d);
858 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
859 ctx->prev = find_branch_descriptor(d, z);
861 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
862 flush_writes(ctx->ohci);
865 static void context_stop(struct context *ctx)
870 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
871 flush_writes(ctx->ohci);
873 for (i = 0; i < 10; i++) {
874 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
875 if ((reg & CONTEXT_ACTIVE) == 0)
878 fw_notify("context_stop: still active (0x%08x)\n", reg);
884 struct fw_packet *packet;
888 * This function apppends a packet to the DMA queue for transmission.
889 * Must always be called with the ochi->lock held to ensure proper
890 * generation handling and locking around packet queue manipulation.
893 at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
895 struct fw_ohci *ohci = ctx->ohci;
896 dma_addr_t d_bus, uninitialized_var(payload_bus);
897 struct driver_data *driver_data;
898 struct descriptor *d, *last;
903 d = context_get_descriptors(ctx, 4, &d_bus);
905 packet->ack = RCODE_SEND_ERROR;
909 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
910 d[0].res_count = cpu_to_le16(packet->timestamp);
913 * The DMA format for asyncronous link packets is different
914 * from the IEEE1394 layout, so shift the fields around
915 * accordingly. If header_length is 8, it's a PHY packet, to
916 * which we need to prepend an extra quadlet.
919 header = (__le32 *) &d[1];
920 if (packet->header_length > 8) {
921 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
922 (packet->speed << 16));
923 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
924 (packet->header[0] & 0xffff0000));
925 header[2] = cpu_to_le32(packet->header[2]);
927 tcode = (packet->header[0] >> 4) & 0x0f;
928 if (TCODE_IS_BLOCK_PACKET(tcode))
929 header[3] = cpu_to_le32(packet->header[3]);
931 header[3] = (__force __le32) packet->header[3];
933 d[0].req_count = cpu_to_le16(packet->header_length);
935 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
936 (packet->speed << 16));
937 header[1] = cpu_to_le32(packet->header[0]);
938 header[2] = cpu_to_le32(packet->header[1]);
939 d[0].req_count = cpu_to_le16(12);
942 driver_data = (struct driver_data *) &d[3];
943 driver_data->packet = packet;
944 packet->driver_data = driver_data;
946 if (packet->payload_length > 0) {
948 dma_map_single(ohci->card.device, packet->payload,
949 packet->payload_length, DMA_TO_DEVICE);
950 if (dma_mapping_error(payload_bus)) {
951 packet->ack = RCODE_SEND_ERROR;
955 d[2].req_count = cpu_to_le16(packet->payload_length);
956 d[2].data_address = cpu_to_le32(payload_bus);
964 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
965 DESCRIPTOR_IRQ_ALWAYS |
966 DESCRIPTOR_BRANCH_ALWAYS);
969 * If the controller and packet generations don't match, we need to
970 * bail out and try again. If IntEvent.busReset is set, the AT context
971 * is halted, so appending to the context and trying to run it is
972 * futile. Most controllers do the right thing and just flush the AT
973 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
974 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
975 * up stalling out. So we just bail out in software and try again
976 * later, and everyone is happy.
977 * FIXME: Document how the locking works.
979 if (ohci->generation != packet->generation ||
980 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
981 if (packet->payload_length > 0)
982 dma_unmap_single(ohci->card.device, payload_bus,
983 packet->payload_length, DMA_TO_DEVICE);
984 packet->ack = RCODE_GENERATION;
988 context_append(ctx, d, z, 4 - z);
990 /* If the context isn't already running, start it up. */
991 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
992 if ((reg & CONTEXT_RUN) == 0)
998 static int handle_at_packet(struct context *context,
999 struct descriptor *d,
1000 struct descriptor *last)
1002 struct driver_data *driver_data;
1003 struct fw_packet *packet;
1004 struct fw_ohci *ohci = context->ohci;
1005 dma_addr_t payload_bus;
1008 if (last->transfer_status == 0)
1009 /* This descriptor isn't done yet, stop iteration. */
1012 driver_data = (struct driver_data *) &d[3];
1013 packet = driver_data->packet;
1015 /* This packet was cancelled, just continue. */
1018 payload_bus = le32_to_cpu(last->data_address);
1019 if (payload_bus != 0)
1020 dma_unmap_single(ohci->card.device, payload_bus,
1021 packet->payload_length, DMA_TO_DEVICE);
1023 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1024 packet->timestamp = le16_to_cpu(last->res_count);
1026 log_ar_at_event('T', packet->speed, packet->header, evt);
1029 case OHCI1394_evt_timeout:
1030 /* Async response transmit timed out. */
1031 packet->ack = RCODE_CANCELLED;
1034 case OHCI1394_evt_flushed:
1036 * The packet was flushed should give same error as
1037 * when we try to use a stale generation count.
1039 packet->ack = RCODE_GENERATION;
1042 case OHCI1394_evt_missing_ack:
1044 * Using a valid (current) generation count, but the
1045 * node is not on the bus or not sending acks.
1047 packet->ack = RCODE_NO_ACK;
1050 case ACK_COMPLETE + 0x10:
1051 case ACK_PENDING + 0x10:
1052 case ACK_BUSY_X + 0x10:
1053 case ACK_BUSY_A + 0x10:
1054 case ACK_BUSY_B + 0x10:
1055 case ACK_DATA_ERROR + 0x10:
1056 case ACK_TYPE_ERROR + 0x10:
1057 packet->ack = evt - 0x10;
1061 packet->ack = RCODE_SEND_ERROR;
1065 packet->callback(packet, &ohci->card, packet->ack);
1070 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1071 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1072 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1073 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1074 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1077 handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
1079 struct fw_packet response;
1080 int tcode, length, i;
1082 tcode = HEADER_GET_TCODE(packet->header[0]);
1083 if (TCODE_IS_BLOCK_PACKET(tcode))
1084 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1088 i = csr - CSR_CONFIG_ROM;
1089 if (i + length > CONFIG_ROM_SIZE) {
1090 fw_fill_response(&response, packet->header,
1091 RCODE_ADDRESS_ERROR, NULL, 0);
1092 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1093 fw_fill_response(&response, packet->header,
1094 RCODE_TYPE_ERROR, NULL, 0);
1096 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1097 (void *) ohci->config_rom + i, length);
1100 fw_core_handle_response(&ohci->card, &response);
1104 handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
1106 struct fw_packet response;
1107 int tcode, length, ext_tcode, sel;
1108 __be32 *payload, lock_old;
1109 u32 lock_arg, lock_data;
1111 tcode = HEADER_GET_TCODE(packet->header[0]);
1112 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1113 payload = packet->payload;
1114 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1116 if (tcode == TCODE_LOCK_REQUEST &&
1117 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1118 lock_arg = be32_to_cpu(payload[0]);
1119 lock_data = be32_to_cpu(payload[1]);
1120 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1124 fw_fill_response(&response, packet->header,
1125 RCODE_TYPE_ERROR, NULL, 0);
1129 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1130 reg_write(ohci, OHCI1394_CSRData, lock_data);
1131 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1132 reg_write(ohci, OHCI1394_CSRControl, sel);
1134 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1135 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1137 fw_notify("swap not done yet\n");
1139 fw_fill_response(&response, packet->header,
1140 RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1142 fw_core_handle_response(&ohci->card, &response);
1146 handle_local_request(struct context *ctx, struct fw_packet *packet)
1151 if (ctx == &ctx->ohci->at_request_ctx) {
1152 packet->ack = ACK_PENDING;
1153 packet->callback(packet, &ctx->ohci->card, packet->ack);
1157 ((unsigned long long)
1158 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1160 csr = offset - CSR_REGISTER_BASE;
1162 /* Handle config rom reads. */
1163 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1164 handle_local_rom(ctx->ohci, packet, csr);
1166 case CSR_BUS_MANAGER_ID:
1167 case CSR_BANDWIDTH_AVAILABLE:
1168 case CSR_CHANNELS_AVAILABLE_HI:
1169 case CSR_CHANNELS_AVAILABLE_LO:
1170 handle_local_lock(ctx->ohci, packet, csr);
1173 if (ctx == &ctx->ohci->at_request_ctx)
1174 fw_core_handle_request(&ctx->ohci->card, packet);
1176 fw_core_handle_response(&ctx->ohci->card, packet);
1180 if (ctx == &ctx->ohci->at_response_ctx) {
1181 packet->ack = ACK_COMPLETE;
1182 packet->callback(packet, &ctx->ohci->card, packet->ack);
1187 at_context_transmit(struct context *ctx, struct fw_packet *packet)
1189 unsigned long flags;
1192 spin_lock_irqsave(&ctx->ohci->lock, flags);
1194 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1195 ctx->ohci->generation == packet->generation) {
1196 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1197 handle_local_request(ctx, packet);
1201 retval = at_context_queue_packet(ctx, packet);
1202 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1205 packet->callback(packet, &ctx->ohci->card, packet->ack);
1209 static void bus_reset_tasklet(unsigned long data)
1211 struct fw_ohci *ohci = (struct fw_ohci *)data;
1212 int self_id_count, i, j, reg;
1213 int generation, new_generation;
1214 unsigned long flags;
1215 void *free_rom = NULL;
1216 dma_addr_t free_rom_bus = 0;
1218 reg = reg_read(ohci, OHCI1394_NodeID);
1219 if (!(reg & OHCI1394_NodeID_idValid)) {
1220 fw_notify("node ID not valid, new bus reset in progress\n");
1223 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1224 fw_notify("malconfigured bus\n");
1227 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1228 OHCI1394_NodeID_nodeNumber);
1230 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1231 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1232 fw_notify("inconsistent self IDs\n");
1236 * The count in the SelfIDCount register is the number of
1237 * bytes in the self ID receive buffer. Since we also receive
1238 * the inverted quadlets and a header quadlet, we shift one
1239 * bit extra to get the actual number of self IDs.
1241 self_id_count = (reg >> 3) & 0x3ff;
1242 if (self_id_count == 0) {
1243 fw_notify("inconsistent self IDs\n");
1246 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1249 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1250 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1251 fw_notify("inconsistent self IDs\n");
1254 ohci->self_id_buffer[j] =
1255 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1260 * Check the consistency of the self IDs we just read. The
1261 * problem we face is that a new bus reset can start while we
1262 * read out the self IDs from the DMA buffer. If this happens,
1263 * the DMA buffer will be overwritten with new self IDs and we
1264 * will read out inconsistent data. The OHCI specification
1265 * (section 11.2) recommends a technique similar to
1266 * linux/seqlock.h, where we remember the generation of the
1267 * self IDs in the buffer before reading them out and compare
1268 * it to the current generation after reading them out. If
1269 * the two generations match we know we have a consistent set
1273 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1274 if (new_generation != generation) {
1275 fw_notify("recursive bus reset detected, "
1276 "discarding self ids\n");
1280 /* FIXME: Document how the locking works. */
1281 spin_lock_irqsave(&ohci->lock, flags);
1283 ohci->generation = generation;
1284 context_stop(&ohci->at_request_ctx);
1285 context_stop(&ohci->at_response_ctx);
1286 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1289 * This next bit is unrelated to the AT context stuff but we
1290 * have to do it under the spinlock also. If a new config rom
1291 * was set up before this reset, the old one is now no longer
1292 * in use and we can free it. Update the config rom pointers
1293 * to point to the current config rom and clear the
1294 * next_config_rom pointer so a new udpate can take place.
1297 if (ohci->next_config_rom != NULL) {
1298 if (ohci->next_config_rom != ohci->config_rom) {
1299 free_rom = ohci->config_rom;
1300 free_rom_bus = ohci->config_rom_bus;
1302 ohci->config_rom = ohci->next_config_rom;
1303 ohci->config_rom_bus = ohci->next_config_rom_bus;
1304 ohci->next_config_rom = NULL;
1307 * Restore config_rom image and manually update
1308 * config_rom registers. Writing the header quadlet
1309 * will indicate that the config rom is ready, so we
1312 reg_write(ohci, OHCI1394_BusOptions,
1313 be32_to_cpu(ohci->config_rom[2]));
1314 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
1315 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
1318 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1319 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1320 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1323 spin_unlock_irqrestore(&ohci->lock, flags);
1326 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1327 free_rom, free_rom_bus);
1329 log_selfids(ohci->node_id, generation,
1330 self_id_count, ohci->self_id_buffer);
1332 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1333 self_id_count, ohci->self_id_buffer);
1336 static irqreturn_t irq_handler(int irq, void *data)
1338 struct fw_ohci *ohci = data;
1339 u32 event, iso_event, cycle_time;
1342 event = reg_read(ohci, OHCI1394_IntEventClear);
1344 if (!event || !~event)
1347 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1348 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1351 if (event & OHCI1394_selfIDComplete)
1352 tasklet_schedule(&ohci->bus_reset_tasklet);
1354 if (event & OHCI1394_RQPkt)
1355 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1357 if (event & OHCI1394_RSPkt)
1358 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1360 if (event & OHCI1394_reqTxComplete)
1361 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1363 if (event & OHCI1394_respTxComplete)
1364 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1366 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1367 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1370 i = ffs(iso_event) - 1;
1371 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1372 iso_event &= ~(1 << i);
1375 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1376 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1379 i = ffs(iso_event) - 1;
1380 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1381 iso_event &= ~(1 << i);
1384 if (unlikely(event & OHCI1394_regAccessFail))
1385 fw_error("Register access failure - "
1386 "please notify linux1394-devel@lists.sf.net\n");
1388 if (unlikely(event & OHCI1394_postedWriteErr))
1389 fw_error("PCI posted write error\n");
1391 if (unlikely(event & OHCI1394_cycleTooLong)) {
1392 if (printk_ratelimit())
1393 fw_notify("isochronous cycle too long\n");
1394 reg_write(ohci, OHCI1394_LinkControlSet,
1395 OHCI1394_LinkControl_cycleMaster);
1398 if (event & OHCI1394_cycle64Seconds) {
1399 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1400 if ((cycle_time & 0x80000000) == 0)
1401 ohci->bus_seconds++;
1407 static int software_reset(struct fw_ohci *ohci)
1411 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1413 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1414 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1415 OHCI1394_HCControl_softReset) == 0)
1423 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1425 struct fw_ohci *ohci = fw_ohci(card);
1426 struct pci_dev *dev = to_pci_dev(card->device);
1430 if (software_reset(ohci)) {
1431 fw_error("Failed to reset ohci card.\n");
1436 * Now enable LPS, which we need in order to start accessing
1437 * most of the registers. In fact, on some cards (ALI M5251),
1438 * accessing registers in the SClk domain without LPS enabled
1439 * will lock up the machine. Wait 50msec to make sure we have
1440 * full link enabled. However, with some cards (well, at least
1441 * a JMicron PCIe card), we have to try again sometimes.
1443 reg_write(ohci, OHCI1394_HCControlSet,
1444 OHCI1394_HCControl_LPS |
1445 OHCI1394_HCControl_postedWriteEnable);
1448 for (lps = 0, i = 0; !lps && i < 3; i++) {
1450 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1451 OHCI1394_HCControl_LPS;
1455 fw_error("Failed to set Link Power Status\n");
1459 reg_write(ohci, OHCI1394_HCControlClear,
1460 OHCI1394_HCControl_noByteSwapData);
1462 reg_write(ohci, OHCI1394_LinkControlSet,
1463 OHCI1394_LinkControl_rcvSelfID |
1464 OHCI1394_LinkControl_cycleTimerEnable |
1465 OHCI1394_LinkControl_cycleMaster);
1467 reg_write(ohci, OHCI1394_ATRetries,
1468 OHCI1394_MAX_AT_REQ_RETRIES |
1469 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1470 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1472 ar_context_run(&ohci->ar_request_ctx);
1473 ar_context_run(&ohci->ar_response_ctx);
1475 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1476 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1477 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1478 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1479 reg_write(ohci, OHCI1394_IntMaskSet,
1480 OHCI1394_selfIDComplete |
1481 OHCI1394_RQPkt | OHCI1394_RSPkt |
1482 OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1483 OHCI1394_isochRx | OHCI1394_isochTx |
1484 OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1485 OHCI1394_cycle64Seconds | OHCI1394_regAccessFail |
1486 OHCI1394_masterIntEnable);
1487 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1488 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
1490 /* Activate link_on bit and contender bit in our self ID packets.*/
1491 if (ohci_update_phy_reg(card, 4, 0,
1492 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1496 * When the link is not yet enabled, the atomic config rom
1497 * update mechanism described below in ohci_set_config_rom()
1498 * is not active. We have to update ConfigRomHeader and
1499 * BusOptions manually, and the write to ConfigROMmap takes
1500 * effect immediately. We tie this to the enabling of the
1501 * link, so we have a valid config rom before enabling - the
1502 * OHCI requires that ConfigROMhdr and BusOptions have valid
1503 * values before enabling.
1505 * However, when the ConfigROMmap is written, some controllers
1506 * always read back quadlets 0 and 2 from the config rom to
1507 * the ConfigRomHeader and BusOptions registers on bus reset.
1508 * They shouldn't do that in this initial case where the link
1509 * isn't enabled. This means we have to use the same
1510 * workaround here, setting the bus header to 0 and then write
1511 * the right values in the bus reset tasklet.
1515 ohci->next_config_rom =
1516 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1517 &ohci->next_config_rom_bus,
1519 if (ohci->next_config_rom == NULL)
1522 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1523 fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1526 * In the suspend case, config_rom is NULL, which
1527 * means that we just reuse the old config rom.
1529 ohci->next_config_rom = ohci->config_rom;
1530 ohci->next_config_rom_bus = ohci->config_rom_bus;
1533 ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]);
1534 ohci->next_config_rom[0] = 0;
1535 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1536 reg_write(ohci, OHCI1394_BusOptions,
1537 be32_to_cpu(ohci->next_config_rom[2]));
1538 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1540 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1542 if (request_irq(dev->irq, irq_handler,
1543 IRQF_SHARED, ohci_driver_name, ohci)) {
1544 fw_error("Failed to allocate shared interrupt %d.\n",
1546 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1547 ohci->config_rom, ohci->config_rom_bus);
1551 reg_write(ohci, OHCI1394_HCControlSet,
1552 OHCI1394_HCControl_linkEnable |
1553 OHCI1394_HCControl_BIBimageValid);
1557 * We are ready to go, initiate bus reset to finish the
1561 fw_core_initiate_bus_reset(&ohci->card, 1);
1567 ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
1569 struct fw_ohci *ohci;
1570 unsigned long flags;
1571 int retval = -EBUSY;
1572 __be32 *next_config_rom;
1573 dma_addr_t uninitialized_var(next_config_rom_bus);
1575 ohci = fw_ohci(card);
1578 * When the OHCI controller is enabled, the config rom update
1579 * mechanism is a bit tricky, but easy enough to use. See
1580 * section 5.5.6 in the OHCI specification.
1582 * The OHCI controller caches the new config rom address in a
1583 * shadow register (ConfigROMmapNext) and needs a bus reset
1584 * for the changes to take place. When the bus reset is
1585 * detected, the controller loads the new values for the
1586 * ConfigRomHeader and BusOptions registers from the specified
1587 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1588 * shadow register. All automatically and atomically.
1590 * Now, there's a twist to this story. The automatic load of
1591 * ConfigRomHeader and BusOptions doesn't honor the
1592 * noByteSwapData bit, so with a be32 config rom, the
1593 * controller will load be32 values in to these registers
1594 * during the atomic update, even on litte endian
1595 * architectures. The workaround we use is to put a 0 in the
1596 * header quadlet; 0 is endian agnostic and means that the
1597 * config rom isn't ready yet. In the bus reset tasklet we
1598 * then set up the real values for the two registers.
1600 * We use ohci->lock to avoid racing with the code that sets
1601 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1605 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1606 &next_config_rom_bus, GFP_KERNEL);
1607 if (next_config_rom == NULL)
1610 spin_lock_irqsave(&ohci->lock, flags);
1612 if (ohci->next_config_rom == NULL) {
1613 ohci->next_config_rom = next_config_rom;
1614 ohci->next_config_rom_bus = next_config_rom_bus;
1616 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1617 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1620 ohci->next_header = config_rom[0];
1621 ohci->next_config_rom[0] = 0;
1623 reg_write(ohci, OHCI1394_ConfigROMmap,
1624 ohci->next_config_rom_bus);
1628 spin_unlock_irqrestore(&ohci->lock, flags);
1631 * Now initiate a bus reset to have the changes take
1632 * effect. We clean up the old config rom memory and DMA
1633 * mappings in the bus reset tasklet, since the OHCI
1634 * controller could need to access it before the bus reset
1638 fw_core_initiate_bus_reset(&ohci->card, 1);
1640 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1641 next_config_rom, next_config_rom_bus);
1646 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1648 struct fw_ohci *ohci = fw_ohci(card);
1650 at_context_transmit(&ohci->at_request_ctx, packet);
1653 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1655 struct fw_ohci *ohci = fw_ohci(card);
1657 at_context_transmit(&ohci->at_response_ctx, packet);
1660 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1662 struct fw_ohci *ohci = fw_ohci(card);
1663 struct context *ctx = &ohci->at_request_ctx;
1664 struct driver_data *driver_data = packet->driver_data;
1665 int retval = -ENOENT;
1667 tasklet_disable(&ctx->tasklet);
1669 if (packet->ack != 0)
1672 log_ar_at_event('T', packet->speed, packet->header, 0x20);
1673 driver_data->packet = NULL;
1674 packet->ack = RCODE_CANCELLED;
1675 packet->callback(packet, &ohci->card, packet->ack);
1679 tasklet_enable(&ctx->tasklet);
1685 ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
1687 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1690 struct fw_ohci *ohci = fw_ohci(card);
1691 unsigned long flags;
1695 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1696 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1699 spin_lock_irqsave(&ohci->lock, flags);
1701 if (ohci->generation != generation) {
1707 * Note, if the node ID contains a non-local bus ID, physical DMA is
1708 * enabled for _all_ nodes on remote buses.
1711 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1713 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1715 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1719 spin_unlock_irqrestore(&ohci->lock, flags);
1721 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1725 ohci_get_bus_time(struct fw_card *card)
1727 struct fw_ohci *ohci = fw_ohci(card);
1731 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1732 bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time;
1737 static int handle_ir_dualbuffer_packet(struct context *context,
1738 struct descriptor *d,
1739 struct descriptor *last)
1741 struct iso_context *ctx =
1742 container_of(context, struct iso_context, context);
1743 struct db_descriptor *db = (struct db_descriptor *) d;
1745 size_t header_length;
1749 if (db->first_res_count != 0 && db->second_res_count != 0) {
1750 if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
1751 /* This descriptor isn't done yet, stop iteration. */
1754 ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
1757 header_length = le16_to_cpu(db->first_req_count) -
1758 le16_to_cpu(db->first_res_count);
1760 i = ctx->header_length;
1762 end = p + header_length;
1763 while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
1765 * The iso header is byteswapped to little endian by
1766 * the controller, but the remaining header quadlets
1767 * are big endian. We want to present all the headers
1768 * as big endian, so we have to swap the first
1771 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1772 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1773 i += ctx->base.header_size;
1774 ctx->excess_bytes +=
1775 (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff;
1776 p += ctx->base.header_size + 4;
1778 ctx->header_length = i;
1780 ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
1781 le16_to_cpu(db->second_res_count);
1783 if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1784 ir_header = (__le32 *) (db + 1);
1785 ctx->base.callback(&ctx->base,
1786 le32_to_cpu(ir_header[0]) & 0xffff,
1787 ctx->header_length, ctx->header,
1788 ctx->base.callback_data);
1789 ctx->header_length = 0;
1795 static int handle_ir_packet_per_buffer(struct context *context,
1796 struct descriptor *d,
1797 struct descriptor *last)
1799 struct iso_context *ctx =
1800 container_of(context, struct iso_context, context);
1801 struct descriptor *pd;
1806 for (pd = d; pd <= last; pd++) {
1807 if (pd->transfer_status)
1811 /* Descriptor(s) not done yet, stop iteration */
1814 i = ctx->header_length;
1817 if (ctx->base.header_size > 0 &&
1818 i + ctx->base.header_size <= PAGE_SIZE) {
1820 * The iso header is byteswapped to little endian by
1821 * the controller, but the remaining header quadlets
1822 * are big endian. We want to present all the headers
1823 * as big endian, so we have to swap the first quadlet.
1825 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1826 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1827 ctx->header_length += ctx->base.header_size;
1830 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1831 ir_header = (__le32 *) p;
1832 ctx->base.callback(&ctx->base,
1833 le32_to_cpu(ir_header[0]) & 0xffff,
1834 ctx->header_length, ctx->header,
1835 ctx->base.callback_data);
1836 ctx->header_length = 0;
1842 static int handle_it_packet(struct context *context,
1843 struct descriptor *d,
1844 struct descriptor *last)
1846 struct iso_context *ctx =
1847 container_of(context, struct iso_context, context);
1849 if (last->transfer_status == 0)
1850 /* This descriptor isn't done yet, stop iteration. */
1853 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
1854 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1855 0, NULL, ctx->base.callback_data);
1860 static struct fw_iso_context *
1861 ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size)
1863 struct fw_ohci *ohci = fw_ohci(card);
1864 struct iso_context *ctx, *list;
1865 descriptor_callback_t callback;
1867 unsigned long flags;
1868 int index, retval = -ENOMEM;
1870 if (type == FW_ISO_CONTEXT_TRANSMIT) {
1871 mask = &ohci->it_context_mask;
1872 list = ohci->it_context_list;
1873 callback = handle_it_packet;
1875 mask = &ohci->ir_context_mask;
1876 list = ohci->ir_context_list;
1877 if (ohci->version >= OHCI_VERSION_1_1)
1878 callback = handle_ir_dualbuffer_packet;
1880 callback = handle_ir_packet_per_buffer;
1883 spin_lock_irqsave(&ohci->lock, flags);
1884 index = ffs(*mask) - 1;
1886 *mask &= ~(1 << index);
1887 spin_unlock_irqrestore(&ohci->lock, flags);
1890 return ERR_PTR(-EBUSY);
1892 if (type == FW_ISO_CONTEXT_TRANSMIT)
1893 regs = OHCI1394_IsoXmitContextBase(index);
1895 regs = OHCI1394_IsoRcvContextBase(index);
1898 memset(ctx, 0, sizeof(*ctx));
1899 ctx->header_length = 0;
1900 ctx->header = (void *) __get_free_page(GFP_KERNEL);
1901 if (ctx->header == NULL)
1904 retval = context_init(&ctx->context, ohci, regs, callback);
1906 goto out_with_header;
1911 free_page((unsigned long)ctx->header);
1913 spin_lock_irqsave(&ohci->lock, flags);
1914 *mask |= 1 << index;
1915 spin_unlock_irqrestore(&ohci->lock, flags);
1917 return ERR_PTR(retval);
1920 static int ohci_start_iso(struct fw_iso_context *base,
1921 s32 cycle, u32 sync, u32 tags)
1923 struct iso_context *ctx = container_of(base, struct iso_context, base);
1924 struct fw_ohci *ohci = ctx->context.ohci;
1928 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1929 index = ctx - ohci->it_context_list;
1932 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
1933 (cycle & 0x7fff) << 16;
1935 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1936 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1937 context_run(&ctx->context, match);
1939 index = ctx - ohci->ir_context_list;
1940 control = IR_CONTEXT_ISOCH_HEADER;
1941 if (ohci->version >= OHCI_VERSION_1_1)
1942 control |= IR_CONTEXT_DUAL_BUFFER_MODE;
1943 match = (tags << 28) | (sync << 8) | ctx->base.channel;
1945 match |= (cycle & 0x07fff) << 12;
1946 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
1949 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
1950 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
1951 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
1952 context_run(&ctx->context, control);
1958 static int ohci_stop_iso(struct fw_iso_context *base)
1960 struct fw_ohci *ohci = fw_ohci(base->card);
1961 struct iso_context *ctx = container_of(base, struct iso_context, base);
1964 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1965 index = ctx - ohci->it_context_list;
1966 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1968 index = ctx - ohci->ir_context_list;
1969 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1972 context_stop(&ctx->context);
1977 static void ohci_free_iso_context(struct fw_iso_context *base)
1979 struct fw_ohci *ohci = fw_ohci(base->card);
1980 struct iso_context *ctx = container_of(base, struct iso_context, base);
1981 unsigned long flags;
1984 ohci_stop_iso(base);
1985 context_release(&ctx->context);
1986 free_page((unsigned long)ctx->header);
1988 spin_lock_irqsave(&ohci->lock, flags);
1990 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1991 index = ctx - ohci->it_context_list;
1992 ohci->it_context_mask |= 1 << index;
1994 index = ctx - ohci->ir_context_list;
1995 ohci->ir_context_mask |= 1 << index;
1998 spin_unlock_irqrestore(&ohci->lock, flags);
2002 ohci_queue_iso_transmit(struct fw_iso_context *base,
2003 struct fw_iso_packet *packet,
2004 struct fw_iso_buffer *buffer,
2005 unsigned long payload)
2007 struct iso_context *ctx = container_of(base, struct iso_context, base);
2008 struct descriptor *d, *last, *pd;
2009 struct fw_iso_packet *p;
2011 dma_addr_t d_bus, page_bus;
2012 u32 z, header_z, payload_z, irq;
2013 u32 payload_index, payload_end_index, next_page_index;
2014 int page, end_page, i, length, offset;
2017 * FIXME: Cycle lost behavior should be configurable: lose
2018 * packet, retransmit or terminate..
2022 payload_index = payload;
2028 if (p->header_length > 0)
2031 /* Determine the first page the payload isn't contained in. */
2032 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2033 if (p->payload_length > 0)
2034 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2040 /* Get header size in number of descriptors. */
2041 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2043 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2048 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2049 d[0].req_count = cpu_to_le16(8);
2051 header = (__le32 *) &d[1];
2052 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2053 IT_HEADER_TAG(p->tag) |
2054 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2055 IT_HEADER_CHANNEL(ctx->base.channel) |
2056 IT_HEADER_SPEED(ctx->base.speed));
2058 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2059 p->payload_length));
2062 if (p->header_length > 0) {
2063 d[2].req_count = cpu_to_le16(p->header_length);
2064 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2065 memcpy(&d[z], p->header, p->header_length);
2068 pd = d + z - payload_z;
2069 payload_end_index = payload_index + p->payload_length;
2070 for (i = 0; i < payload_z; i++) {
2071 page = payload_index >> PAGE_SHIFT;
2072 offset = payload_index & ~PAGE_MASK;
2073 next_page_index = (page + 1) << PAGE_SHIFT;
2075 min(next_page_index, payload_end_index) - payload_index;
2076 pd[i].req_count = cpu_to_le16(length);
2078 page_bus = page_private(buffer->pages[page]);
2079 pd[i].data_address = cpu_to_le32(page_bus + offset);
2081 payload_index += length;
2085 irq = DESCRIPTOR_IRQ_ALWAYS;
2087 irq = DESCRIPTOR_NO_IRQ;
2089 last = z == 2 ? d : d + z - 1;
2090 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2092 DESCRIPTOR_BRANCH_ALWAYS |
2095 context_append(&ctx->context, d, z, header_z);
2101 ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
2102 struct fw_iso_packet *packet,
2103 struct fw_iso_buffer *buffer,
2104 unsigned long payload)
2106 struct iso_context *ctx = container_of(base, struct iso_context, base);
2107 struct db_descriptor *db = NULL;
2108 struct descriptor *d;
2109 struct fw_iso_packet *p;
2110 dma_addr_t d_bus, page_bus;
2111 u32 z, header_z, length, rest;
2112 int page, offset, packet_count, header_size;
2115 * FIXME: Cycle lost behavior should be configurable: lose
2116 * packet, retransmit or terminate..
2123 * The OHCI controller puts the status word in the header
2124 * buffer too, so we need 4 extra bytes per packet.
2126 packet_count = p->header_length / ctx->base.header_size;
2127 header_size = packet_count * (ctx->base.header_size + 4);
2129 /* Get header size in number of descriptors. */
2130 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2131 page = payload >> PAGE_SHIFT;
2132 offset = payload & ~PAGE_MASK;
2133 rest = p->payload_length;
2135 /* FIXME: make packet-per-buffer/dual-buffer a context option */
2137 d = context_get_descriptors(&ctx->context,
2138 z + header_z, &d_bus);
2142 db = (struct db_descriptor *) d;
2143 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
2144 DESCRIPTOR_BRANCH_ALWAYS);
2145 db->first_size = cpu_to_le16(ctx->base.header_size + 4);
2146 if (p->skip && rest == p->payload_length) {
2147 db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2148 db->first_req_count = db->first_size;
2150 db->first_req_count = cpu_to_le16(header_size);
2152 db->first_res_count = db->first_req_count;
2153 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
2155 if (p->skip && rest == p->payload_length)
2157 else if (offset + rest < PAGE_SIZE)
2160 length = PAGE_SIZE - offset;
2162 db->second_req_count = cpu_to_le16(length);
2163 db->second_res_count = db->second_req_count;
2164 page_bus = page_private(buffer->pages[page]);
2165 db->second_buffer = cpu_to_le32(page_bus + offset);
2167 if (p->interrupt && length == rest)
2168 db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2170 context_append(&ctx->context, d, z, header_z);
2171 offset = (offset + length) & ~PAGE_MASK;
2181 ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2182 struct fw_iso_packet *packet,
2183 struct fw_iso_buffer *buffer,
2184 unsigned long payload)
2186 struct iso_context *ctx = container_of(base, struct iso_context, base);
2187 struct descriptor *d = NULL, *pd = NULL;
2188 struct fw_iso_packet *p = packet;
2189 dma_addr_t d_bus, page_bus;
2190 u32 z, header_z, rest;
2192 int page, offset, packet_count, header_size, payload_per_buffer;
2195 * The OHCI controller puts the status word in the
2196 * buffer too, so we need 4 extra bytes per packet.
2198 packet_count = p->header_length / ctx->base.header_size;
2199 header_size = ctx->base.header_size + 4;
2201 /* Get header size in number of descriptors. */
2202 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2203 page = payload >> PAGE_SHIFT;
2204 offset = payload & ~PAGE_MASK;
2205 payload_per_buffer = p->payload_length / packet_count;
2207 for (i = 0; i < packet_count; i++) {
2208 /* d points to the header descriptor */
2209 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2210 d = context_get_descriptors(&ctx->context,
2211 z + header_z, &d_bus);
2215 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2216 DESCRIPTOR_INPUT_MORE);
2217 if (p->skip && i == 0)
2218 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2219 d->req_count = cpu_to_le16(header_size);
2220 d->res_count = d->req_count;
2221 d->transfer_status = 0;
2222 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2224 rest = payload_per_buffer;
2225 for (j = 1; j < z; j++) {
2227 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2228 DESCRIPTOR_INPUT_MORE);
2230 if (offset + rest < PAGE_SIZE)
2233 length = PAGE_SIZE - offset;
2234 pd->req_count = cpu_to_le16(length);
2235 pd->res_count = pd->req_count;
2236 pd->transfer_status = 0;
2238 page_bus = page_private(buffer->pages[page]);
2239 pd->data_address = cpu_to_le32(page_bus + offset);
2241 offset = (offset + length) & ~PAGE_MASK;
2246 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2247 DESCRIPTOR_INPUT_LAST |
2248 DESCRIPTOR_BRANCH_ALWAYS);
2249 if (p->interrupt && i == packet_count - 1)
2250 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2252 context_append(&ctx->context, d, z, header_z);
2259 ohci_queue_iso(struct fw_iso_context *base,
2260 struct fw_iso_packet *packet,
2261 struct fw_iso_buffer *buffer,
2262 unsigned long payload)
2264 struct iso_context *ctx = container_of(base, struct iso_context, base);
2265 unsigned long flags;
2268 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2269 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2270 retval = ohci_queue_iso_transmit(base, packet, buffer, payload);
2271 else if (ctx->context.ohci->version >= OHCI_VERSION_1_1)
2272 retval = ohci_queue_iso_receive_dualbuffer(base, packet,
2275 retval = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2278 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2283 static const struct fw_card_driver ohci_driver = {
2284 .name = ohci_driver_name,
2285 .enable = ohci_enable,
2286 .update_phy_reg = ohci_update_phy_reg,
2287 .set_config_rom = ohci_set_config_rom,
2288 .send_request = ohci_send_request,
2289 .send_response = ohci_send_response,
2290 .cancel_packet = ohci_cancel_packet,
2291 .enable_phys_dma = ohci_enable_phys_dma,
2292 .get_bus_time = ohci_get_bus_time,
2294 .allocate_iso_context = ohci_allocate_iso_context,
2295 .free_iso_context = ohci_free_iso_context,
2296 .queue_iso = ohci_queue_iso,
2297 .start_iso = ohci_start_iso,
2298 .stop_iso = ohci_stop_iso,
2301 #ifdef CONFIG_PPC_PMAC
2302 static void ohci_pmac_on(struct pci_dev *dev)
2304 if (machine_is(powermac)) {
2305 struct device_node *ofn = pci_device_to_OF_node(dev);
2308 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2309 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2314 static void ohci_pmac_off(struct pci_dev *dev)
2316 if (machine_is(powermac)) {
2317 struct device_node *ofn = pci_device_to_OF_node(dev);
2320 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2321 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2326 #define ohci_pmac_on(dev)
2327 #define ohci_pmac_off(dev)
2328 #endif /* CONFIG_PPC_PMAC */
2330 static int __devinit
2331 pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
2333 struct fw_ohci *ohci;
2334 u32 bus_options, max_receive, link_speed;
2339 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2341 fw_error("Could not malloc fw_ohci data.\n");
2345 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2349 err = pci_enable_device(dev);
2351 fw_error("Failed to enable OHCI hardware.\n");
2355 pci_set_master(dev);
2356 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2357 pci_set_drvdata(dev, ohci);
2359 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2360 ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE &&
2361 dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW;
2363 spin_lock_init(&ohci->lock);
2365 tasklet_init(&ohci->bus_reset_tasklet,
2366 bus_reset_tasklet, (unsigned long)ohci);
2368 err = pci_request_region(dev, 0, ohci_driver_name);
2370 fw_error("MMIO resource unavailable\n");
2374 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2375 if (ohci->registers == NULL) {
2376 fw_error("Failed to remap registers\n");
2381 ar_context_init(&ohci->ar_request_ctx, ohci,
2382 OHCI1394_AsReqRcvContextControlSet);
2384 ar_context_init(&ohci->ar_response_ctx, ohci,
2385 OHCI1394_AsRspRcvContextControlSet);
2387 context_init(&ohci->at_request_ctx, ohci,
2388 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2390 context_init(&ohci->at_response_ctx, ohci,
2391 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2393 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2394 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2395 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2396 size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
2397 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2399 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2400 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2401 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2402 size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
2403 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2405 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2406 fw_error("Out of memory for it/ir contexts.\n");
2408 goto fail_registers;
2411 /* self-id dma buffer allocation */
2412 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2416 if (ohci->self_id_cpu == NULL) {
2417 fw_error("Out of memory for self ID buffer.\n");
2419 goto fail_registers;
2422 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2423 max_receive = (bus_options >> 12) & 0xf;
2424 link_speed = bus_options & 0x7;
2425 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2426 reg_read(ohci, OHCI1394_GUIDLo);
2428 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2432 ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2433 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2434 dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff);
2438 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2439 ohci->self_id_cpu, ohci->self_id_bus);
2441 kfree(ohci->it_context_list);
2442 kfree(ohci->ir_context_list);
2443 pci_iounmap(dev, ohci->registers);
2445 pci_release_region(dev, 0);
2447 pci_disable_device(dev);
2455 static void pci_remove(struct pci_dev *dev)
2457 struct fw_ohci *ohci;
2459 ohci = pci_get_drvdata(dev);
2460 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2462 fw_core_remove_card(&ohci->card);
2465 * FIXME: Fail all pending packets here, now that the upper
2466 * layers can't queue any more.
2469 software_reset(ohci);
2470 free_irq(dev->irq, ohci);
2471 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2472 ohci->self_id_cpu, ohci->self_id_bus);
2473 kfree(ohci->it_context_list);
2474 kfree(ohci->ir_context_list);
2475 pci_iounmap(dev, ohci->registers);
2476 pci_release_region(dev, 0);
2477 pci_disable_device(dev);
2481 fw_notify("Removed fw-ohci device.\n");
2485 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2487 struct fw_ohci *ohci = pci_get_drvdata(dev);
2490 software_reset(ohci);
2491 free_irq(dev->irq, ohci);
2492 err = pci_save_state(dev);
2494 fw_error("pci_save_state failed\n");
2497 err = pci_set_power_state(dev, pci_choose_state(dev, state));
2499 fw_error("pci_set_power_state failed with %d\n", err);
2505 static int pci_resume(struct pci_dev *dev)
2507 struct fw_ohci *ohci = pci_get_drvdata(dev);
2511 pci_set_power_state(dev, PCI_D0);
2512 pci_restore_state(dev);
2513 err = pci_enable_device(dev);
2515 fw_error("pci_enable_device failed\n");
2519 return ohci_enable(&ohci->card, NULL, 0);
2523 static struct pci_device_id pci_table[] = {
2524 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2528 MODULE_DEVICE_TABLE(pci, pci_table);
2530 static struct pci_driver fw_ohci_pci_driver = {
2531 .name = ohci_driver_name,
2532 .id_table = pci_table,
2534 .remove = pci_remove,
2536 .resume = pci_resume,
2537 .suspend = pci_suspend,
2541 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2542 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2543 MODULE_LICENSE("GPL");
2545 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2546 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2547 MODULE_ALIAS("ohci1394");
2550 static int __init fw_ohci_init(void)
2552 return pci_register_driver(&fw_ohci_pci_driver);
2555 static void __exit fw_ohci_cleanup(void)
2557 pci_unregister_driver(&fw_ohci_pci_driver);
2560 module_init(fw_ohci_init);
2561 module_exit(fw_ohci_cleanup);