2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/gfp.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/pci.h>
32 #include <linux/spinlock.h>
35 #include <asm/system.h>
37 #ifdef CONFIG_PPC_PMAC
38 #include <asm/pmac_feature.h>
42 #include "fw-transaction.h"
44 #define DESCRIPTOR_OUTPUT_MORE 0
45 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
46 #define DESCRIPTOR_INPUT_MORE (2 << 12)
47 #define DESCRIPTOR_INPUT_LAST (3 << 12)
48 #define DESCRIPTOR_STATUS (1 << 11)
49 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
50 #define DESCRIPTOR_PING (1 << 7)
51 #define DESCRIPTOR_YY (1 << 6)
52 #define DESCRIPTOR_NO_IRQ (0 << 4)
53 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
54 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
55 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
56 #define DESCRIPTOR_WAIT (3 << 0)
62 __le32 branch_address;
64 __le16 transfer_status;
65 } __attribute__((aligned(16)));
67 struct db_descriptor {
70 __le16 second_req_count;
71 __le16 first_req_count;
72 __le32 branch_address;
73 __le16 second_res_count;
74 __le16 first_res_count;
79 } __attribute__((aligned(16)));
81 #define CONTROL_SET(regs) (regs)
82 #define CONTROL_CLEAR(regs) ((regs) + 4)
83 #define COMMAND_PTR(regs) ((regs) + 12)
84 #define CONTEXT_MATCH(regs) ((regs) + 16)
87 struct descriptor descriptor;
88 struct ar_buffer *next;
94 struct ar_buffer *current_buffer;
95 struct ar_buffer *last_buffer;
98 struct tasklet_struct tasklet;
103 typedef int (*descriptor_callback_t)(struct context *ctx,
104 struct descriptor *d,
105 struct descriptor *last);
108 * A buffer that contains a block of DMA-able coherent memory used for
109 * storing a portion of a DMA descriptor program.
111 struct descriptor_buffer {
112 struct list_head list;
113 dma_addr_t buffer_bus;
116 struct descriptor buffer[0];
120 struct fw_ohci *ohci;
122 int total_allocation;
125 * List of page-sized buffers for storing DMA descriptors.
126 * Head of list contains buffers in use and tail of list contains
129 struct list_head buffer_list;
132 * Pointer to a buffer inside buffer_list that contains the tail
133 * end of the current DMA program.
135 struct descriptor_buffer *buffer_tail;
138 * The descriptor containing the branch address of the first
139 * descriptor that has not yet been filled by the device.
141 struct descriptor *last;
144 * The last descriptor in the DMA program. It contains the branch
145 * address that must be updated upon appending a new descriptor.
147 struct descriptor *prev;
149 descriptor_callback_t callback;
151 struct tasklet_struct tasklet;
154 #define IT_HEADER_SY(v) ((v) << 0)
155 #define IT_HEADER_TCODE(v) ((v) << 4)
156 #define IT_HEADER_CHANNEL(v) ((v) << 8)
157 #define IT_HEADER_TAG(v) ((v) << 14)
158 #define IT_HEADER_SPEED(v) ((v) << 16)
159 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
162 struct fw_iso_context base;
163 struct context context;
166 size_t header_length;
169 #define CONFIG_ROM_SIZE 1024
175 __iomem char *registers;
176 dma_addr_t self_id_bus;
178 struct tasklet_struct bus_reset_tasklet;
181 int request_generation; /* for timestamping incoming requests */
184 bool bus_reset_packet_quirk;
187 * Spinlock for accessing fw_ohci data. Never call out of
188 * this driver with this lock held.
191 u32 self_id_buffer[512];
193 /* Config rom buffers */
195 dma_addr_t config_rom_bus;
196 __be32 *next_config_rom;
197 dma_addr_t next_config_rom_bus;
200 struct ar_context ar_request_ctx;
201 struct ar_context ar_response_ctx;
202 struct context at_request_ctx;
203 struct context at_response_ctx;
206 struct iso_context *it_context_list;
208 struct iso_context *ir_context_list;
211 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
213 return container_of(card, struct fw_ohci, card);
216 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
217 #define IR_CONTEXT_BUFFER_FILL 0x80000000
218 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
219 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
220 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
221 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
223 #define CONTEXT_RUN 0x8000
224 #define CONTEXT_WAKE 0x1000
225 #define CONTEXT_DEAD 0x0800
226 #define CONTEXT_ACTIVE 0x0400
228 #define OHCI1394_MAX_AT_REQ_RETRIES 0x2
229 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
230 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
232 #define FW_OHCI_MAJOR 240
233 #define OHCI1394_REGISTER_SIZE 0x800
234 #define OHCI_LOOP_COUNT 500
235 #define OHCI1394_PCI_HCI_Control 0x40
236 #define SELF_ID_BUF_SIZE 0x800
237 #define OHCI_TCODE_PHY_PACKET 0x0e
238 #define OHCI_VERSION_1_1 0x010010
240 static char ohci_driver_name[] = KBUILD_MODNAME;
242 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
244 #define OHCI_PARAM_DEBUG_AT_AR 1
245 #define OHCI_PARAM_DEBUG_SELFIDS 2
246 #define OHCI_PARAM_DEBUG_IRQS 4
247 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
249 static int param_debug;
250 module_param_named(debug, param_debug, int, 0644);
251 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
252 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
253 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
254 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
255 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
256 ", or a combination, or all = -1)");
258 static void log_irqs(u32 evt)
260 if (likely(!(param_debug &
261 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
264 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
265 !(evt & OHCI1394_busReset))
268 printk(KERN_DEBUG KBUILD_MODNAME ": IRQ "
269 "%08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
271 evt & OHCI1394_selfIDComplete ? " selfID" : "",
272 evt & OHCI1394_RQPkt ? " AR_req" : "",
273 evt & OHCI1394_RSPkt ? " AR_resp" : "",
274 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
275 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
276 evt & OHCI1394_isochRx ? " IR" : "",
277 evt & OHCI1394_isochTx ? " IT" : "",
278 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
279 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
280 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
281 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
282 evt & OHCI1394_busReset ? " busReset" : "",
283 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
284 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
285 OHCI1394_respTxComplete | OHCI1394_isochRx |
286 OHCI1394_isochTx | OHCI1394_postedWriteErr |
287 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
288 OHCI1394_regAccessFail | OHCI1394_busReset)
292 static const char *speed[] = {
293 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
295 static const char *power[] = {
296 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
297 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
299 static const char port[] = { '.', '-', 'p', 'c', };
301 static char _p(u32 *s, int shift)
303 return port[*s >> shift & 3];
306 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
308 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
311 printk(KERN_DEBUG KBUILD_MODNAME ": %d selfIDs, generation %d, "
312 "local node ID %04x\n", self_id_count, generation, node_id);
314 for (; self_id_count--; ++s)
315 if ((*s & 1 << 23) == 0)
316 printk(KERN_DEBUG "selfID 0: %08x, phy %d [%c%c%c] "
317 "%s gc=%d %s %s%s%s\n",
318 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
319 speed[*s >> 14 & 3], *s >> 16 & 63,
320 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
321 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
323 printk(KERN_DEBUG "selfID n: %08x, phy %d "
324 "[%c%c%c%c%c%c%c%c]\n",
326 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
327 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
330 static const char *evts[] = {
331 [0x00] = "evt_no_status", [0x01] = "-reserved-",
332 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
333 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
334 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
335 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
336 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
337 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
338 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
339 [0x10] = "-reserved-", [0x11] = "ack_complete",
340 [0x12] = "ack_pending ", [0x13] = "-reserved-",
341 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
342 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
343 [0x18] = "-reserved-", [0x19] = "-reserved-",
344 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
345 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
346 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
347 [0x20] = "pending/cancelled",
349 static const char *tcodes[] = {
350 [0x0] = "QW req", [0x1] = "BW req",
351 [0x2] = "W resp", [0x3] = "-reserved-",
352 [0x4] = "QR req", [0x5] = "BR req",
353 [0x6] = "QR resp", [0x7] = "BR resp",
354 [0x8] = "cycle start", [0x9] = "Lk req",
355 [0xa] = "async stream packet", [0xb] = "Lk resp",
356 [0xc] = "-reserved-", [0xd] = "-reserved-",
357 [0xe] = "link internal", [0xf] = "-reserved-",
359 static const char *phys[] = {
360 [0x0] = "phy config packet", [0x1] = "link-on packet",
361 [0x2] = "self-id packet", [0x3] = "-reserved-",
364 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
366 int tcode = header[0] >> 4 & 0xf;
369 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
372 if (unlikely(evt >= ARRAY_SIZE(evts)))
375 if (evt == OHCI1394_evt_bus_reset) {
376 printk(KERN_DEBUG "A%c evt_bus_reset, generation %d\n",
377 dir, (header[2] >> 16) & 0xff);
381 if (header[0] == ~header[1]) {
382 printk(KERN_DEBUG "A%c %s, %s, %08x\n",
383 dir, evts[evt], phys[header[0] >> 30 & 0x3],
389 case 0x0: case 0x6: case 0x8:
390 snprintf(specific, sizeof(specific), " = %08x",
391 be32_to_cpu((__force __be32)header[3]));
393 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
394 snprintf(specific, sizeof(specific), " %x,%x",
395 header[3] >> 16, header[3] & 0xffff);
403 printk(KERN_DEBUG "A%c %s, %s\n",
404 dir, evts[evt], tcodes[tcode]);
406 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
407 printk(KERN_DEBUG "A%c spd %x tl %02x, "
410 dir, speed, header[0] >> 10 & 0x3f,
411 header[1] >> 16, header[0] >> 16, evts[evt],
412 tcodes[tcode], header[1] & 0xffff, header[2], specific);
415 printk(KERN_DEBUG "A%c spd %x tl %02x, "
418 dir, speed, header[0] >> 10 & 0x3f,
419 header[1] >> 16, header[0] >> 16, evts[evt],
420 tcodes[tcode], specific);
426 #define log_irqs(evt)
427 #define log_selfids(node_id, generation, self_id_count, sid)
428 #define log_ar_at_event(dir, speed, header, evt)
430 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
432 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
434 writel(data, ohci->registers + offset);
437 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
439 return readl(ohci->registers + offset);
442 static inline void flush_writes(const struct fw_ohci *ohci)
444 /* Do a dummy read to flush writes. */
445 reg_read(ohci, OHCI1394_Version);
449 ohci_update_phy_reg(struct fw_card *card, int addr,
450 int clear_bits, int set_bits)
452 struct fw_ohci *ohci = fw_ohci(card);
455 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
458 val = reg_read(ohci, OHCI1394_PhyControl);
459 if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
460 fw_error("failed to set phy reg bits.\n");
464 old = OHCI1394_PhyControl_ReadData(val);
465 old = (old & ~clear_bits) | set_bits;
466 reg_write(ohci, OHCI1394_PhyControl,
467 OHCI1394_PhyControl_Write(addr, old));
472 static int ar_context_add_page(struct ar_context *ctx)
474 struct device *dev = ctx->ohci->card.device;
475 struct ar_buffer *ab;
476 dma_addr_t uninitialized_var(ab_bus);
479 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
483 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
484 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
486 DESCRIPTOR_BRANCH_ALWAYS);
487 offset = offsetof(struct ar_buffer, data);
488 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
489 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
490 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
491 ab->descriptor.branch_address = 0;
493 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
494 ctx->last_buffer->next = ab;
495 ctx->last_buffer = ab;
497 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
498 flush_writes(ctx->ohci);
503 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
504 #define cond_le32_to_cpu(v) \
505 (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
507 #define cond_le32_to_cpu(v) le32_to_cpu(v)
510 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
512 struct fw_ohci *ohci = ctx->ohci;
514 u32 status, length, tcode;
517 p.header[0] = cond_le32_to_cpu(buffer[0]);
518 p.header[1] = cond_le32_to_cpu(buffer[1]);
519 p.header[2] = cond_le32_to_cpu(buffer[2]);
521 tcode = (p.header[0] >> 4) & 0x0f;
523 case TCODE_WRITE_QUADLET_REQUEST:
524 case TCODE_READ_QUADLET_RESPONSE:
525 p.header[3] = (__force __u32) buffer[3];
526 p.header_length = 16;
527 p.payload_length = 0;
530 case TCODE_READ_BLOCK_REQUEST :
531 p.header[3] = cond_le32_to_cpu(buffer[3]);
532 p.header_length = 16;
533 p.payload_length = 0;
536 case TCODE_WRITE_BLOCK_REQUEST:
537 case TCODE_READ_BLOCK_RESPONSE:
538 case TCODE_LOCK_REQUEST:
539 case TCODE_LOCK_RESPONSE:
540 p.header[3] = cond_le32_to_cpu(buffer[3]);
541 p.header_length = 16;
542 p.payload_length = p.header[3] >> 16;
545 case TCODE_WRITE_RESPONSE:
546 case TCODE_READ_QUADLET_REQUEST:
547 case OHCI_TCODE_PHY_PACKET:
548 p.header_length = 12;
549 p.payload_length = 0;
553 /* FIXME: Stop context, discard everything, and restart? */
555 p.payload_length = 0;
558 p.payload = (void *) buffer + p.header_length;
560 /* FIXME: What to do about evt_* errors? */
561 length = (p.header_length + p.payload_length + 3) / 4;
562 status = cond_le32_to_cpu(buffer[length]);
563 evt = (status >> 16) & 0x1f;
566 p.speed = (status >> 21) & 0x7;
567 p.timestamp = status & 0xffff;
568 p.generation = ohci->request_generation;
570 log_ar_at_event('R', p.speed, p.header, evt);
573 * The OHCI bus reset handler synthesizes a phy packet with
574 * the new generation number when a bus reset happens (see
575 * section 8.4.2.3). This helps us determine when a request
576 * was received and make sure we send the response in the same
577 * generation. We only need this for requests; for responses
578 * we use the unique tlabel for finding the matching
581 * Alas some chips sometimes emit bus reset packets with a
582 * wrong generation. We set the correct generation for these
583 * at a slightly incorrect time (in bus_reset_tasklet).
585 if (evt == OHCI1394_evt_bus_reset) {
586 if (!ohci->bus_reset_packet_quirk)
587 ohci->request_generation = (p.header[2] >> 16) & 0xff;
588 } else if (ctx == &ohci->ar_request_ctx) {
589 fw_core_handle_request(&ohci->card, &p);
591 fw_core_handle_response(&ohci->card, &p);
594 return buffer + length + 1;
597 static void ar_context_tasklet(unsigned long data)
599 struct ar_context *ctx = (struct ar_context *)data;
600 struct fw_ohci *ohci = ctx->ohci;
601 struct ar_buffer *ab;
602 struct descriptor *d;
605 ab = ctx->current_buffer;
608 if (d->res_count == 0) {
609 size_t size, rest, offset;
610 dma_addr_t start_bus;
614 * This descriptor is finished and we may have a
615 * packet split across this and the next buffer. We
616 * reuse the page for reassembling the split packet.
619 offset = offsetof(struct ar_buffer, data);
621 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
625 size = buffer + PAGE_SIZE - ctx->pointer;
626 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
627 memmove(buffer, ctx->pointer, size);
628 memcpy(buffer + size, ab->data, rest);
629 ctx->current_buffer = ab;
630 ctx->pointer = (void *) ab->data + rest;
631 end = buffer + size + rest;
634 buffer = handle_ar_packet(ctx, buffer);
636 dma_free_coherent(ohci->card.device, PAGE_SIZE,
638 ar_context_add_page(ctx);
640 buffer = ctx->pointer;
642 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
645 buffer = handle_ar_packet(ctx, buffer);
650 ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs)
656 ctx->last_buffer = &ab;
657 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
659 ar_context_add_page(ctx);
660 ar_context_add_page(ctx);
661 ctx->current_buffer = ab.next;
662 ctx->pointer = ctx->current_buffer->data;
667 static void ar_context_run(struct ar_context *ctx)
669 struct ar_buffer *ab = ctx->current_buffer;
673 offset = offsetof(struct ar_buffer, data);
674 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
676 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
677 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
678 flush_writes(ctx->ohci);
681 static struct descriptor *
682 find_branch_descriptor(struct descriptor *d, int z)
686 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
687 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
689 /* figure out which descriptor the branch address goes in */
690 if (z == 2 && (b == 3 || key == 2))
696 static void context_tasklet(unsigned long data)
698 struct context *ctx = (struct context *) data;
699 struct descriptor *d, *last;
702 struct descriptor_buffer *desc;
704 desc = list_entry(ctx->buffer_list.next,
705 struct descriptor_buffer, list);
707 while (last->branch_address != 0) {
708 struct descriptor_buffer *old_desc = desc;
709 address = le32_to_cpu(last->branch_address);
713 /* If the branch address points to a buffer outside of the
714 * current buffer, advance to the next buffer. */
715 if (address < desc->buffer_bus ||
716 address >= desc->buffer_bus + desc->used)
717 desc = list_entry(desc->list.next,
718 struct descriptor_buffer, list);
719 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
720 last = find_branch_descriptor(d, z);
722 if (!ctx->callback(ctx, d, last))
725 if (old_desc != desc) {
726 /* If we've advanced to the next buffer, move the
727 * previous buffer to the free list. */
730 spin_lock_irqsave(&ctx->ohci->lock, flags);
731 list_move_tail(&old_desc->list, &ctx->buffer_list);
732 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
739 * Allocate a new buffer and add it to the list of free buffers for this
740 * context. Must be called with ohci->lock held.
743 context_add_buffer(struct context *ctx)
745 struct descriptor_buffer *desc;
746 dma_addr_t uninitialized_var(bus_addr);
750 * 16MB of descriptors should be far more than enough for any DMA
751 * program. This will catch run-away userspace or DoS attacks.
753 if (ctx->total_allocation >= 16*1024*1024)
756 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
757 &bus_addr, GFP_ATOMIC);
761 offset = (void *)&desc->buffer - (void *)desc;
762 desc->buffer_size = PAGE_SIZE - offset;
763 desc->buffer_bus = bus_addr + offset;
766 list_add_tail(&desc->list, &ctx->buffer_list);
767 ctx->total_allocation += PAGE_SIZE;
773 context_init(struct context *ctx, struct fw_ohci *ohci,
774 u32 regs, descriptor_callback_t callback)
778 ctx->total_allocation = 0;
780 INIT_LIST_HEAD(&ctx->buffer_list);
781 if (context_add_buffer(ctx) < 0)
784 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
785 struct descriptor_buffer, list);
787 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
788 ctx->callback = callback;
791 * We put a dummy descriptor in the buffer that has a NULL
792 * branch address and looks like it's been sent. That way we
793 * have a descriptor to append DMA programs to.
795 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
796 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
797 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
798 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
799 ctx->last = ctx->buffer_tail->buffer;
800 ctx->prev = ctx->buffer_tail->buffer;
806 context_release(struct context *ctx)
808 struct fw_card *card = &ctx->ohci->card;
809 struct descriptor_buffer *desc, *tmp;
811 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
812 dma_free_coherent(card->device, PAGE_SIZE, desc,
814 ((void *)&desc->buffer - (void *)desc));
817 /* Must be called with ohci->lock held */
818 static struct descriptor *
819 context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus)
821 struct descriptor *d = NULL;
822 struct descriptor_buffer *desc = ctx->buffer_tail;
824 if (z * sizeof(*d) > desc->buffer_size)
827 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
828 /* No room for the descriptor in this buffer, so advance to the
831 if (desc->list.next == &ctx->buffer_list) {
832 /* If there is no free buffer next in the list,
834 if (context_add_buffer(ctx) < 0)
837 desc = list_entry(desc->list.next,
838 struct descriptor_buffer, list);
839 ctx->buffer_tail = desc;
842 d = desc->buffer + desc->used / sizeof(*d);
843 memset(d, 0, z * sizeof(*d));
844 *d_bus = desc->buffer_bus + desc->used;
849 static void context_run(struct context *ctx, u32 extra)
851 struct fw_ohci *ohci = ctx->ohci;
853 reg_write(ohci, COMMAND_PTR(ctx->regs),
854 le32_to_cpu(ctx->last->branch_address));
855 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
856 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
860 static void context_append(struct context *ctx,
861 struct descriptor *d, int z, int extra)
864 struct descriptor_buffer *desc = ctx->buffer_tail;
866 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
868 desc->used += (z + extra) * sizeof(*d);
869 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
870 ctx->prev = find_branch_descriptor(d, z);
872 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
873 flush_writes(ctx->ohci);
876 static void context_stop(struct context *ctx)
881 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
882 flush_writes(ctx->ohci);
884 for (i = 0; i < 10; i++) {
885 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
886 if ((reg & CONTEXT_ACTIVE) == 0)
889 fw_notify("context_stop: still active (0x%08x)\n", reg);
895 struct fw_packet *packet;
899 * This function apppends a packet to the DMA queue for transmission.
900 * Must always be called with the ochi->lock held to ensure proper
901 * generation handling and locking around packet queue manipulation.
904 at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
906 struct fw_ohci *ohci = ctx->ohci;
907 dma_addr_t d_bus, uninitialized_var(payload_bus);
908 struct driver_data *driver_data;
909 struct descriptor *d, *last;
914 d = context_get_descriptors(ctx, 4, &d_bus);
916 packet->ack = RCODE_SEND_ERROR;
920 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
921 d[0].res_count = cpu_to_le16(packet->timestamp);
924 * The DMA format for asyncronous link packets is different
925 * from the IEEE1394 layout, so shift the fields around
926 * accordingly. If header_length is 8, it's a PHY packet, to
927 * which we need to prepend an extra quadlet.
930 header = (__le32 *) &d[1];
931 if (packet->header_length > 8) {
932 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
933 (packet->speed << 16));
934 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
935 (packet->header[0] & 0xffff0000));
936 header[2] = cpu_to_le32(packet->header[2]);
938 tcode = (packet->header[0] >> 4) & 0x0f;
939 if (TCODE_IS_BLOCK_PACKET(tcode))
940 header[3] = cpu_to_le32(packet->header[3]);
942 header[3] = (__force __le32) packet->header[3];
944 d[0].req_count = cpu_to_le16(packet->header_length);
946 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
947 (packet->speed << 16));
948 header[1] = cpu_to_le32(packet->header[0]);
949 header[2] = cpu_to_le32(packet->header[1]);
950 d[0].req_count = cpu_to_le16(12);
953 driver_data = (struct driver_data *) &d[3];
954 driver_data->packet = packet;
955 packet->driver_data = driver_data;
957 if (packet->payload_length > 0) {
959 dma_map_single(ohci->card.device, packet->payload,
960 packet->payload_length, DMA_TO_DEVICE);
961 if (dma_mapping_error(payload_bus)) {
962 packet->ack = RCODE_SEND_ERROR;
966 d[2].req_count = cpu_to_le16(packet->payload_length);
967 d[2].data_address = cpu_to_le32(payload_bus);
975 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
976 DESCRIPTOR_IRQ_ALWAYS |
977 DESCRIPTOR_BRANCH_ALWAYS);
980 * If the controller and packet generations don't match, we need to
981 * bail out and try again. If IntEvent.busReset is set, the AT context
982 * is halted, so appending to the context and trying to run it is
983 * futile. Most controllers do the right thing and just flush the AT
984 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
985 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
986 * up stalling out. So we just bail out in software and try again
987 * later, and everyone is happy.
988 * FIXME: Document how the locking works.
990 if (ohci->generation != packet->generation ||
991 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
992 if (packet->payload_length > 0)
993 dma_unmap_single(ohci->card.device, payload_bus,
994 packet->payload_length, DMA_TO_DEVICE);
995 packet->ack = RCODE_GENERATION;
999 context_append(ctx, d, z, 4 - z);
1001 /* If the context isn't already running, start it up. */
1002 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1003 if ((reg & CONTEXT_RUN) == 0)
1004 context_run(ctx, 0);
1009 static int handle_at_packet(struct context *context,
1010 struct descriptor *d,
1011 struct descriptor *last)
1013 struct driver_data *driver_data;
1014 struct fw_packet *packet;
1015 struct fw_ohci *ohci = context->ohci;
1016 dma_addr_t payload_bus;
1019 if (last->transfer_status == 0)
1020 /* This descriptor isn't done yet, stop iteration. */
1023 driver_data = (struct driver_data *) &d[3];
1024 packet = driver_data->packet;
1026 /* This packet was cancelled, just continue. */
1029 payload_bus = le32_to_cpu(last->data_address);
1030 if (payload_bus != 0)
1031 dma_unmap_single(ohci->card.device, payload_bus,
1032 packet->payload_length, DMA_TO_DEVICE);
1034 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1035 packet->timestamp = le16_to_cpu(last->res_count);
1037 log_ar_at_event('T', packet->speed, packet->header, evt);
1040 case OHCI1394_evt_timeout:
1041 /* Async response transmit timed out. */
1042 packet->ack = RCODE_CANCELLED;
1045 case OHCI1394_evt_flushed:
1047 * The packet was flushed should give same error as
1048 * when we try to use a stale generation count.
1050 packet->ack = RCODE_GENERATION;
1053 case OHCI1394_evt_missing_ack:
1055 * Using a valid (current) generation count, but the
1056 * node is not on the bus or not sending acks.
1058 packet->ack = RCODE_NO_ACK;
1061 case ACK_COMPLETE + 0x10:
1062 case ACK_PENDING + 0x10:
1063 case ACK_BUSY_X + 0x10:
1064 case ACK_BUSY_A + 0x10:
1065 case ACK_BUSY_B + 0x10:
1066 case ACK_DATA_ERROR + 0x10:
1067 case ACK_TYPE_ERROR + 0x10:
1068 packet->ack = evt - 0x10;
1072 packet->ack = RCODE_SEND_ERROR;
1076 packet->callback(packet, &ohci->card, packet->ack);
1081 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1082 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1083 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1084 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1085 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1088 handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
1090 struct fw_packet response;
1091 int tcode, length, i;
1093 tcode = HEADER_GET_TCODE(packet->header[0]);
1094 if (TCODE_IS_BLOCK_PACKET(tcode))
1095 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1099 i = csr - CSR_CONFIG_ROM;
1100 if (i + length > CONFIG_ROM_SIZE) {
1101 fw_fill_response(&response, packet->header,
1102 RCODE_ADDRESS_ERROR, NULL, 0);
1103 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1104 fw_fill_response(&response, packet->header,
1105 RCODE_TYPE_ERROR, NULL, 0);
1107 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1108 (void *) ohci->config_rom + i, length);
1111 fw_core_handle_response(&ohci->card, &response);
1115 handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
1117 struct fw_packet response;
1118 int tcode, length, ext_tcode, sel;
1119 __be32 *payload, lock_old;
1120 u32 lock_arg, lock_data;
1122 tcode = HEADER_GET_TCODE(packet->header[0]);
1123 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1124 payload = packet->payload;
1125 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1127 if (tcode == TCODE_LOCK_REQUEST &&
1128 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1129 lock_arg = be32_to_cpu(payload[0]);
1130 lock_data = be32_to_cpu(payload[1]);
1131 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1135 fw_fill_response(&response, packet->header,
1136 RCODE_TYPE_ERROR, NULL, 0);
1140 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1141 reg_write(ohci, OHCI1394_CSRData, lock_data);
1142 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1143 reg_write(ohci, OHCI1394_CSRControl, sel);
1145 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1146 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1148 fw_notify("swap not done yet\n");
1150 fw_fill_response(&response, packet->header,
1151 RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1153 fw_core_handle_response(&ohci->card, &response);
1157 handle_local_request(struct context *ctx, struct fw_packet *packet)
1162 if (ctx == &ctx->ohci->at_request_ctx) {
1163 packet->ack = ACK_PENDING;
1164 packet->callback(packet, &ctx->ohci->card, packet->ack);
1168 ((unsigned long long)
1169 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1171 csr = offset - CSR_REGISTER_BASE;
1173 /* Handle config rom reads. */
1174 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1175 handle_local_rom(ctx->ohci, packet, csr);
1177 case CSR_BUS_MANAGER_ID:
1178 case CSR_BANDWIDTH_AVAILABLE:
1179 case CSR_CHANNELS_AVAILABLE_HI:
1180 case CSR_CHANNELS_AVAILABLE_LO:
1181 handle_local_lock(ctx->ohci, packet, csr);
1184 if (ctx == &ctx->ohci->at_request_ctx)
1185 fw_core_handle_request(&ctx->ohci->card, packet);
1187 fw_core_handle_response(&ctx->ohci->card, packet);
1191 if (ctx == &ctx->ohci->at_response_ctx) {
1192 packet->ack = ACK_COMPLETE;
1193 packet->callback(packet, &ctx->ohci->card, packet->ack);
1198 at_context_transmit(struct context *ctx, struct fw_packet *packet)
1200 unsigned long flags;
1203 spin_lock_irqsave(&ctx->ohci->lock, flags);
1205 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1206 ctx->ohci->generation == packet->generation) {
1207 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1208 handle_local_request(ctx, packet);
1212 retval = at_context_queue_packet(ctx, packet);
1213 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1216 packet->callback(packet, &ctx->ohci->card, packet->ack);
1220 static void bus_reset_tasklet(unsigned long data)
1222 struct fw_ohci *ohci = (struct fw_ohci *)data;
1223 int self_id_count, i, j, reg;
1224 int generation, new_generation;
1225 unsigned long flags;
1226 void *free_rom = NULL;
1227 dma_addr_t free_rom_bus = 0;
1229 reg = reg_read(ohci, OHCI1394_NodeID);
1230 if (!(reg & OHCI1394_NodeID_idValid)) {
1231 fw_notify("node ID not valid, new bus reset in progress\n");
1234 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1235 fw_notify("malconfigured bus\n");
1238 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1239 OHCI1394_NodeID_nodeNumber);
1241 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1242 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1243 fw_notify("inconsistent self IDs\n");
1247 * The count in the SelfIDCount register is the number of
1248 * bytes in the self ID receive buffer. Since we also receive
1249 * the inverted quadlets and a header quadlet, we shift one
1250 * bit extra to get the actual number of self IDs.
1252 self_id_count = (reg >> 3) & 0x3ff;
1253 if (self_id_count == 0) {
1254 fw_notify("inconsistent self IDs\n");
1257 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1260 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1261 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1262 fw_notify("inconsistent self IDs\n");
1265 ohci->self_id_buffer[j] =
1266 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1271 * Check the consistency of the self IDs we just read. The
1272 * problem we face is that a new bus reset can start while we
1273 * read out the self IDs from the DMA buffer. If this happens,
1274 * the DMA buffer will be overwritten with new self IDs and we
1275 * will read out inconsistent data. The OHCI specification
1276 * (section 11.2) recommends a technique similar to
1277 * linux/seqlock.h, where we remember the generation of the
1278 * self IDs in the buffer before reading them out and compare
1279 * it to the current generation after reading them out. If
1280 * the two generations match we know we have a consistent set
1284 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1285 if (new_generation != generation) {
1286 fw_notify("recursive bus reset detected, "
1287 "discarding self ids\n");
1291 /* FIXME: Document how the locking works. */
1292 spin_lock_irqsave(&ohci->lock, flags);
1294 ohci->generation = generation;
1295 context_stop(&ohci->at_request_ctx);
1296 context_stop(&ohci->at_response_ctx);
1297 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1299 if (ohci->bus_reset_packet_quirk)
1300 ohci->request_generation = generation;
1303 * This next bit is unrelated to the AT context stuff but we
1304 * have to do it under the spinlock also. If a new config rom
1305 * was set up before this reset, the old one is now no longer
1306 * in use and we can free it. Update the config rom pointers
1307 * to point to the current config rom and clear the
1308 * next_config_rom pointer so a new udpate can take place.
1311 if (ohci->next_config_rom != NULL) {
1312 if (ohci->next_config_rom != ohci->config_rom) {
1313 free_rom = ohci->config_rom;
1314 free_rom_bus = ohci->config_rom_bus;
1316 ohci->config_rom = ohci->next_config_rom;
1317 ohci->config_rom_bus = ohci->next_config_rom_bus;
1318 ohci->next_config_rom = NULL;
1321 * Restore config_rom image and manually update
1322 * config_rom registers. Writing the header quadlet
1323 * will indicate that the config rom is ready, so we
1326 reg_write(ohci, OHCI1394_BusOptions,
1327 be32_to_cpu(ohci->config_rom[2]));
1328 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
1329 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
1332 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1333 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1334 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1337 spin_unlock_irqrestore(&ohci->lock, flags);
1340 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1341 free_rom, free_rom_bus);
1343 log_selfids(ohci->node_id, generation,
1344 self_id_count, ohci->self_id_buffer);
1346 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1347 self_id_count, ohci->self_id_buffer);
1350 static irqreturn_t irq_handler(int irq, void *data)
1352 struct fw_ohci *ohci = data;
1353 u32 event, iso_event, cycle_time;
1356 event = reg_read(ohci, OHCI1394_IntEventClear);
1358 if (!event || !~event)
1361 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1362 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1365 if (event & OHCI1394_selfIDComplete)
1366 tasklet_schedule(&ohci->bus_reset_tasklet);
1368 if (event & OHCI1394_RQPkt)
1369 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1371 if (event & OHCI1394_RSPkt)
1372 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1374 if (event & OHCI1394_reqTxComplete)
1375 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1377 if (event & OHCI1394_respTxComplete)
1378 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1380 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1381 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1384 i = ffs(iso_event) - 1;
1385 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1386 iso_event &= ~(1 << i);
1389 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1390 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1393 i = ffs(iso_event) - 1;
1394 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1395 iso_event &= ~(1 << i);
1398 if (unlikely(event & OHCI1394_regAccessFail))
1399 fw_error("Register access failure - "
1400 "please notify linux1394-devel@lists.sf.net\n");
1402 if (unlikely(event & OHCI1394_postedWriteErr))
1403 fw_error("PCI posted write error\n");
1405 if (unlikely(event & OHCI1394_cycleTooLong)) {
1406 if (printk_ratelimit())
1407 fw_notify("isochronous cycle too long\n");
1408 reg_write(ohci, OHCI1394_LinkControlSet,
1409 OHCI1394_LinkControl_cycleMaster);
1412 if (event & OHCI1394_cycle64Seconds) {
1413 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1414 if ((cycle_time & 0x80000000) == 0)
1415 ohci->bus_seconds++;
1421 static int software_reset(struct fw_ohci *ohci)
1425 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1427 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1428 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1429 OHCI1394_HCControl_softReset) == 0)
1437 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1439 struct fw_ohci *ohci = fw_ohci(card);
1440 struct pci_dev *dev = to_pci_dev(card->device);
1444 if (software_reset(ohci)) {
1445 fw_error("Failed to reset ohci card.\n");
1450 * Now enable LPS, which we need in order to start accessing
1451 * most of the registers. In fact, on some cards (ALI M5251),
1452 * accessing registers in the SClk domain without LPS enabled
1453 * will lock up the machine. Wait 50msec to make sure we have
1454 * full link enabled. However, with some cards (well, at least
1455 * a JMicron PCIe card), we have to try again sometimes.
1457 reg_write(ohci, OHCI1394_HCControlSet,
1458 OHCI1394_HCControl_LPS |
1459 OHCI1394_HCControl_postedWriteEnable);
1462 for (lps = 0, i = 0; !lps && i < 3; i++) {
1464 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1465 OHCI1394_HCControl_LPS;
1469 fw_error("Failed to set Link Power Status\n");
1473 reg_write(ohci, OHCI1394_HCControlClear,
1474 OHCI1394_HCControl_noByteSwapData);
1476 reg_write(ohci, OHCI1394_LinkControlSet,
1477 OHCI1394_LinkControl_rcvSelfID |
1478 OHCI1394_LinkControl_cycleTimerEnable |
1479 OHCI1394_LinkControl_cycleMaster);
1481 reg_write(ohci, OHCI1394_ATRetries,
1482 OHCI1394_MAX_AT_REQ_RETRIES |
1483 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1484 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1486 ar_context_run(&ohci->ar_request_ctx);
1487 ar_context_run(&ohci->ar_response_ctx);
1489 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1490 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1491 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1492 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1493 reg_write(ohci, OHCI1394_IntMaskSet,
1494 OHCI1394_selfIDComplete |
1495 OHCI1394_RQPkt | OHCI1394_RSPkt |
1496 OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1497 OHCI1394_isochRx | OHCI1394_isochTx |
1498 OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1499 OHCI1394_cycle64Seconds | OHCI1394_regAccessFail |
1500 OHCI1394_masterIntEnable);
1501 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1502 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
1504 /* Activate link_on bit and contender bit in our self ID packets.*/
1505 if (ohci_update_phy_reg(card, 4, 0,
1506 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1510 * When the link is not yet enabled, the atomic config rom
1511 * update mechanism described below in ohci_set_config_rom()
1512 * is not active. We have to update ConfigRomHeader and
1513 * BusOptions manually, and the write to ConfigROMmap takes
1514 * effect immediately. We tie this to the enabling of the
1515 * link, so we have a valid config rom before enabling - the
1516 * OHCI requires that ConfigROMhdr and BusOptions have valid
1517 * values before enabling.
1519 * However, when the ConfigROMmap is written, some controllers
1520 * always read back quadlets 0 and 2 from the config rom to
1521 * the ConfigRomHeader and BusOptions registers on bus reset.
1522 * They shouldn't do that in this initial case where the link
1523 * isn't enabled. This means we have to use the same
1524 * workaround here, setting the bus header to 0 and then write
1525 * the right values in the bus reset tasklet.
1529 ohci->next_config_rom =
1530 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1531 &ohci->next_config_rom_bus,
1533 if (ohci->next_config_rom == NULL)
1536 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1537 fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1540 * In the suspend case, config_rom is NULL, which
1541 * means that we just reuse the old config rom.
1543 ohci->next_config_rom = ohci->config_rom;
1544 ohci->next_config_rom_bus = ohci->config_rom_bus;
1547 ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]);
1548 ohci->next_config_rom[0] = 0;
1549 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1550 reg_write(ohci, OHCI1394_BusOptions,
1551 be32_to_cpu(ohci->next_config_rom[2]));
1552 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1554 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1556 if (request_irq(dev->irq, irq_handler,
1557 IRQF_SHARED, ohci_driver_name, ohci)) {
1558 fw_error("Failed to allocate shared interrupt %d.\n",
1560 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1561 ohci->config_rom, ohci->config_rom_bus);
1565 reg_write(ohci, OHCI1394_HCControlSet,
1566 OHCI1394_HCControl_linkEnable |
1567 OHCI1394_HCControl_BIBimageValid);
1571 * We are ready to go, initiate bus reset to finish the
1575 fw_core_initiate_bus_reset(&ohci->card, 1);
1581 ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
1583 struct fw_ohci *ohci;
1584 unsigned long flags;
1585 int retval = -EBUSY;
1586 __be32 *next_config_rom;
1587 dma_addr_t uninitialized_var(next_config_rom_bus);
1589 ohci = fw_ohci(card);
1592 * When the OHCI controller is enabled, the config rom update
1593 * mechanism is a bit tricky, but easy enough to use. See
1594 * section 5.5.6 in the OHCI specification.
1596 * The OHCI controller caches the new config rom address in a
1597 * shadow register (ConfigROMmapNext) and needs a bus reset
1598 * for the changes to take place. When the bus reset is
1599 * detected, the controller loads the new values for the
1600 * ConfigRomHeader and BusOptions registers from the specified
1601 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1602 * shadow register. All automatically and atomically.
1604 * Now, there's a twist to this story. The automatic load of
1605 * ConfigRomHeader and BusOptions doesn't honor the
1606 * noByteSwapData bit, so with a be32 config rom, the
1607 * controller will load be32 values in to these registers
1608 * during the atomic update, even on litte endian
1609 * architectures. The workaround we use is to put a 0 in the
1610 * header quadlet; 0 is endian agnostic and means that the
1611 * config rom isn't ready yet. In the bus reset tasklet we
1612 * then set up the real values for the two registers.
1614 * We use ohci->lock to avoid racing with the code that sets
1615 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1619 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1620 &next_config_rom_bus, GFP_KERNEL);
1621 if (next_config_rom == NULL)
1624 spin_lock_irqsave(&ohci->lock, flags);
1626 if (ohci->next_config_rom == NULL) {
1627 ohci->next_config_rom = next_config_rom;
1628 ohci->next_config_rom_bus = next_config_rom_bus;
1630 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1631 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1634 ohci->next_header = config_rom[0];
1635 ohci->next_config_rom[0] = 0;
1637 reg_write(ohci, OHCI1394_ConfigROMmap,
1638 ohci->next_config_rom_bus);
1642 spin_unlock_irqrestore(&ohci->lock, flags);
1645 * Now initiate a bus reset to have the changes take
1646 * effect. We clean up the old config rom memory and DMA
1647 * mappings in the bus reset tasklet, since the OHCI
1648 * controller could need to access it before the bus reset
1652 fw_core_initiate_bus_reset(&ohci->card, 1);
1654 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1655 next_config_rom, next_config_rom_bus);
1660 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1662 struct fw_ohci *ohci = fw_ohci(card);
1664 at_context_transmit(&ohci->at_request_ctx, packet);
1667 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1669 struct fw_ohci *ohci = fw_ohci(card);
1671 at_context_transmit(&ohci->at_response_ctx, packet);
1674 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1676 struct fw_ohci *ohci = fw_ohci(card);
1677 struct context *ctx = &ohci->at_request_ctx;
1678 struct driver_data *driver_data = packet->driver_data;
1679 int retval = -ENOENT;
1681 tasklet_disable(&ctx->tasklet);
1683 if (packet->ack != 0)
1686 log_ar_at_event('T', packet->speed, packet->header, 0x20);
1687 driver_data->packet = NULL;
1688 packet->ack = RCODE_CANCELLED;
1689 packet->callback(packet, &ohci->card, packet->ack);
1693 tasklet_enable(&ctx->tasklet);
1699 ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
1701 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1704 struct fw_ohci *ohci = fw_ohci(card);
1705 unsigned long flags;
1709 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1710 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1713 spin_lock_irqsave(&ohci->lock, flags);
1715 if (ohci->generation != generation) {
1721 * Note, if the node ID contains a non-local bus ID, physical DMA is
1722 * enabled for _all_ nodes on remote buses.
1725 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1727 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1729 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1733 spin_unlock_irqrestore(&ohci->lock, flags);
1735 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1739 ohci_get_bus_time(struct fw_card *card)
1741 struct fw_ohci *ohci = fw_ohci(card);
1745 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1746 bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time;
1751 static int handle_ir_dualbuffer_packet(struct context *context,
1752 struct descriptor *d,
1753 struct descriptor *last)
1755 struct iso_context *ctx =
1756 container_of(context, struct iso_context, context);
1757 struct db_descriptor *db = (struct db_descriptor *) d;
1759 size_t header_length;
1763 if (db->first_res_count != 0 && db->second_res_count != 0) {
1764 if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
1765 /* This descriptor isn't done yet, stop iteration. */
1768 ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
1771 header_length = le16_to_cpu(db->first_req_count) -
1772 le16_to_cpu(db->first_res_count);
1774 i = ctx->header_length;
1776 end = p + header_length;
1777 while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
1779 * The iso header is byteswapped to little endian by
1780 * the controller, but the remaining header quadlets
1781 * are big endian. We want to present all the headers
1782 * as big endian, so we have to swap the first
1785 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1786 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1787 i += ctx->base.header_size;
1788 ctx->excess_bytes +=
1789 (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff;
1790 p += ctx->base.header_size + 4;
1792 ctx->header_length = i;
1794 ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
1795 le16_to_cpu(db->second_res_count);
1797 if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1798 ir_header = (__le32 *) (db + 1);
1799 ctx->base.callback(&ctx->base,
1800 le32_to_cpu(ir_header[0]) & 0xffff,
1801 ctx->header_length, ctx->header,
1802 ctx->base.callback_data);
1803 ctx->header_length = 0;
1809 static int handle_ir_packet_per_buffer(struct context *context,
1810 struct descriptor *d,
1811 struct descriptor *last)
1813 struct iso_context *ctx =
1814 container_of(context, struct iso_context, context);
1815 struct descriptor *pd;
1820 for (pd = d; pd <= last; pd++) {
1821 if (pd->transfer_status)
1825 /* Descriptor(s) not done yet, stop iteration */
1828 i = ctx->header_length;
1831 if (ctx->base.header_size > 0 &&
1832 i + ctx->base.header_size <= PAGE_SIZE) {
1834 * The iso header is byteswapped to little endian by
1835 * the controller, but the remaining header quadlets
1836 * are big endian. We want to present all the headers
1837 * as big endian, so we have to swap the first quadlet.
1839 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1840 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1841 ctx->header_length += ctx->base.header_size;
1844 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1845 ir_header = (__le32 *) p;
1846 ctx->base.callback(&ctx->base,
1847 le32_to_cpu(ir_header[0]) & 0xffff,
1848 ctx->header_length, ctx->header,
1849 ctx->base.callback_data);
1850 ctx->header_length = 0;
1856 static int handle_it_packet(struct context *context,
1857 struct descriptor *d,
1858 struct descriptor *last)
1860 struct iso_context *ctx =
1861 container_of(context, struct iso_context, context);
1863 if (last->transfer_status == 0)
1864 /* This descriptor isn't done yet, stop iteration. */
1867 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
1868 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1869 0, NULL, ctx->base.callback_data);
1874 static struct fw_iso_context *
1875 ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size)
1877 struct fw_ohci *ohci = fw_ohci(card);
1878 struct iso_context *ctx, *list;
1879 descriptor_callback_t callback;
1881 unsigned long flags;
1882 int index, retval = -ENOMEM;
1884 if (type == FW_ISO_CONTEXT_TRANSMIT) {
1885 mask = &ohci->it_context_mask;
1886 list = ohci->it_context_list;
1887 callback = handle_it_packet;
1889 mask = &ohci->ir_context_mask;
1890 list = ohci->ir_context_list;
1891 if (ohci->version >= OHCI_VERSION_1_1)
1892 callback = handle_ir_dualbuffer_packet;
1894 callback = handle_ir_packet_per_buffer;
1897 spin_lock_irqsave(&ohci->lock, flags);
1898 index = ffs(*mask) - 1;
1900 *mask &= ~(1 << index);
1901 spin_unlock_irqrestore(&ohci->lock, flags);
1904 return ERR_PTR(-EBUSY);
1906 if (type == FW_ISO_CONTEXT_TRANSMIT)
1907 regs = OHCI1394_IsoXmitContextBase(index);
1909 regs = OHCI1394_IsoRcvContextBase(index);
1912 memset(ctx, 0, sizeof(*ctx));
1913 ctx->header_length = 0;
1914 ctx->header = (void *) __get_free_page(GFP_KERNEL);
1915 if (ctx->header == NULL)
1918 retval = context_init(&ctx->context, ohci, regs, callback);
1920 goto out_with_header;
1925 free_page((unsigned long)ctx->header);
1927 spin_lock_irqsave(&ohci->lock, flags);
1928 *mask |= 1 << index;
1929 spin_unlock_irqrestore(&ohci->lock, flags);
1931 return ERR_PTR(retval);
1934 static int ohci_start_iso(struct fw_iso_context *base,
1935 s32 cycle, u32 sync, u32 tags)
1937 struct iso_context *ctx = container_of(base, struct iso_context, base);
1938 struct fw_ohci *ohci = ctx->context.ohci;
1942 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1943 index = ctx - ohci->it_context_list;
1946 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
1947 (cycle & 0x7fff) << 16;
1949 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1950 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1951 context_run(&ctx->context, match);
1953 index = ctx - ohci->ir_context_list;
1954 control = IR_CONTEXT_ISOCH_HEADER;
1955 if (ohci->version >= OHCI_VERSION_1_1)
1956 control |= IR_CONTEXT_DUAL_BUFFER_MODE;
1957 match = (tags << 28) | (sync << 8) | ctx->base.channel;
1959 match |= (cycle & 0x07fff) << 12;
1960 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
1963 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
1964 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
1965 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
1966 context_run(&ctx->context, control);
1972 static int ohci_stop_iso(struct fw_iso_context *base)
1974 struct fw_ohci *ohci = fw_ohci(base->card);
1975 struct iso_context *ctx = container_of(base, struct iso_context, base);
1978 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1979 index = ctx - ohci->it_context_list;
1980 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1982 index = ctx - ohci->ir_context_list;
1983 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1986 context_stop(&ctx->context);
1991 static void ohci_free_iso_context(struct fw_iso_context *base)
1993 struct fw_ohci *ohci = fw_ohci(base->card);
1994 struct iso_context *ctx = container_of(base, struct iso_context, base);
1995 unsigned long flags;
1998 ohci_stop_iso(base);
1999 context_release(&ctx->context);
2000 free_page((unsigned long)ctx->header);
2002 spin_lock_irqsave(&ohci->lock, flags);
2004 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2005 index = ctx - ohci->it_context_list;
2006 ohci->it_context_mask |= 1 << index;
2008 index = ctx - ohci->ir_context_list;
2009 ohci->ir_context_mask |= 1 << index;
2012 spin_unlock_irqrestore(&ohci->lock, flags);
2016 ohci_queue_iso_transmit(struct fw_iso_context *base,
2017 struct fw_iso_packet *packet,
2018 struct fw_iso_buffer *buffer,
2019 unsigned long payload)
2021 struct iso_context *ctx = container_of(base, struct iso_context, base);
2022 struct descriptor *d, *last, *pd;
2023 struct fw_iso_packet *p;
2025 dma_addr_t d_bus, page_bus;
2026 u32 z, header_z, payload_z, irq;
2027 u32 payload_index, payload_end_index, next_page_index;
2028 int page, end_page, i, length, offset;
2031 * FIXME: Cycle lost behavior should be configurable: lose
2032 * packet, retransmit or terminate..
2036 payload_index = payload;
2042 if (p->header_length > 0)
2045 /* Determine the first page the payload isn't contained in. */
2046 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2047 if (p->payload_length > 0)
2048 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2054 /* Get header size in number of descriptors. */
2055 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2057 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2062 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2063 d[0].req_count = cpu_to_le16(8);
2065 header = (__le32 *) &d[1];
2066 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2067 IT_HEADER_TAG(p->tag) |
2068 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2069 IT_HEADER_CHANNEL(ctx->base.channel) |
2070 IT_HEADER_SPEED(ctx->base.speed));
2072 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2073 p->payload_length));
2076 if (p->header_length > 0) {
2077 d[2].req_count = cpu_to_le16(p->header_length);
2078 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2079 memcpy(&d[z], p->header, p->header_length);
2082 pd = d + z - payload_z;
2083 payload_end_index = payload_index + p->payload_length;
2084 for (i = 0; i < payload_z; i++) {
2085 page = payload_index >> PAGE_SHIFT;
2086 offset = payload_index & ~PAGE_MASK;
2087 next_page_index = (page + 1) << PAGE_SHIFT;
2089 min(next_page_index, payload_end_index) - payload_index;
2090 pd[i].req_count = cpu_to_le16(length);
2092 page_bus = page_private(buffer->pages[page]);
2093 pd[i].data_address = cpu_to_le32(page_bus + offset);
2095 payload_index += length;
2099 irq = DESCRIPTOR_IRQ_ALWAYS;
2101 irq = DESCRIPTOR_NO_IRQ;
2103 last = z == 2 ? d : d + z - 1;
2104 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2106 DESCRIPTOR_BRANCH_ALWAYS |
2109 context_append(&ctx->context, d, z, header_z);
2115 ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
2116 struct fw_iso_packet *packet,
2117 struct fw_iso_buffer *buffer,
2118 unsigned long payload)
2120 struct iso_context *ctx = container_of(base, struct iso_context, base);
2121 struct db_descriptor *db = NULL;
2122 struct descriptor *d;
2123 struct fw_iso_packet *p;
2124 dma_addr_t d_bus, page_bus;
2125 u32 z, header_z, length, rest;
2126 int page, offset, packet_count, header_size;
2129 * FIXME: Cycle lost behavior should be configurable: lose
2130 * packet, retransmit or terminate..
2137 * The OHCI controller puts the status word in the header
2138 * buffer too, so we need 4 extra bytes per packet.
2140 packet_count = p->header_length / ctx->base.header_size;
2141 header_size = packet_count * (ctx->base.header_size + 4);
2143 /* Get header size in number of descriptors. */
2144 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2145 page = payload >> PAGE_SHIFT;
2146 offset = payload & ~PAGE_MASK;
2147 rest = p->payload_length;
2149 /* FIXME: make packet-per-buffer/dual-buffer a context option */
2151 d = context_get_descriptors(&ctx->context,
2152 z + header_z, &d_bus);
2156 db = (struct db_descriptor *) d;
2157 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
2158 DESCRIPTOR_BRANCH_ALWAYS);
2159 db->first_size = cpu_to_le16(ctx->base.header_size + 4);
2160 if (p->skip && rest == p->payload_length) {
2161 db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2162 db->first_req_count = db->first_size;
2164 db->first_req_count = cpu_to_le16(header_size);
2166 db->first_res_count = db->first_req_count;
2167 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
2169 if (p->skip && rest == p->payload_length)
2171 else if (offset + rest < PAGE_SIZE)
2174 length = PAGE_SIZE - offset;
2176 db->second_req_count = cpu_to_le16(length);
2177 db->second_res_count = db->second_req_count;
2178 page_bus = page_private(buffer->pages[page]);
2179 db->second_buffer = cpu_to_le32(page_bus + offset);
2181 if (p->interrupt && length == rest)
2182 db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2184 context_append(&ctx->context, d, z, header_z);
2185 offset = (offset + length) & ~PAGE_MASK;
2195 ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2196 struct fw_iso_packet *packet,
2197 struct fw_iso_buffer *buffer,
2198 unsigned long payload)
2200 struct iso_context *ctx = container_of(base, struct iso_context, base);
2201 struct descriptor *d = NULL, *pd = NULL;
2202 struct fw_iso_packet *p = packet;
2203 dma_addr_t d_bus, page_bus;
2204 u32 z, header_z, rest;
2206 int page, offset, packet_count, header_size, payload_per_buffer;
2209 * The OHCI controller puts the status word in the
2210 * buffer too, so we need 4 extra bytes per packet.
2212 packet_count = p->header_length / ctx->base.header_size;
2213 header_size = ctx->base.header_size + 4;
2215 /* Get header size in number of descriptors. */
2216 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2217 page = payload >> PAGE_SHIFT;
2218 offset = payload & ~PAGE_MASK;
2219 payload_per_buffer = p->payload_length / packet_count;
2221 for (i = 0; i < packet_count; i++) {
2222 /* d points to the header descriptor */
2223 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2224 d = context_get_descriptors(&ctx->context,
2225 z + header_z, &d_bus);
2229 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2230 DESCRIPTOR_INPUT_MORE);
2231 if (p->skip && i == 0)
2232 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2233 d->req_count = cpu_to_le16(header_size);
2234 d->res_count = d->req_count;
2235 d->transfer_status = 0;
2236 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2238 rest = payload_per_buffer;
2239 for (j = 1; j < z; j++) {
2241 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2242 DESCRIPTOR_INPUT_MORE);
2244 if (offset + rest < PAGE_SIZE)
2247 length = PAGE_SIZE - offset;
2248 pd->req_count = cpu_to_le16(length);
2249 pd->res_count = pd->req_count;
2250 pd->transfer_status = 0;
2252 page_bus = page_private(buffer->pages[page]);
2253 pd->data_address = cpu_to_le32(page_bus + offset);
2255 offset = (offset + length) & ~PAGE_MASK;
2260 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2261 DESCRIPTOR_INPUT_LAST |
2262 DESCRIPTOR_BRANCH_ALWAYS);
2263 if (p->interrupt && i == packet_count - 1)
2264 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2266 context_append(&ctx->context, d, z, header_z);
2273 ohci_queue_iso(struct fw_iso_context *base,
2274 struct fw_iso_packet *packet,
2275 struct fw_iso_buffer *buffer,
2276 unsigned long payload)
2278 struct iso_context *ctx = container_of(base, struct iso_context, base);
2279 unsigned long flags;
2282 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2283 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2284 retval = ohci_queue_iso_transmit(base, packet, buffer, payload);
2285 else if (ctx->context.ohci->version >= OHCI_VERSION_1_1)
2286 retval = ohci_queue_iso_receive_dualbuffer(base, packet,
2289 retval = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2292 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2297 static const struct fw_card_driver ohci_driver = {
2298 .name = ohci_driver_name,
2299 .enable = ohci_enable,
2300 .update_phy_reg = ohci_update_phy_reg,
2301 .set_config_rom = ohci_set_config_rom,
2302 .send_request = ohci_send_request,
2303 .send_response = ohci_send_response,
2304 .cancel_packet = ohci_cancel_packet,
2305 .enable_phys_dma = ohci_enable_phys_dma,
2306 .get_bus_time = ohci_get_bus_time,
2308 .allocate_iso_context = ohci_allocate_iso_context,
2309 .free_iso_context = ohci_free_iso_context,
2310 .queue_iso = ohci_queue_iso,
2311 .start_iso = ohci_start_iso,
2312 .stop_iso = ohci_stop_iso,
2315 #ifdef CONFIG_PPC_PMAC
2316 static void ohci_pmac_on(struct pci_dev *dev)
2318 if (machine_is(powermac)) {
2319 struct device_node *ofn = pci_device_to_OF_node(dev);
2322 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2323 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2328 static void ohci_pmac_off(struct pci_dev *dev)
2330 if (machine_is(powermac)) {
2331 struct device_node *ofn = pci_device_to_OF_node(dev);
2334 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2335 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2340 #define ohci_pmac_on(dev)
2341 #define ohci_pmac_off(dev)
2342 #endif /* CONFIG_PPC_PMAC */
2344 static int __devinit
2345 pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
2347 struct fw_ohci *ohci;
2348 u32 bus_options, max_receive, link_speed;
2353 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2355 fw_error("Could not malloc fw_ohci data.\n");
2359 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2363 err = pci_enable_device(dev);
2365 fw_error("Failed to enable OHCI hardware.\n");
2369 pci_set_master(dev);
2370 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2371 pci_set_drvdata(dev, ohci);
2373 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2374 ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE &&
2375 dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW;
2377 ohci->bus_reset_packet_quirk = dev->vendor == PCI_VENDOR_ID_TI;
2379 spin_lock_init(&ohci->lock);
2381 tasklet_init(&ohci->bus_reset_tasklet,
2382 bus_reset_tasklet, (unsigned long)ohci);
2384 err = pci_request_region(dev, 0, ohci_driver_name);
2386 fw_error("MMIO resource unavailable\n");
2390 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2391 if (ohci->registers == NULL) {
2392 fw_error("Failed to remap registers\n");
2397 ar_context_init(&ohci->ar_request_ctx, ohci,
2398 OHCI1394_AsReqRcvContextControlSet);
2400 ar_context_init(&ohci->ar_response_ctx, ohci,
2401 OHCI1394_AsRspRcvContextControlSet);
2403 context_init(&ohci->at_request_ctx, ohci,
2404 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2406 context_init(&ohci->at_response_ctx, ohci,
2407 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2409 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2410 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2411 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2412 size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
2413 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2415 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2416 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2417 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2418 size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
2419 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2421 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2422 fw_error("Out of memory for it/ir contexts.\n");
2424 goto fail_registers;
2427 /* self-id dma buffer allocation */
2428 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2432 if (ohci->self_id_cpu == NULL) {
2433 fw_error("Out of memory for self ID buffer.\n");
2435 goto fail_registers;
2438 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2439 max_receive = (bus_options >> 12) & 0xf;
2440 link_speed = bus_options & 0x7;
2441 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2442 reg_read(ohci, OHCI1394_GUIDLo);
2444 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2448 ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2449 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2450 dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff);
2454 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2455 ohci->self_id_cpu, ohci->self_id_bus);
2457 kfree(ohci->it_context_list);
2458 kfree(ohci->ir_context_list);
2459 pci_iounmap(dev, ohci->registers);
2461 pci_release_region(dev, 0);
2463 pci_disable_device(dev);
2471 static void pci_remove(struct pci_dev *dev)
2473 struct fw_ohci *ohci;
2475 ohci = pci_get_drvdata(dev);
2476 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2478 fw_core_remove_card(&ohci->card);
2481 * FIXME: Fail all pending packets here, now that the upper
2482 * layers can't queue any more.
2485 software_reset(ohci);
2486 free_irq(dev->irq, ohci);
2487 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2488 ohci->self_id_cpu, ohci->self_id_bus);
2489 kfree(ohci->it_context_list);
2490 kfree(ohci->ir_context_list);
2491 pci_iounmap(dev, ohci->registers);
2492 pci_release_region(dev, 0);
2493 pci_disable_device(dev);
2497 fw_notify("Removed fw-ohci device.\n");
2501 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2503 struct fw_ohci *ohci = pci_get_drvdata(dev);
2506 software_reset(ohci);
2507 free_irq(dev->irq, ohci);
2508 err = pci_save_state(dev);
2510 fw_error("pci_save_state failed\n");
2513 err = pci_set_power_state(dev, pci_choose_state(dev, state));
2515 fw_error("pci_set_power_state failed with %d\n", err);
2521 static int pci_resume(struct pci_dev *dev)
2523 struct fw_ohci *ohci = pci_get_drvdata(dev);
2527 pci_set_power_state(dev, PCI_D0);
2528 pci_restore_state(dev);
2529 err = pci_enable_device(dev);
2531 fw_error("pci_enable_device failed\n");
2535 return ohci_enable(&ohci->card, NULL, 0);
2539 static struct pci_device_id pci_table[] = {
2540 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2544 MODULE_DEVICE_TABLE(pci, pci_table);
2546 static struct pci_driver fw_ohci_pci_driver = {
2547 .name = ohci_driver_name,
2548 .id_table = pci_table,
2550 .remove = pci_remove,
2552 .resume = pci_resume,
2553 .suspend = pci_suspend,
2557 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2558 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2559 MODULE_LICENSE("GPL");
2561 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2562 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2563 MODULE_ALIAS("ohci1394");
2566 static int __init fw_ohci_init(void)
2568 return pci_register_driver(&fw_ohci_pci_driver);
2571 static void __exit fw_ohci_cleanup(void)
2573 pci_unregister_driver(&fw_ohci_pci_driver);
2576 module_init(fw_ohci_init);
2577 module_exit(fw_ohci_cleanup);