2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/gfp.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/pci.h>
32 #include <linux/spinlock.h>
35 #include <asm/system.h>
37 #ifdef CONFIG_PPC_PMAC
38 #include <asm/pmac_feature.h>
42 #include "fw-transaction.h"
44 #define DESCRIPTOR_OUTPUT_MORE 0
45 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
46 #define DESCRIPTOR_INPUT_MORE (2 << 12)
47 #define DESCRIPTOR_INPUT_LAST (3 << 12)
48 #define DESCRIPTOR_STATUS (1 << 11)
49 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
50 #define DESCRIPTOR_PING (1 << 7)
51 #define DESCRIPTOR_YY (1 << 6)
52 #define DESCRIPTOR_NO_IRQ (0 << 4)
53 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
54 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
55 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
56 #define DESCRIPTOR_WAIT (3 << 0)
62 __le32 branch_address;
64 __le16 transfer_status;
65 } __attribute__((aligned(16)));
67 struct db_descriptor {
70 __le16 second_req_count;
71 __le16 first_req_count;
72 __le32 branch_address;
73 __le16 second_res_count;
74 __le16 first_res_count;
79 } __attribute__((aligned(16)));
81 #define CONTROL_SET(regs) (regs)
82 #define CONTROL_CLEAR(regs) ((regs) + 4)
83 #define COMMAND_PTR(regs) ((regs) + 12)
84 #define CONTEXT_MATCH(regs) ((regs) + 16)
87 struct descriptor descriptor;
88 struct ar_buffer *next;
94 struct ar_buffer *current_buffer;
95 struct ar_buffer *last_buffer;
98 struct tasklet_struct tasklet;
103 typedef int (*descriptor_callback_t)(struct context *ctx,
104 struct descriptor *d,
105 struct descriptor *last);
108 * A buffer that contains a block of DMA-able coherent memory used for
109 * storing a portion of a DMA descriptor program.
111 struct descriptor_buffer {
112 struct list_head list;
113 dma_addr_t buffer_bus;
116 struct descriptor buffer[0];
120 struct fw_ohci *ohci;
122 int total_allocation;
125 * List of page-sized buffers for storing DMA descriptors.
126 * Head of list contains buffers in use and tail of list contains
129 struct list_head buffer_list;
132 * Pointer to a buffer inside buffer_list that contains the tail
133 * end of the current DMA program.
135 struct descriptor_buffer *buffer_tail;
138 * The descriptor containing the branch address of the first
139 * descriptor that has not yet been filled by the device.
141 struct descriptor *last;
144 * The last descriptor in the DMA program. It contains the branch
145 * address that must be updated upon appending a new descriptor.
147 struct descriptor *prev;
149 descriptor_callback_t callback;
151 struct tasklet_struct tasklet;
154 #define IT_HEADER_SY(v) ((v) << 0)
155 #define IT_HEADER_TCODE(v) ((v) << 4)
156 #define IT_HEADER_CHANNEL(v) ((v) << 8)
157 #define IT_HEADER_TAG(v) ((v) << 14)
158 #define IT_HEADER_SPEED(v) ((v) << 16)
159 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
162 struct fw_iso_context base;
163 struct context context;
166 size_t header_length;
169 #define CONFIG_ROM_SIZE 1024
175 __iomem char *registers;
176 dma_addr_t self_id_bus;
178 struct tasklet_struct bus_reset_tasklet;
181 int request_generation;
186 * Spinlock for accessing fw_ohci data. Never call out of
187 * this driver with this lock held.
190 u32 self_id_buffer[512];
192 /* Config rom buffers */
194 dma_addr_t config_rom_bus;
195 __be32 *next_config_rom;
196 dma_addr_t next_config_rom_bus;
199 struct ar_context ar_request_ctx;
200 struct ar_context ar_response_ctx;
201 struct context at_request_ctx;
202 struct context at_response_ctx;
205 struct iso_context *it_context_list;
207 struct iso_context *ir_context_list;
210 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
212 return container_of(card, struct fw_ohci, card);
215 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
216 #define IR_CONTEXT_BUFFER_FILL 0x80000000
217 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
218 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
219 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
220 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
222 #define CONTEXT_RUN 0x8000
223 #define CONTEXT_WAKE 0x1000
224 #define CONTEXT_DEAD 0x0800
225 #define CONTEXT_ACTIVE 0x0400
227 #define OHCI1394_MAX_AT_REQ_RETRIES 0x2
228 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
229 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
231 #define FW_OHCI_MAJOR 240
232 #define OHCI1394_REGISTER_SIZE 0x800
233 #define OHCI_LOOP_COUNT 500
234 #define OHCI1394_PCI_HCI_Control 0x40
235 #define SELF_ID_BUF_SIZE 0x800
236 #define OHCI_TCODE_PHY_PACKET 0x0e
237 #define OHCI_VERSION_1_1 0x010010
239 static char ohci_driver_name[] = KBUILD_MODNAME;
241 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
243 #define OHCI_PARAM_DEBUG_IRQS 1
244 #define OHCI_PARAM_DEBUG_SELFIDS 2
245 #define OHCI_PARAM_DEBUG_AT_AR 4
247 static int param_debug;
248 module_param_named(debug, param_debug, int, 0644);
249 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
250 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
251 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
252 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
253 ", or a combination, or all = -1)");
255 static void log_irqs(u32 evt)
257 if (likely(!(param_debug & OHCI_PARAM_DEBUG_IRQS)))
260 printk(KERN_DEBUG KBUILD_MODNAME ": IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s\n",
262 evt & OHCI1394_selfIDComplete ? " selfID" : "",
263 evt & OHCI1394_RQPkt ? " AR_req" : "",
264 evt & OHCI1394_RSPkt ? " AR_resp" : "",
265 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
266 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
267 evt & OHCI1394_isochRx ? " IR" : "",
268 evt & OHCI1394_isochTx ? " IT" : "",
269 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
270 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
271 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
272 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
273 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
274 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
275 OHCI1394_respTxComplete | OHCI1394_isochRx |
276 OHCI1394_isochTx | OHCI1394_postedWriteErr |
277 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
278 OHCI1394_regAccessFail)
282 static const char *speed[] = {
283 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
285 static const char *power[] = {
286 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
287 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
289 static const char port[] = { '.', '-', 'p', 'c', };
291 static char _p(u32 *s, int shift)
293 return port[*s >> shift & 3];
296 static void log_selfids(int generation, int self_id_count, u32 *s)
298 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
301 printk(KERN_DEBUG KBUILD_MODNAME ": %d selfIDs, generation %d\n",
302 self_id_count, generation);
304 for (; self_id_count--; ++s)
305 if ((*s & 1 << 23) == 0)
306 printk(KERN_DEBUG "selfID 0: %08x, phy %d [%c%c%c] "
307 "%s gc=%d %s %s%s%s\n",
308 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
309 speed[*s >> 14 & 3], *s >> 16 & 63,
310 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
311 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
313 printk(KERN_DEBUG "selfID n: %08x, phy %d "
314 "[%c%c%c%c%c%c%c%c]\n",
316 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
317 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
320 static const char *evts[] = {
321 [0x00] = "evt_no_status", [0x01] = "-reserved-",
322 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
323 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
324 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
325 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
326 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
327 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
328 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
329 [0x10] = "-reserved-", [0x11] = "ack_complete",
330 [0x12] = "ack_pending ", [0x13] = "-reserved-",
331 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
332 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
333 [0x18] = "-reserved-", [0x19] = "-reserved-",
334 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
335 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
336 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
337 [0x20] = "pending/cancelled",
339 static const char *tcodes[] = {
340 [0x0] = "QW req", [0x1] = "BW req",
341 [0x2] = "W resp", [0x3] = "-reserved-",
342 [0x4] = "QR req", [0x5] = "BR req",
343 [0x6] = "QR resp", [0x7] = "BR resp",
344 [0x8] = "cycle start", [0x9] = "Lk req",
345 [0xa] = "async stream packet", [0xb] = "Lk resp",
346 [0xc] = "-reserved-", [0xd] = "-reserved-",
347 [0xe] = "link internal", [0xf] = "-reserved-",
349 static const char *phys[] = {
350 [0x0] = "phy config packet", [0x1] = "link-on packet",
351 [0x2] = "self-id packet", [0x3] = "-reserved-",
354 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
356 int tcode = header[0] >> 4 & 0xf;
359 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
362 if (unlikely(evt >= ARRAY_SIZE(evts)))
365 if (header[0] == ~header[1]) {
366 printk(KERN_DEBUG "A%c %s, %s, %08x\n",
367 dir, evts[evt], phys[header[0] >> 30 & 0x3],
373 case 0x0: case 0x6: case 0x8:
374 snprintf(specific, sizeof(specific), " = %08x",
375 be32_to_cpu((__force __be32)header[3]));
377 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
378 snprintf(specific, sizeof(specific), " %x,%x",
379 header[3] >> 16, header[3] & 0xffff);
387 printk(KERN_DEBUG "A%c %s, %s\n",
388 dir, evts[evt], tcodes[tcode]);
390 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
391 printk(KERN_DEBUG "A%c spd %x tl %02x, "
394 dir, speed, header[0] >> 10 & 0x3f,
395 header[1] >> 16, header[0] >> 16, evts[evt],
396 tcodes[tcode], header[1] & 0xffff, header[2], specific);
399 printk(KERN_DEBUG "A%c spd %x tl %02x, "
402 dir, speed, header[0] >> 10 & 0x3f,
403 header[1] >> 16, header[0] >> 16, evts[evt],
404 tcodes[tcode], specific);
410 #define log_irqs(evt)
411 #define log_selfids(generation, self_id_count, sid)
412 #define log_ar_at_event(dir, speed, header, evt)
414 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
416 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
418 writel(data, ohci->registers + offset);
421 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
423 return readl(ohci->registers + offset);
426 static inline void flush_writes(const struct fw_ohci *ohci)
428 /* Do a dummy read to flush writes. */
429 reg_read(ohci, OHCI1394_Version);
433 ohci_update_phy_reg(struct fw_card *card, int addr,
434 int clear_bits, int set_bits)
436 struct fw_ohci *ohci = fw_ohci(card);
439 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
442 val = reg_read(ohci, OHCI1394_PhyControl);
443 if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
444 fw_error("failed to set phy reg bits.\n");
448 old = OHCI1394_PhyControl_ReadData(val);
449 old = (old & ~clear_bits) | set_bits;
450 reg_write(ohci, OHCI1394_PhyControl,
451 OHCI1394_PhyControl_Write(addr, old));
456 static int ar_context_add_page(struct ar_context *ctx)
458 struct device *dev = ctx->ohci->card.device;
459 struct ar_buffer *ab;
460 dma_addr_t uninitialized_var(ab_bus);
463 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
467 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
468 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
470 DESCRIPTOR_BRANCH_ALWAYS);
471 offset = offsetof(struct ar_buffer, data);
472 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
473 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
474 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
475 ab->descriptor.branch_address = 0;
477 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
478 ctx->last_buffer->next = ab;
479 ctx->last_buffer = ab;
481 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
482 flush_writes(ctx->ohci);
487 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
488 #define cond_le32_to_cpu(v) \
489 (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
491 #define cond_le32_to_cpu(v) le32_to_cpu(v)
494 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
496 struct fw_ohci *ohci = ctx->ohci;
498 u32 status, length, tcode;
501 p.header[0] = cond_le32_to_cpu(buffer[0]);
502 p.header[1] = cond_le32_to_cpu(buffer[1]);
503 p.header[2] = cond_le32_to_cpu(buffer[2]);
505 tcode = (p.header[0] >> 4) & 0x0f;
507 case TCODE_WRITE_QUADLET_REQUEST:
508 case TCODE_READ_QUADLET_RESPONSE:
509 p.header[3] = (__force __u32) buffer[3];
510 p.header_length = 16;
511 p.payload_length = 0;
514 case TCODE_READ_BLOCK_REQUEST :
515 p.header[3] = cond_le32_to_cpu(buffer[3]);
516 p.header_length = 16;
517 p.payload_length = 0;
520 case TCODE_WRITE_BLOCK_REQUEST:
521 case TCODE_READ_BLOCK_RESPONSE:
522 case TCODE_LOCK_REQUEST:
523 case TCODE_LOCK_RESPONSE:
524 p.header[3] = cond_le32_to_cpu(buffer[3]);
525 p.header_length = 16;
526 p.payload_length = p.header[3] >> 16;
529 case TCODE_WRITE_RESPONSE:
530 case TCODE_READ_QUADLET_REQUEST:
531 case OHCI_TCODE_PHY_PACKET:
532 p.header_length = 12;
533 p.payload_length = 0;
537 p.payload = (void *) buffer + p.header_length;
539 /* FIXME: What to do about evt_* errors? */
540 length = (p.header_length + p.payload_length + 3) / 4;
541 status = cond_le32_to_cpu(buffer[length]);
542 evt = (status >> 16) & 0x1f;
545 p.speed = (status >> 21) & 0x7;
546 p.timestamp = status & 0xffff;
547 p.generation = ohci->request_generation;
549 log_ar_at_event('R', p.speed, p.header, evt);
552 * The OHCI bus reset handler synthesizes a phy packet with
553 * the new generation number when a bus reset happens (see
554 * section 8.4.2.3). This helps us determine when a request
555 * was received and make sure we send the response in the same
556 * generation. We only need this for requests; for responses
557 * we use the unique tlabel for finding the matching
561 if (evt == OHCI1394_evt_bus_reset)
562 ohci->request_generation = (p.header[2] >> 16) & 0xff;
563 else if (ctx == &ohci->ar_request_ctx)
564 fw_core_handle_request(&ohci->card, &p);
566 fw_core_handle_response(&ohci->card, &p);
568 return buffer + length + 1;
571 static void ar_context_tasklet(unsigned long data)
573 struct ar_context *ctx = (struct ar_context *)data;
574 struct fw_ohci *ohci = ctx->ohci;
575 struct ar_buffer *ab;
576 struct descriptor *d;
579 ab = ctx->current_buffer;
582 if (d->res_count == 0) {
583 size_t size, rest, offset;
584 dma_addr_t start_bus;
588 * This descriptor is finished and we may have a
589 * packet split across this and the next buffer. We
590 * reuse the page for reassembling the split packet.
593 offset = offsetof(struct ar_buffer, data);
595 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
599 size = buffer + PAGE_SIZE - ctx->pointer;
600 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
601 memmove(buffer, ctx->pointer, size);
602 memcpy(buffer + size, ab->data, rest);
603 ctx->current_buffer = ab;
604 ctx->pointer = (void *) ab->data + rest;
605 end = buffer + size + rest;
608 buffer = handle_ar_packet(ctx, buffer);
610 dma_free_coherent(ohci->card.device, PAGE_SIZE,
612 ar_context_add_page(ctx);
614 buffer = ctx->pointer;
616 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
619 buffer = handle_ar_packet(ctx, buffer);
624 ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs)
630 ctx->last_buffer = &ab;
631 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
633 ar_context_add_page(ctx);
634 ar_context_add_page(ctx);
635 ctx->current_buffer = ab.next;
636 ctx->pointer = ctx->current_buffer->data;
641 static void ar_context_run(struct ar_context *ctx)
643 struct ar_buffer *ab = ctx->current_buffer;
647 offset = offsetof(struct ar_buffer, data);
648 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
650 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
651 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
652 flush_writes(ctx->ohci);
655 static struct descriptor *
656 find_branch_descriptor(struct descriptor *d, int z)
660 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
661 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
663 /* figure out which descriptor the branch address goes in */
664 if (z == 2 && (b == 3 || key == 2))
670 static void context_tasklet(unsigned long data)
672 struct context *ctx = (struct context *) data;
673 struct descriptor *d, *last;
676 struct descriptor_buffer *desc;
678 desc = list_entry(ctx->buffer_list.next,
679 struct descriptor_buffer, list);
681 while (last->branch_address != 0) {
682 struct descriptor_buffer *old_desc = desc;
683 address = le32_to_cpu(last->branch_address);
687 /* If the branch address points to a buffer outside of the
688 * current buffer, advance to the next buffer. */
689 if (address < desc->buffer_bus ||
690 address >= desc->buffer_bus + desc->used)
691 desc = list_entry(desc->list.next,
692 struct descriptor_buffer, list);
693 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
694 last = find_branch_descriptor(d, z);
696 if (!ctx->callback(ctx, d, last))
699 if (old_desc != desc) {
700 /* If we've advanced to the next buffer, move the
701 * previous buffer to the free list. */
704 spin_lock_irqsave(&ctx->ohci->lock, flags);
705 list_move_tail(&old_desc->list, &ctx->buffer_list);
706 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
713 * Allocate a new buffer and add it to the list of free buffers for this
714 * context. Must be called with ohci->lock held.
717 context_add_buffer(struct context *ctx)
719 struct descriptor_buffer *desc;
720 dma_addr_t uninitialized_var(bus_addr);
724 * 16MB of descriptors should be far more than enough for any DMA
725 * program. This will catch run-away userspace or DoS attacks.
727 if (ctx->total_allocation >= 16*1024*1024)
730 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
731 &bus_addr, GFP_ATOMIC);
735 offset = (void *)&desc->buffer - (void *)desc;
736 desc->buffer_size = PAGE_SIZE - offset;
737 desc->buffer_bus = bus_addr + offset;
740 list_add_tail(&desc->list, &ctx->buffer_list);
741 ctx->total_allocation += PAGE_SIZE;
747 context_init(struct context *ctx, struct fw_ohci *ohci,
748 u32 regs, descriptor_callback_t callback)
752 ctx->total_allocation = 0;
754 INIT_LIST_HEAD(&ctx->buffer_list);
755 if (context_add_buffer(ctx) < 0)
758 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
759 struct descriptor_buffer, list);
761 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
762 ctx->callback = callback;
765 * We put a dummy descriptor in the buffer that has a NULL
766 * branch address and looks like it's been sent. That way we
767 * have a descriptor to append DMA programs to.
769 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
770 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
771 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
772 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
773 ctx->last = ctx->buffer_tail->buffer;
774 ctx->prev = ctx->buffer_tail->buffer;
780 context_release(struct context *ctx)
782 struct fw_card *card = &ctx->ohci->card;
783 struct descriptor_buffer *desc, *tmp;
785 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
786 dma_free_coherent(card->device, PAGE_SIZE, desc,
788 ((void *)&desc->buffer - (void *)desc));
791 /* Must be called with ohci->lock held */
792 static struct descriptor *
793 context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus)
795 struct descriptor *d = NULL;
796 struct descriptor_buffer *desc = ctx->buffer_tail;
798 if (z * sizeof(*d) > desc->buffer_size)
801 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
802 /* No room for the descriptor in this buffer, so advance to the
805 if (desc->list.next == &ctx->buffer_list) {
806 /* If there is no free buffer next in the list,
808 if (context_add_buffer(ctx) < 0)
811 desc = list_entry(desc->list.next,
812 struct descriptor_buffer, list);
813 ctx->buffer_tail = desc;
816 d = desc->buffer + desc->used / sizeof(*d);
817 memset(d, 0, z * sizeof(*d));
818 *d_bus = desc->buffer_bus + desc->used;
823 static void context_run(struct context *ctx, u32 extra)
825 struct fw_ohci *ohci = ctx->ohci;
827 reg_write(ohci, COMMAND_PTR(ctx->regs),
828 le32_to_cpu(ctx->last->branch_address));
829 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
830 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
834 static void context_append(struct context *ctx,
835 struct descriptor *d, int z, int extra)
838 struct descriptor_buffer *desc = ctx->buffer_tail;
840 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
842 desc->used += (z + extra) * sizeof(*d);
843 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
844 ctx->prev = find_branch_descriptor(d, z);
846 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
847 flush_writes(ctx->ohci);
850 static void context_stop(struct context *ctx)
855 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
856 flush_writes(ctx->ohci);
858 for (i = 0; i < 10; i++) {
859 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
860 if ((reg & CONTEXT_ACTIVE) == 0)
863 fw_notify("context_stop: still active (0x%08x)\n", reg);
869 struct fw_packet *packet;
873 * This function apppends a packet to the DMA queue for transmission.
874 * Must always be called with the ochi->lock held to ensure proper
875 * generation handling and locking around packet queue manipulation.
878 at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
880 struct fw_ohci *ohci = ctx->ohci;
881 dma_addr_t d_bus, uninitialized_var(payload_bus);
882 struct driver_data *driver_data;
883 struct descriptor *d, *last;
888 d = context_get_descriptors(ctx, 4, &d_bus);
890 packet->ack = RCODE_SEND_ERROR;
894 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
895 d[0].res_count = cpu_to_le16(packet->timestamp);
898 * The DMA format for asyncronous link packets is different
899 * from the IEEE1394 layout, so shift the fields around
900 * accordingly. If header_length is 8, it's a PHY packet, to
901 * which we need to prepend an extra quadlet.
904 header = (__le32 *) &d[1];
905 if (packet->header_length > 8) {
906 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
907 (packet->speed << 16));
908 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
909 (packet->header[0] & 0xffff0000));
910 header[2] = cpu_to_le32(packet->header[2]);
912 tcode = (packet->header[0] >> 4) & 0x0f;
913 if (TCODE_IS_BLOCK_PACKET(tcode))
914 header[3] = cpu_to_le32(packet->header[3]);
916 header[3] = (__force __le32) packet->header[3];
918 d[0].req_count = cpu_to_le16(packet->header_length);
920 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
921 (packet->speed << 16));
922 header[1] = cpu_to_le32(packet->header[0]);
923 header[2] = cpu_to_le32(packet->header[1]);
924 d[0].req_count = cpu_to_le16(12);
927 driver_data = (struct driver_data *) &d[3];
928 driver_data->packet = packet;
929 packet->driver_data = driver_data;
931 if (packet->payload_length > 0) {
933 dma_map_single(ohci->card.device, packet->payload,
934 packet->payload_length, DMA_TO_DEVICE);
935 if (dma_mapping_error(payload_bus)) {
936 packet->ack = RCODE_SEND_ERROR;
940 d[2].req_count = cpu_to_le16(packet->payload_length);
941 d[2].data_address = cpu_to_le32(payload_bus);
949 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
950 DESCRIPTOR_IRQ_ALWAYS |
951 DESCRIPTOR_BRANCH_ALWAYS);
954 * If the controller and packet generations don't match, we need to
955 * bail out and try again. If IntEvent.busReset is set, the AT context
956 * is halted, so appending to the context and trying to run it is
957 * futile. Most controllers do the right thing and just flush the AT
958 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
959 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
960 * up stalling out. So we just bail out in software and try again
961 * later, and everyone is happy.
962 * FIXME: Document how the locking works.
964 if (ohci->generation != packet->generation ||
965 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
966 if (packet->payload_length > 0)
967 dma_unmap_single(ohci->card.device, payload_bus,
968 packet->payload_length, DMA_TO_DEVICE);
969 packet->ack = RCODE_GENERATION;
973 context_append(ctx, d, z, 4 - z);
975 /* If the context isn't already running, start it up. */
976 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
977 if ((reg & CONTEXT_RUN) == 0)
983 static int handle_at_packet(struct context *context,
984 struct descriptor *d,
985 struct descriptor *last)
987 struct driver_data *driver_data;
988 struct fw_packet *packet;
989 struct fw_ohci *ohci = context->ohci;
990 dma_addr_t payload_bus;
993 if (last->transfer_status == 0)
994 /* This descriptor isn't done yet, stop iteration. */
997 driver_data = (struct driver_data *) &d[3];
998 packet = driver_data->packet;
1000 /* This packet was cancelled, just continue. */
1003 payload_bus = le32_to_cpu(last->data_address);
1004 if (payload_bus != 0)
1005 dma_unmap_single(ohci->card.device, payload_bus,
1006 packet->payload_length, DMA_TO_DEVICE);
1008 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1009 packet->timestamp = le16_to_cpu(last->res_count);
1011 log_ar_at_event('T', packet->speed, packet->header, evt);
1014 case OHCI1394_evt_timeout:
1015 /* Async response transmit timed out. */
1016 packet->ack = RCODE_CANCELLED;
1019 case OHCI1394_evt_flushed:
1021 * The packet was flushed should give same error as
1022 * when we try to use a stale generation count.
1024 packet->ack = RCODE_GENERATION;
1027 case OHCI1394_evt_missing_ack:
1029 * Using a valid (current) generation count, but the
1030 * node is not on the bus or not sending acks.
1032 packet->ack = RCODE_NO_ACK;
1035 case ACK_COMPLETE + 0x10:
1036 case ACK_PENDING + 0x10:
1037 case ACK_BUSY_X + 0x10:
1038 case ACK_BUSY_A + 0x10:
1039 case ACK_BUSY_B + 0x10:
1040 case ACK_DATA_ERROR + 0x10:
1041 case ACK_TYPE_ERROR + 0x10:
1042 packet->ack = evt - 0x10;
1046 packet->ack = RCODE_SEND_ERROR;
1050 packet->callback(packet, &ohci->card, packet->ack);
1055 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1056 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1057 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1058 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1059 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1062 handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
1064 struct fw_packet response;
1065 int tcode, length, i;
1067 tcode = HEADER_GET_TCODE(packet->header[0]);
1068 if (TCODE_IS_BLOCK_PACKET(tcode))
1069 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1073 i = csr - CSR_CONFIG_ROM;
1074 if (i + length > CONFIG_ROM_SIZE) {
1075 fw_fill_response(&response, packet->header,
1076 RCODE_ADDRESS_ERROR, NULL, 0);
1077 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1078 fw_fill_response(&response, packet->header,
1079 RCODE_TYPE_ERROR, NULL, 0);
1081 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1082 (void *) ohci->config_rom + i, length);
1085 fw_core_handle_response(&ohci->card, &response);
1089 handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
1091 struct fw_packet response;
1092 int tcode, length, ext_tcode, sel;
1093 __be32 *payload, lock_old;
1094 u32 lock_arg, lock_data;
1096 tcode = HEADER_GET_TCODE(packet->header[0]);
1097 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1098 payload = packet->payload;
1099 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1101 if (tcode == TCODE_LOCK_REQUEST &&
1102 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1103 lock_arg = be32_to_cpu(payload[0]);
1104 lock_data = be32_to_cpu(payload[1]);
1105 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1109 fw_fill_response(&response, packet->header,
1110 RCODE_TYPE_ERROR, NULL, 0);
1114 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1115 reg_write(ohci, OHCI1394_CSRData, lock_data);
1116 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1117 reg_write(ohci, OHCI1394_CSRControl, sel);
1119 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1120 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1122 fw_notify("swap not done yet\n");
1124 fw_fill_response(&response, packet->header,
1125 RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1127 fw_core_handle_response(&ohci->card, &response);
1131 handle_local_request(struct context *ctx, struct fw_packet *packet)
1136 if (ctx == &ctx->ohci->at_request_ctx) {
1137 packet->ack = ACK_PENDING;
1138 packet->callback(packet, &ctx->ohci->card, packet->ack);
1142 ((unsigned long long)
1143 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1145 csr = offset - CSR_REGISTER_BASE;
1147 /* Handle config rom reads. */
1148 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1149 handle_local_rom(ctx->ohci, packet, csr);
1151 case CSR_BUS_MANAGER_ID:
1152 case CSR_BANDWIDTH_AVAILABLE:
1153 case CSR_CHANNELS_AVAILABLE_HI:
1154 case CSR_CHANNELS_AVAILABLE_LO:
1155 handle_local_lock(ctx->ohci, packet, csr);
1158 if (ctx == &ctx->ohci->at_request_ctx)
1159 fw_core_handle_request(&ctx->ohci->card, packet);
1161 fw_core_handle_response(&ctx->ohci->card, packet);
1165 if (ctx == &ctx->ohci->at_response_ctx) {
1166 packet->ack = ACK_COMPLETE;
1167 packet->callback(packet, &ctx->ohci->card, packet->ack);
1172 at_context_transmit(struct context *ctx, struct fw_packet *packet)
1174 unsigned long flags;
1177 spin_lock_irqsave(&ctx->ohci->lock, flags);
1179 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1180 ctx->ohci->generation == packet->generation) {
1181 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1182 handle_local_request(ctx, packet);
1186 retval = at_context_queue_packet(ctx, packet);
1187 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1190 packet->callback(packet, &ctx->ohci->card, packet->ack);
1194 static void bus_reset_tasklet(unsigned long data)
1196 struct fw_ohci *ohci = (struct fw_ohci *)data;
1197 int self_id_count, i, j, reg;
1198 int generation, new_generation;
1199 unsigned long flags;
1200 void *free_rom = NULL;
1201 dma_addr_t free_rom_bus = 0;
1203 reg = reg_read(ohci, OHCI1394_NodeID);
1204 if (!(reg & OHCI1394_NodeID_idValid)) {
1205 fw_notify("node ID not valid, new bus reset in progress\n");
1208 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1209 fw_notify("malconfigured bus\n");
1212 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1213 OHCI1394_NodeID_nodeNumber);
1215 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1216 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1217 fw_notify("inconsistent self IDs\n");
1221 * The count in the SelfIDCount register is the number of
1222 * bytes in the self ID receive buffer. Since we also receive
1223 * the inverted quadlets and a header quadlet, we shift one
1224 * bit extra to get the actual number of self IDs.
1226 self_id_count = (reg >> 3) & 0x3ff;
1227 if (self_id_count == 0) {
1228 fw_notify("inconsistent self IDs\n");
1231 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1234 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1235 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1236 fw_notify("inconsistent self IDs\n");
1239 ohci->self_id_buffer[j] =
1240 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1245 * Check the consistency of the self IDs we just read. The
1246 * problem we face is that a new bus reset can start while we
1247 * read out the self IDs from the DMA buffer. If this happens,
1248 * the DMA buffer will be overwritten with new self IDs and we
1249 * will read out inconsistent data. The OHCI specification
1250 * (section 11.2) recommends a technique similar to
1251 * linux/seqlock.h, where we remember the generation of the
1252 * self IDs in the buffer before reading them out and compare
1253 * it to the current generation after reading them out. If
1254 * the two generations match we know we have a consistent set
1258 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1259 if (new_generation != generation) {
1260 fw_notify("recursive bus reset detected, "
1261 "discarding self ids\n");
1265 /* FIXME: Document how the locking works. */
1266 spin_lock_irqsave(&ohci->lock, flags);
1268 ohci->generation = generation;
1269 context_stop(&ohci->at_request_ctx);
1270 context_stop(&ohci->at_response_ctx);
1271 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1274 * This next bit is unrelated to the AT context stuff but we
1275 * have to do it under the spinlock also. If a new config rom
1276 * was set up before this reset, the old one is now no longer
1277 * in use and we can free it. Update the config rom pointers
1278 * to point to the current config rom and clear the
1279 * next_config_rom pointer so a new udpate can take place.
1282 if (ohci->next_config_rom != NULL) {
1283 if (ohci->next_config_rom != ohci->config_rom) {
1284 free_rom = ohci->config_rom;
1285 free_rom_bus = ohci->config_rom_bus;
1287 ohci->config_rom = ohci->next_config_rom;
1288 ohci->config_rom_bus = ohci->next_config_rom_bus;
1289 ohci->next_config_rom = NULL;
1292 * Restore config_rom image and manually update
1293 * config_rom registers. Writing the header quadlet
1294 * will indicate that the config rom is ready, so we
1297 reg_write(ohci, OHCI1394_BusOptions,
1298 be32_to_cpu(ohci->config_rom[2]));
1299 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
1300 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
1303 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1304 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1305 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1308 spin_unlock_irqrestore(&ohci->lock, flags);
1311 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1312 free_rom, free_rom_bus);
1314 log_selfids(generation, self_id_count, ohci->self_id_buffer);
1316 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1317 self_id_count, ohci->self_id_buffer);
1320 static irqreturn_t irq_handler(int irq, void *data)
1322 struct fw_ohci *ohci = data;
1323 u32 event, iso_event, cycle_time;
1326 event = reg_read(ohci, OHCI1394_IntEventClear);
1328 if (!event || !~event)
1331 reg_write(ohci, OHCI1394_IntEventClear, event);
1334 if (event & OHCI1394_selfIDComplete)
1335 tasklet_schedule(&ohci->bus_reset_tasklet);
1337 if (event & OHCI1394_RQPkt)
1338 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1340 if (event & OHCI1394_RSPkt)
1341 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1343 if (event & OHCI1394_reqTxComplete)
1344 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1346 if (event & OHCI1394_respTxComplete)
1347 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1349 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1350 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1353 i = ffs(iso_event) - 1;
1354 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1355 iso_event &= ~(1 << i);
1358 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1359 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1362 i = ffs(iso_event) - 1;
1363 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1364 iso_event &= ~(1 << i);
1367 if (unlikely(event & OHCI1394_regAccessFail))
1368 fw_error("Register access failure - "
1369 "please notify linux1394-devel@lists.sf.net\n");
1371 if (unlikely(event & OHCI1394_postedWriteErr))
1372 fw_error("PCI posted write error\n");
1374 if (unlikely(event & OHCI1394_cycleTooLong)) {
1375 if (printk_ratelimit())
1376 fw_notify("isochronous cycle too long\n");
1377 reg_write(ohci, OHCI1394_LinkControlSet,
1378 OHCI1394_LinkControl_cycleMaster);
1381 if (event & OHCI1394_cycle64Seconds) {
1382 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1383 if ((cycle_time & 0x80000000) == 0)
1384 ohci->bus_seconds++;
1390 static int software_reset(struct fw_ohci *ohci)
1394 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1396 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1397 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1398 OHCI1394_HCControl_softReset) == 0)
1406 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1408 struct fw_ohci *ohci = fw_ohci(card);
1409 struct pci_dev *dev = to_pci_dev(card->device);
1413 if (software_reset(ohci)) {
1414 fw_error("Failed to reset ohci card.\n");
1419 * Now enable LPS, which we need in order to start accessing
1420 * most of the registers. In fact, on some cards (ALI M5251),
1421 * accessing registers in the SClk domain without LPS enabled
1422 * will lock up the machine. Wait 50msec to make sure we have
1423 * full link enabled. However, with some cards (well, at least
1424 * a JMicron PCIe card), we have to try again sometimes.
1426 reg_write(ohci, OHCI1394_HCControlSet,
1427 OHCI1394_HCControl_LPS |
1428 OHCI1394_HCControl_postedWriteEnable);
1431 for (lps = 0, i = 0; !lps && i < 3; i++) {
1433 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1434 OHCI1394_HCControl_LPS;
1438 fw_error("Failed to set Link Power Status\n");
1442 reg_write(ohci, OHCI1394_HCControlClear,
1443 OHCI1394_HCControl_noByteSwapData);
1445 reg_write(ohci, OHCI1394_LinkControlSet,
1446 OHCI1394_LinkControl_rcvSelfID |
1447 OHCI1394_LinkControl_cycleTimerEnable |
1448 OHCI1394_LinkControl_cycleMaster);
1450 reg_write(ohci, OHCI1394_ATRetries,
1451 OHCI1394_MAX_AT_REQ_RETRIES |
1452 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1453 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1455 ar_context_run(&ohci->ar_request_ctx);
1456 ar_context_run(&ohci->ar_response_ctx);
1458 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1459 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1460 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1461 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1462 reg_write(ohci, OHCI1394_IntMaskSet,
1463 OHCI1394_selfIDComplete |
1464 OHCI1394_RQPkt | OHCI1394_RSPkt |
1465 OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1466 OHCI1394_isochRx | OHCI1394_isochTx |
1467 OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1468 OHCI1394_cycle64Seconds | OHCI1394_regAccessFail |
1469 OHCI1394_masterIntEnable);
1471 /* Activate link_on bit and contender bit in our self ID packets.*/
1472 if (ohci_update_phy_reg(card, 4, 0,
1473 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1477 * When the link is not yet enabled, the atomic config rom
1478 * update mechanism described below in ohci_set_config_rom()
1479 * is not active. We have to update ConfigRomHeader and
1480 * BusOptions manually, and the write to ConfigROMmap takes
1481 * effect immediately. We tie this to the enabling of the
1482 * link, so we have a valid config rom before enabling - the
1483 * OHCI requires that ConfigROMhdr and BusOptions have valid
1484 * values before enabling.
1486 * However, when the ConfigROMmap is written, some controllers
1487 * always read back quadlets 0 and 2 from the config rom to
1488 * the ConfigRomHeader and BusOptions registers on bus reset.
1489 * They shouldn't do that in this initial case where the link
1490 * isn't enabled. This means we have to use the same
1491 * workaround here, setting the bus header to 0 and then write
1492 * the right values in the bus reset tasklet.
1496 ohci->next_config_rom =
1497 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1498 &ohci->next_config_rom_bus,
1500 if (ohci->next_config_rom == NULL)
1503 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1504 fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1507 * In the suspend case, config_rom is NULL, which
1508 * means that we just reuse the old config rom.
1510 ohci->next_config_rom = ohci->config_rom;
1511 ohci->next_config_rom_bus = ohci->config_rom_bus;
1514 ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]);
1515 ohci->next_config_rom[0] = 0;
1516 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1517 reg_write(ohci, OHCI1394_BusOptions,
1518 be32_to_cpu(ohci->next_config_rom[2]));
1519 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1521 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1523 if (request_irq(dev->irq, irq_handler,
1524 IRQF_SHARED, ohci_driver_name, ohci)) {
1525 fw_error("Failed to allocate shared interrupt %d.\n",
1527 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1528 ohci->config_rom, ohci->config_rom_bus);
1532 reg_write(ohci, OHCI1394_HCControlSet,
1533 OHCI1394_HCControl_linkEnable |
1534 OHCI1394_HCControl_BIBimageValid);
1538 * We are ready to go, initiate bus reset to finish the
1542 fw_core_initiate_bus_reset(&ohci->card, 1);
1548 ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
1550 struct fw_ohci *ohci;
1551 unsigned long flags;
1552 int retval = -EBUSY;
1553 __be32 *next_config_rom;
1554 dma_addr_t uninitialized_var(next_config_rom_bus);
1556 ohci = fw_ohci(card);
1559 * When the OHCI controller is enabled, the config rom update
1560 * mechanism is a bit tricky, but easy enough to use. See
1561 * section 5.5.6 in the OHCI specification.
1563 * The OHCI controller caches the new config rom address in a
1564 * shadow register (ConfigROMmapNext) and needs a bus reset
1565 * for the changes to take place. When the bus reset is
1566 * detected, the controller loads the new values for the
1567 * ConfigRomHeader and BusOptions registers from the specified
1568 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1569 * shadow register. All automatically and atomically.
1571 * Now, there's a twist to this story. The automatic load of
1572 * ConfigRomHeader and BusOptions doesn't honor the
1573 * noByteSwapData bit, so with a be32 config rom, the
1574 * controller will load be32 values in to these registers
1575 * during the atomic update, even on litte endian
1576 * architectures. The workaround we use is to put a 0 in the
1577 * header quadlet; 0 is endian agnostic and means that the
1578 * config rom isn't ready yet. In the bus reset tasklet we
1579 * then set up the real values for the two registers.
1581 * We use ohci->lock to avoid racing with the code that sets
1582 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1586 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1587 &next_config_rom_bus, GFP_KERNEL);
1588 if (next_config_rom == NULL)
1591 spin_lock_irqsave(&ohci->lock, flags);
1593 if (ohci->next_config_rom == NULL) {
1594 ohci->next_config_rom = next_config_rom;
1595 ohci->next_config_rom_bus = next_config_rom_bus;
1597 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1598 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1601 ohci->next_header = config_rom[0];
1602 ohci->next_config_rom[0] = 0;
1604 reg_write(ohci, OHCI1394_ConfigROMmap,
1605 ohci->next_config_rom_bus);
1609 spin_unlock_irqrestore(&ohci->lock, flags);
1612 * Now initiate a bus reset to have the changes take
1613 * effect. We clean up the old config rom memory and DMA
1614 * mappings in the bus reset tasklet, since the OHCI
1615 * controller could need to access it before the bus reset
1619 fw_core_initiate_bus_reset(&ohci->card, 1);
1621 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1622 next_config_rom, next_config_rom_bus);
1627 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1629 struct fw_ohci *ohci = fw_ohci(card);
1631 at_context_transmit(&ohci->at_request_ctx, packet);
1634 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1636 struct fw_ohci *ohci = fw_ohci(card);
1638 at_context_transmit(&ohci->at_response_ctx, packet);
1641 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1643 struct fw_ohci *ohci = fw_ohci(card);
1644 struct context *ctx = &ohci->at_request_ctx;
1645 struct driver_data *driver_data = packet->driver_data;
1646 int retval = -ENOENT;
1648 tasklet_disable(&ctx->tasklet);
1650 if (packet->ack != 0)
1653 log_ar_at_event('T', packet->speed, packet->header, 0x20);
1654 driver_data->packet = NULL;
1655 packet->ack = RCODE_CANCELLED;
1656 packet->callback(packet, &ohci->card, packet->ack);
1660 tasklet_enable(&ctx->tasklet);
1666 ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
1668 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1671 struct fw_ohci *ohci = fw_ohci(card);
1672 unsigned long flags;
1676 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1677 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1680 spin_lock_irqsave(&ohci->lock, flags);
1682 if (ohci->generation != generation) {
1688 * Note, if the node ID contains a non-local bus ID, physical DMA is
1689 * enabled for _all_ nodes on remote buses.
1692 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1694 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1696 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1700 spin_unlock_irqrestore(&ohci->lock, flags);
1702 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1706 ohci_get_bus_time(struct fw_card *card)
1708 struct fw_ohci *ohci = fw_ohci(card);
1712 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1713 bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time;
1718 static int handle_ir_dualbuffer_packet(struct context *context,
1719 struct descriptor *d,
1720 struct descriptor *last)
1722 struct iso_context *ctx =
1723 container_of(context, struct iso_context, context);
1724 struct db_descriptor *db = (struct db_descriptor *) d;
1726 size_t header_length;
1730 if (db->first_res_count != 0 && db->second_res_count != 0) {
1731 if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
1732 /* This descriptor isn't done yet, stop iteration. */
1735 ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
1738 header_length = le16_to_cpu(db->first_req_count) -
1739 le16_to_cpu(db->first_res_count);
1741 i = ctx->header_length;
1743 end = p + header_length;
1744 while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
1746 * The iso header is byteswapped to little endian by
1747 * the controller, but the remaining header quadlets
1748 * are big endian. We want to present all the headers
1749 * as big endian, so we have to swap the first
1752 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1753 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1754 i += ctx->base.header_size;
1755 ctx->excess_bytes +=
1756 (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff;
1757 p += ctx->base.header_size + 4;
1759 ctx->header_length = i;
1761 ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
1762 le16_to_cpu(db->second_res_count);
1764 if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1765 ir_header = (__le32 *) (db + 1);
1766 ctx->base.callback(&ctx->base,
1767 le32_to_cpu(ir_header[0]) & 0xffff,
1768 ctx->header_length, ctx->header,
1769 ctx->base.callback_data);
1770 ctx->header_length = 0;
1776 static int handle_ir_packet_per_buffer(struct context *context,
1777 struct descriptor *d,
1778 struct descriptor *last)
1780 struct iso_context *ctx =
1781 container_of(context, struct iso_context, context);
1782 struct descriptor *pd;
1787 for (pd = d; pd <= last; pd++) {
1788 if (pd->transfer_status)
1792 /* Descriptor(s) not done yet, stop iteration */
1795 i = ctx->header_length;
1798 if (ctx->base.header_size > 0 &&
1799 i + ctx->base.header_size <= PAGE_SIZE) {
1801 * The iso header is byteswapped to little endian by
1802 * the controller, but the remaining header quadlets
1803 * are big endian. We want to present all the headers
1804 * as big endian, so we have to swap the first quadlet.
1806 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1807 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1808 ctx->header_length += ctx->base.header_size;
1811 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1812 ir_header = (__le32 *) p;
1813 ctx->base.callback(&ctx->base,
1814 le32_to_cpu(ir_header[0]) & 0xffff,
1815 ctx->header_length, ctx->header,
1816 ctx->base.callback_data);
1817 ctx->header_length = 0;
1823 static int handle_it_packet(struct context *context,
1824 struct descriptor *d,
1825 struct descriptor *last)
1827 struct iso_context *ctx =
1828 container_of(context, struct iso_context, context);
1830 if (last->transfer_status == 0)
1831 /* This descriptor isn't done yet, stop iteration. */
1834 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
1835 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1836 0, NULL, ctx->base.callback_data);
1841 static struct fw_iso_context *
1842 ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size)
1844 struct fw_ohci *ohci = fw_ohci(card);
1845 struct iso_context *ctx, *list;
1846 descriptor_callback_t callback;
1848 unsigned long flags;
1849 int index, retval = -ENOMEM;
1851 if (type == FW_ISO_CONTEXT_TRANSMIT) {
1852 mask = &ohci->it_context_mask;
1853 list = ohci->it_context_list;
1854 callback = handle_it_packet;
1856 mask = &ohci->ir_context_mask;
1857 list = ohci->ir_context_list;
1858 if (ohci->version >= OHCI_VERSION_1_1)
1859 callback = handle_ir_dualbuffer_packet;
1861 callback = handle_ir_packet_per_buffer;
1864 spin_lock_irqsave(&ohci->lock, flags);
1865 index = ffs(*mask) - 1;
1867 *mask &= ~(1 << index);
1868 spin_unlock_irqrestore(&ohci->lock, flags);
1871 return ERR_PTR(-EBUSY);
1873 if (type == FW_ISO_CONTEXT_TRANSMIT)
1874 regs = OHCI1394_IsoXmitContextBase(index);
1876 regs = OHCI1394_IsoRcvContextBase(index);
1879 memset(ctx, 0, sizeof(*ctx));
1880 ctx->header_length = 0;
1881 ctx->header = (void *) __get_free_page(GFP_KERNEL);
1882 if (ctx->header == NULL)
1885 retval = context_init(&ctx->context, ohci, regs, callback);
1887 goto out_with_header;
1892 free_page((unsigned long)ctx->header);
1894 spin_lock_irqsave(&ohci->lock, flags);
1895 *mask |= 1 << index;
1896 spin_unlock_irqrestore(&ohci->lock, flags);
1898 return ERR_PTR(retval);
1901 static int ohci_start_iso(struct fw_iso_context *base,
1902 s32 cycle, u32 sync, u32 tags)
1904 struct iso_context *ctx = container_of(base, struct iso_context, base);
1905 struct fw_ohci *ohci = ctx->context.ohci;
1909 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1910 index = ctx - ohci->it_context_list;
1913 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
1914 (cycle & 0x7fff) << 16;
1916 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1917 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1918 context_run(&ctx->context, match);
1920 index = ctx - ohci->ir_context_list;
1921 control = IR_CONTEXT_ISOCH_HEADER;
1922 if (ohci->version >= OHCI_VERSION_1_1)
1923 control |= IR_CONTEXT_DUAL_BUFFER_MODE;
1924 match = (tags << 28) | (sync << 8) | ctx->base.channel;
1926 match |= (cycle & 0x07fff) << 12;
1927 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
1930 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
1931 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
1932 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
1933 context_run(&ctx->context, control);
1939 static int ohci_stop_iso(struct fw_iso_context *base)
1941 struct fw_ohci *ohci = fw_ohci(base->card);
1942 struct iso_context *ctx = container_of(base, struct iso_context, base);
1945 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1946 index = ctx - ohci->it_context_list;
1947 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1949 index = ctx - ohci->ir_context_list;
1950 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1953 context_stop(&ctx->context);
1958 static void ohci_free_iso_context(struct fw_iso_context *base)
1960 struct fw_ohci *ohci = fw_ohci(base->card);
1961 struct iso_context *ctx = container_of(base, struct iso_context, base);
1962 unsigned long flags;
1965 ohci_stop_iso(base);
1966 context_release(&ctx->context);
1967 free_page((unsigned long)ctx->header);
1969 spin_lock_irqsave(&ohci->lock, flags);
1971 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1972 index = ctx - ohci->it_context_list;
1973 ohci->it_context_mask |= 1 << index;
1975 index = ctx - ohci->ir_context_list;
1976 ohci->ir_context_mask |= 1 << index;
1979 spin_unlock_irqrestore(&ohci->lock, flags);
1983 ohci_queue_iso_transmit(struct fw_iso_context *base,
1984 struct fw_iso_packet *packet,
1985 struct fw_iso_buffer *buffer,
1986 unsigned long payload)
1988 struct iso_context *ctx = container_of(base, struct iso_context, base);
1989 struct descriptor *d, *last, *pd;
1990 struct fw_iso_packet *p;
1992 dma_addr_t d_bus, page_bus;
1993 u32 z, header_z, payload_z, irq;
1994 u32 payload_index, payload_end_index, next_page_index;
1995 int page, end_page, i, length, offset;
1998 * FIXME: Cycle lost behavior should be configurable: lose
1999 * packet, retransmit or terminate..
2003 payload_index = payload;
2009 if (p->header_length > 0)
2012 /* Determine the first page the payload isn't contained in. */
2013 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2014 if (p->payload_length > 0)
2015 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2021 /* Get header size in number of descriptors. */
2022 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2024 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2029 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2030 d[0].req_count = cpu_to_le16(8);
2032 header = (__le32 *) &d[1];
2033 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2034 IT_HEADER_TAG(p->tag) |
2035 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2036 IT_HEADER_CHANNEL(ctx->base.channel) |
2037 IT_HEADER_SPEED(ctx->base.speed));
2039 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2040 p->payload_length));
2043 if (p->header_length > 0) {
2044 d[2].req_count = cpu_to_le16(p->header_length);
2045 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2046 memcpy(&d[z], p->header, p->header_length);
2049 pd = d + z - payload_z;
2050 payload_end_index = payload_index + p->payload_length;
2051 for (i = 0; i < payload_z; i++) {
2052 page = payload_index >> PAGE_SHIFT;
2053 offset = payload_index & ~PAGE_MASK;
2054 next_page_index = (page + 1) << PAGE_SHIFT;
2056 min(next_page_index, payload_end_index) - payload_index;
2057 pd[i].req_count = cpu_to_le16(length);
2059 page_bus = page_private(buffer->pages[page]);
2060 pd[i].data_address = cpu_to_le32(page_bus + offset);
2062 payload_index += length;
2066 irq = DESCRIPTOR_IRQ_ALWAYS;
2068 irq = DESCRIPTOR_NO_IRQ;
2070 last = z == 2 ? d : d + z - 1;
2071 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2073 DESCRIPTOR_BRANCH_ALWAYS |
2076 context_append(&ctx->context, d, z, header_z);
2082 ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
2083 struct fw_iso_packet *packet,
2084 struct fw_iso_buffer *buffer,
2085 unsigned long payload)
2087 struct iso_context *ctx = container_of(base, struct iso_context, base);
2088 struct db_descriptor *db = NULL;
2089 struct descriptor *d;
2090 struct fw_iso_packet *p;
2091 dma_addr_t d_bus, page_bus;
2092 u32 z, header_z, length, rest;
2093 int page, offset, packet_count, header_size;
2096 * FIXME: Cycle lost behavior should be configurable: lose
2097 * packet, retransmit or terminate..
2104 * The OHCI controller puts the status word in the header
2105 * buffer too, so we need 4 extra bytes per packet.
2107 packet_count = p->header_length / ctx->base.header_size;
2108 header_size = packet_count * (ctx->base.header_size + 4);
2110 /* Get header size in number of descriptors. */
2111 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2112 page = payload >> PAGE_SHIFT;
2113 offset = payload & ~PAGE_MASK;
2114 rest = p->payload_length;
2116 /* FIXME: make packet-per-buffer/dual-buffer a context option */
2118 d = context_get_descriptors(&ctx->context,
2119 z + header_z, &d_bus);
2123 db = (struct db_descriptor *) d;
2124 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
2125 DESCRIPTOR_BRANCH_ALWAYS);
2126 db->first_size = cpu_to_le16(ctx->base.header_size + 4);
2127 if (p->skip && rest == p->payload_length) {
2128 db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2129 db->first_req_count = db->first_size;
2131 db->first_req_count = cpu_to_le16(header_size);
2133 db->first_res_count = db->first_req_count;
2134 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
2136 if (p->skip && rest == p->payload_length)
2138 else if (offset + rest < PAGE_SIZE)
2141 length = PAGE_SIZE - offset;
2143 db->second_req_count = cpu_to_le16(length);
2144 db->second_res_count = db->second_req_count;
2145 page_bus = page_private(buffer->pages[page]);
2146 db->second_buffer = cpu_to_le32(page_bus + offset);
2148 if (p->interrupt && length == rest)
2149 db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2151 context_append(&ctx->context, d, z, header_z);
2152 offset = (offset + length) & ~PAGE_MASK;
2162 ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2163 struct fw_iso_packet *packet,
2164 struct fw_iso_buffer *buffer,
2165 unsigned long payload)
2167 struct iso_context *ctx = container_of(base, struct iso_context, base);
2168 struct descriptor *d = NULL, *pd = NULL;
2169 struct fw_iso_packet *p = packet;
2170 dma_addr_t d_bus, page_bus;
2171 u32 z, header_z, rest;
2173 int page, offset, packet_count, header_size, payload_per_buffer;
2176 * The OHCI controller puts the status word in the
2177 * buffer too, so we need 4 extra bytes per packet.
2179 packet_count = p->header_length / ctx->base.header_size;
2180 header_size = ctx->base.header_size + 4;
2182 /* Get header size in number of descriptors. */
2183 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2184 page = payload >> PAGE_SHIFT;
2185 offset = payload & ~PAGE_MASK;
2186 payload_per_buffer = p->payload_length / packet_count;
2188 for (i = 0; i < packet_count; i++) {
2189 /* d points to the header descriptor */
2190 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2191 d = context_get_descriptors(&ctx->context,
2192 z + header_z, &d_bus);
2196 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2197 DESCRIPTOR_INPUT_MORE);
2198 if (p->skip && i == 0)
2199 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2200 d->req_count = cpu_to_le16(header_size);
2201 d->res_count = d->req_count;
2202 d->transfer_status = 0;
2203 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2205 rest = payload_per_buffer;
2206 for (j = 1; j < z; j++) {
2208 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2209 DESCRIPTOR_INPUT_MORE);
2211 if (offset + rest < PAGE_SIZE)
2214 length = PAGE_SIZE - offset;
2215 pd->req_count = cpu_to_le16(length);
2216 pd->res_count = pd->req_count;
2217 pd->transfer_status = 0;
2219 page_bus = page_private(buffer->pages[page]);
2220 pd->data_address = cpu_to_le32(page_bus + offset);
2222 offset = (offset + length) & ~PAGE_MASK;
2227 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2228 DESCRIPTOR_INPUT_LAST |
2229 DESCRIPTOR_BRANCH_ALWAYS);
2230 if (p->interrupt && i == packet_count - 1)
2231 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2233 context_append(&ctx->context, d, z, header_z);
2240 ohci_queue_iso(struct fw_iso_context *base,
2241 struct fw_iso_packet *packet,
2242 struct fw_iso_buffer *buffer,
2243 unsigned long payload)
2245 struct iso_context *ctx = container_of(base, struct iso_context, base);
2246 unsigned long flags;
2249 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2250 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2251 retval = ohci_queue_iso_transmit(base, packet, buffer, payload);
2252 else if (ctx->context.ohci->version >= OHCI_VERSION_1_1)
2253 retval = ohci_queue_iso_receive_dualbuffer(base, packet,
2256 retval = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2259 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2264 static const struct fw_card_driver ohci_driver = {
2265 .name = ohci_driver_name,
2266 .enable = ohci_enable,
2267 .update_phy_reg = ohci_update_phy_reg,
2268 .set_config_rom = ohci_set_config_rom,
2269 .send_request = ohci_send_request,
2270 .send_response = ohci_send_response,
2271 .cancel_packet = ohci_cancel_packet,
2272 .enable_phys_dma = ohci_enable_phys_dma,
2273 .get_bus_time = ohci_get_bus_time,
2275 .allocate_iso_context = ohci_allocate_iso_context,
2276 .free_iso_context = ohci_free_iso_context,
2277 .queue_iso = ohci_queue_iso,
2278 .start_iso = ohci_start_iso,
2279 .stop_iso = ohci_stop_iso,
2282 #ifdef CONFIG_PPC_PMAC
2283 static void ohci_pmac_on(struct pci_dev *dev)
2285 if (machine_is(powermac)) {
2286 struct device_node *ofn = pci_device_to_OF_node(dev);
2289 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2290 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2295 static void ohci_pmac_off(struct pci_dev *dev)
2297 if (machine_is(powermac)) {
2298 struct device_node *ofn = pci_device_to_OF_node(dev);
2301 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2302 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2307 #define ohci_pmac_on(dev)
2308 #define ohci_pmac_off(dev)
2309 #endif /* CONFIG_PPC_PMAC */
2311 static int __devinit
2312 pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
2314 struct fw_ohci *ohci;
2315 u32 bus_options, max_receive, link_speed;
2320 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2322 fw_error("Could not malloc fw_ohci data.\n");
2326 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2330 err = pci_enable_device(dev);
2332 fw_error("Failed to enable OHCI hardware.\n");
2336 pci_set_master(dev);
2337 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2338 pci_set_drvdata(dev, ohci);
2340 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2341 ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE &&
2342 dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW;
2344 spin_lock_init(&ohci->lock);
2346 tasklet_init(&ohci->bus_reset_tasklet,
2347 bus_reset_tasklet, (unsigned long)ohci);
2349 err = pci_request_region(dev, 0, ohci_driver_name);
2351 fw_error("MMIO resource unavailable\n");
2355 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2356 if (ohci->registers == NULL) {
2357 fw_error("Failed to remap registers\n");
2362 ar_context_init(&ohci->ar_request_ctx, ohci,
2363 OHCI1394_AsReqRcvContextControlSet);
2365 ar_context_init(&ohci->ar_response_ctx, ohci,
2366 OHCI1394_AsRspRcvContextControlSet);
2368 context_init(&ohci->at_request_ctx, ohci,
2369 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2371 context_init(&ohci->at_response_ctx, ohci,
2372 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2374 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2375 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2376 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2377 size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
2378 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2380 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2381 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2382 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2383 size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
2384 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2386 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2387 fw_error("Out of memory for it/ir contexts.\n");
2389 goto fail_registers;
2392 /* self-id dma buffer allocation */
2393 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2397 if (ohci->self_id_cpu == NULL) {
2398 fw_error("Out of memory for self ID buffer.\n");
2400 goto fail_registers;
2403 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2404 max_receive = (bus_options >> 12) & 0xf;
2405 link_speed = bus_options & 0x7;
2406 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2407 reg_read(ohci, OHCI1394_GUIDLo);
2409 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2413 ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2414 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2415 dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff);
2419 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2420 ohci->self_id_cpu, ohci->self_id_bus);
2422 kfree(ohci->it_context_list);
2423 kfree(ohci->ir_context_list);
2424 pci_iounmap(dev, ohci->registers);
2426 pci_release_region(dev, 0);
2428 pci_disable_device(dev);
2436 static void pci_remove(struct pci_dev *dev)
2438 struct fw_ohci *ohci;
2440 ohci = pci_get_drvdata(dev);
2441 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2443 fw_core_remove_card(&ohci->card);
2446 * FIXME: Fail all pending packets here, now that the upper
2447 * layers can't queue any more.
2450 software_reset(ohci);
2451 free_irq(dev->irq, ohci);
2452 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2453 ohci->self_id_cpu, ohci->self_id_bus);
2454 kfree(ohci->it_context_list);
2455 kfree(ohci->ir_context_list);
2456 pci_iounmap(dev, ohci->registers);
2457 pci_release_region(dev, 0);
2458 pci_disable_device(dev);
2462 fw_notify("Removed fw-ohci device.\n");
2466 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2468 struct fw_ohci *ohci = pci_get_drvdata(dev);
2471 software_reset(ohci);
2472 free_irq(dev->irq, ohci);
2473 err = pci_save_state(dev);
2475 fw_error("pci_save_state failed\n");
2478 err = pci_set_power_state(dev, pci_choose_state(dev, state));
2480 fw_error("pci_set_power_state failed with %d\n", err);
2486 static int pci_resume(struct pci_dev *dev)
2488 struct fw_ohci *ohci = pci_get_drvdata(dev);
2492 pci_set_power_state(dev, PCI_D0);
2493 pci_restore_state(dev);
2494 err = pci_enable_device(dev);
2496 fw_error("pci_enable_device failed\n");
2500 return ohci_enable(&ohci->card, NULL, 0);
2504 static struct pci_device_id pci_table[] = {
2505 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2509 MODULE_DEVICE_TABLE(pci, pci_table);
2511 static struct pci_driver fw_ohci_pci_driver = {
2512 .name = ohci_driver_name,
2513 .id_table = pci_table,
2515 .remove = pci_remove,
2517 .resume = pci_resume,
2518 .suspend = pci_suspend,
2522 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2523 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2524 MODULE_LICENSE("GPL");
2526 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2527 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2528 MODULE_ALIAS("ohci1394");
2531 static int __init fw_ohci_init(void)
2533 return pci_register_driver(&fw_ohci_pci_driver);
2536 static void __exit fw_ohci_cleanup(void)
2538 pci_unregister_driver(&fw_ohci_pci_driver);
2541 module_init(fw_ohci_init);
2542 module_exit(fw_ohci_cleanup);